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----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800015";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE1B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800005";
when 16#00074# => romdata <= X"03200000";
when 16#00075# => romdata <= X"0539A81B";
when 16#00076# => romdata <= X"8410A260";
when 16#00077# => romdata <= X"C4204000";
when 16#00078# => romdata <= X"05000080";
when 16#00079# => romdata <= X"82100000";
when 16#0007A# => romdata <= X"80A0E000";
when 16#0007B# => romdata <= X"02800005";
when 16#0007C# => romdata <= X"01000000";
when 16#0007D# => romdata <= X"82004002";
when 16#0007E# => romdata <= X"10BFFFFC";
when 16#0007F# => romdata <= X"8620E001";
when 16#00080# => romdata <= X"3D1003FF";
when 16#00081# => romdata <= X"BC17A3E0";
when 16#00082# => romdata <= X"BC278001";
when 16#00083# => romdata <= X"9C27A060";
when 16#00084# => romdata <= X"03100000";
when 16#00085# => romdata <= X"81C04000";
when 16#00086# => romdata <= X"01000000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_36x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_36x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(36-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(36-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_36x512_hf_top_wrapper;
architecture xilinx of fifo_36x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_36x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(36-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_36x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
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`protect end_protected
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 4;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000008#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5936)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5936)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sqrt is
port(pulse : in std_logic;
btn : in std_logic_vector(2 downto 0);
sw : in std_logic_vector(9 downto 0);
led : out std_logic_vector(9 downto 0);
hex0 : out std_logic_vector(7 downto 0);
hex1 : out std_logic_vector(7 downto 0);
hex2 : out std_logic_vector(7 downto 0);
hex3 : out std_logic_vector(7 downto 0));
end sqrt;
architecture BEHAVIOR of sqrt is
--component clock is
-- port(pulse : out std_logic);
--end component;
component alu is
port(func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0));
end component;
component bB is
port(S_GRB : in std_logic_vector(15 downto 0);
S_PR_F : in std_logic_vector(15 downto 0);
S_MAR_F : in std_logic_vector(15 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0));
end component;
--component bC is
-- port(S_BUS_C : inout std_logic_vector(15 downto 0));
--end component;
component busA is
port(clock : in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector(7 downto 0);
SI : in std_logic_vector(2 downto 0);
busA_out : out std_logic_vector(15 downto 0));
end component;
component csgc is
port(clk : in std_logic;
init_phase : in std_logic_vector(3 downto 0);
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0));
end component;
component fr is
port(clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic);
end component;
component gr is
port(clk : in std_logic;
S_GRlat : in std_logic;
S_ctl_a : in std_logic_vector(3 downto 0);
S_ctl_b : in std_logic_vector(3 downto 0);
S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A : out std_logic_vector(15 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View : out std_logic_vector(15 downto 0);
GR1_View : out std_logic_vector(15 downto 0);
GR2_View : out std_logic_vector(15 downto 0);
GR3_View : out std_logic_vector(15 downto 0);
GR4_View : out std_logic_vector(15 downto 0);
GR5_View : out std_logic_vector(15 downto 0);
GR6_View : out std_logic_vector(15 downto 0);
GR7_View : out std_logic_vector(15 downto 0);
GR8_View : out std_logic_vector(15 downto 0);
GR9_View : out std_logic_vector(15 downto 0);
GR10_View : out std_logic_vector(15 downto 0);
GR11_View : out std_logic_vector(15 downto 0);
GR12_View : out std_logic_vector(15 downto 0);
GR13_View : out std_logic_vector(15 downto 0);
GR14_View : out std_logic_vector(15 downto 0);
GR15_View : out std_logic_vector(15 downto 0));
end component;
component inst is
port(clock : in std_logic;
busA : in std_logic_vector(15 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0));
end component;
component MAR is
port(clk : in std_logic;
lat : in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16 : out std_logic_vector(15 downto 0);
M_ad8 : out std_logic_vector(7 downto 0));
end component;
component mdr is
port(clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0));
end component;
--component mem is
-- port(clk : in std_logic;
-- read : in std_logic;
-- write : in std_logic;
-- init_phase : in std_logic_vector(3 downto 0);
-- input : in std_logic_vector(15 downto 0);
-- S_MAR_F : in std_logic_vector(7 downto 0);
-- S_MDR_F : in std_logic_vector(15 downto 0);
-- data : out std_logic_vector(15 downto 0));
--end component;
component M9K_RAM is
port(address : in std_logic_vector(7 downto 0);
clock : in std_logic;
init_phase : in std_logic_vector(3 downto 0);
input : in std_logic_vector(15 downto 0);
data : in std_logic_vector(15 downto 0);
rden : in std_logic;
wren : in std_logic;
q : out std_logic_vector(15 downto 0));
end component;
component pr is
port(clk : in std_logic;
S_PRlat : in std_logic;
S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end component;
--signal pulse : std_logic;
signal alu_fr_z : std_logic;
signal alu_fr_s : std_logic;
signal alu_fr_o : std_logic;
signal busb_alu : std_logic_vector(15 downto 0);
signal alu_busc_others : std_logic_vector(15 downto 0);
signal busa_alu_ir : std_logic_vector(15 downto 0);
signal csgc_busa_ctl : std_logic_vector(2 downto 0);
signal csgc_busb_ctl : std_logic_vector(4 downto 0);
signal csgc_busab_addr : std_logic_vector(7 downto 0);
signal csgc_gr_lat : std_logic;
signal csgc_gr_asel : std_logic_vector(3 downto 0);
signal csgc_gr_bsel : std_logic_vector(3 downto 0);
signal csgc_gr_csel : std_logic_vector(3 downto 0);
signal csgc_ir_lat : std_logic;
signal csgc_fr_lat : std_logic;
signal csgc_pr_lat : std_logic;
signal csgc_pr_cntup : std_logic;
signal csgc_mar_lat : std_logic;
signal csgc_mdr_lat : std_logic;
signal csgc_mdr_sel : std_logic;
signal csgc_mem_read : std_logic;
signal csgc_mem_write : std_logic;
signal csgc_alu_func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
signal fr_alu_z : std_logic;
signal fr_alu_s : std_logic;
signal fr_alu_o : std_logic;
signal gr_busa : std_logic_vector(15 downto 0);
signal gr_busb : std_logic_vector(15 downto 0);
signal GR0_View : std_logic_vector(15 downto 0);
signal GR1_View : std_logic_vector(15 downto 0);
signal GR2_View : std_logic_vector(15 downto 0);
signal GR3_View : std_logic_vector(15 downto 0);
signal GR4_View : std_logic_vector(15 downto 0);
signal GR5_View : std_logic_vector(15 downto 0);
signal GR6_View : std_logic_vector(15 downto 0);
signal GR7_View : std_logic_vector(15 downto 0);
signal GR8_View : std_logic_vector(15 downto 0);
signal GR9_View : std_logic_vector(15 downto 0);
signal GR10_View : std_logic_vector(15 downto 0);
signal GR11_View : std_logic_vector(15 downto 0);
signal GR12_View : std_logic_vector(15 downto 0);
signal GR13_View : std_logic_vector(15 downto 0);
signal GR14_View : std_logic_vector(15 downto 0);
signal GR15_View : std_logic_vector(15 downto 0);
signal ir_csgc : std_logic_vector(15 downto 0);
signal mar_busb : std_logic_vector(15 downto 0);
signal mar_mem : std_logic_vector(7 downto 0);
signal mdr_busab_mem : std_logic_vector(15 downto 0);
signal mem_mdr : std_logic_vector(15 downto 0);
signal pr_busb : std_logic_vector(15 downto 0);
signal init_phase : std_logic_vector(3 downto 0);
signal input : std_logic_vector(15 downto 0);
function LedDec(num : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case num is
when X"0" => return "11000000";
when X"1" => return "11111001";
when X"2" => return "10100100";
when X"3" => return "10110000";
when X"4" => return "10011001";
when X"5" => return "10010010";
when X"6" => return "10000010";
when X"7" => return "11111000";
when X"8" => return "10000000";
when X"9" => return "10011000";
when X"a" => return "10001000";
when X"b" => return "10000011";
when X"c" => return "10100111";
when X"d" => return "10100001";
when X"e" => return "10000110";
when X"f" => return "10001110";
when others => return "11111111";
end case;
end function;
begin
led(2 downto 0) <= not btn(2 downto 0);
led(6 downto 3) <= init_phase;
-- clock_a : clock port map(pulse => pulse);
alu_a : alu port map(func => csgc_alu_func,
busA => busa_alu_ir,
busB => busb_alu,
inZ => fr_alu_z,
inS => fr_alu_s,
inO => fr_alu_o,
outZ => alu_fr_z,
outS => alu_fr_s,
outO => alu_fr_o,
busC => alu_busc_others);
bB_a : bB port map(S_GRB => gr_busb,
S_PR_F => pr_busb,
S_MAR_F => mar_busb,
S_MDR_F => mdr_busab_mem,
addr => csgc_busab_addr,
S_s_ctl => csgc_busb_ctl,
S_BUS_B => busb_alu);
--bC_a : bC port map(S_BUS_C => alu_busc_others);
busA_a : busA port map(clock => pulse,
MDR => mdr_busab_mem,
GR => gr_busa,
ADDR => csgc_busab_addr,
SI => csgc_busa_ctl,
busA_out => busa_alu_ir);
csgc_a : csgc port map(clk => pulse,
init_phase => init_phase,
mlang => ir_csgc,
ba_ctl => csgc_busa_ctl,
bb_ctl => csgc_busb_ctl,
address => csgc_busab_addr,
gr_lat => csgc_gr_lat,
gra => csgc_gr_asel,
grb => csgc_gr_bsel,
grc => csgc_gr_csel,
ir_lat => csgc_ir_lat,
fr_lat => csgc_fr_lat,
pr_lat => csgc_pr_lat,
pr_cnt => csgc_pr_cntup,
mar_lat => csgc_mar_lat,
mdr_lat => csgc_mdr_lat,
mdr_sel => csgc_mdr_sel,
m_read => csgc_mem_read,
m_write => csgc_mem_write,
func => csgc_alu_func,
phaseView => phaseView);
fr_a : fr port map(clk => pulse,
latch => csgc_fr_lat,
inZF => alu_fr_z,
inSF => alu_fr_s,
inOF => alu_fr_o,
outZF => fr_alu_z,
outSF => fr_alu_s,
outOF => fr_alu_o);
gr_a : gr port map(clk => pulse,
S_GRlat => csgc_gr_lat,
S_ctl_a => csgc_gr_asel,
S_ctl_b => csgc_gr_bsel,
S_ctl_c => csgc_gr_csel,
S_BUS_C => alu_busc_others,
S_BUS_A => gr_busa,
S_BUS_B => gr_busb,
GR0_View => GR0_View,
GR1_View => GR1_View,
GR2_View => GR2_View,
GR3_View => GR3_View,
GR4_View => GR4_View,
GR5_View => GR5_View,
GR6_View => GR6_View,
GR7_View => GR7_View,
GR8_View => GR8_View,
GR9_View => GR9_View,
GR10_View => GR10_View,
GR11_View => GR11_View,
GR12_View => GR12_View,
GR13_View => GR13_View,
GR14_View => GR14_View,
GR15_View => GR15_View);
inst_a : inst port map(clock => pulse,
busA => busa_alu_ir,
latch => csgc_ir_lat,
Mlang => ir_csgc);
MAR_a : MAR port map(clk => pulse,
lat => csgc_mar_lat,
busC => alu_busc_others,
M_ad16 => mar_busb,
M_ad8 => mar_mem);
mdr_a : mdr port map(clock => pulse,
busC => alu_busc_others,
latch => csgc_mdr_lat,
memo => mem_mdr,
sel => csgc_mdr_sel,
data => mdr_busab_mem);
-- mem_a : mem port map(clk => pulse,
-- read => csgc_mem_read,
-- write => csgc_mem_write,
-- init_phase => init_phase,
-- input => input,
-- S_MAR_F => mar_mem,
-- S_MDR_F => mdr_busab_mem,
-- data => mem_mdr);
M9K_RAM_inst : M9K_RAM port map(address => mar_mem,
clock => pulse,
init_phase => init_phase,
input => input,
data => mdr_busab_mem,
rden => csgc_mem_read,
wren => csgc_mem_write,
q => mem_mdr);
pr_a : pr port map(clk => pulse,
S_PRlat => csgc_pr_lat,
S_s_inc => csgc_pr_cntup,
S_BUS_C => alu_busc_others,
S_PR_F => pr_busb);
process(pulse)
variable GR_View : std_logic_vector(15 downto 0);
begin
if pulse'event and pulse = '1' then
if btn(0) = '0' then
input(7 downto 0) <= sw(7 downto 0);
init_phase <= X"1";
end if;
if btn(1) = '0' then
input(15 downto 8) <= sw(7 downto 0);
init_phase <= X"1";
end if;
if btn(2) = '0' then
if (init_phase = X"1") then
init_phase <= X"2";
end if;
end if;
if init_phase >= X"2" then
if init_phase = X"f" then
init_phase <= X"0";
end if;
init_phase <= init_phase + 1;
end if;
if ir_csgc(15 downto 12) = X"f" then
case ir_csgc(11 downto 8) is
when X"0" => GR_View := GR0_View;
when X"1" => GR_View := GR1_View;
when X"2" => GR_View := GR2_View;
when X"3" => GR_View := GR3_View;
when X"4" => GR_View := GR4_View;
when X"5" => GR_View := GR5_View;
when X"6" => GR_View := GR6_View;
when X"7" => GR_View := GR7_View;
when X"8" => GR_View := GR8_View;
when X"9" => GR_View := GR9_View;
when X"a" => GR_View := GR10_View;
when X"b" => GR_View := GR11_View;
when X"c" => GR_View := GR12_View;
when X"d" => GR_View := GR13_View;
when X"e" => GR_View := GR14_View;
when X"f" => GR_View := GR15_View;
when others => null;
end case;
case ir_csgc(3 downto 0) is
when X"0" => hex0 <= LedDec(GR_View(3 downto 0));
when X"1" => hex1 <= LedDec(GR_View(3 downto 0));
when X"2" => hex2 <= LedDec(GR_View(3 downto 0));
when X"3" => hex3 <= LedDec(GR_View(3 downto 0));
when others => null;
end case;
hex2(7) <= '0';
elsif init_phase = X"1" then
hex0 <= LedDec(input(3 downto 0));
hex1 <= LedDec(input(7 downto 4));
hex2 <= LedDec(input(11 downto 8));
hex3 <= LedDec(input(15 downto 12));
hex0(7) <= '0';
end if;
end if;
end process;
end BEHAVIOR;
|
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART PARITY BIT GENERATOR
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end UART_PARITY;
architecture FULL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART RECEIVER
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_RX is
Generic (
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_RXD : in std_logic;
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end UART_RX;
architecture FULL of UART_RX is
signal rx_clk_en : std_logic;
signal rx_ticks : unsigned(3 downto 0);
signal rx_clk_divider_en : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_bit_count : unsigned(2 downto 0);
signal rx_bit_count_en : std_logic;
signal rx_data_shreg_en : std_logic;
signal rx_parity_bit : std_logic;
signal rx_parity_error : std_logic;
signal rx_parity_check_en : std_logic;
signal rx_output_reg_en : std_logic;
type state is (idle, startbit, databits, paritybit, stopbit);
signal rx_pstate : state;
signal rx_nstate : state;
begin
-- -------------------------------------------------------------------------
-- UART RECEIVER CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_rx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (rx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (rx_ticks = "1111") then
rx_ticks <= (others => '0');
rx_clk_en <= '0';
elsif (rx_ticks = "0111") then
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '1';
else
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '0';
end if;
else
rx_ticks <= rx_ticks;
rx_clk_en <= '0';
end if;
else
rx_ticks <= (others => '0');
rx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER BIT COUNTER
-- -------------------------------------------------------------------------
uart_rx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_bit_count <= (others => '0');
elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
if (rx_bit_count = "111") then
rx_bit_count <= (others => '0');
else
rx_bit_count <= rx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER DATA SHIFT REGISTER
-- -------------------------------------------------------------------------
uart_rx_data_shift_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_data <= (others => '0');
elsif (rx_clk_en = '1' AND rx_data_shreg_en = '1') then
rx_data <= UART_RXD & rx_data(7 downto 1);
end if;
end if;
end process;
DATA_OUT <= rx_data;
-- -------------------------------------------------------------------------
-- UART RECEIVER PARITY GENERATOR AND CHECK
-- -------------------------------------------------------------------------
uart_rx_parity_g : if (PARITY_BIT /= "none") generate
uart_rx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => rx_data,
PARITY_OUT => rx_parity_bit
);
uart_rx_parity_check_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_parity_error <= '0';
elsif (rx_parity_check_en = '1') then
rx_parity_error <= rx_parity_bit XOR UART_RXD;
end if;
end if;
end process;
end generate;
uart_rx_noparity_g : if (PARITY_BIT = "none") generate
rx_parity_error <= '0';
end generate;
-- -------------------------------------------------------------------------
-- UART RECEIVER OUTPUT REGISTER
-- -------------------------------------------------------------------------
uart_rx_output_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
DATA_VLD <= '0';
FRAME_ERROR <= '0';
else
if (rx_output_reg_en = '1') then
DATA_VLD <= NOT rx_parity_error AND UART_RXD;
FRAME_ERROR <= NOT UART_RXD;
else
DATA_VLD <= '0';
FRAME_ERROR <= '0';
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_pstate <= idle;
else
rx_pstate <= rx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (rx_pstate, UART_RXD, rx_clk_en, rx_bit_count)
begin
case rx_pstate is
when idle =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
if (UART_RXD = '0') then
rx_nstate <= startbit;
else
rx_nstate <= idle;
end if;
when startbit =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= databits;
else
rx_nstate <= startbit;
end if;
when databits =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '1';
rx_data_shreg_en <= '1';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
if (PARITY_BIT = "none") then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if ;
else
rx_nstate <= databits;
end if;
when paritybit =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '1';
if (rx_clk_en = '1') then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if;
when stopbit =>
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= idle;
rx_output_reg_en <= '1';
else
rx_nstate <= stopbit;
rx_output_reg_en <= '0';
end if;
when others =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
rx_nstate <= idle;
end case;
end process;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART TRANSMITTER
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic (
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_TXD : out std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
);
end UART_TX;
architecture FULL of UART_TX is
signal tx_clk_en : std_logic;
signal tx_clk_divider_en : std_logic;
signal tx_ticks : unsigned(3 downto 0);
signal tx_data : std_logic_vector(7 downto 0);
signal tx_bit_count : unsigned(2 downto 0);
signal tx_bit_count_en : std_logic;
signal tx_busy : std_logic;
signal tx_parity_bit : std_logic;
signal tx_data_out_sel : std_logic_vector(1 downto 0);
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
begin
BUSY <= tx_busy;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_tx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (tx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (tx_ticks = "1111") then
tx_ticks <= (others => '0');
tx_clk_en <= '0';
elsif (tx_ticks = "0001") then
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '1';
else
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '0';
end if;
else
tx_ticks <= tx_ticks;
tx_clk_en <= '0';
end if;
else
tx_ticks <= (others => '0');
tx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_input_data_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_data <= (others => '0');
elsif (DATA_SEND = '1' AND tx_busy = '0') then
tx_data <= DATA_IN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
uart_tx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_bit_count <= (others => '0');
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = "111") then
tx_bit_count <= (others => '0');
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
uart_tx_parity_g : if (PARITY_BIT /= "none") generate
uart_tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
tx_parity_bit <= 'Z';
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER OUTPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_output_data_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
UART_TXD <= '1';
else
case tx_data_out_sel is
when "01" => -- START BIT
UART_TXD <= '0';
when "10" => -- DATA BITS
UART_TXD <= tx_data(to_integer(tx_bit_count));
when "11" => -- PARITY BIT
UART_TXD <= tx_parity_bit;
when others => -- STOP BIT OR IDLE
UART_TXD <= '1';
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, DATA_SEND, tx_clk_en, tx_bit_count)
begin
case tx_pstate is
when idle =>
tx_busy <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '0';
if (DATA_SEND = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_busy <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_busy <= '1';
tx_data_out_sel <= "01";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_busy <= '1';
tx_data_out_sel <= "10";
tx_bit_count_en <= '1';
tx_clk_divider_en <= '1';
if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
if (PARITY_BIT = "none") then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_busy <= '1';
tx_data_out_sel <= "11";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if;
when stopbit =>
tx_busy <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (DATA_SEND = '1') then
tx_nstate <= txsync;
elsif (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= stopbit;
end if;
when others =>
tx_busy <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '0';
tx_nstate <= idle;
end case;
end process;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART TOP MODULE
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!!
-- OTHER PARAMETERS CAN BE SET USING GENERICS.
entity UART is
Generic (
CLK_FREQ : integer := 50e6; -- set system clock frequency in Hz
BAUD_RATE : integer := 115200; -- baud rate value
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic; -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end UART;
architecture FULL of UART is
constant divider_value : integer := CLK_FREQ/(16*BAUD_RATE);
signal uart_ticks : integer range 0 to divider_value-1;
signal uart_clk_en : std_logic;
signal uart_rxd_shreg : std_logic_vector(3 downto 0);
signal uart_rxd_debounced : std_logic;
begin
-- -------------------------------------------------------------------------
-- UART OVERSAMPLING CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_oversampling_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_ticks <= 0;
uart_clk_en <= '0';
elsif (uart_ticks = divider_value-1) then
uart_ticks <= 0;
uart_clk_en <= '1';
else
uart_ticks <= uart_ticks + 1;
uart_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RXD DEBAUNCER
-- -------------------------------------------------------------------------
uart_rxd_debouncer : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_rxd_shreg <= (others => '1');
uart_rxd_debounced <= '1';
else
uart_rxd_shreg <= UART_RXD & uart_rxd_shreg(3 downto 1);
uart_rxd_debounced <= uart_rxd_shreg(0) OR
uart_rxd_shreg(1) OR
uart_rxd_shreg(2) OR
uart_rxd_shreg(3);
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER
-- -------------------------------------------------------------------------
uart_tx_i: entity work.UART_TX
generic map (
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => uart_clk_en,
UART_TXD => UART_TXD,
-- USER DATA INPUT INTERFACE
DATA_IN => DATA_IN,
DATA_SEND => DATA_SEND,
BUSY => BUSY
);
-- -------------------------------------------------------------------------
-- UART RECEIVER
-- -------------------------------------------------------------------------
uart_rx_i: entity work.UART_RX
generic map (
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => uart_clk_en,
UART_RXD => uart_rxd_debounced,
-- USER DATA OUTPUT INTERFACE
DATA_OUT => DATA_OUT,
DATA_VLD => DATA_VLD,
FRAME_ERROR => FRAME_ERROR
);
end FULL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity test;
architecture beh of test is
signal s_clk : std_logic;
signal s_register : std_logic_vector(7 downto 0);
begin
process is
begin
wait until rising_edge(s_clk);
-- In VHDL code, hex/bin literals work
s_register <= x"00";
s_register <= b"00000000";
s_register <= "00" & o"00";
end process;
default clock is rising_edge(s_clk);
-- In PSL code they don't work
FOOTER_VALID_hex : cover {s_register = x"00"};
FOOTER_VALID_bin : cover {s_register = b"00000000"};
FOOTER_VALID_oct : cover {s_register = "00" & o"00"};
FOOTER_VALID : cover {s_register = "00000000"};
process
begin
for i in 1 to 2 loop
s_clk <= '0';
wait for 1 ns;
s_clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
end architecture beh;
|
library ieee;
use ieee.std_logic_1164.all;
entity mux_gen is
generic ( width : integer := 32 );
port(
in1 : in std_logic_vector(width-1 downto 0);
in0 : in std_logic_vector(width-1 downto 0);
sel : in std_logic;
output : out std_logic_vector(width-1 downto 0)
);
end mux_gen;
architecture bhv of mux_gen is
begin
process(in0,in1,sel)
begin
case sel is
when '1' =>
output <= in1;
when others =>
output <= in0;
end case;
end process;
end bhv;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY vgagraph_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END vgagraph_fifo;
ARCHITECTURE vgagraph_fifo_arch OF vgagraph_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF vgagraph_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF vgagraph_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF vgagraph_fifo_arch : ARCHITECTURE IS "vgagraph_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF vgagraph_fifo_arch: ARCHITECTURE IS "vgagraph_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=16,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" &
"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_T" &
"HRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=2048,C_RD_FREQ=1,C_RD_PNTR_WIDTH=11,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTE" &
"RFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_W" &
"IDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_T" &
"YPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C" &
"_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=" &
"10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=" &
"1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_AS" &
"SERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 16,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 2048,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 11,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END vgagraph_fifo_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity registerFile is
Port ( we : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
dataToWrite : in STD_LOGIC_VECTOR (31 downto 0);
CRs1 : out STD_LOGIC_VECTOR (31 downto 0);
CRs2 : out STD_LOGIC_VECTOR (31 downto 0);
CRd : out STD_LOGIC_VECTOR (31 downto 0));
end registerFile;
architecture Behavioral of registerFile is
type ram_type is array (0 to 39) of std_logic_vector(31 downto 0);
signal ceros : std_logic_vector (31 downto 0) := (others=>'0');
signal regFile : ram_type := (others => x"00000000");
begin
process(rs1,rs2,rd,rst,dataToWrite)
begin
if (rst = '1') then
CRs1 <= ceros;
CRs2 <= ceros;
CRd <= ceros;
elsif (we = '1') then
if (conv_integer(rs1) = 0) then
CRs1 <= ceros;
else
CRs1 <= regFile(conv_integer(rs1));
end if;
if (conv_integer(rs2) = 0) then
CRs2 <= ceros;
else
CRs2 <= regFile(conv_integer(rs2));
end if;
if (not (rd = "00000")) then
regFile(conv_integer(rd)) <= dataToWrite;
end if;
CRd <= regFile(conv_integer(rd));
else
CRs1 <= ceros;
CRs2 <= ceros;
CRd <= ceros;
end if;
end process;
end Behavioral; |
--##############################################################################
-- mcu80_l80irq : Interrupt controller for light8080-based mcu80 MCU.
--##############################################################################
--
-- This is a basic interrupt controller for the light8080 core. It is meant for
-- demonstration purposes only (demonstration of the light8080 core) and has
-- not passed any serious verification test bench.
-- It has been built on the same principles as the rest of the modules in this
-- project: no more functionality than strictly needed, minimized area.
--
-- The interrupt controller operates under these rules:
--
-- -# All interrupt inputs are active at rising edge.
-- -# No logic is included for input sinchronization. You must take care to
-- prevent metastability issues yourself by the usual means.
-- -# If a new edge is detected before the first is serviced, it is lost.
-- -# As soon as a rising edge in enabled irq input K is detected, bit K in the
-- interrupt pending register 'irq_pending_reg' will be asserted.
-- Than is, disabled interrupts never get detected at all.
-- -# Output cpu_intr_o will be asserted as long as there's a bit asserted in
-- the interrupt pending register.
-- -# For each interrupt there is a predefined priority level and a predefined
-- interrupt vector -- see comments below.
-- -# As soon as an INTA cycle is done by the CPU (inta=1 and fetch=1) the
-- following will happen:
-- * The module will supply the interrupt vector of the highes priority
-- pending interrupt.
-- * The highest priority pending interrupt bit in the pending interrupt
-- register will be deasserted -- UNLESS the interrupts happens to trigger
-- again at the same time, in which case the pending bit will remain
-- asserted.
-- * If there are no more interrupts pending, the cpu_intr_o output will
-- be deasserted.
-- -# The CPU will have its interrupts disabled from the INTA cycle to the
-- execution of instruction EI.
-- -# The cpu_intr_o will be asserted for a single cycle.
-- -# The irq vectors are hardcoded to RST instructions (single byte calls).
--
-- The priorities and vectors are hardcoded to the following values:
--
-- irq_i(3) Priority 3 Vector RST 7
-- irq_i(2) Priority 2 Vector RST 5
-- irq_i(1) Priority 1 Vector RST 3
-- irq_i(0) Priority 0 Vector RST 1
--
-- (Priority order: 3 > 2 > 1 > 0).
--
-- This module is used in the mcu80 module, for which a basic test bench
-- exists. Both can be used as usage example.
-- The module and its application is so simple than no documentation other than
-- these comments should be necessary.
--
-- Please see the LICENSE file in the project root for license matters.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--##############################################################################
--
--##############################################################################
entity mcu80_irq is
port (
cpu_inta_i : in std_logic;
cpu_intr_o : out std_logic;
cpu_fetch_i : in std_logic;
data_we_i : in std_logic;
addr_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
irq_i : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic
);
end mcu80_irq;
--##############################################################################
--
--##############################################################################
architecture hardwired of mcu80_irq is
-- irq_pending: 1 when irq[i] is pending service
signal irq_pending_reg : std_logic_vector(3 downto 0);
-- irq_enable: 1 when irq[i] is enabled
signal irq_enable_reg : std_logic_vector(3 downto 0);
-- irq_q: registered irq input used to catch rising edges
signal irq_q : std_logic_vector(3 downto 0);
-- irq_trigger: asserted to 1 when a rising edge is detected
signal irq_trigger : std_logic_vector(3 downto 0);
signal irq_clear : std_logic_vector(3 downto 0);
signal irq_clear_mask:std_logic_vector(3 downto 0);
signal data_rd : std_logic_vector(7 downto 0);
signal vector : std_logic_vector(7 downto 0);
signal irq_level : std_logic_vector(2 downto 0);
begin
edge_detection:
for i in 0 to 3 generate
begin
irq_trigger(i) <= '1' when -- IRQ(i) is triggered when...
irq_q(i)='0' and -- ...we see a rising edge...
irq_i(i)='1' and
irq_enable_reg(i)='1' -- ...and the irq input us enabled.
else '0';
end generate edge_detection;
interrupt_pending_reg:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
irq_pending_reg <= (others => '0');
irq_q <= (others => '0');
else
irq_pending_reg <= (irq_pending_reg and (not irq_clear)) or irq_trigger;
irq_q <= irq_i;
end if;
end if;
end process interrupt_pending_reg;
with irq_level select irq_clear_mask <=
"1000" when "111",
"0100" when "101",
"0010" when "011",
"0001" when others;
irq_clear <= irq_clear_mask when cpu_inta_i='1' and cpu_fetch_i='1' else "0000";
interrupt_enable_reg:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
-- All interrupts disabled at reset
irq_enable_reg <= (others => '0');
else
if data_we_i = '1' and addr_i = '0' then
irq_enable_reg <= data_i(3 downto 0);
end if;
end if;
end if;
end process interrupt_enable_reg;
-- Interrupt priority & vector decoding
irq_level <=
"001" when irq_pending_reg(0) = '1' else
"011" when irq_pending_reg(1) = '1' else
"110" when irq_pending_reg(2) = '1' else
"111";
-- Raise interrupt request when there's any irq pending
cpu_intr_o <= '1' when irq_pending_reg /= "0000" else '0';
-- The IRQ vector is hardcoded to a RST instruction, whose opcode is
-- RST <n> ---> 11nnn111
process(clk)
begin
if clk'event and clk='1' then
if cpu_inta_i='1' and cpu_fetch_i='1' then
vector <= "11" & irq_level & "111";
end if;
end if;
end process;
-- There's only an internal register, the irq enable register, so we
-- don't need an output register mux.
data_rd <= "0000" & irq_enable_reg;
-- The mdule will output the register being read, if any, OR the irq vector.
data_o <= vector when cpu_inta_i = '1' else data_rd;
end hardwired;
|
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- TOP level of the decoder block.
-- contains: SEE_det, NRZI decode, shift_greg, timer
-- also contains a top-level state machine to coordinate all the blocks.
ENTITY decoder is
port(clk, rst, data0, data1:in STD_LOGIC; -- data0 = data+, data1 = data-
halt: in STD_LOGIC; -- Halt when intercept is in progress. No need to decode our data.
data: out STD_LOGIC_VECTOR(1 downto 0); -- 00 indicates IDLE, 01 indicated recieving valid data, 11 indicates valid data received.
inst: out STD_LOGIC_VECTOR(3 downto 0); -- decoded PID. let the other blocks know what kind of packet this is.
data_out: out STD_LOGIC_VECTOR(7 downto 0); -- output data to all other blocks
dclk: out STD_LOGIC; -- data clock. divide the device clock to data rate and resynchronize if necessary. Also let interceptor to work correctly.
eopOut : out STD_LOGIC -- OUTPUT EOP detected
);
end decoder;
architecture BLK of decoder is
component SEE_det
port(clk, rst, data0, data1: in STD_LOGIC;
EGDE, F_EGDE:OUT STD_LOGIC;
EOP: OUT STD_LOGIC
);
end component;
component NRZIdecode
port(clk, rst, data0: IN STD_LOGIC; -- data0 = data+, data1 = data-, clk goes to normal clock
enable: IN STD_LOGIC;
EOP: IN STD_LOGIC;
data_out: OUT STD_LOGIC
);
end component;
component shift_greg
port(clk, rst, shift_en, data_in: IN STD_LOGIC;
data_out: out STD_LOGIC_VECTOR(7 downto 0);
data_ready: out STD_LOGIC
);
end component;
component timer
port(clk, rst:IN STD_LOGIC;
egde_det, f_egde_det, EOP:IN STD_LOGIC;
data_clk: OUT STD_LOGIC;
--NRZI_en: OUT STD_LOGIC;
shift_en:OUT STD_LOGIC
);
end component;
-- internal signal
signal egde, fegde, act_data: STD_LOGIC;
signal data_buf: STD_LOGIC_VECTOR(7 downto 0);
signal eop: STD_LOGIC;
signal shift_enable: STD_LOGIC; -- shift data in and update NRZI decoder
signal data_ready: STD_LOGIC;
-- output signal
signal cur_sync, nxt_sync: STD_LOGIC;
signal cur_data, nxt_data: STD_LOGIC_VECTOR(1 downto 0);
signal cur_inst, nxt_inst: STD_LOGIC_VECTOR(3 downto 0);
signal cur_addr, nxt_addr: STD_LOGIC;
signal data_ready_0, data_ready_1: STD_LOGIC;
type states is (IDLE, SYNCS, WAIT1, PID, WAITADDR, TRANSA, WAITDATA, TRANSD, INTER, HALTS);
signal CS, NS: states;
begin
eopOut <= eop;
data <= cur_data;
inst <= cur_inst;
-- address <= cur_addr;
data_out <= data_buf;
seq1:process(clk, rst)
begin
if rst = '0' then
CS <= IDLE;
cur_sync <= '0';
cur_inst <= x"0";
cur_data <= "00";
cur_addr <= '0';
data_ready_0 <= '0';
data_ready_1 <= '0';
elsif (clk'event AND clk = '1') then
CS <= NS;
cur_data <= nxt_data;
cur_addr <= nxt_addr;
cur_inst <= nxt_inst;
cur_sync <= nxt_sync;
data_ready_0 <= data_ready;
data_ready_1 <= data_ready_0;
end if;
end process; -- reset - clock process.
seq2:process(CS, data_ready_0, data_ready_1, halt, data_buf, EOP)
begin
NS <= CS;
case CS is
when IDLE => -- IDLE state when nothing is on the BUS or just waiting for a non-data packet to pass.
if (data_ready_0 = '1' AND data_ready_1 = '0') then
NS <= SYNCS;
end if;
when SYNCS => -- Sync state, after receive the 1st byte , check if it is SYNC.
if data_buf = x"80" then -- sync match
NS <= WAIT1;
else
NS <= IDLE;
end if;
when WAIT1 => -- if it is SYNC, wait for the next packet.
if (data_ready_0 = '1' AND data_ready_1 = '0') then
NS <= PID;
end if;
when PID => -- the byte following should be PID. decode the PID in this state.
if (data_buf = x"87" OR data_buf = x"96" OR data_buf = x"A5" OR data_buf = x"B4") then
NS <= WAITADDR;
elsif (data_buf = x"C3" OR data_buf = x"D2" OR data_buf = x"E1" OR data_buf = x"F0") then
NS <= WAITDATA;
else
NS <= IDLE;
end if;
when WAITADDR => -- if it is a token, wait for it and give the PID out to controller
if EOP = '1' then
NS <= IDLE;
elsif (data_ready_0 = '1' AND data_ready_1 = '0') then
NS <= TRANSA;
end if;
when TRANSA => -- token received and being transfered to other blocks
if EOP = '1' then
NS <= IDLE;
else
NS <= WAITADDR; -- Unless EOP detected, otherwise keep transfer the TOKEN block.
end if;
when WAITDATA => -- if it is a datapacket, wait for data byte being transferred.
if EOP = '1' then
NS <= IDLE;
elsif halt = '1' then
NS <= HALTS; -- within data state, interceptor might work. Thus this machine will go to HALT state unless EOP found.
elsif (data_ready_0 = '1' AND data_ready_1 = '0') then
NS <= TRANSD; -- if data byte recieved, process it.
end if;
when TRANSD => -- keep receiving data byte unless EOP found.
if EOP = '1' then
NS <= IDLE;
elsif halt = '1' then
NS <= HALTS;
else
NS <= WAITDATA;
end if;
when HALTS => -- HALT the state machine while interceptor is working.
if EOP = '1' then
NS <= IDLE;
end if;
when others =>
NS <= IDLE;
end case;
end process;
seq3: process(CS, data_buf)
begin
case CS is
when IDLE =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
when SYNCS =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '1';
nxt_inst <= x"0";
when WAIT1 =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
when PID =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= data_buf(4) & data_buf(5) & data_buf(6) & data_buf(7); -- USB transfer data LSB first, so re-format the PID.
when WAITADDR =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
when TRANSA =>
nxt_data <= "00";
nxt_addr <= '1'; -- indicate TOKED is being transferred
nxt_sync <= '0';
nxt_inst <= x"0";
when WAITDATA =>
nxt_data <= "01"; -- indicate getting a valid data is.
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
when TRANSD =>
nxt_data <= "11"; -- indicate the data is ready to transfer out.
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
when HALTS =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
when others =>
nxt_data <= "00";
nxt_addr <= '0';
nxt_sync <= '0';
nxt_inst <= x"0";
end case;
end process;
part2:SEE_det
port map(
clk => clk,
rst => rst,
data0 => data0,
data1 => data1,
EGDE => egde,
F_EGDE => fegde,
EOP => eop
);
part3:NRZIdecode
port map(
clk => clk,
rst => rst,
data0 => data0,
enable => shift_enable,
EOP => eop,
data_out => act_data
);
part4:shift_greg
port map(
clk => clk,
rst => rst,
shift_en => shift_enable,
data_in => act_data,
data_out => data_buf,
data_ready => data_ready
);
part5:timer
port map(
clk => clk,
rst => rst,
egde_det => egde,
f_egde_det => fegde,
EOP => eop,
data_clk => dclk,
shift_en => shift_enable
);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic;
Ttimer : out std_logic_vector( 0 to 31)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
signal timer : std_logic_vector(0 to 31);
type timer_state_machine is ( idle,counting);
signal timer_cs : timer_state_machine :=idle;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
WHILE_LOOP_1,
WHILE_LOOP_2,
WHILE_LOOP_3,
WHILE_LOOP_4,
WHILE_LOOP_4a,
WHILE_LOOP_5,
WHILE_LOOP_6,
WHILE_LOOP_7,
WHILE_LOOP_8,
WHILE_LOOP_9,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_WHILE_LOOP_3 : std_logic_vector(0 to 15) := x"0103";
constant U_WHILE_LOOP_6 : std_logic_vector(0 to 15) := x"0106";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal xAddr, xAddr_next : std_logic_vector(0 to 31);
signal yAddr, yAddr_next : std_logic_vector(0 to 31);
signal zAddr, zAddr_next : std_logic_vector(0 to 31);
signal xVal, xVal_next : std_logic_vector(0 to 31);
signal yVal, yVal_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
Ttimer <= timer;
timer_process: process(clock)
begin
if (clock'event and (clock = '1')) then
case timer_cs is
when idle=>
timer <= (others =>'0');
if current_state= FUNCTION_START then
timer_cs <= counting;
end if;
when counting =>
timer <= timer + x"00000001";
if (current_state= FUNCTION_RESET or current_state=FUNCTION_EXIT_1) then
timer_cs <= idle;
end if;
when others =>
timer <= (others =>'0');
timer_cs <= idle;
end case;
end if;
end process timer_process;
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, exist) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
index <= index_next;
xAddr <= xAddr_next;
yAddr <= yAddr_next;
zAddr <= zAddr_next;
xVal <= xVal_next;
yVal <= yVal_next;
mutexAddr <= mutexAddr_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_WHILE_LOOP_3 =>
current_state <= WHILE_LOOP_3;
when U_WHILE_LOOP_6 =>
current_state <= WHILE_LOOP_6;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
index_next <= index;
xAddr_next <= xAddr;
yAddr_next <= yAddr;
zAddr_next <= zAddr;
xVal_next <= xVal;
yVal_next <= yVal;
count_next <= count;
mutexAddr_next <= mutexAddr ;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, xAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= SETUP_3;
when SETUP_3 =>
-- Read the value of xAddr
xAddr_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, yAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= SETUP_4;
when SETUP_4 =>
-- Read the value of yAddr
yAddr_next <= toUser_value;
-- Initiate the reading of the fifth variable in the struct, zAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= SETUP_5;
when SETUP_5 =>
-- Read the value of zAddr
zAddr_next <= toUser_value;
-- Initiate the reading of the sixth variable in the struct, mutexAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= SETUP_6;
when SETUP_6 =>
-- Read the value of mutexAddr
mutexAddr_next <= toUser_value;
next_state <=WHILE_LOOP_1;
new_request <= '0';
when WHILE_LOOP_1 =>
-- Lock the mutex, push the address of the mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_2;
when WHILE_LOOP_2 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_3;
next_state <= WAIT_STATE;
when WHILE_LOOP_3 =>
-- We now have a lock on index, initiate the read on index
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4;
when WHILE_LOOP_4 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000004";
thrd2intrfc_value <= toUser_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4a;
when WHILE_LOOP_4a =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_5;
when WHILE_LOOP_5 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_6;
next_state <= WAIT_STATE;
when WHILE_LOOP_6 =>
-- Check to see if the index is over the size
if ( index < size ) then
-- More work to be done
-- Initiate the read of the X matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= xAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_7;
else
-- we may exit
next_state <= FUNCTION_EXIT_1;
new_request <= '0';
end if;
when WHILE_LOOP_7 =>
xVal_next <= ToUser_value;
-- Initiate the read of the Y matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= yAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_8;
when WHILE_LOOP_8 =>
yVal_next <= ToUser_value;
next_state <= WHILE_LOOP_9;
new_request <= '0';
when WHILE_LOOP_9 =>
-- Initiate the writing of the Z matrix
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= zAddr + (index(2 to 31) & "00");
thrd2intrfc_value <= xVal + yVal;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_1;
-- Increment count
count_next <= count + x"00000001";
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= timer;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_390 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_390;
architecture augh of add_390 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_390 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_390;
architecture augh of add_390 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity antonella is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end antonella;
architecture beh of antonella is
type stati is (idle, getOP, codOP, exeLD, exeAND, exeADD);
type memory is array (0 to 1) of std_logic_vector(15 downto 0);
signal st : stati;
signal REG : memory;
signal OPE : std_logic_vector(1 downto 0); -- sto salvando su un registro OP poichè assumo che in ingresso il valore di OP sia presente solo per un ciclo di clock
signal enOP, enLD, enAND, enADD : std_logic;
-- signal enCOD : std_logic; non serve a niente, vedi segnali di controllo sotto :D
signal counter : integer range 2 downto 0;
function next_state (st: stati; start : std_logic; ope : std_logic_vector(1 downto 0); counter : integer range 2 downto 0)
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then nxt := getOP;
else nxt := idle;
end if;
when getOP =>
nxt := codOP;
when codOP =>
case ope is
when "00" | "01" => nxt := exeLD;
when "10" => nxt := exeAND;
when others => nxt := exeADD;
end case;
when exeLD =>
nxt := idle;
when exeAND =>
if counter < 1 then nxt := exeAND;
else nxt := idle;
end if;
when exeADD =>
if counter < 2 then nxt := exeADD;
else nxt := idle;
end if;
end case;
return nxt;
end next_state;
begin
-- CU
process (clk) is
begin
if clk'event and clk = '0' then
st <= next_state(st, start, ope, counter);
end if;
end process;
-- State Control Bits
enOP <= '1' when st = getOP else '0';
-- enCOD <= '1' when st = codOP else '0'; non serve a niente, poichè la decodifica la faccio nella funct next_state
enLD <= '1' when st = exeLD else '0';
enAND <= '1' when st = exeAND else '0';
enADD <= '1' when st = exeADD else '0';
-- DATAPATH
process (clk) is
begin
if enOP = '1' then
ope <= op;
counter <= 0;
end if;
if enLD = '1' then
REG(conv_integer(ope)) <= din;
end if;
if enAND = '1' then
if counter = 1 then
REG(1) <= REG(0) and REG(1);
else
counter <= counter + 1;
end if;
end if;
if enADD = '1' then
if counter = 2 then
res <= REG(0) + REG(1);
else
counter <= counter +1;
end if;
end if;
if enLD = '1' or (enAND = '1' and counter = 1) or (enADD = '1' and counter = 2) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end beh; |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity antonella is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end antonella;
architecture beh of antonella is
type stati is (idle, getOP, codOP, exeLD, exeAND, exeADD);
type memory is array (0 to 1) of std_logic_vector(15 downto 0);
signal st : stati;
signal REG : memory;
signal OPE : std_logic_vector(1 downto 0); -- sto salvando su un registro OP poichè assumo che in ingresso il valore di OP sia presente solo per un ciclo di clock
signal enOP, enLD, enAND, enADD : std_logic;
-- signal enCOD : std_logic; non serve a niente, vedi segnali di controllo sotto :D
signal counter : integer range 2 downto 0;
function next_state (st: stati; start : std_logic; ope : std_logic_vector(1 downto 0); counter : integer range 2 downto 0)
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then nxt := getOP;
else nxt := idle;
end if;
when getOP =>
nxt := codOP;
when codOP =>
case ope is
when "00" | "01" => nxt := exeLD;
when "10" => nxt := exeAND;
when others => nxt := exeADD;
end case;
when exeLD =>
nxt := idle;
when exeAND =>
if counter < 1 then nxt := exeAND;
else nxt := idle;
end if;
when exeADD =>
if counter < 2 then nxt := exeADD;
else nxt := idle;
end if;
end case;
return nxt;
end next_state;
begin
-- CU
process (clk) is
begin
if clk'event and clk = '0' then
st <= next_state(st, start, ope, counter);
end if;
end process;
-- State Control Bits
enOP <= '1' when st = getOP else '0';
-- enCOD <= '1' when st = codOP else '0'; non serve a niente, poichè la decodifica la faccio nella funct next_state
enLD <= '1' when st = exeLD else '0';
enAND <= '1' when st = exeAND else '0';
enADD <= '1' when st = exeADD else '0';
-- DATAPATH
process (clk) is
begin
if enOP = '1' then
ope <= op;
counter <= 0;
end if;
if enLD = '1' then
REG(conv_integer(ope)) <= din;
end if;
if enAND = '1' then
if counter = 1 then
REG(1) <= REG(0) and REG(1);
else
counter <= counter + 1;
end if;
end if;
if enADD = '1' then
if counter = 2 then
res <= REG(0) + REG(1);
else
counter <= counter +1;
end if;
end if;
if enLD = '1' or (enAND = '1' and counter = 1) or (enADD = '1' and counter = 2) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end beh; |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
s_open_i : in std_ulogic;
s_open_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TRFSM1 is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
Out10_o : out std_logic;
Out11_o : out std_logic;
Out12_o : out std_logic;
Out13_o : out std_logic;
Out14_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end TRFSM1;
architecture struct of TRFSM1 is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(14 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 15,
StateWidth => 6,
UseResetRow => 0,
NumRows0 => 10,
NumRows1 => 20,
NumRows2 => 6,
NumRows3 => 6,
NumRows4 => 4,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
Out10_o <= Output_s(10);
Out11_o <= Output_s(11);
Out12_o <= Output_s(12);
Out13_o <= Output_s(13);
Out14_o <= Output_s(14);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/29/2017 11:06:31 AM
-- Design Name:
-- Module Name: Decoder2x4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder3x8 is Port ( D_IN : in STD_LOGIC_VECTOR(3 downto 0);
nD_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end Decoder3x8;
architecture Behavioral of Decoder3x8 is begin
process (D_IN) begin
case D_IN is
when "000" => nD_OUT <= "11111110";
when "001" => nD_OUT <= "11111101";
when "010" => nD_OUT <= "11111011";
when "011" => nD_OUT <= "11110111";
when "100" => nD_OUT <= "11101111";
when "101" => nD_OUT <= "11011111";
when "110" => nD_OUT <= "10111111";
when "111" => nD_OUT <= "01111111";
when others => nD_OUT <= "00000000";
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package pwm_pkg is
component pwm is
generic(
sys_clk : INTEGER := 50_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 100_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 8; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
port(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0) --pwm inverse outputs
);
end component;
end package;
|
-- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- The code is inspired by Xilinx example rams_04.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 16 16*RAM16X1S
-- 5 16 - 32 16*RAM32X1S
-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
architecture syn of ram_1swar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDR))) <= DI;
end if;
end if;
end process proc_clk;
DO <= RAM(to_integer(unsigned(ADDR)));
end syn;
|
-- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- The code is inspired by Xilinx example rams_04.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 16 16*RAM16X1S
-- 5 16 - 32 16*RAM32X1S
-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
architecture syn of ram_1swar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDR))) <= DI;
end if;
end if;
end process proc_clk;
DO <= RAM(to_integer(unsigned(ADDR)));
end syn;
|
-- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE STD.textio.ALL;
PACKAGE alt_vipvfr131_common_package IS
CONSTANT SIMULATION_ON : INTEGER := 1;
CONSTANT SIMULATION_OFF : INTEGER := 0;
CONSTANT OPTIMIZED_ON : INTEGER := 1;
CONSTANT OPTIMIZED_OFF : INTEGER := 0;
CONSTANT FAMILY_NONE : INTEGER := 0;
CONSTANT FAMILY_STRATIX : INTEGER := 10;
CONSTANT FAMILY_STRATIXII : INTEGER := 11;
CONSTANT FAMILY_STRATIXIII : INTEGER := 12;
CONSTANT FAMILY_STRATIXIV : INTEGER := 13;
CONSTANT FAMILY_CYCLONE : INTEGER := 30;
CONSTANT FAMILY_CYCLONEII : INTEGER := 31;
CONSTANT FAMILY_CYCLONEIII : INTEGER := 32;
CONSTANT FAMILY_CYCLONELPS : INTEGER := 33;
CONSTANT FAMILY_HARDCOPYII : INTEGER := 40;
CONSTANT FAMILY_HARDCOPYIII : INTEGER := 41;
CONSTANT ALT_MEM_MODE_AUTO : INTEGER := -1;
CONSTANT ALT_MEM_MODE_LE : INTEGER := 0;
CONSTANT ALT_MEM_MODE_M512 : INTEGER := 1;
CONSTANT ALT_MEM_MODE_M4K : INTEGER := 2;
CONSTANT ALT_MEM_MODE_MRAM : INTEGER := 3;
CONSTANT ALT_SHIFT_MODE_LOGICAL : INTEGER := 0;
CONSTANT ALT_SHIFT_MODE_ARITH : INTEGER := 1;
CONSTANT ALT_SHIFT_MODE_ROTATE : INTEGER := 2;
CONSTANT ALT_SHIFT_DIREC_LEFT : INTEGER := 0;
CONSTANT ALT_SHIFT_DIREC_RIGHT : INTEGER := 1;
CONSTANT ALT_SHIFT_DIREC_BOTH : INTEGER := 2;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
function wide_enough_for(max : integer) return integer;
function two_to_the_power(v : integer) return integer;
function dead_bits(b : integer) return std_logic_vector;
function maximum(a, b : integer) return integer;
function minimum(a, b : integer) return integer;
function calculate_be_width(be_used : boolean; data_width : integer) return integer;
function calculate_be_width(be_used : integer; data_width : integer) return integer;
function calculate_be_width(data_width : integer) return integer;
function family_string(f : integer) return string;
function to_string(slv : std_logic_vector) return string;
function boolean_to_int(value : boolean) return integer;
COMPONENT alt_vipvfr131_common_avalon_mm_master IS
GENERIC (
-- NAME : STRING := "";
-- OPTIMIZED : INTEGER := OPTIMIZED_ON;
-- FAMILY : INTEGER := FAMILY_STRATIX;
ADDR_WIDTH : INTEGER := 16;
DATA_WIDTH : INTEGER := 16;
-- BYTEENABLE_WIDTH : INTEGER := 2;
-- BYTEENABLE_USED : INTEGER := 1;
READ_USED : INTEGER := 1;
WRITE_USED : INTEGER := 1;
-- CLOCKS_ARE_SYNC : INTEGER := 0;
-- ADDRESS_GROUP : integer := 1;
-- INTERRUPT_USED : INTEGER := 1;
-- INTERRUPT_WIDTH : INTEGER := 8
-- new:
MAX_BURST_LENGTH : INTEGER := 1024;
READ_FIFO_DEPTH : INTEGER := 8;
WRITE_FIFO_DEPTH : INTEGER := 8;
COMMAND_FIFO_DEPTH : INTEGER := 8;
WRITE_TARGET_BURST_SIZE : INTEGER := 5;
READ_TARGET_BURST_SIZE : INTEGER := 5;
BURST_WIDTH : INTEGER := 6;
CLOCKS_ARE_SAME : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
command : IN STD_LOGIC;
is_write_not_read : IN STD_LOGIC;
is_burst : IN STD_LOGIC;
burst_length : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- addr_en : IN STD_LOGIC := '0';
writedata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
write : IN STD_LOGIC := '0';
-- byteenable : IN STD_LOGIC_VECTOR(BYTEENABLE_WIDTH-1 DOWNTO 0) := (OTHERS=>'1');
-- byteenable_en : IN STD_LOGIC := '0';
readdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
read : IN STD_LOGIC := '0';
-- ready : OUT STD_LOGIC;
stall_command : OUT STD_LOGIC;
stall_out : OUT STD_LOGIC;
stall_in : OUT STD_LOGIC;
-- activeirqs : OUT STD_LOGIC_VECTOR(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
av_address : OUT STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) ;
av_writedata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
-- av_byteenable : OUT STD_LOGIC_VECTOR(BYTEENABLE_WIDTH-1 DOWNTO 0);
av_write : OUT STD_LOGIC;
av_read : OUT STD_LOGIC;
av_clock : IN STD_LOGIC;
-- av_reset : IN STD_LOGIC := '0';
av_readdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
av_readdatavalid : IN STD_LOGIC;
av_waitrequest : IN STD_LOGIC := '0';
av_burstcount : OUT STD_LOGIC_VECTOR(BURST_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
-- av_interrupt : IN STD_LOGIC_VECTOR(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_master_fifo IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
ADDR_WIDTH : INTEGER := 16;
DATA_WIDTH : INTEGER := 16;
BYTEENABLE_WIDTH : INTEGER := 2;
BYTEENABLE_USED : INTEGER := 1;
READ_USED : INTEGER := 1;
WRITE_USED : INTEGER := 1;
OLD_STYLE : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
addr_en : IN STD_LOGIC := '0';
wdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
wdata_en : IN STD_LOGIC := '0';
rdata_en : IN STD_LOGIC := '0';
byteenable : IN STD_LOGIC_VECTOR( BYTEENABLE_WIDTH-1 DOWNTO 0) := (OTHERS=>'1');
byteenable_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
ready : OUT STD_LOGIC;
stall : OUT STD_LOGIC;
av_address : OUT STD_LOGIC_VECTOR( ADDR_WIDTH-1 DOWNTO 0) ;
av_writedata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
av_byteenable : OUT STD_LOGIC_VECTOR( BYTEENABLE_WIDTH-1 DOWNTO 0);
av_write : OUT STD_LOGIC;
av_read : OUT STD_LOGIC;
av_clock : IN STD_LOGIC;
av_reset : IN STD_LOGIC := '0';
av_readdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0):= (OTHERS=>'0');
av_readdatavalid : IN STD_LOGIC := '0';
av_waitrequest : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_mem_slave IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DEPTH : INTEGER := -1;
INTERRUPT_USED : INTEGER := 1;
DELAY_SLOTS : INTEGER := 0;
LATENCY : INTEGER := 1;
MODE : INTEGER := ALT_MEM_MODE_AUTO;
CLOCKS_ARE_SYNC : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
setirq : IN STD_LOGIC := '0';
setirq_en : IN STD_LOGIC := '0';
irqactive : IN STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_waitrequest : OUT STD_LOGIC := '0';
av_interrupt : OUT STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_st_credit_user IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
ADDR_WIDTH : INTEGER := 32;
DATA_WIDTH : INTEGER := 32;
CREDIT_WIDTH : INTEGER := 10;
CREDIT_INCREMENT : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
hascredit : OUT STD_LOGIC;
getcredit : IN STD_LOGIC := '0';
getcredit_en : IN STD_LOGIC := '0';
trygetcredit : IN STD_LOGIC := '0';
trygetcredit_en: IN STD_LOGIC := '0';
gotcredit : OUT STD_LOGIC;
stall : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR( ADDR_WIDTH-1 DOWNTO 0);
waitrequest : IN STD_LOGIC := '0';
readdatavalid : IN STD_LOGIC := '0';
readdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0):= (OTHERS=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_st_input IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
WIDTH : integer := 16;
END_PACKET_USED : integer := 0;
SYM_PER_BEAT : integer := 0;
READY_LATENCY : integer := 1
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
stall : out std_logic;
dataavail : out std_logic;
datavalid : out std_logic;
rdata : out std_logic_vector(WIDTH - 1 downto 0);
takeb : in std_logic;
takeb_en : in std_logic;
takenb : in std_logic;
takenb_en : in std_logic;
expecteop : in std_logic := '1';
eop : out std_logic;
ready : out std_logic;
valid : in std_logic := '1';
data : in std_logic_vector(width-1 downto 0);
startofpacket : in std_logic := '0';
endofpacket : in std_logic := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_st_output IS
GENERIC (
NAME : STRING := "";
WIDTH : INTEGER := 16;
READY_USED : INTEGER := 1;
END_PACKET_USED : INTEGER := 0;
SYM_PER_BEAT : integer := 0;
READY_LATENCY : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
spaceavail : OUT STD_LOGIC;
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
takeb : IN STD_LOGIC := '0';
takeb_en : IN STD_LOGIC := '0';
takenb : IN STD_LOGIC := '0';
takenb_en : IN STD_LOGIC := '0';
eop : IN STD_LOGIC := '0';
seteop : IN STD_LOGIC := '0';
seteop_en : IN STD_LOGIC := '0';
stall : OUT STD_LOGIC;
ready : IN STD_LOGIC := '1';
valid : OUT STD_LOGIC;
data : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
startofpacket : OUT STD_LOGIC;
endofpacket : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_select IS
GENERIC (
NAME : STRING := "";
WIDTH_D : INTEGER := 16;
WIDTH_Q : INTEGER := 16;
SELECT_LOW : INTEGER := 0;
SIGN_EXTEND : INTEGER := 1
);
PORT (
d : IN STD_LOGIC_VECTOR( WIDTH_D-1 DOWNTO 0) := (others =>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH_Q-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_stack IS
GENERIC (
NAME : STRING := "";
DEPTH : INTEGER := 16;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
pushNpop : IN STD_LOGIC := '0';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_trigger_to_synced_pulse IS
port (
signal reset : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal sync_clk : IN STD_LOGIC;
signal trigger : IN STD_LOGIC;
signal return_pulse : IN STD_LOGIC;
signal synced_pulse : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_loadable_pc IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PROGRAM_FILE : STRING := "program.mif";
PROGRAM_TRACE: STRING := "program.trace";
LATENCY : INTEGER := 3;
PC_WIDTH : INTEGER := 16;
PC_NUM_WORDS : INTEGER := 256;
PCW_WIDTH : INTEGER := 32;
PCW_ROUND : INTEGER := 0;
TTA_WIDTH : INTEGER := 16;
TTA_NUM_WORDS : INTEGER := 256;
TTAW_WIDTH : INTEGER := 32;
AV_WIDTH : INTEGER := 15;
AV_NUM_WORDS : INTEGER := 128;
AVW_WIDTH : INTEGER := 32
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
reset_req : OUT STD_LOGIC;
ena : IN STD_LOGIC := '1';
pcw : OUT STD_LOGIC_VECTOR( PCW_WIDTH-1 DOWNTO 0);
pc : OUT STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0);
stall : OUT STD_LOGIC;
nextpc : IN STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
usenextpc : IN STD_LOGIC := '0';
usenextpc_en : IN STD_LOGIC := '0';
hold : IN STD_LOGIC := '0';
hold_en : IN STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( AV_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( AVW_WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( AVW_WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_byteenable : IN STD_LOGIC_VECTOR( (AVW_WIDTH/8)-1 DOWNTO 0) := (others=>'1')
);
END COMPONENT;
COMPONENT tta_x_addwithsload IS
GENERIC (
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
L : INTEGER
);
PORT (
clk, reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
sreset : IN STD_LOGIC := '0';
sload : IN STD_LOGIC;
loadval_in : IN UNSIGNED(L-1 DOWNTO 0);
doAddnSub : IN STD_LOGIC := '1';
addL_in : IN UNSIGNED(L-1 DOWNTO 0);
addR_in : IN UNSIGNED(L-1 DOWNTO 0);
sum_out : OUT UNSIGNED(L-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_acounter IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_en : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT tta_x_au IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
LATENCY : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '0';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
c : IN STD_LOGIC := '0';
c_en : IN STD_LOGIC := '0';
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
l_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
S : OUT STD_LOGIC;
nS : OUT STD_LOGIC;
CC : OUT STD_LOGIC;
nCC : OUT STD_LOGIC;
sclr : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_16_16 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_16_16_cii IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_36_16 IS
PORT
(
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_36_16_cii IS
PORT
(
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_bshift IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
SEL_WIDTH : INTEGER := 2;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
sel : IN STD_LOGIC_VECTOR( SEL_WIDTH-1 DOWNTO 0) := (others=>'0');
arithNlogic : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sclr_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_channel IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WAIT_STATES : INTEGER := 0;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
d_ena : IN STD_LOGIC := '1';
d_ready: OUT STD_LOGIC;
d_stall: OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_ready: OUT STD_LOGIC;
q_en : IN STD_LOGIC := '0';
q_ena : IN STD_LOGIC := '1';
q_stall: OUT STD_LOGIC
);
END COMPONENT;
COMPONENT tta_x_cmult IS
generic (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DELAY_SLOTS : integer := 2;
WIDTH : integer := 32;
USE_COMPLEX_INPUT_PORTS : STRING := "TRUE"
);
port (
clock : in std_logic;
ena : in std_logic := '1';
reset : in std_logic;
aR_en : in std_logic := '0';
aR: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
aI: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
bR: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
bI: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
a_en : in std_logic := '0';
a: in std_logic_vector(WIDTH-1 downto 0) := (others=>'0');
b: in std_logic_vector(WIDTH-1 downto 0) := (others=>'0');
q : out std_logic_vector((2*WIDTH)-1 downto 0);
q_hi: out std_logic_vector(WIDTH-1 downto 0);
q_lo: out std_logic_vector(WIDTH-1 downto 0);
qs : out std_logic_vector((2*WIDTH)-1 downto 0);
qs_hi: out std_logic_vector(WIDTH-1 downto 0);
qs_lo: out std_logic_vector(WIDTH-1 downto 0);
qR: out std_logic_vector(WIDTH-1 downto 0);
qI: out std_logic_vector(WIDTH-1 downto 0);
qR_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qI_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qR_lo: out std_logic_vector((WIDTH/2)-1 downto 0);
qI_lo: out std_logic_vector((WIDTH/2)-1 downto 0);
qsR: out std_logic_vector(WIDTH-1 downto 0);
qsI: out std_logic_vector(WIDTH-1 downto 0);
qsR_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qsI_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qsR_lo: out std_logic_vector((WIDTH/2)-1 downto 0);
qsI_lo: out std_logic_vector((WIDTH/2)-1 downto 0)
);
END COMPONENT;
COMPONENT tta_x_combine_vec_vec IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
A_WIDTH : INTEGER := 16;
B_WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC_VECTOR( A_WIDTH-1 DOWNTO 0) := (others=>'0');
b : IN STD_LOGIC_VECTOR( B_WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( A_WIDTH+B_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_constant IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
VALUE : INTEGER := 0
);
PORT (
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_constant_accumulator IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
CSEL : INTEGER := 0;
CNSEL : INTEGER := 1;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
l_en : IN STD_LOGIC := '0';
vsel : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
S : OUT STD_LOGIC;
nS : OUT STD_LOGIC;
sclr : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_dmem IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
Aaddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Aaddr_en : IN STD_LOGIC := '0';
Ardata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
Awdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
Awdata_en : IN STD_LOGIC := '0';
Baddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Baddr_en : IN STD_LOGIC := '0';
Brdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
Bwdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
Bwdata_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_hdmem IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 8;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
Aaddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Aaddr_en : IN STD_LOGIC := '0';
Ardata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
Awdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
Awdata_en : IN STD_LOGIC := '0';
Baddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Baddr_en : IN STD_LOGIC := '0';
Brdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_immed IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
value : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_immed_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX
);
PORT (
value : IN STD_LOGIC := '0';
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT tta_x_mac IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH_2 : INTEGER := 32;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR( (2*WIDTH)-1 DOWNTO 0);
qs_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs : OUT STD_LOGIC_VECTOR( (2*WIDTH)-1 DOWNTO 0);
mulNmac : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_mod_counter IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
MODULO : INTEGER := 66;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC ;
ena : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0' ;
cnt : IN STD_LOGIC := '0';
cnt_en : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
sclr_en : IN STD_LOGIC := '0';
d : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others => '0');
d_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_mult IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR( WIDTH*2-1 DOWNTO 0);
qs_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs : OUT STD_LOGIC_VECTOR( WIDTH*2-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_register IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
d_en : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT tta_x_register3 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
b_en : IN STD_LOGIC := '0';
c : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
c_en : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_rshift IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
logicalNarithmetic : IN STD_LOGIC := '1';
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
l_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
d_en : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT tta_x_smem IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_smem_av IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DEPTH : INTEGER := -1;
DELAY_SLOTS : INTEGER := 0;
MODE : INTEGER := ALT_MEM_MODE_AUTO;
ASYNC : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_waitrequest : OUT STD_LOGIC := '0';
test_writetog : OUT STD_LOGIC;
test_writeack : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_smem_av_db IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
setHalf : IN STD_LOGIC := '0';
setHalf_en : IN STD_LOGIC := '0';
getHalf : OUT STD_LOGIC ;
machineHalf : OUT STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_addsubcarry IS
GENERIC (
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
L : INTEGER
);
PORT (
clk, reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
sreset : IN STD_LOGIC := '0';
sload : IN STD_LOGIC;
loadval_in : IN UNSIGNED(L-1 DOWNTO 0);
doAddnSub : IN STD_LOGIC := '1';
addL_in : IN UNSIGNED(L-1 DOWNTO 0);
addR_in : IN UNSIGNED(L-1 DOWNTO 0);
sum_out : OUT UNSIGNED(L-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_atlantic_reporter IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
ISSIGNED : INTEGER := 1;
CONSTANT WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
valid : IN STD_LOGIC := '1';
ready : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_au IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
LATENCY : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_bursting_master_fifo IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
ADDR_WIDTH : integer := 16;
DATA_WIDTH : integer := 16;
READ_USED : integer := 1;
WRITE_USED : integer := 1;
CMD_FIFO_DEPTH : integer := 8;
RDATA_FIFO_DEPTH : integer := 8;
WDATA_FIFO_DEPTH : integer := 8;
WDATA_TARGET_BURST_SIZE : integer := 5;
RDATA_TARGET_BURST_SIZE : integer := 5;
CLOCKS_ARE_SYNC : integer := 1;
ADDRESS_GROUP : integer := 1;
BYTEENABLE_USED : integer := 1;
LEN_BE_WIDTH : integer := 11;
BURST_WIDTH : integer := 6;
INTERRUPT_USED : INTEGER := 1;
INTERRUPT_WIDTH : INTEGER := 8
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
ready : out std_logic;
stall : out std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
write : in std_logic := '0';
burst : in std_logic := '0';
len_be : in std_logic_vector(LEN_BE_WIDTH-1 downto 0) := (others => '0');
cenable : in std_logic;
cenable_en : in std_logic;
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
wenable : in std_logic;
wenable_en : in std_logic := '0';
rdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
renable : in std_logic := '0';
renable_en : in std_logic := '0';
activeirqs : out std_logic_vector(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
av_address : out std_logic_vector(ADDR_WIDTH-1 downto 0);
av_burstcount : out std_logic_vector(BURST_WIDTH-1 downto 0);
av_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
av_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
av_write : out std_logic;
av_read : out std_logic;
av_clock : in std_logic;
av_reset : in std_logic := '0';
av_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_interrupt : in std_logic_vector(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_raw_slave IS
GENERIC (
NAME : STRING := "";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
READ_USED : INTEGER := 1;
WRITE_USED : INTEGER := 1;
INTERRUPT_USED : INTEGER := 1;
CLOCKS_ARE_SYNC : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
stall : OUT STD_LOGIC;
waitaccess : IN STD_LOGIC := '0';
waitaccess_en: IN STD_LOGIC := '0';
finish : IN STD_LOGIC := '0';
finish_en : IN STD_LOGIC := '0';
hasaccess : OUT STD_LOGIC;
isread : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
rdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
setirq : IN STD_LOGIC := '0';
setirq_en : IN STD_LOGIC := '0';
setirq_ena : IN STD_LOGIC := '1';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_waitrequest : OUT STD_LOGIC := '0';
av_interrupt : OUT STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_clock_reset IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PERIOD : TIME := 10 ns
);
PORT (
clock : OUT STD_LOGIC;
reset : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_cmp IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
b : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
sign : IN STD_LOGIC :='0';
equals : IN STD_LOGIC := '1';
less : IN STD_LOGIC := '0';
invert : IN STD_LOGIC := '0';
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_debug IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
LATENCY : INTEGER := 1;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '0';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_exit IS
GENERIC (
NAME : STRING := "";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
return_code : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
return_code_en : IN STD_LOGIC := '0';
test_stopped : OUT STD_LOGIC;
test_return_code : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fifo IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
WIDTH : integer := 16;
READ_TRIGGER_TO_READ_DATA_CHANGE_CYCLES : integer := 2;
DEPTH : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic := '0';
ena_read : in std_logic := '1';
stall_read : out std_logic := '0';
readnext : in std_logic := '0';
readnext_en : in std_logic := '0';
rdata : out std_logic_vector(width - 1 downto 0);
ena_write : in std_logic := '1';
stall_write : out std_logic := '0';
writenext : in std_logic := '0';
writenext_en : in std_logic := '0';
wdata : in std_logic_vector(width - 1 downto 0) := (others => '0');
dataavail : out std_logic;
spaceavail : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fifo_paged IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 8;
PAGE_SIZE : INTEGER := 8;
PAGES : INTEGER := 4;
LOG2_PAGES : INTEGER := 2;
FULL_BIDIR : INTEGER := 1;
SINK_ACTIVE_PAGES : INTEGER := 1;
SOURCE_ACTIVE_PAGES : INTEGER := 1;
FULL_AT_START : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
a_ena : IN STD_LOGIC := '1';
a_addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
a_rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
a_wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_wdataen : IN STD_LOGIC := '0';
a_wdataen_en : IN STD_LOGIC := '0';
a_takeb : IN STD_LOGIC := '0';
a_takeb_en : IN STD_LOGIC := '0';
a_takenb : IN STD_LOGIC := '0';
a_takenb_en : IN STD_LOGIC := '0';
a_returnnb : IN STD_LOGIC := '0';
a_returnnb_en : IN STD_LOGIC := '0';
a_pagesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others=>'0');
a_pagesel_en : IN STD_LOGIC := '0';
a_page_to_take : OUT STD_LOGIC;
a_stall : OUT STD_LOGIC;
b_ena : IN STD_LOGIC := '1';
b_addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
b_rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
b_wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
b_wdataen : IN STD_LOGIC := '0';
b_wdataen_en : IN STD_LOGIC := '0';
b_takeb : IN STD_LOGIC := '0';
b_takeb_en : IN STD_LOGIC := '0';
b_takenb : IN STD_LOGIC := '0';
b_takenb_en : IN STD_LOGIC := '0';
b_returnnb : IN STD_LOGIC := '0';
b_returnnb_en : IN STD_LOGIC := '0';
b_pagesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others=>'0');
b_pagesel_en : IN STD_LOGIC := '0';
b_page_to_take : OUT STD_LOGIC;
b_stall : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fifo_usedw_calculator IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 9;
READ_TO_WRITE_DELAY : integer := 3;
WRITE_TO_READ_DELAY : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE
);
port
(
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_dp_l7 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_dp_l8 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_sp_l7 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_sp_l8 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_au IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 32;
LATENCY : INTEGER := 5
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_cmp IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
LATENCY : INTEGER := 7;
WIDTH : INTEGER := 32
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_mult IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 32;
LATENCY : INTEGER := 5;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '0';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_general_fifo IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 4;
CLOCKS_ARE_SAME : boolean := TRUE;
DEVICE_FAMILY : string;
RDREQ_TO_Q_LATENCY : integer := 1
);
port
(
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gpi IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATATYPE : STRING := "";
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
gpio_in : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_en: IN STD_LOGIC := '0';
wait_change: IN STD_LOGIC := '0';
wait_change_en: IN STD_LOGIC := '0';
stall : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gpio IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATATYPE : STRING := "";
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '1';
enable_en : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_en: IN STD_LOGIC := '0';
wait_change: IN STD_LOGIC := '0';
wait_change_en: IN STD_LOGIC := '0';
stall : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gpo IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATATYPE : STRING := "";
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '1';
enable_en : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
gpio_out : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gray_clock_crosser IS
generic
(
WIDTH : integer := 8
);
port
(
inclock : in std_logic;
outclock : in std_logic;
inena : in std_logic;
outena : in std_logic;
reset : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_logic_fifo IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 3
);
port
(
clock : in std_logic;
rdena : in std_logic := '1';
wrena : in std_logic := '1';
reset : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_lu IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
andNor : IN STD_LOGIC := '0';
invert : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_lu_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC := '0';
b : IN STD_LOGIC := '0';
andNor : IN STD_LOGIC := '0';
invert : IN STD_LOGIC := '0';
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mac IS
GENERIC (
NAME : STRinG := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
WIDTHOUT : INTEGER := 32;
LATENCY : INTEGER := 3
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
signa : IN STD_LOGIC := '0';
signb : IN STD_LOGIC := '0';
mulNmac : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTHOUT-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mem IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
INIT_CONTENTS : STRING := "UNUSED";
DATA_WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DEPTH : INTEGER := 16;
LATENCY : INTEGER := 2;
READ_PORTS : INTEGER := 0;
WRITE_PORTS : INTEGER := 0;
READ_WRITE_PORTS : INTEGER := 2;
MODE : INTEGER := ALT_MEM_MODE_AUTO;
ALLOW_MULTI_THREAD : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
Aena : IN STD_LOGIC := '1';
Bena : IN STD_LOGIC := '0';
Cena : IN STD_LOGIC := '0';
Aenable : IN STD_LOGIC := '0';
Aenable_en : IN STD_LOGIC := '0';
Aaddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Awdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Awdata_en : IN STD_LOGIC := '0';
Ardata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
Benable : IN STD_LOGIC := '0';
Benable_en : IN STD_LOGIC := '0';
Baddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Bwdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Bwdata_en : IN STD_LOGIC := '0';
Brdata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
Cenable : IN STD_LOGIC := '0';
Cenable_en : IN STD_LOGIC := '0';
Caddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Crdata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mult IS
GENERIC (
NAME : STRinG := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
WIDTHX2 : INTEGER := 32;
LATENCY : INTEGER := 2;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
signa : IN STD_LOGIC := '0';
signb : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTHx2-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_multadd IS
GENERIC (
NAME : STRinG := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIXII;
WIDTH : INTEGER := 16;
WIDTHOUT : INTEGER := 33;
LATENCY : INTEGER := 3;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
c : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
signa : IN STD_LOGIC := '0';
signb : IN STD_LOGIC := '0';
signc : IN STD_LOGIC := '0';
signd : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTHOUT-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux2 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC := '0';
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux2_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
CONSTANT PORTS : INTEGER := 2
);
PORT (
sel : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0):= (others => '0');
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux3 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux4 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( 3 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux5 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( 4 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0):= (others => '0');
data : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0):= (others => '0');
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_x20 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 21;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data8 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data9 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data10 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data11 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data12 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data13 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data14 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data15 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data16 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data17 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data18 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data19 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data20 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_x40 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 41;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data8 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data9 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data10 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data11 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data12 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data13 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data14 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data15 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data16 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data17 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data18 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data19 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data20 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data21 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data22 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data23 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data24 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data25 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data26 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data27 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data28 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data29 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data30 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data31 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data32 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data33 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data34 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data35 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data36 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data37 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data38 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data39 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data40 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_x80 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 81;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data8 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data9 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data10 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data11 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data12 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data13 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data14 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data15 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data16 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data17 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data18 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data19 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data20 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data21 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data22 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data23 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data24 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data25 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data26 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data27 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data28 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data29 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data30 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data31 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data32 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data33 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data34 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data35 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data36 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data37 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data38 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data39 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data40 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data41 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data42 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data43 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data44 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data45 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data46 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data47 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data48 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data49 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data50 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data51 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data52 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data53 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data54 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data55 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data56 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data57 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data58 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data59 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data60 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data61 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data62 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data63 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data64 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data65 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data66 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data67 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data68 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data69 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data70 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data71 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data72 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data73 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data74 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data75 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data76 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data77 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data78 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data79 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data80 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data81 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxfast4 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 4;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data0 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxfast8 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 8;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
data0 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_one_bit_delay IS
generic
(
DELAY : integer := 0
);
port
(
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
data : in std_logic;
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_pc IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PROGRAM_FILE : STRING := "";
PROGRAM_TRACE: STRING := "program.trace";
LATENCY : INTEGER := 3;
DECODE_LATENCY : INTEGER := 2;
INFER_MEMORY : INTEGER := 0;
PC_WIDTH : INTEGER := 16;
PC_NUM_WORDS : INTEGER := 256;
PCW_WIDTH : INTEGER := 32
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
pcw : OUT STD_LOGIC_VECTOR( PCW_WIDTH-1 DOWNTO 0);
pc : OUT STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0);
pcf : OUT STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0);
step : OUT STD_LOGIC;
stallnext : OUT STD_LOGIC;
nextpc : IN STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
usenextpc : IN STD_LOGIC := '0';
usenextpc_en : IN STD_LOGIC := '0';
hold : IN STD_LOGIC := '0';
hold_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_pulling_width_adapter IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
input : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
need_input : out std_logic;
output : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
pull : in std_logic;
pull_en : in std_logic;
discard : in std_logic;
discard_en : in std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_pushing_width_adapter IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
input : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
push : in std_logic;
push_en : in std_logic;
flush : in std_logic;
flush_en : in std_logic;
output : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
output_valid : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_ram_fifo IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE;
DEVICE_FAMILY : string
);
port
(
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_reg IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
RESET_VALUE : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_shift IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATA_WIDTH : POSITIVE := 16;
SHIFT_WIDTH : POSITIVE := 4;
LATENCY : INTEGER := 0;
MODE : INTEGER := ALT_SHIFT_MODE_LOGICAL;
DIRECTION : INTEGER := ALT_SHIFT_DIREC_RIGHT
);
PORT (
clock : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
data_en : IN STD_LOGIC := '1';
shift : IN STD_LOGIC_VECTOR(SHIFT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
direc : IN STD_LOGIC := '0';
result : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_std_logic_vector_delay IS
generic
(
WIDTH : integer := 1;
DELAY : integer := 0
);
port
(
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin2_wire IS
generic (
NAME : string := "";
PORTS : integer := 2;
WIDTH : integer := 1
);
port (
sel : in std_logic := '0';
data0 : in std_logic := '0';
data1 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin2 IS
generic (
NAME : string := "";
PORTS : integer := 2;
WIDTH : integer := 16
);
port (
sel : in std_logic := '0';
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin4_wire IS
generic (
NAME : string := "";
PORTS : integer := 4;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin4 IS
generic (
NAME : string := "";
PORTS : integer := 4;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin8_wire IS
generic (
NAME : string := "";
PORTS : integer := 8;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(2 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin8 IS
generic (
NAME : string := "";
PORTS : integer := 8;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(2 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin16_wire IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(3 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin16 IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(3 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin32_wire IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(4 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin32 IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(4 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin64_wire IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(5 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin64 IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(5 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin128_wire IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(6 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
data64 : in std_logic := '0';
data65 : in std_logic := '0';
data66 : in std_logic := '0';
data67 : in std_logic := '0';
data68 : in std_logic := '0';
data69 : in std_logic := '0';
data70 : in std_logic := '0';
data71 : in std_logic := '0';
data72 : in std_logic := '0';
data73 : in std_logic := '0';
data74 : in std_logic := '0';
data75 : in std_logic := '0';
data76 : in std_logic := '0';
data77 : in std_logic := '0';
data78 : in std_logic := '0';
data79 : in std_logic := '0';
data80 : in std_logic := '0';
data81 : in std_logic := '0';
data82 : in std_logic := '0';
data83 : in std_logic := '0';
data84 : in std_logic := '0';
data85 : in std_logic := '0';
data86 : in std_logic := '0';
data87 : in std_logic := '0';
data88 : in std_logic := '0';
data89 : in std_logic := '0';
data90 : in std_logic := '0';
data91 : in std_logic := '0';
data92 : in std_logic := '0';
data93 : in std_logic := '0';
data94 : in std_logic := '0';
data95 : in std_logic := '0';
data96 : in std_logic := '0';
data97 : in std_logic := '0';
data98 : in std_logic := '0';
data99 : in std_logic := '0';
data100 : in std_logic := '0';
data101 : in std_logic := '0';
data102 : in std_logic := '0';
data103 : in std_logic := '0';
data104 : in std_logic := '0';
data105 : in std_logic := '0';
data106 : in std_logic := '0';
data107 : in std_logic := '0';
data108 : in std_logic := '0';
data109 : in std_logic := '0';
data110 : in std_logic := '0';
data111 : in std_logic := '0';
data112 : in std_logic := '0';
data113 : in std_logic := '0';
data114 : in std_logic := '0';
data115 : in std_logic := '0';
data116 : in std_logic := '0';
data117 : in std_logic := '0';
data118 : in std_logic := '0';
data119 : in std_logic := '0';
data120 : in std_logic := '0';
data121 : in std_logic := '0';
data122 : in std_logic := '0';
data123 : in std_logic := '0';
data124 : in std_logic := '0';
data125 : in std_logic := '0';
data126 : in std_logic := '0';
data127 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin128 IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(6 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data64 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data65 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data66 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data67 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data68 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data69 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data70 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data71 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data72 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data73 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data74 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data75 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data76 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data77 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data78 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data79 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data80 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data81 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data82 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data83 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data84 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data85 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data86 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data87 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data88 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data89 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data90 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data91 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data92 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data93 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data94 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data95 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data96 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data97 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data98 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data99 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data100 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data101 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data102 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data103 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data104 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data105 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data106 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data107 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data108 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data109 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data110 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data111 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data112 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data113 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data114 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data115 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data116 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data117 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data118 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data119 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data120 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data121 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data122 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data123 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data124 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data125 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data126 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data127 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot16_wire IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot16 IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot32_wire IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot32 IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot64_wire IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot64 IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot128_wire IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
data64 : in std_logic := '0';
data65 : in std_logic := '0';
data66 : in std_logic := '0';
data67 : in std_logic := '0';
data68 : in std_logic := '0';
data69 : in std_logic := '0';
data70 : in std_logic := '0';
data71 : in std_logic := '0';
data72 : in std_logic := '0';
data73 : in std_logic := '0';
data74 : in std_logic := '0';
data75 : in std_logic := '0';
data76 : in std_logic := '0';
data77 : in std_logic := '0';
data78 : in std_logic := '0';
data79 : in std_logic := '0';
data80 : in std_logic := '0';
data81 : in std_logic := '0';
data82 : in std_logic := '0';
data83 : in std_logic := '0';
data84 : in std_logic := '0';
data85 : in std_logic := '0';
data86 : in std_logic := '0';
data87 : in std_logic := '0';
data88 : in std_logic := '0';
data89 : in std_logic := '0';
data90 : in std_logic := '0';
data91 : in std_logic := '0';
data92 : in std_logic := '0';
data93 : in std_logic := '0';
data94 : in std_logic := '0';
data95 : in std_logic := '0';
data96 : in std_logic := '0';
data97 : in std_logic := '0';
data98 : in std_logic := '0';
data99 : in std_logic := '0';
data100 : in std_logic := '0';
data101 : in std_logic := '0';
data102 : in std_logic := '0';
data103 : in std_logic := '0';
data104 : in std_logic := '0';
data105 : in std_logic := '0';
data106 : in std_logic := '0';
data107 : in std_logic := '0';
data108 : in std_logic := '0';
data109 : in std_logic := '0';
data110 : in std_logic := '0';
data111 : in std_logic := '0';
data112 : in std_logic := '0';
data113 : in std_logic := '0';
data114 : in std_logic := '0';
data115 : in std_logic := '0';
data116 : in std_logic := '0';
data117 : in std_logic := '0';
data118 : in std_logic := '0';
data119 : in std_logic := '0';
data120 : in std_logic := '0';
data121 : in std_logic := '0';
data122 : in std_logic := '0';
data123 : in std_logic := '0';
data124 : in std_logic := '0';
data125 : in std_logic := '0';
data126 : in std_logic := '0';
data127 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot128 IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data64 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data65 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data66 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data67 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data68 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data69 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data70 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data71 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data72 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data73 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data74 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data75 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data76 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data77 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data78 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data79 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data80 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data81 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data82 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data83 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data84 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data85 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data86 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data87 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data88 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data89 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data90 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data91 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data92 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data93 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data94 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data95 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data96 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data97 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data98 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data99 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data100 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data101 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data102 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data103 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data104 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data105 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data106 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data107 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data108 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data109 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data110 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data111 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data112 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data113 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data114 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data115 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data116 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data117 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data118 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data119 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data120 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data121 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data122 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data123 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data124 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data125 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data126 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data127 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- synopsys synthesis_off
TYPE TTA_X_D_STRING_PTR IS ACCESS STRING;
TYPE TTA_X_D_SLV_PTR IS ACCESS STD_LOGIC_VECTOR;
TYPE TTA_X_D_RN_T IS ARRAY ( INTEGER RANGE <> ) OF TTA_X_D_STRING_PTR;
TYPE TTA_X_D_RV_T IS ARRAY ( INTEGER RANGE <> ) OF TTA_X_D_SLV_PTR;
PROCEDURE TTA_X_D_registerTrace (
opAddress : IN STRING;
opCode : IN STRING;
opDecode: IN STRING
);
PROCEDURE TTA_X_D_registerDump (
fuName : IN STRING;
registerNames : INOUT TTA_X_D_RN_T;
registerValues : INOUT TTA_X_D_RV_T
);
PROCEDURE TTA_X_D_openTrace (
fileName : IN STRING := "trace.out";
shortFileName : IN STRING := "shorttrace.out"
);
-- synopsys synthesis_on
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
END alt_vipvfr131_common_package;
PACKAGE BODY alt_vipvfr131_common_package IS
-- -----------------------------------------------------------
-- Fifo functions
-- -----------------------------------------------------------
-- find the width of a signal of "unsigned" type wide
-- enough to hold numbers as big as "max"
-- this is equivalent to log-2 max rounded up
function wide_enough_for(max : integer) return integer is
variable r : integer := 0;
variable m : integer := max;
begin
while m > 0 loop
m := m / 2;
r := r + 1;
end loop;
return r;
end function wide_enough_for;
function two_to_the_power(v : integer) return integer is
variable r : integer := 1;
variable i : integer := v;
begin
while i > 0 loop
r := r * 2;
i := i - 1;
end loop;
return r;
end function two_to_the_power;
-- generate as many repeating copies of the hexadecimal string
-- DEAD as will fit into a "b" bit std_logic_vector
function dead_bits(b : integer) return std_logic_vector is
variable r : std_logic_vector(b - 1 downto 0);
constant DEAD : std_logic_vector(15 downto 0) := "1101111010101101";
begin
for i in 0 to b - 1 loop
r(i) := DEAD(i mod 16);
end loop;
return r;
end function dead_bits;
-- return the higher of the two passed integers
-- can't believe there isn't a handy library function for this,
-- but a quick google couldn't find it
function maximum(a, b : integer) return integer is
begin
if (a > b) then
return a;
else
return b;
end if;
end function maximum;
-- find the minimum, likewise
function minimum(a, b : integer) return integer is
begin
if (a > b) then
return b;
else
return a;
end if;
end function minimum;
-- calculate the width of a byte enable port
-- depends on whether byte enables are required and what the
-- data width of the quantity to be byte enabled is
function calculate_be_width(be_used : boolean; data_width : integer) return integer is
begin
if not be_used then
return 0;
else
assert data_width mod 8 = 0
report "Tried to calculate the byte enable width of a data width not divisble by 8"
severity warning;
return data_width / 8;
end if;
end function calculate_be_width;
function calculate_be_width(be_used : integer; data_width : integer) return integer is
begin
if (be_used = 1) then
return calculate_be_width(true, data_width);
else
return calculate_be_width(false, data_width);
end if;
end function calculate_be_width;
function calculate_be_width(data_width : integer) return integer is
begin
return calculate_be_width(true, data_width);
end function calculate_be_width;
-- translate from cusp integer representation of families to the
-- string representation used by altera megafunctions and the like
function family_string(f : integer) return string is
begin
case f is
when FAMILY_STRATIX => return "Stratix";
when FAMILY_STRATIXII => return "Stratix II";
when FAMILY_STRATIXIII => return "Stratix III";
when FAMILY_CYCLONE => return "Cyclone";
when FAMILY_CYCLONEII => return "Cyclone II";
when FAMILY_HARDCOPYII => return "HardCopy II";
when others => return "Stratix";
end case;
end function family_string;
-- translate a std_logic_vector into a binary string represenation of same
function to_string(slv : std_logic_vector) return string is
variable s : string(slv'LENGTH downto 1);
begin
for i in slv'HIGH downto slv'LOW loop
if slv(i) = '1' then
s(1 + i) := '1';
else
s(1 + i) := '0';
end if;
end loop;
return s;
end function to_string;
function boolean_to_int(value : boolean) return integer is
begin
if value then
return 1;
else
return 0;
end if;
end function boolean_to_int;
-- synopsys synthesis_off
type reg_list_t;
type reg_list_ptr_t is access reg_list_t;
type reg_list_t is record
reg_name : TTA_X_D_string_ptr;
reg_value : TTA_X_D_slv_ptr;
next_elem : reg_list_ptr_t;
end record;
type fu_list_t;
type fu_list_ptr_t is access fu_list_t;
type fu_list_t is record
fu_name : TTA_X_D_string_ptr;
reg_values : reg_list_ptr_t;
next_elem : fu_list_ptr_t;
end record;
shared variable fu_state : fu_list_ptr_t := null;
shared variable fu_state_previous : fu_list_ptr_t := null;
shared variable ENABLE_DEBUG_TRACE : INTEGER := 0;
constant CURRENT_STATE : INTEGER := 0;
constant PREVIOUS_STATE : INTEGER := 1;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------------------------------------
-- Convert Integer to Hex
-----------------------------------------
FUNCTION TIntegerToHex(i : INTEGER; ndigits : INTEGER) RETURN STRING IS
VARIABLE s : STRING(1 TO 256) := (others => '0');
VARIABLE Num, ThisDigit, si : INTEGER;
BEGIN
Num := i;
si := 256;
WHILE (Num > 0) LOOP
ThisDigit := Num - ((Num / 16) * 16);
CASE ThisDigit IS
WHEN 1 => s(si) := '1';
WHEN 2 => s(si) := '2';
WHEN 3 => s(si) := '3';
WHEN 4 => s(si) := '4';
WHEN 5 => s(si) := '5';
WHEN 6 => s(si) := '6';
WHEN 7 => s(si) := '7';
WHEN 8 => s(si) := '8';
WHEN 9 => s(si) := '9';
WHEN 10 => s(si) := 'A';
WHEN 11 => s(si) := 'B';
WHEN 12 => s(si) := 'C';
WHEN 13 => s(si) := 'D';
WHEN 14 => s(si) := 'E';
WHEN 15 => s(si) := 'F';
WHEN OTHERS => s(si) := '0';
END CASE;
si := si - 1;
Num := Num / 16;
END LOOP;
IF (i = 0) THEN
si := si - 1;
END IF;
RETURN s(257-ndigits TO 256);
END ;
-----------------------------------------
-- convert integer to string
function TIntegerToString( value : integer ) return string is
variable ivalue : integer := 0;
variable index : integer := 1;
variable digit : integer := 0;
variable temp: string(10 downto 1) := "0000000000";
begin
index := 1;
if (value < 0 ) then
ivalue := -value;
else
ivalue := value;
end if;
while (ivalue > 0) loop
digit := ivalue mod 10;
ivalue := ivalue/10;
case digit is
when 0 => temp(index) := '0';
when 1 => temp(index) := '1';
when 2 => temp(index) := '2';
when 3 => temp(index) := '3';
when 4 => temp(index) := '4';
when 5 => temp(index) := '5';
when 6 => temp(index) := '6';
when 7 => temp(index) := '7';
when 8 => temp(index) := '8';
when 9 => temp(index) := '9';
when others => ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
if value /= 0 then
index := index - 1;
end if;
if (value < 0) then
return ('-'& temp(index downto 1));
else
return temp(index downto 1);
end if;
end ;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- search along the state looking for an FU with name fu_name
-- if not found create a new fu record, set the name, and
-- place it at the head of the list
procedure findFU ( fu_name : IN STRING;
fu : OUT fu_list_ptr_t ) is
variable iter : fu_list_ptr_t;
begin
iter := fu_state;
find: loop
if iter = null then
iter := new fu_list_t;
iter.fu_name := new String(fu_name'high downto fu_name'low);
iter.fu_name.all := fu_name;
iter.next_elem := fu_state;
fu_state := iter;
end if;
exit when iter.fu_name.all = fu_name;
iter := iter.next_elem;
end loop;
fu := iter;
end;
-- like FU - works on _previous state
procedure findFU_previous ( fu_name : IN STRING;
fu : OUT fu_list_ptr_t ) is
variable iter : fu_list_ptr_t;
begin
iter := fu_state_previous;
find: loop
if iter = null then
iter := new fu_list_t;
iter.fu_name := new String(fu_name'high downto fu_name'low);
iter.fu_name.all := fu_name;
iter.next_elem := fu_state;
fu_state_previous := iter;
end if;
exit when iter.fu_name.all = fu_name;
iter := iter.next_elem;
end loop;
fu := iter;
end;
-- search along the FU looking for an reg with name reg_name
-- if not found create a new reg record, set the name, and
-- place it at the head of the list
procedure findReg ( fu_name : IN STRING;
state : IN INTEGER;
reg_name : INOUT TTA_X_D_string_ptr;
reg : OUT reg_list_ptr_t ) is
variable iter : reg_list_ptr_t;
variable fu : fu_list_ptr_t;
begin
if state = CURRENT_STATE then
findFu(fu_name, fu);
else
findFu_previous(fu_name, fu);
end if;
iter := fu.reg_values;
find: loop
if iter = null then
iter := new reg_list_t;
iter.reg_name := new String(reg_name.all'high downto reg_name.all'low);
iter.reg_name.all := reg_name.all;
iter.next_elem := fu.reg_values;
fu.reg_values := iter;
end if;
exit when iter.reg_name.all = reg_name.all;
iter := iter.next_elem;
end loop;
reg := iter;
end;
-- update the value for (fu_name, reg_name) creating a new record if one is needed
procedure updateReg ( fu_name : IN STRING;
state : IN INTEGER;
reg_name : INOUT TTA_X_D_string_ptr;
reg_value : INOUT TTA_X_D_slv_ptr ) is
variable reg : reg_list_ptr_t;
begin
findReg(fu_name, state, reg_name, reg);
if reg.reg_value = null then
reg.reg_value := new std_logic_vector(reg_value.all'high downto reg_value.all'low);
end if;
reg.reg_value.all := reg_value.all;
end;
PROCEDURE TTA_X_D_registerDump (
fuName : IN STRING;
registerNames : INOUT TTA_X_D_RN_T;
registerValues : INOUT TTA_X_D_RV_T
) IS
BEGIN
if ENABLE_DEBUG_TRACE /= 0 then
for count in registerNames'high downto registerNames'low loop
updateReg ( fuName, CURRENT_STATE, registerNames(count), registerValues(count) );
end loop;
end if; -- debug trace enabled
END;
-- ----------------------------------------------
FILE traceFile : TEXT;
FILE shortTraceFile : TEXT;
shared variable traceFileOpen : integer := 0;
PROCEDURE TTA_X_D_openTrace (
fileName : IN STRING := "trace.out";
shortFileName : IN STRING := "shorttrace.out"
) IS
BEGIN
if ENABLE_DEBUG_TRACE /= 0 then
FILE_OPEN (traceFile, fileName, WRITE_MODE);
FILE_OPEN (shorttraceFile, shortFileName, WRITE_MODE);
traceFileOpen := 1;
end if; -- debug trace enabled
END;
-- create / update
procedure save_fu_state is
variable last_fu_iter : fu_list_ptr_t;
variable last_reg_iter : reg_list_ptr_t;
variable fu_iter : fu_list_ptr_t;
variable reg_iter : reg_list_ptr_t;
begin
fu_iter := fu_state;
fu_loop: loop
exit fu_loop when fu_iter = null;
reg_iter := fu_iter.reg_values;
reg_loop: loop
exit reg_loop when reg_iter = null;
updateReg ( fu_iter.fu_name.all, PREVIOUS_STATE, reg_iter.reg_name, reg_iter.reg_value );
reg_iter := reg_iter.next_elem;
end loop;
fu_iter := fu_iter.next_elem;
end loop;
end;
-- generate trace information for the specified address, opcode, operation
--
PROCEDURE TTA_X_D_registerTrace (
opAddress : IN STRING;
opCode : IN STRING;
opDecode: IN STRING
) IS
variable fu_iter : fu_list_ptr_t;
variable reg_iter : reg_list_ptr_t;
variable l:line;
variable current_reg_value : reg_list_ptr_t;
BEGIN
if ENABLE_DEBUG_TRACE /= 0 then
if traceFileOpen = 0 then
TTA_X_D_openTrace;
end if;
-- -----------------------------------------------------------
-- COMPLETE REGISTER DUMP
-- -----------------------------------------------------------
fu_iter := fu_state;
write(l, opAddress);
write(l, STRING'(" ") );
write(l, opCode);
write(l, STRING'(" ") );
fu_loop: loop
exit fu_loop when fu_iter = null;
reg_iter := fu_iter.reg_values;
reg_loop: loop
exit reg_loop when reg_iter = null;
write(l, fu_iter.fu_name.all);
write(l, STRING'("."));
write(l, reg_iter.reg_name.all);
write(l, STRING'("="));
-- write(l, TIntegerToHex(To_Integer(unsigned(reg_iter.reg_value.all)),
-- (reg_iter.reg_value.all'length+3)/4) );
if reg_iter.reg_value.all'length = 1 then
write(l, TIntegerToString(To_Integer(unsigned(reg_iter.reg_value.all))));
elsif Is_X(reg_iter.reg_value.all) then
assert false report ("Register " & fu_iter.fu_name.all & STRING'(".") & reg_iter.reg_name.all & " contains undefined value trace shows 0" ) severity warning;
write(l, STRING'("."));
else
write(l, TIntegerToString(To_Integer(signed(reg_iter.reg_value.all))));
end if;
write(l, STRING'(" "));
reg_iter := reg_iter.next_elem;
end loop;
fu_iter := fu_iter.next_elem;
end loop;
write(l, opDecode);
writeline(traceFile, l);
-- -----------------------------------------------------------
-- REGISTER CHANGE DUMP
-- -----------------------------------------------------------
if fu_state_previous /= null then
fu_iter := fu_state_previous;
write(l, "0x" & opAddress);
write(l, STRING'(" ") );
-- write(l, opCode);
-- write(l, STRING'(" ") );
write(l, opDecode);
writeline(shortTraceFile, l);
short_fu_loop: loop
exit short_fu_loop when fu_iter = null;
reg_iter := fu_iter.reg_values;
short_reg_loop: loop
exit short_reg_loop when reg_iter = null;
findReg( fu_iter.fu_name.all, CURRENT_STATE, reg_iter.reg_name, current_reg_value );
if current_reg_value.reg_value /= null and reg_iter.reg_value /= null then
if current_reg_value.reg_value.all /= reg_iter.reg_value.all then
write(l, fu_iter.fu_name.all);
write(l, STRING'("."));
write(l, reg_iter.reg_name.all);
write(l, STRING'("="));
-- write(l, TIntegerToHex(To_Integer(unsigned(current_reg_value.reg_value.all)),
-- (reg_iter.reg_value.all'length+3)/4) );
if current_reg_value.reg_value.all'length = 1 then
write(l, TIntegerToString(To_Integer(unsigned(current_reg_value.reg_value.all))));
else
write(l, TIntegerToString(To_Integer(signed(current_reg_value.reg_value.all))));
end if;
write(l, STRING'(" "));
end if;
end if;
reg_iter := reg_iter.next_elem;
end loop;
fu_iter := fu_iter.next_elem;
end loop;
writeline(shortTraceFile, l);
end if;
-- -----------------------------------------------------------
-- SAVE STATE TO COMPUTE REGISTER CHANGES
-- -----------------------------------------------------------
save_fu_state;
end if; -- debug trace enabled
END;
-- synopsys synthesis_on
END alt_vipvfr131_common_package;
|
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
use work.init_funcs.all;
use std.textio.all;
entity test_init_funcs is
end test_init_funcs;
architecture behavioural of test_init_funcs is
begin
process
constant test_storage : memory_16b := (
"11111111",
"10000000",
"10000000",
"10000001",
"00000001",
"00001001",
"00001000",
"00001000",
"00010100",
"00001000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"11111111"
);
variable data : memory_16b;
begin
data := read_file("rom_lut.mif");
assert data = test_storage
report "data should match testcase" severity error;
wait;
end process;
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_z80 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_z80 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F3";
when x"001" => DATA <= x"11";
when x"002" => DATA <= x"00";
when x"003" => DATA <= x"F0";
when x"004" => DATA <= x"21";
when x"005" => DATA <= x"00";
when x"006" => DATA <= x"00";
when x"007" => DATA <= x"01";
when x"008" => DATA <= x"00";
when x"009" => DATA <= x"10";
when x"00A" => DATA <= x"ED";
when x"00B" => DATA <= x"B0";
when x"00C" => DATA <= x"C3";
when x"00D" => DATA <= x"80";
when x"00E" => DATA <= x"F2";
when x"00F" => DATA <= x"43";
when x"010" => DATA <= x"6F";
when x"011" => DATA <= x"70";
when x"012" => DATA <= x"79";
when x"013" => DATA <= x"72";
when x"014" => DATA <= x"69";
when x"015" => DATA <= x"67";
when x"016" => DATA <= x"68";
when x"017" => DATA <= x"74";
when x"018" => DATA <= x"20";
when x"019" => DATA <= x"41";
when x"01A" => DATA <= x"63";
when x"01B" => DATA <= x"6F";
when x"01C" => DATA <= x"72";
when x"01D" => DATA <= x"6E";
when x"01E" => DATA <= x"20";
when x"01F" => DATA <= x"43";
when x"020" => DATA <= x"6F";
when x"021" => DATA <= x"6D";
when x"022" => DATA <= x"70";
when x"023" => DATA <= x"75";
when x"024" => DATA <= x"74";
when x"025" => DATA <= x"65";
when x"026" => DATA <= x"72";
when x"027" => DATA <= x"73";
when x"028" => DATA <= x"20";
when x"029" => DATA <= x"4C";
when x"02A" => DATA <= x"74";
when x"02B" => DATA <= x"64";
when x"02C" => DATA <= x"2E";
when x"02D" => DATA <= x"20";
when x"02E" => DATA <= x"31";
when x"02F" => DATA <= x"39";
when x"030" => DATA <= x"38";
when x"031" => DATA <= x"34";
when x"032" => DATA <= x"0D";
when x"033" => DATA <= x"48";
when x"034" => DATA <= x"3A";
when x"035" => DATA <= x"7D";
when x"036" => DATA <= x"3C";
when x"037" => DATA <= x"B7";
when x"038" => DATA <= x"C4";
when x"039" => DATA <= x"C0";
when x"03A" => DATA <= x"2C";
when x"03B" => DATA <= x"3A";
when x"03C" => DATA <= x"22";
when x"03D" => DATA <= x"3A";
when x"03E" => DATA <= x"B7";
when x"03F" => DATA <= x"C4";
when x"040" => DATA <= x"F1";
when x"041" => DATA <= x"2C";
when x"042" => DATA <= x"F1";
when x"043" => DATA <= x"21";
when x"044" => DATA <= x"1B";
when x"045" => DATA <= x"3A";
when x"046" => DATA <= x"34";
when x"047" => DATA <= x"7E";
when x"048" => DATA <= x"3D";
when x"049" => DATA <= x"C2";
when x"04A" => DATA <= x"AB";
when x"04B" => DATA <= x"2B";
when x"04C" => DATA <= x"21";
when x"04D" => DATA <= x"EC";
when x"04E" => DATA <= x"3B";
when x"04F" => DATA <= x"7E";
when x"050" => DATA <= x"B7";
when x"051" => DATA <= x"C2";
when x"052" => DATA <= x"34";
when x"053" => DATA <= x"2B";
when x"054" => DATA <= x"21";
when x"055" => DATA <= x"4A";
when x"056" => DATA <= x"3B";
when x"057" => DATA <= x"7E";
when x"058" => DATA <= x"B7";
when x"059" => DATA <= x"C2";
when x"05A" => DATA <= x"34";
when x"05B" => DATA <= x"2B";
when x"05C" => DATA <= x"21";
when x"05D" => DATA <= x"58";
when x"05E" => DATA <= x"3D";
when x"05F" => DATA <= x"23";
when x"060" => DATA <= x"01";
when x"061" => DATA <= x"06";
when x"062" => DATA <= x"00";
when x"063" => DATA <= x"11";
when x"064" => DATA <= x"EC";
when x"065" => DATA <= x"3B";
when x"066" => DATA <= x"C3";
when x"067" => DATA <= x"61";
when x"068" => DATA <= x"FC";
when x"069" => DATA <= x"54";
when x"06A" => DATA <= x"68";
when x"06B" => DATA <= x"65";
when x"06C" => DATA <= x"20";
when x"06D" => DATA <= x"42";
when x"06E" => DATA <= x"75";
when x"06F" => DATA <= x"73";
when x"070" => DATA <= x"69";
when x"071" => DATA <= x"6E";
when x"072" => DATA <= x"65";
when x"073" => DATA <= x"73";
when x"074" => DATA <= x"73";
when x"075" => DATA <= x"20";
when x"076" => DATA <= x"53";
when x"077" => DATA <= x"79";
when x"078" => DATA <= x"73";
when x"079" => DATA <= x"74";
when x"07A" => DATA <= x"65";
when x"07B" => DATA <= x"6D";
when x"07C" => DATA <= x"73";
when x"07D" => DATA <= x"20";
when x"07E" => DATA <= x"47";
when x"07F" => DATA <= x"72";
when x"080" => DATA <= x"6F";
when x"081" => DATA <= x"75";
when x"082" => DATA <= x"70";
when x"083" => DATA <= x"20";
when x"084" => DATA <= x"77";
when x"085" => DATA <= x"6F";
when x"086" => DATA <= x"75";
when x"087" => DATA <= x"6C";
when x"088" => DATA <= x"64";
when x"089" => DATA <= x"20";
when x"08A" => DATA <= x"6C";
when x"08B" => DATA <= x"69";
when x"08C" => DATA <= x"6B";
when x"08D" => DATA <= x"65";
when x"08E" => DATA <= x"20";
when x"08F" => DATA <= x"74";
when x"090" => DATA <= x"6F";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"74";
when x"093" => DATA <= x"68";
when x"094" => DATA <= x"61";
when x"095" => DATA <= x"6E";
when x"096" => DATA <= x"6B";
when x"097" => DATA <= x"4D";
when x"098" => DATA <= x"69";
when x"099" => DATA <= x"6B";
when x"09A" => DATA <= x"65";
when x"09B" => DATA <= x"20";
when x"09C" => DATA <= x"42";
when x"09D" => DATA <= x"6F";
when x"09E" => DATA <= x"6C";
when x"09F" => DATA <= x"6C";
when x"0A0" => DATA <= x"65";
when x"0A1" => DATA <= x"79";
when x"0A2" => DATA <= x"2C";
when x"0A3" => DATA <= x"4D";
when x"0A4" => DATA <= x"69";
when x"0A5" => DATA <= x"6B";
when x"0A6" => DATA <= x"65";
when x"0A7" => DATA <= x"20";
when x"0A8" => DATA <= x"26";
when x"0A9" => DATA <= x"20";
when x"0AA" => DATA <= x"41";
when x"0AB" => DATA <= x"6C";
when x"0AC" => DATA <= x"6C";
when x"0AD" => DATA <= x"65";
when x"0AE" => DATA <= x"6E";
when x"0AF" => DATA <= x"20";
when x"0B0" => DATA <= x"42";
when x"0B1" => DATA <= x"6F";
when x"0B2" => DATA <= x"6F";
when x"0B3" => DATA <= x"74";
when x"0B4" => DATA <= x"68";
when x"0B5" => DATA <= x"72";
when x"0B6" => DATA <= x"6F";
when x"0B7" => DATA <= x"79";
when x"0B8" => DATA <= x"64";
when x"0B9" => DATA <= x"2C";
when x"0BA" => DATA <= x"52";
when x"0BB" => DATA <= x"69";
when x"0BC" => DATA <= x"63";
when x"0BD" => DATA <= x"68";
when x"0BE" => DATA <= x"61";
when x"0BF" => DATA <= x"72";
when x"0C0" => DATA <= x"64";
when x"0C1" => DATA <= x"20";
when x"0C2" => DATA <= x"43";
when x"0C3" => DATA <= x"6C";
when x"0C4" => DATA <= x"61";
when x"0C5" => DATA <= x"79";
when x"0C6" => DATA <= x"74";
when x"0C7" => DATA <= x"6F";
when x"0C8" => DATA <= x"6E";
when x"0C9" => DATA <= x"2C";
when x"0CA" => DATA <= x"41";
when x"0CB" => DATA <= x"6E";
when x"0CC" => DATA <= x"64";
when x"0CD" => DATA <= x"72";
when x"0CE" => DATA <= x"65";
when x"0CF" => DATA <= x"77";
when x"0D0" => DATA <= x"20";
when x"0D1" => DATA <= x"47";
when x"0D2" => DATA <= x"6F";
when x"0D3" => DATA <= x"72";
when x"0D4" => DATA <= x"64";
when x"0D5" => DATA <= x"6F";
when x"0D6" => DATA <= x"6E";
when x"0D7" => DATA <= x"2C";
when x"0D8" => DATA <= x"43";
when x"0D9" => DATA <= x"68";
when x"0DA" => DATA <= x"72";
when x"0DB" => DATA <= x"69";
when x"0DC" => DATA <= x"73";
when x"0DD" => DATA <= x"20";
when x"0DE" => DATA <= x"48";
when x"0DF" => DATA <= x"61";
when x"0E0" => DATA <= x"6C";
when x"0E1" => DATA <= x"6C";
when x"0E2" => DATA <= x"2C";
when x"0E3" => DATA <= x"4B";
when x"0E4" => DATA <= x"69";
when x"0E5" => DATA <= x"6D";
when x"0E6" => DATA <= x"20";
when x"0E7" => DATA <= x"53";
when x"0E8" => DATA <= x"70";
when x"0E9" => DATA <= x"65";
when x"0EA" => DATA <= x"6E";
when x"0EB" => DATA <= x"63";
when x"0EC" => DATA <= x"65";
when x"0ED" => DATA <= x"2D";
when x"0EE" => DATA <= x"4A";
when x"0EF" => DATA <= x"6F";
when x"0F0" => DATA <= x"6E";
when x"0F1" => DATA <= x"65";
when x"0F2" => DATA <= x"73";
when x"0F3" => DATA <= x"2C";
when x"0F4" => DATA <= x"50";
when x"0F5" => DATA <= x"61";
when x"0F6" => DATA <= x"75";
when x"0F7" => DATA <= x"6C";
when x"0F8" => DATA <= x"20";
when x"0F9" => DATA <= x"4F";
when x"0FA" => DATA <= x"76";
when x"0FB" => DATA <= x"65";
when x"0FC" => DATA <= x"72";
when x"0FD" => DATA <= x"65";
when x"0FE" => DATA <= x"6C";
when x"0FF" => DATA <= x"6C";
when x"100" => DATA <= x"2C";
when x"101" => DATA <= x"44";
when x"102" => DATA <= x"61";
when x"103" => DATA <= x"76";
when x"104" => DATA <= x"69";
when x"105" => DATA <= x"64";
when x"106" => DATA <= x"20";
when x"107" => DATA <= x"50";
when x"108" => DATA <= x"61";
when x"109" => DATA <= x"72";
when x"10A" => DATA <= x"6B";
when x"10B" => DATA <= x"69";
when x"10C" => DATA <= x"6E";
when x"10D" => DATA <= x"73";
when x"10E" => DATA <= x"6F";
when x"10F" => DATA <= x"6E";
when x"110" => DATA <= x"2C";
when x"111" => DATA <= x"4A";
when x"112" => DATA <= x"6F";
when x"113" => DATA <= x"68";
when x"114" => DATA <= x"6E";
when x"115" => DATA <= x"20";
when x"116" => DATA <= x"54";
when x"117" => DATA <= x"75";
when x"118" => DATA <= x"74";
when x"119" => DATA <= x"65";
when x"11A" => DATA <= x"6E";
when x"11B" => DATA <= x"20";
when x"11C" => DATA <= x"61";
when x"11D" => DATA <= x"6E";
when x"11E" => DATA <= x"64";
when x"11F" => DATA <= x"20";
when x"120" => DATA <= x"45";
when x"121" => DATA <= x"72";
when x"122" => DATA <= x"69";
when x"123" => DATA <= x"63";
when x"124" => DATA <= x"20";
when x"125" => DATA <= x"74";
when x"126" => DATA <= x"68";
when x"127" => DATA <= x"65";
when x"128" => DATA <= x"20";
when x"129" => DATA <= x"68";
when x"12A" => DATA <= x"61";
when x"12B" => DATA <= x"6C";
when x"12C" => DATA <= x"66";
when x"12D" => DATA <= x"20";
when x"12E" => DATA <= x"54";
when x"12F" => DATA <= x"55";
when x"130" => DATA <= x"42";
when x"131" => DATA <= x"45";
when x"132" => DATA <= x"54";
when x"133" => DATA <= x"68";
when x"134" => DATA <= x"65";
when x"135" => DATA <= x"20";
when x"136" => DATA <= x"42";
when x"137" => DATA <= x"53";
when x"138" => DATA <= x"47";
when x"139" => DATA <= x"20";
when x"13A" => DATA <= x"69";
when x"13B" => DATA <= x"73";
when x"13C" => DATA <= x"20";
when x"13D" => DATA <= x"42";
when x"13E" => DATA <= x"69";
when x"13F" => DATA <= x"67";
when x"140" => DATA <= x"20";
when x"141" => DATA <= x"41";
when x"142" => DATA <= x"72";
when x"143" => DATA <= x"74";
when x"144" => DATA <= x"68";
when x"145" => DATA <= x"75";
when x"146" => DATA <= x"72";
when x"147" => DATA <= x"20";
when x"148" => DATA <= x"54";
when x"149" => DATA <= x"68";
when x"14A" => DATA <= x"65";
when x"14B" => DATA <= x"20";
when x"14C" => DATA <= x"54";
when x"14D" => DATA <= x"6F";
when x"14E" => DATA <= x"75";
when x"14F" => DATA <= x"63";
when x"150" => DATA <= x"61";
when x"151" => DATA <= x"6E";
when x"152" => DATA <= x"2C";
when x"153" => DATA <= x"4A";
when x"154" => DATA <= x"20";
when x"155" => DATA <= x"4D";
when x"156" => DATA <= x"61";
when x"157" => DATA <= x"72";
when x"158" => DATA <= x"6B";
when x"159" => DATA <= x"20";
when x"15A" => DATA <= x"43";
when x"15B" => DATA <= x"61";
when x"15C" => DATA <= x"72";
when x"15D" => DATA <= x"72";
when x"15E" => DATA <= x"69";
when x"15F" => DATA <= x"6E";
when x"160" => DATA <= x"67";
when x"161" => DATA <= x"74";
when x"162" => DATA <= x"6F";
when x"163" => DATA <= x"6E";
when x"164" => DATA <= x"2C";
when x"165" => DATA <= x"48";
when x"166" => DATA <= x"6F";
when x"167" => DATA <= x"77";
when x"168" => DATA <= x"61";
when x"169" => DATA <= x"72";
when x"16A" => DATA <= x"64";
when x"16B" => DATA <= x"20";
when x"16C" => DATA <= x"46";
when x"16D" => DATA <= x"69";
when x"16E" => DATA <= x"73";
when x"16F" => DATA <= x"68";
when x"170" => DATA <= x"65";
when x"171" => DATA <= x"72";
when x"172" => DATA <= x"2C";
when x"173" => DATA <= x"49";
when x"174" => DATA <= x"61";
when x"175" => DATA <= x"6E";
when x"176" => DATA <= x"20";
when x"177" => DATA <= x"47";
when x"178" => DATA <= x"20";
when x"179" => DATA <= x"4A";
when x"17A" => DATA <= x"61";
when x"17B" => DATA <= x"63";
when x"17C" => DATA <= x"6B";
when x"17D" => DATA <= x"2C";
when x"17E" => DATA <= x"4E";
when x"17F" => DATA <= x"65";
when x"180" => DATA <= x"69";
when x"181" => DATA <= x"6C";
when x"182" => DATA <= x"20";
when x"183" => DATA <= x"52";
when x"184" => DATA <= x"6F";
when x"185" => DATA <= x"62";
when x"186" => DATA <= x"69";
when x"187" => DATA <= x"6E";
when x"188" => DATA <= x"73";
when x"189" => DATA <= x"6F";
when x"18A" => DATA <= x"6E";
when x"18B" => DATA <= x"2C";
when x"18C" => DATA <= x"53";
when x"18D" => DATA <= x"69";
when x"18E" => DATA <= x"6D";
when x"18F" => DATA <= x"6F";
when x"190" => DATA <= x"6E";
when x"191" => DATA <= x"20";
when x"192" => DATA <= x"57";
when x"193" => DATA <= x"6F";
when x"194" => DATA <= x"6F";
when x"195" => DATA <= x"64";
when x"196" => DATA <= x"77";
when x"197" => DATA <= x"61";
when x"198" => DATA <= x"72";
when x"199" => DATA <= x"64";
when x"19A" => DATA <= x"2C";
when x"19B" => DATA <= x"4A";
when x"19C" => DATA <= x"6F";
when x"19D" => DATA <= x"68";
when x"19E" => DATA <= x"6E";
when x"19F" => DATA <= x"20";
when x"1A0" => DATA <= x"43";
when x"1A1" => DATA <= x"6F";
when x"1A2" => DATA <= x"72";
when x"1A3" => DATA <= x"72";
when x"1A4" => DATA <= x"61";
when x"1A5" => DATA <= x"6C";
when x"1A6" => DATA <= x"6C";
when x"1A7" => DATA <= x"2C";
when x"1A8" => DATA <= x"54";
when x"1A9" => DATA <= x"6F";
when x"1AA" => DATA <= x"62";
when x"1AB" => DATA <= x"79";
when x"1AC" => DATA <= x"20";
when x"1AD" => DATA <= x"43";
when x"1AE" => DATA <= x"72";
when x"1AF" => DATA <= x"6F";
when x"1B0" => DATA <= x"73";
when x"1B1" => DATA <= x"73";
when x"1B2" => DATA <= x"2C";
when x"1B3" => DATA <= x"49";
when x"1B4" => DATA <= x"61";
when x"1B5" => DATA <= x"6E";
when x"1B6" => DATA <= x"20";
when x"1B7" => DATA <= x"4D";
when x"1B8" => DATA <= x"69";
when x"1B9" => DATA <= x"6C";
when x"1BA" => DATA <= x"6C";
when x"1BB" => DATA <= x"65";
when x"1BC" => DATA <= x"72";
when x"1BD" => DATA <= x"2C";
when x"1BE" => DATA <= x"42";
when x"1BF" => DATA <= x"6F";
when x"1C0" => DATA <= x"72";
when x"1C1" => DATA <= x"69";
when x"1C2" => DATA <= x"73";
when x"1C3" => DATA <= x"20";
when x"1C4" => DATA <= x"53";
when x"1C5" => DATA <= x"6F";
when x"1C6" => DATA <= x"75";
when x"1C7" => DATA <= x"74";
when x"1C8" => DATA <= x"68";
when x"1C9" => DATA <= x"65";
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when x"1CB" => DATA <= x"72";
when x"1CC" => DATA <= x"73";
when x"1CD" => DATA <= x"72";
when x"1CE" => DATA <= x"6F";
when x"1CF" => DATA <= x"72";
when x"1D0" => DATA <= x"28";
when x"1D1" => DATA <= x"73";
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when x"1D3" => DATA <= x"00";
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when x"1D5" => DATA <= x"57";
when x"1D6" => DATA <= x"61";
when x"1D7" => DATA <= x"72";
when x"1D8" => DATA <= x"6E";
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when x"1DA" => DATA <= x"6E";
when x"1DB" => DATA <= x"67";
when x"1DC" => DATA <= x"28";
when x"1DD" => DATA <= x"73";
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when x"1DF" => DATA <= x"00";
when x"1E0" => DATA <= x"0E";
when x"1E1" => DATA <= x"00";
when x"1E2" => DATA <= x"3A";
when x"1E3" => DATA <= x"00";
when x"1E4" => DATA <= x"3B";
when x"1E5" => DATA <= x"47";
when x"1E6" => DATA <= x"CD";
when x"1E7" => DATA <= x"48";
when x"1E8" => DATA <= x"1A";
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when x"1EA" => DATA <= x"6B";
when x"1EB" => DATA <= x"2B";
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when x"1ED" => DATA <= x"16";
when x"1EE" => DATA <= x"2D";
when x"1EF" => DATA <= x"21";
when x"1F0" => DATA <= x"CF";
when x"1F1" => DATA <= x"2C";
when x"1F2" => DATA <= x"CD";
when x"1F3" => DATA <= x"19";
when x"1F4" => DATA <= x"2D";
when x"1F5" => DATA <= x"CD";
when x"1F6" => DATA <= x"CA";
when x"1F7" => DATA <= x"19";
when x"1F8" => DATA <= x"C3";
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when x"1FA" => DATA <= x"2C";
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when x"1FC" => DATA <= x"45";
when x"1FD" => DATA <= x"50";
when x"1FE" => DATA <= x"54";
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when x"200" => DATA <= x"49";
when x"201" => DATA <= x"52";
when x"202" => DATA <= x"50";
when x"203" => DATA <= x"2F";
when x"204" => DATA <= x"49";
when x"205" => DATA <= x"52";
when x"206" => DATA <= x"50";
when x"207" => DATA <= x"43";
when x"208" => DATA <= x"2F";
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when x"20A" => DATA <= x"41";
when x"20B" => DATA <= x"43";
when x"20C" => DATA <= x"52";
when x"20D" => DATA <= x"4F";
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when x"20F" => DATA <= x"55";
when x"210" => DATA <= x"6E";
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when x"212" => DATA <= x"65";
when x"213" => DATA <= x"72";
when x"214" => DATA <= x"6D";
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when x"216" => DATA <= x"6E";
when x"217" => DATA <= x"61";
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when x"21B" => DATA <= x"20";
when x"21C" => DATA <= x"00";
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when x"21F" => DATA <= x"2D";
when x"220" => DATA <= x"21";
when x"221" => DATA <= x"26";
when x"222" => DATA <= x"2D";
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when x"224" => DATA <= x"19";
when x"225" => DATA <= x"2D";
when x"226" => DATA <= x"CD";
when x"227" => DATA <= x"CA";
when x"228" => DATA <= x"19";
when x"229" => DATA <= x"3E";
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when x"22B" => DATA <= x"CD";
when x"22C" => DATA <= x"FC";
when x"22D" => DATA <= x"18";
when x"22E" => DATA <= x"3E";
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when x"230" => DATA <= x"CD";
when x"231" => DATA <= x"FC";
when x"232" => DATA <= x"18";
when x"233" => DATA <= x"3A";
when x"234" => DATA <= x"37";
when x"235" => DATA <= x"3D";
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when x"237" => DATA <= x"C8";
when x"238" => DATA <= x"3E";
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when x"23B" => DATA <= x"4E";
when x"23C" => DATA <= x"47";
when x"23D" => DATA <= x"3E";
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when x"23F" => DATA <= x"C3";
when x"240" => DATA <= x"4E";
when x"241" => DATA <= x"47";
when x"242" => DATA <= x"21";
when x"243" => DATA <= x"E3";
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when x"245" => DATA <= x"E5";
when x"246" => DATA <= x"CD";
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when x"248" => DATA <= x"19";
when x"249" => DATA <= x"E1";
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when x"24B" => DATA <= x"37";
when x"24C" => DATA <= x"3D";
when x"24D" => DATA <= x"3C";
when x"24E" => DATA <= x"C8";
when x"24F" => DATA <= x"C3";
when x"250" => DATA <= x"4F";
when x"251" => DATA <= x"43";
when x"252" => DATA <= x"43";
when x"253" => DATA <= x"6F";
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when x"255" => DATA <= x"64";
when x"256" => DATA <= x"69";
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when x"25C" => DATA <= x"6C";
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when x"25F" => DATA <= x"79";
when x"260" => DATA <= x"6D";
when x"261" => DATA <= x"62";
when x"262" => DATA <= x"6F";
when x"263" => DATA <= x"6C";
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when x"265" => DATA <= x"3A";
when x"266" => DATA <= x"0D";
when x"267" => DATA <= x"0A";
when x"268" => DATA <= x"00";
when x"269" => DATA <= x"4D";
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when x"26B" => DATA <= x"63";
when x"26C" => DATA <= x"72";
when x"26D" => DATA <= x"6F";
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when x"26F" => DATA <= x"3A";
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when x"272" => DATA <= x"00";
when x"273" => DATA <= x"21";
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when x"276" => DATA <= x"39";
when x"277" => DATA <= x"EB";
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when x"279" => DATA <= x"AC";
when x"27A" => DATA <= x"3C";
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when x"27C" => DATA <= x"82";
when x"27D" => DATA <= x"0D";
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when x"280" => DATA <= x"31";
when x"281" => DATA <= x"80";
when x"282" => DATA <= x"FF";
when x"283" => DATA <= x"CD";
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when x"285" => DATA <= x"F6";
when x"286" => DATA <= x"3E";
when x"287" => DATA <= x"FF";
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when x"289" => DATA <= x"47";
when x"28A" => DATA <= x"ED";
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when x"28C" => DATA <= x"FB";
when x"28D" => DATA <= x"CD";
when x"28E" => DATA <= x"0E";
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when x"290" => DATA <= x"16";
when x"291" => DATA <= x"08";
when x"292" => DATA <= x"0D";
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when x"294" => DATA <= x"63";
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when x"296" => DATA <= x"72";
when x"297" => DATA <= x"6E";
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when x"299" => DATA <= x"54";
when x"29A" => DATA <= x"55";
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when x"29C" => DATA <= x"45";
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when x"2A0" => DATA <= x"30";
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when x"2A2" => DATA <= x"36";
when x"2A3" => DATA <= x"34";
when x"2A4" => DATA <= x"4B";
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when x"2A6" => DATA <= x"31";
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when x"2A9" => DATA <= x"31";
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when x"2AC" => DATA <= x"00";
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when x"2B2" => DATA <= x"F5";
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when x"2B5" => DATA <= x"21";
when x"2B6" => DATA <= x"00";
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when x"2BB" => DATA <= x"7D";
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when x"2C2" => DATA <= x"21";
when x"2C3" => DATA <= x"01";
when x"2C4" => DATA <= x"00";
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when x"2C8" => DATA <= x"C3";
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when x"2CA" => DATA <= x"F7";
when x"2CB" => DATA <= x"CD";
when x"2CC" => DATA <= x"E7";
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when x"2D0" => DATA <= x"FF";
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when x"2D2" => DATA <= x"80";
when x"2D3" => DATA <= x"FF";
when x"2D4" => DATA <= x"CB";
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when x"2D6" => DATA <= x"28";
when x"2D7" => DATA <= x"08";
when x"2D8" => DATA <= x"3E";
when x"2D9" => DATA <= x"7E";
when x"2DA" => DATA <= x"21";
when x"2DB" => DATA <= x"00";
when x"2DC" => DATA <= x"00";
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when x"2E0" => DATA <= x"3E";
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when x"2E2" => DATA <= x"CD";
when x"2E3" => DATA <= x"71";
when x"2E4" => DATA <= x"F6";
when x"2E5" => DATA <= x"21";
when x"2E6" => DATA <= x"9D";
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when x"2E8" => DATA <= x"AF";
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when x"2EA" => DATA <= x"EF";
when x"2EB" => DATA <= x"F8";
when x"2EC" => DATA <= x"DA";
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when x"2EE" => DATA <= x"F2";
when x"2EF" => DATA <= x"21";
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when x"2F2" => DATA <= x"CD";
when x"2F3" => DATA <= x"B7";
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when x"2F5" => DATA <= x"18";
when x"2F6" => DATA <= x"D7";
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when x"2FD" => DATA <= x"8E";
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when x"300" => DATA <= x"11";
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when x"305" => DATA <= x"70";
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when x"310" => DATA <= x"F7";
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when x"314" => DATA <= x"06";
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when x"319" => DATA <= x"CD";
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when x"31C" => DATA <= x"FE";
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when x"31F" => DATA <= x"CC";
when x"320" => DATA <= x"F7";
when x"321" => DATA <= x"3A";
when x"322" => DATA <= x"AA";
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when x"324" => DATA <= x"32";
when x"325" => DATA <= x"A8";
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when x"328" => DATA <= x"AB";
when x"329" => DATA <= x"FC";
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when x"32B" => DATA <= x"A9";
when x"32C" => DATA <= x"FC";
when x"32D" => DATA <= x"C3";
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when x"32F" => DATA <= x"F7";
when x"330" => DATA <= x"CD";
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when x"333" => DATA <= x"06";
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when x"336" => DATA <= x"39";
when x"337" => DATA <= x"F4";
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when x"33A" => DATA <= x"F8";
when x"33B" => DATA <= x"FE";
when x"33C" => DATA <= x"0D";
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when x"340" => DATA <= x"3E";
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when x"342" => DATA <= x"21";
when x"343" => DATA <= x"01";
when x"344" => DATA <= x"00";
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when x"347" => DATA <= x"FF";
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when x"349" => DATA <= x"32";
when x"34A" => DATA <= x"AE";
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when x"34C" => DATA <= x"2A";
when x"34D" => DATA <= x"AA";
when x"34E" => DATA <= x"FC";
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when x"350" => DATA <= x"E7";
when x"351" => DATA <= x"FF";
when x"352" => DATA <= x"CD";
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when x"354" => DATA <= x"F4";
when x"355" => DATA <= x"CD";
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when x"357" => DATA <= x"F4";
when x"358" => DATA <= x"7E";
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when x"35C" => DATA <= x"CD";
when x"35D" => DATA <= x"1D";
when x"35E" => DATA <= x"F4";
when x"35F" => DATA <= x"7E";
when x"360" => DATA <= x"CD";
when x"361" => DATA <= x"76";
when x"362" => DATA <= x"F4";
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when x"364" => DATA <= x"06";
when x"365" => DATA <= x"01";
when x"366" => DATA <= x"21";
when x"367" => DATA <= x"00";
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when x"36C" => DATA <= x"CD";
when x"36D" => DATA <= x"40";
when x"36E" => DATA <= x"F4";
when x"36F" => DATA <= x"06";
when x"370" => DATA <= x"00";
when x"371" => DATA <= x"5D";
when x"372" => DATA <= x"E1";
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when x"374" => DATA <= x"8A";
when x"375" => DATA <= x"28";
when x"376" => DATA <= x"27";
when x"377" => DATA <= x"FE";
when x"378" => DATA <= x"8B";
when x"379" => DATA <= x"28";
when x"37A" => DATA <= x"20";
when x"37B" => DATA <= x"FE";
when x"37C" => DATA <= x"01";
when x"37D" => DATA <= x"C2";
when x"37E" => DATA <= x"A1";
when x"37F" => DATA <= x"F3";
when x"380" => DATA <= x"7E";
when x"381" => DATA <= x"CB";
when x"382" => DATA <= x"27";
when x"383" => DATA <= x"CB";
when x"384" => DATA <= x"27";
when x"385" => DATA <= x"CB";
when x"386" => DATA <= x"27";
when x"387" => DATA <= x"CB";
when x"388" => DATA <= x"27";
when x"389" => DATA <= x"83";
when x"38A" => DATA <= x"77";
when x"38B" => DATA <= x"3E";
when x"38C" => DATA <= x"08";
when x"38D" => DATA <= x"CD";
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when x"38F" => DATA <= x"F6";
when x"390" => DATA <= x"CD";
when x"391" => DATA <= x"71";
when x"392" => DATA <= x"F6";
when x"393" => DATA <= x"CD";
when x"394" => DATA <= x"71";
when x"395" => DATA <= x"F6";
when x"396" => DATA <= x"CD";
when x"397" => DATA <= x"71";
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when x"399" => DATA <= x"18";
when x"39A" => DATA <= x"BD";
when x"39B" => DATA <= x"23";
when x"39C" => DATA <= x"18";
when x"39D" => DATA <= x"B1";
when x"39E" => DATA <= x"2B";
when x"39F" => DATA <= x"18";
when x"3A0" => DATA <= x"AE";
when x"3A1" => DATA <= x"3A";
when x"3A2" => DATA <= x"AE";
when x"3A3" => DATA <= x"FC";
when x"3A4" => DATA <= x"6F";
when x"3A5" => DATA <= x"26";
when x"3A6" => DATA <= x"00";
when x"3A7" => DATA <= x"3E";
when x"3A8" => DATA <= x"04";
when x"3A9" => DATA <= x"CD";
when x"3AA" => DATA <= x"F4";
when x"3AB" => DATA <= x"FF";
when x"3AC" => DATA <= x"CD";
when x"3AD" => DATA <= x"E7";
when x"3AE" => DATA <= x"FF";
when x"3AF" => DATA <= x"D1";
when x"3B0" => DATA <= x"C1";
when x"3B1" => DATA <= x"F1";
when x"3B2" => DATA <= x"C9";
when x"3B3" => DATA <= x"CD";
when x"3B4" => DATA <= x"76";
when x"3B5" => DATA <= x"F8";
when x"3B6" => DATA <= x"06";
when x"3B7" => DATA <= x"00";
when x"3B8" => DATA <= x"CD";
when x"3B9" => DATA <= x"39";
when x"3BA" => DATA <= x"F4";
when x"3BB" => DATA <= x"FE";
when x"3BC" => DATA <= x"0D";
when x"3BD" => DATA <= x"28";
when x"3BE" => DATA <= x"10";
when x"3BF" => DATA <= x"FE";
when x"3C0" => DATA <= x"20";
when x"3C1" => DATA <= x"C2";
when x"3C2" => DATA <= x"CC";
when x"3C3" => DATA <= x"F7";
when x"3C4" => DATA <= x"2A";
when x"3C5" => DATA <= x"AA";
when x"3C6" => DATA <= x"FC";
when x"3C7" => DATA <= x"CD";
when x"3C8" => DATA <= x"77";
when x"3C9" => DATA <= x"F8";
when x"3CA" => DATA <= x"CD";
when x"3CB" => DATA <= x"39";
when x"3CC" => DATA <= x"F4";
when x"3CD" => DATA <= x"18";
when x"3CE" => DATA <= x"03";
when x"3CF" => DATA <= x"2A";
when x"3D0" => DATA <= x"AA";
when x"3D1" => DATA <= x"FC";
when x"3D2" => DATA <= x"ED";
when x"3D3" => DATA <= x"5B";
when x"3D4" => DATA <= x"AA";
when x"3D5" => DATA <= x"FC";
when x"3D6" => DATA <= x"3A";
when x"3D7" => DATA <= x"80";
when x"3D8" => DATA <= x"FF";
when x"3D9" => DATA <= x"CB";
when x"3DA" => DATA <= x"7F";
when x"3DB" => DATA <= x"C2";
when x"3DC" => DATA <= x"F7";
when x"3DD" => DATA <= x"F2";
when x"3DE" => DATA <= x"CD";
when x"3DF" => DATA <= x"E7";
when x"3E0" => DATA <= x"FF";
when x"3E1" => DATA <= x"CD";
when x"3E2" => DATA <= x"71";
when x"3E3" => DATA <= x"F4";
when x"3E4" => DATA <= x"06";
when x"3E5" => DATA <= x"08";
when x"3E6" => DATA <= x"E5";
when x"3E7" => DATA <= x"CD";
when x"3E8" => DATA <= x"1D";
when x"3E9" => DATA <= x"F4";
when x"3EA" => DATA <= x"7E";
when x"3EB" => DATA <= x"CD";
when x"3EC" => DATA <= x"76";
when x"3ED" => DATA <= x"F4";
when x"3EE" => DATA <= x"23";
when x"3EF" => DATA <= x"10";
when x"3F0" => DATA <= x"F6";
when x"3F1" => DATA <= x"06";
when x"3F2" => DATA <= x"08";
when x"3F3" => DATA <= x"E1";
when x"3F4" => DATA <= x"CD";
when x"3F5" => DATA <= x"1D";
when x"3F6" => DATA <= x"F4";
when x"3F7" => DATA <= x"7E";
when x"3F8" => DATA <= x"CD";
when x"3F9" => DATA <= x"0D";
when x"3FA" => DATA <= x"F4";
when x"3FB" => DATA <= x"23";
when x"3FC" => DATA <= x"10";
when x"3FD" => DATA <= x"F9";
when x"3FE" => DATA <= x"CD";
when x"3FF" => DATA <= x"23";
when x"400" => DATA <= x"F4";
when x"401" => DATA <= x"D2";
when x"402" => DATA <= x"06";
when x"403" => DATA <= x"F4";
when x"404" => DATA <= x"18";
when x"405" => DATA <= x"D0";
when x"406" => DATA <= x"CD";
when x"407" => DATA <= x"E7";
when x"408" => DATA <= x"FF";
when x"409" => DATA <= x"D1";
when x"40A" => DATA <= x"C1";
when x"40B" => DATA <= x"F1";
when x"40C" => DATA <= x"C9";
when x"40D" => DATA <= x"FE";
when x"40E" => DATA <= x"20";
when x"40F" => DATA <= x"38";
when x"410" => DATA <= x"06";
when x"411" => DATA <= x"FE";
when x"412" => DATA <= x"7F";
when x"413" => DATA <= x"30";
when x"414" => DATA <= x"02";
when x"415" => DATA <= x"18";
when x"416" => DATA <= x"02";
when x"417" => DATA <= x"3E";
when x"418" => DATA <= x"2E";
when x"419" => DATA <= x"CD";
when x"41A" => DATA <= x"71";
when x"41B" => DATA <= x"F6";
when x"41C" => DATA <= x"C9";
when x"41D" => DATA <= x"3E";
when x"41E" => DATA <= x"20";
when x"41F" => DATA <= x"CD";
when x"420" => DATA <= x"71";
when x"421" => DATA <= x"F6";
when x"422" => DATA <= x"C9";
when x"423" => DATA <= x"E5";
when x"424" => DATA <= x"01";
when x"425" => DATA <= x"08";
when x"426" => DATA <= x"00";
when x"427" => DATA <= x"BF";
when x"428" => DATA <= x"ED";
when x"429" => DATA <= x"42";
when x"42A" => DATA <= x"30";
when x"42B" => DATA <= x"06";
when x"42C" => DATA <= x"21";
when x"42D" => DATA <= x"00";
when x"42E" => DATA <= x"00";
when x"42F" => DATA <= x"BF";
when x"430" => DATA <= x"18";
when x"431" => DATA <= x"02";
when x"432" => DATA <= x"E1";
when x"433" => DATA <= x"E5";
when x"434" => DATA <= x"2B";
when x"435" => DATA <= x"ED";
when x"436" => DATA <= x"52";
when x"437" => DATA <= x"E1";
when x"438" => DATA <= x"C9";
when x"439" => DATA <= x"22";
when x"43A" => DATA <= x"AC";
when x"43B" => DATA <= x"FC";
when x"43C" => DATA <= x"21";
when x"43D" => DATA <= x"00";
when x"43E" => DATA <= x"00";
when x"43F" => DATA <= x"1A";
when x"440" => DATA <= x"CB";
when x"441" => DATA <= x"77";
when x"442" => DATA <= x"28";
when x"443" => DATA <= x"02";
when x"444" => DATA <= x"E6";
when x"445" => DATA <= x"DF";
when x"446" => DATA <= x"FE";
when x"447" => DATA <= x"30";
when x"448" => DATA <= x"FA";
when x"449" => DATA <= x"6D";
when x"44A" => DATA <= x"F4";
when x"44B" => DATA <= x"FE";
when x"44C" => DATA <= x"47";
when x"44D" => DATA <= x"F2";
when x"44E" => DATA <= x"6D";
when x"44F" => DATA <= x"F4";
when x"450" => DATA <= x"FE";
when x"451" => DATA <= x"3A";
when x"452" => DATA <= x"38";
when x"453" => DATA <= x"07";
when x"454" => DATA <= x"FE";
when x"455" => DATA <= x"41";
when x"456" => DATA <= x"FA";
when x"457" => DATA <= x"6D";
when x"458" => DATA <= x"F4";
when x"459" => DATA <= x"C6";
when x"45A" => DATA <= x"09";
when x"45B" => DATA <= x"E6";
when x"45C" => DATA <= x"0F";
when x"45D" => DATA <= x"29";
when x"45E" => DATA <= x"29";
when x"45F" => DATA <= x"29";
when x"460" => DATA <= x"29";
when x"461" => DATA <= x"B5";
when x"462" => DATA <= x"6F";
when x"463" => DATA <= x"3E";
when x"464" => DATA <= x"01";
when x"465" => DATA <= x"B8";
when x"466" => DATA <= x"C8";
when x"467" => DATA <= x"13";
when x"468" => DATA <= x"22";
when x"469" => DATA <= x"AA";
when x"46A" => DATA <= x"FC";
when x"46B" => DATA <= x"18";
when x"46C" => DATA <= x"D2";
when x"46D" => DATA <= x"2A";
when x"46E" => DATA <= x"AC";
when x"46F" => DATA <= x"FC";
when x"470" => DATA <= x"C9";
when x"471" => DATA <= x"7C";
when x"472" => DATA <= x"CD";
when x"473" => DATA <= x"76";
when x"474" => DATA <= x"F4";
when x"475" => DATA <= x"7D";
when x"476" => DATA <= x"F5";
when x"477" => DATA <= x"0F";
when x"478" => DATA <= x"0F";
when x"479" => DATA <= x"0F";
when x"47A" => DATA <= x"0F";
when x"47B" => DATA <= x"CD";
when x"47C" => DATA <= x"7F";
when x"47D" => DATA <= x"F4";
when x"47E" => DATA <= x"F1";
when x"47F" => DATA <= x"E6";
when x"480" => DATA <= x"0F";
when x"481" => DATA <= x"C6";
when x"482" => DATA <= x"30";
when x"483" => DATA <= x"FE";
when x"484" => DATA <= x"3A";
when x"485" => DATA <= x"FA";
when x"486" => DATA <= x"71";
when x"487" => DATA <= x"F6";
when x"488" => DATA <= x"C6";
when x"489" => DATA <= x"07";
when x"48A" => DATA <= x"C3";
when x"48B" => DATA <= x"71";
when x"48C" => DATA <= x"F6";
when x"48D" => DATA <= x"13";
when x"48E" => DATA <= x"1A";
when x"48F" => DATA <= x"E6";
when x"490" => DATA <= x"DF";
when x"491" => DATA <= x"FE";
when x"492" => DATA <= x"50";
when x"493" => DATA <= x"C2";
when x"494" => DATA <= x"CC";
when x"495" => DATA <= x"F7";
when x"496" => DATA <= x"13";
when x"497" => DATA <= x"1A";
when x"498" => DATA <= x"E6";
when x"499" => DATA <= x"DF";
when x"49A" => DATA <= x"FE";
when x"49B" => DATA <= x"4D";
when x"49C" => DATA <= x"C2";
when x"49D" => DATA <= x"CC";
when x"49E" => DATA <= x"F7";
when x"49F" => DATA <= x"CD";
when x"4A0" => DATA <= x"76";
when x"4A1" => DATA <= x"F8";
when x"4A2" => DATA <= x"FE";
when x"4A3" => DATA <= x"0D";
when x"4A4" => DATA <= x"C2";
when x"4A5" => DATA <= x"CC";
when x"4A6" => DATA <= x"F7";
when x"4A7" => DATA <= x"18";
when x"4A8" => DATA <= x"26";
when x"4A9" => DATA <= x"CD";
when x"4AA" => DATA <= x"0E";
when x"4AB" => DATA <= x"F6";
when x"4AC" => DATA <= x"49";
when x"4AD" => DATA <= x"6E";
when x"4AE" => DATA <= x"73";
when x"4AF" => DATA <= x"65";
when x"4B0" => DATA <= x"72";
when x"4B1" => DATA <= x"74";
when x"4B2" => DATA <= x"20";
when x"4B3" => DATA <= x"43";
when x"4B4" => DATA <= x"50";
when x"4B5" => DATA <= x"2F";
when x"4B6" => DATA <= x"4D";
when x"4B7" => DATA <= x"20";
when x"4B8" => DATA <= x"53";
when x"4B9" => DATA <= x"79";
when x"4BA" => DATA <= x"73";
when x"4BB" => DATA <= x"74";
when x"4BC" => DATA <= x"65";
when x"4BD" => DATA <= x"6D";
when x"4BE" => DATA <= x"20";
when x"4BF" => DATA <= x"64";
when x"4C0" => DATA <= x"69";
when x"4C1" => DATA <= x"73";
when x"4C2" => DATA <= x"63";
when x"4C3" => DATA <= x"20";
when x"4C4" => DATA <= x"69";
when x"4C5" => DATA <= x"6E";
when x"4C6" => DATA <= x"20";
when x"4C7" => DATA <= x"64";
when x"4C8" => DATA <= x"72";
when x"4C9" => DATA <= x"69";
when x"4CA" => DATA <= x"76";
when x"4CB" => DATA <= x"65";
when x"4CC" => DATA <= x"20";
when x"4CD" => DATA <= x"41";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"3E";
when x"4D0" => DATA <= x"E5";
when x"4D1" => DATA <= x"21";
when x"4D2" => DATA <= x"01";
when x"4D3" => DATA <= x"00";
when x"4D4" => DATA <= x"CD";
when x"4D5" => DATA <= x"8E";
when x"4D6" => DATA <= x"F8";
when x"4D7" => DATA <= x"21";
when x"4D8" => DATA <= x"82";
when x"4D9" => DATA <= x"F5";
when x"4DA" => DATA <= x"CD";
when x"4DB" => DATA <= x"4A";
when x"4DC" => DATA <= x"F5";
when x"4DD" => DATA <= x"21";
when x"4DE" => DATA <= x"00";
when x"4DF" => DATA <= x"EB";
when x"4E0" => DATA <= x"11";
when x"4E1" => DATA <= x"F0";
when x"4E2" => DATA <= x"EA";
when x"4E3" => DATA <= x"01";
when x"4E4" => DATA <= x"F0";
when x"4E5" => DATA <= x"00";
when x"4E6" => DATA <= x"ED";
when x"4E7" => DATA <= x"B0";
when x"4E8" => DATA <= x"21";
when x"4E9" => DATA <= x"F0";
when x"4EA" => DATA <= x"EB";
when x"4EB" => DATA <= x"11";
when x"4EC" => DATA <= x"E0";
when x"4ED" => DATA <= x"EB";
when x"4EE" => DATA <= x"01";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"06";
when x"4F1" => DATA <= x"ED";
when x"4F2" => DATA <= x"B0";
when x"4F3" => DATA <= x"CD";
when x"4F4" => DATA <= x"3B";
when x"4F5" => DATA <= x"F5";
when x"4F6" => DATA <= x"3A";
when x"4F7" => DATA <= x"00";
when x"4F8" => DATA <= x"D4";
when x"4F9" => DATA <= x"FE";
when x"4FA" => DATA <= x"C3";
when x"4FB" => DATA <= x"CA";
when x"4FC" => DATA <= x"22";
when x"4FD" => DATA <= x"F5";
when x"4FE" => DATA <= x"3E";
when x"4FF" => DATA <= x"E5";
when x"500" => DATA <= x"21";
when x"501" => DATA <= x"00";
when x"502" => DATA <= x"00";
when x"503" => DATA <= x"CD";
when x"504" => DATA <= x"8E";
when x"505" => DATA <= x"F8";
when x"506" => DATA <= x"CD";
when x"507" => DATA <= x"E7";
when x"508" => DATA <= x"FF";
when x"509" => DATA <= x"FF";
when x"50A" => DATA <= x"C8";
when x"50B" => DATA <= x"4E";
when x"50C" => DATA <= x"6F";
when x"50D" => DATA <= x"74";
when x"50E" => DATA <= x"20";
when x"50F" => DATA <= x"61";
when x"510" => DATA <= x"20";
when x"511" => DATA <= x"43";
when x"512" => DATA <= x"50";
when x"513" => DATA <= x"2F";
when x"514" => DATA <= x"4D";
when x"515" => DATA <= x"20";
when x"516" => DATA <= x"53";
when x"517" => DATA <= x"79";
when x"518" => DATA <= x"73";
when x"519" => DATA <= x"74";
when x"51A" => DATA <= x"65";
when x"51B" => DATA <= x"6D";
when x"51C" => DATA <= x"20";
when x"51D" => DATA <= x"64";
when x"51E" => DATA <= x"69";
when x"51F" => DATA <= x"73";
when x"520" => DATA <= x"63";
when x"521" => DATA <= x"00";
when x"522" => DATA <= x"21";
when x"523" => DATA <= x"B2";
when x"524" => DATA <= x"FA";
when x"525" => DATA <= x"22";
when x"526" => DATA <= x"FA";
when x"527" => DATA <= x"FF";
when x"528" => DATA <= x"3E";
when x"529" => DATA <= x"90";
when x"52A" => DATA <= x"32";
when x"52B" => DATA <= x"A3";
when x"52C" => DATA <= x"FC";
when x"52D" => DATA <= x"21";
when x"52E" => DATA <= x"00";
when x"52F" => DATA <= x"01";
when x"530" => DATA <= x"CD";
when x"531" => DATA <= x"8E";
when x"532" => DATA <= x"F8";
when x"533" => DATA <= x"CD";
when x"534" => DATA <= x"0E";
when x"535" => DATA <= x"F6";
when x"536" => DATA <= x"16";
when x"537" => DATA <= x"00";
when x"538" => DATA <= x"C3";
when x"539" => DATA <= x"00";
when x"53A" => DATA <= x"EA";
when x"53B" => DATA <= x"21";
when x"53C" => DATA <= x"8D";
when x"53D" => DATA <= x"F5";
when x"53E" => DATA <= x"CD";
when x"53F" => DATA <= x"4A";
when x"540" => DATA <= x"F5";
when x"541" => DATA <= x"21";
when x"542" => DATA <= x"98";
when x"543" => DATA <= x"F5";
when x"544" => DATA <= x"CD";
when x"545" => DATA <= x"4A";
when x"546" => DATA <= x"F5";
when x"547" => DATA <= x"21";
when x"548" => DATA <= x"A3";
when x"549" => DATA <= x"F5";
when x"54A" => DATA <= x"CD";
when x"54B" => DATA <= x"5C";
when x"54C" => DATA <= x"F5";
when x"54D" => DATA <= x"B7";
when x"54E" => DATA <= x"C8";
when x"54F" => DATA <= x"FF";
when x"550" => DATA <= x"C7";
when x"551" => DATA <= x"44";
when x"552" => DATA <= x"69";
when x"553" => DATA <= x"73";
when x"554" => DATA <= x"63";
when x"555" => DATA <= x"20";
when x"556" => DATA <= x"66";
when x"557" => DATA <= x"61";
when x"558" => DATA <= x"75";
when x"559" => DATA <= x"6C";
when x"55A" => DATA <= x"74";
when x"55B" => DATA <= x"00";
when x"55C" => DATA <= x"06";
when x"55D" => DATA <= x"04";
when x"55E" => DATA <= x"48";
when x"55F" => DATA <= x"06";
when x"560" => DATA <= x"0A";
when x"561" => DATA <= x"3E";
when x"562" => DATA <= x"7F";
when x"563" => DATA <= x"CD";
when x"564" => DATA <= x"EF";
when x"565" => DATA <= x"F8";
when x"566" => DATA <= x"11";
when x"567" => DATA <= x"0A";
when x"568" => DATA <= x"00";
when x"569" => DATA <= x"EB";
when x"56A" => DATA <= x"19";
when x"56B" => DATA <= x"7E";
when x"56C" => DATA <= x"32";
when x"56D" => DATA <= x"A7";
when x"56E" => DATA <= x"FC";
when x"56F" => DATA <= x"EB";
when x"570" => DATA <= x"FE";
when x"571" => DATA <= x"12";
when x"572" => DATA <= x"C8";
when x"573" => DATA <= x"B7";
when x"574" => DATA <= x"C8";
when x"575" => DATA <= x"10";
when x"576" => DATA <= x"EA";
when x"577" => DATA <= x"7E";
when x"578" => DATA <= x"CD";
when x"579" => DATA <= x"1B";
when x"57A" => DATA <= x"F6";
when x"57B" => DATA <= x"41";
when x"57C" => DATA <= x"10";
when x"57D" => DATA <= x"E0";
when x"57E" => DATA <= x"3A";
when x"57F" => DATA <= x"A7";
when x"580" => DATA <= x"FC";
when x"581" => DATA <= x"C9";
when x"582" => DATA <= x"00";
when x"583" => DATA <= x"F0";
when x"584" => DATA <= x"E9";
when x"585" => DATA <= x"00";
when x"586" => DATA <= x"00";
when x"587" => DATA <= x"03";
when x"588" => DATA <= x"53";
when x"589" => DATA <= x"00";
when x"58A" => DATA <= x"00";
when x"58B" => DATA <= x"28";
when x"58C" => DATA <= x"FF";
when x"58D" => DATA <= x"00";
when x"58E" => DATA <= x"00";
when x"58F" => DATA <= x"D4";
when x"590" => DATA <= x"00";
when x"591" => DATA <= x"00";
when x"592" => DATA <= x"03";
when x"593" => DATA <= x"53";
when x"594" => DATA <= x"00";
when x"595" => DATA <= x"08";
when x"596" => DATA <= x"22";
when x"597" => DATA <= x"FF";
when x"598" => DATA <= x"00";
when x"599" => DATA <= x"00";
when x"59A" => DATA <= x"D6";
when x"59B" => DATA <= x"00";
when x"59C" => DATA <= x"00";
when x"59D" => DATA <= x"03";
when x"59E" => DATA <= x"53";
when x"59F" => DATA <= x"01";
when x"5A0" => DATA <= x"00";
when x"5A1" => DATA <= x"2A";
when x"5A2" => DATA <= x"FF";
when x"5A3" => DATA <= x"00";
when x"5A4" => DATA <= x"00";
when x"5A5" => DATA <= x"E0";
when x"5A6" => DATA <= x"00";
when x"5A7" => DATA <= x"00";
when x"5A8" => DATA <= x"03";
when x"5A9" => DATA <= x"53";
when x"5AA" => DATA <= x"02";
when x"5AB" => DATA <= x"00";
when x"5AC" => DATA <= x"2A";
when x"5AD" => DATA <= x"FF";
when x"5AE" => DATA <= x"F3";
when x"5AF" => DATA <= x"21";
when x"5B0" => DATA <= x"00";
when x"5B1" => DATA <= x"25";
when x"5B2" => DATA <= x"11";
when x"5B3" => DATA <= x"30";
when x"5B4" => DATA <= x"FD";
when x"5B5" => DATA <= x"06";
when x"5B6" => DATA <= x"AA";
when x"5B7" => DATA <= x"CD";
when x"5B8" => DATA <= x"F3";
when x"5B9" => DATA <= x"F5";
when x"5BA" => DATA <= x"21";
when x"5BB" => DATA <= x"00";
when x"5BC" => DATA <= x"02";
when x"5BD" => DATA <= x"11";
when x"5BE" => DATA <= x"DC";
when x"5BF" => DATA <= x"FD";
when x"5C0" => DATA <= x"06";
when x"5C1" => DATA <= x"02";
when x"5C2" => DATA <= x"CD";
when x"5C3" => DATA <= x"DD";
when x"5C4" => DATA <= x"F5";
when x"5C5" => DATA <= x"21";
when x"5C6" => DATA <= x"03";
when x"5C7" => DATA <= x"25";
when x"5C8" => DATA <= x"11";
when x"5C9" => DATA <= x"DC";
when x"5CA" => DATA <= x"FD";
when x"5CB" => DATA <= x"06";
when x"5CC" => DATA <= x"02";
when x"5CD" => DATA <= x"CD";
when x"5CE" => DATA <= x"F3";
when x"5CF" => DATA <= x"F5";
when x"5D0" => DATA <= x"21";
when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"02";
when x"5D3" => DATA <= x"11";
when x"5D4" => DATA <= x"DA";
when x"5D5" => DATA <= x"FD";
when x"5D6" => DATA <= x"06";
when x"5D7" => DATA <= x"02";
when x"5D8" => DATA <= x"CD";
when x"5D9" => DATA <= x"F3";
when x"5DA" => DATA <= x"F5";
when x"5DB" => DATA <= x"FB";
when x"5DC" => DATA <= x"C9";
when x"5DD" => DATA <= x"22";
when x"5DE" => DATA <= x"09";
when x"5DF" => DATA <= x"F6";
when x"5E0" => DATA <= x"E5";
when x"5E1" => DATA <= x"21";
when x"5E2" => DATA <= x"09";
when x"5E3" => DATA <= x"F6";
when x"5E4" => DATA <= x"3E";
when x"5E5" => DATA <= x"05";
when x"5E6" => DATA <= x"CD";
when x"5E7" => DATA <= x"F1";
when x"5E8" => DATA <= x"FF";
when x"5E9" => DATA <= x"3A";
when x"5EA" => DATA <= x"0D";
when x"5EB" => DATA <= x"F6";
when x"5EC" => DATA <= x"12";
when x"5ED" => DATA <= x"13";
when x"5EE" => DATA <= x"E1";
when x"5EF" => DATA <= x"23";
when x"5F0" => DATA <= x"10";
when x"5F1" => DATA <= x"EB";
when x"5F2" => DATA <= x"C9";
when x"5F3" => DATA <= x"22";
when x"5F4" => DATA <= x"09";
when x"5F5" => DATA <= x"F6";
when x"5F6" => DATA <= x"1A";
when x"5F7" => DATA <= x"32";
when x"5F8" => DATA <= x"0D";
when x"5F9" => DATA <= x"F6";
when x"5FA" => DATA <= x"E5";
when x"5FB" => DATA <= x"21";
when x"5FC" => DATA <= x"09";
when x"5FD" => DATA <= x"F6";
when x"5FE" => DATA <= x"3E";
when x"5FF" => DATA <= x"06";
when x"600" => DATA <= x"CD";
when x"601" => DATA <= x"F1";
when x"602" => DATA <= x"FF";
when x"603" => DATA <= x"13";
when x"604" => DATA <= x"E1";
when x"605" => DATA <= x"23";
when x"606" => DATA <= x"10";
when x"607" => DATA <= x"EB";
when x"608" => DATA <= x"C9";
when x"609" => DATA <= x"00";
when x"60A" => DATA <= x"00";
when x"60B" => DATA <= x"00";
when x"60C" => DATA <= x"00";
when x"60D" => DATA <= x"00";
when x"60E" => DATA <= x"E3";
when x"60F" => DATA <= x"F5";
when x"610" => DATA <= x"7E";
when x"611" => DATA <= x"CD";
when x"612" => DATA <= x"E3";
when x"613" => DATA <= x"FF";
when x"614" => DATA <= x"23";
when x"615" => DATA <= x"B7";
when x"616" => DATA <= x"20";
when x"617" => DATA <= x"F8";
when x"618" => DATA <= x"F1";
when x"619" => DATA <= x"E3";
when x"61A" => DATA <= x"C9";
when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"E5";
when x"61D" => DATA <= x"32";
when x"61E" => DATA <= x"36";
when x"61F" => DATA <= x"F6";
when x"620" => DATA <= x"21";
when x"621" => DATA <= x"36";
when x"622" => DATA <= x"F6";
when x"623" => DATA <= x"3E";
when x"624" => DATA <= x"7F";
when x"625" => DATA <= x"ED";
when x"626" => DATA <= x"73";
when x"627" => DATA <= x"A5";
when x"628" => DATA <= x"FC";
when x"629" => DATA <= x"31";
when x"62A" => DATA <= x"80";
when x"62B" => DATA <= x"FF";
when x"62C" => DATA <= x"CD";
when x"62D" => DATA <= x"EF";
when x"62E" => DATA <= x"F8";
when x"62F" => DATA <= x"ED";
when x"630" => DATA <= x"7B";
when x"631" => DATA <= x"A5";
when x"632" => DATA <= x"FC";
when x"633" => DATA <= x"E1";
when x"634" => DATA <= x"F1";
when x"635" => DATA <= x"C9";
when x"636" => DATA <= x"00";
when x"637" => DATA <= x"00";
when x"638" => DATA <= x"00";
when x"639" => DATA <= x"00";
when x"63A" => DATA <= x"00";
when x"63B" => DATA <= x"01";
when x"63C" => DATA <= x"69";
when x"63D" => DATA <= x"00";
when x"63E" => DATA <= x"00";
when x"63F" => DATA <= x"E5";
when x"640" => DATA <= x"21";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"3E";
when x"644" => DATA <= x"80";
when x"645" => DATA <= x"CD";
when x"646" => DATA <= x"8E";
when x"647" => DATA <= x"F8";
when x"648" => DATA <= x"7D";
when x"649" => DATA <= x"B7";
when x"64A" => DATA <= x"28";
when x"64B" => DATA <= x"02";
when x"64C" => DATA <= x"18";
when x"64D" => DATA <= x"0C";
when x"64E" => DATA <= x"3E";
when x"64F" => DATA <= x"D8";
when x"650" => DATA <= x"21";
when x"651" => DATA <= x"00";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"CD";
when x"654" => DATA <= x"8E";
when x"655" => DATA <= x"F8";
when x"656" => DATA <= x"7D";
when x"657" => DATA <= x"B7";
when x"658" => DATA <= x"28";
when x"659" => DATA <= x"02";
when x"65A" => DATA <= x"3E";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"E1";
when x"65D" => DATA <= x"C9";
when x"65E" => DATA <= x"C5";
when x"65F" => DATA <= x"D5";
when x"660" => DATA <= x"E5";
when x"661" => DATA <= x"21";
when x"662" => DATA <= x"BC";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"11";
when x"665" => DATA <= x"38";
when x"666" => DATA <= x"00";
when x"667" => DATA <= x"01";
when x"668" => DATA <= x"03";
when x"669" => DATA <= x"00";
when x"66A" => DATA <= x"ED";
when x"66B" => DATA <= x"B0";
when x"66C" => DATA <= x"E1";
when x"66D" => DATA <= x"D1";
when x"66E" => DATA <= x"C1";
when x"66F" => DATA <= x"C9";
when x"670" => DATA <= x"C9";
when x"671" => DATA <= x"F5";
when x"672" => DATA <= x"DB";
when x"673" => DATA <= x"00";
when x"674" => DATA <= x"CB";
when x"675" => DATA <= x"77";
when x"676" => DATA <= x"28";
when x"677" => DATA <= x"FA";
when x"678" => DATA <= x"F1";
when x"679" => DATA <= x"D3";
when x"67A" => DATA <= x"01";
when x"67B" => DATA <= x"C9";
when x"67C" => DATA <= x"DB";
when x"67D" => DATA <= x"00";
when x"67E" => DATA <= x"CB";
when x"67F" => DATA <= x"7F";
when x"680" => DATA <= x"20";
when x"681" => DATA <= x"0B";
when x"682" => DATA <= x"DB";
when x"683" => DATA <= x"06";
when x"684" => DATA <= x"CB";
when x"685" => DATA <= x"7F";
when x"686" => DATA <= x"28";
when x"687" => DATA <= x"F4";
when x"688" => DATA <= x"CD";
when x"689" => DATA <= x"0B";
when x"68A" => DATA <= x"FB";
when x"68B" => DATA <= x"18";
when x"68C" => DATA <= x"EF";
when x"68D" => DATA <= x"DB";
when x"68E" => DATA <= x"01";
when x"68F" => DATA <= x"C9";
when x"690" => DATA <= x"3E";
when x"691" => DATA <= x"00";
when x"692" => DATA <= x"CD";
when x"693" => DATA <= x"A3";
when x"694" => DATA <= x"F6";
when x"695" => DATA <= x"CD";
when x"696" => DATA <= x"9A";
when x"697" => DATA <= x"F6";
when x"698" => DATA <= x"CB";
when x"699" => DATA <= x"27";
when x"69A" => DATA <= x"DB";
when x"69B" => DATA <= x"02";
when x"69C" => DATA <= x"CB";
when x"69D" => DATA <= x"7F";
when x"69E" => DATA <= x"28";
when x"69F" => DATA <= x"FA";
when x"6A0" => DATA <= x"DB";
when x"6A1" => DATA <= x"03";
when x"6A2" => DATA <= x"C9";
when x"6A3" => DATA <= x"F5";
when x"6A4" => DATA <= x"DB";
when x"6A5" => DATA <= x"02";
when x"6A6" => DATA <= x"CB";
when x"6A7" => DATA <= x"77";
when x"6A8" => DATA <= x"28";
when x"6A9" => DATA <= x"FA";
when x"6AA" => DATA <= x"F1";
when x"6AB" => DATA <= x"D3";
when x"6AC" => DATA <= x"03";
when x"6AD" => DATA <= x"C9";
when x"6AE" => DATA <= x"DB";
when x"6AF" => DATA <= x"06";
when x"6B0" => DATA <= x"CB";
when x"6B1" => DATA <= x"7F";
when x"6B2" => DATA <= x"28";
when x"6B3" => DATA <= x"FA";
when x"6B4" => DATA <= x"DB";
when x"6B5" => DATA <= x"07";
when x"6B6" => DATA <= x"C9";
when x"6B7" => DATA <= x"F5";
when x"6B8" => DATA <= x"C5";
when x"6B9" => DATA <= x"D5";
when x"6BA" => DATA <= x"54";
when x"6BB" => DATA <= x"5D";
when x"6BC" => DATA <= x"CD";
when x"6BD" => DATA <= x"7E";
when x"6BE" => DATA <= x"F8";
when x"6BF" => DATA <= x"CD";
when x"6C0" => DATA <= x"77";
when x"6C1" => DATA <= x"F8";
when x"6C2" => DATA <= x"FE";
when x"6C3" => DATA <= x"2A";
when x"6C4" => DATA <= x"28";
when x"6C5" => DATA <= x"F6";
when x"6C6" => DATA <= x"E6";
when x"6C7" => DATA <= x"DF";
when x"6C8" => DATA <= x"FE";
when x"6C9" => DATA <= x"48";
when x"6CA" => DATA <= x"28";
when x"6CB" => DATA <= x"20";
when x"6CC" => DATA <= x"4F";
when x"6CD" => DATA <= x"3A";
when x"6CE" => DATA <= x"A3";
when x"6CF" => DATA <= x"FC";
when x"6D0" => DATA <= x"B7";
when x"6D1" => DATA <= x"79";
when x"6D2" => DATA <= x"C2";
when x"6D3" => DATA <= x"CC";
when x"6D4" => DATA <= x"F7";
when x"6D5" => DATA <= x"FE";
when x"6D6" => DATA <= x"47";
when x"6D7" => DATA <= x"CA";
when x"6D8" => DATA <= x"08";
when x"6D9" => DATA <= x"F3";
when x"6DA" => DATA <= x"FE";
when x"6DB" => DATA <= x"44";
when x"6DC" => DATA <= x"CA";
when x"6DD" => DATA <= x"B3";
when x"6DE" => DATA <= x"F3";
when x"6DF" => DATA <= x"FE";
when x"6E0" => DATA <= x"53";
when x"6E1" => DATA <= x"CA";
when x"6E2" => DATA <= x"30";
when x"6E3" => DATA <= x"F3";
when x"6E4" => DATA <= x"FE";
when x"6E5" => DATA <= x"43";
when x"6E6" => DATA <= x"CA";
when x"6E7" => DATA <= x"8D";
when x"6E8" => DATA <= x"F4";
when x"6E9" => DATA <= x"C3";
when x"6EA" => DATA <= x"CC";
when x"6EB" => DATA <= x"F7";
when x"6EC" => DATA <= x"13";
when x"6ED" => DATA <= x"1A";
when x"6EE" => DATA <= x"FE";
when x"6EF" => DATA <= x"2E";
when x"6F0" => DATA <= x"28";
when x"6F1" => DATA <= x"2E";
when x"6F2" => DATA <= x"E6";
when x"6F3" => DATA <= x"DF";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"45";
when x"6F6" => DATA <= x"C2";
when x"6F7" => DATA <= x"CC";
when x"6F8" => DATA <= x"F7";
when x"6F9" => DATA <= x"13";
when x"6FA" => DATA <= x"1A";
when x"6FB" => DATA <= x"FE";
when x"6FC" => DATA <= x"2E";
when x"6FD" => DATA <= x"28";
when x"6FE" => DATA <= x"21";
when x"6FF" => DATA <= x"E6";
when x"700" => DATA <= x"DF";
when x"701" => DATA <= x"FE";
when x"702" => DATA <= x"4C";
when x"703" => DATA <= x"C2";
when x"704" => DATA <= x"CC";
when x"705" => DATA <= x"F7";
when x"706" => DATA <= x"13";
when x"707" => DATA <= x"1A";
when x"708" => DATA <= x"FE";
when x"709" => DATA <= x"2E";
when x"70A" => DATA <= x"28";
when x"70B" => DATA <= x"14";
when x"70C" => DATA <= x"E6";
when x"70D" => DATA <= x"DF";
when x"70E" => DATA <= x"FE";
when x"70F" => DATA <= x"50";
when x"710" => DATA <= x"C2";
when x"711" => DATA <= x"CC";
when x"712" => DATA <= x"F7";
when x"713" => DATA <= x"13";
when x"714" => DATA <= x"1A";
when x"715" => DATA <= x"CD";
when x"716" => DATA <= x"6D";
when x"717" => DATA <= x"F8";
when x"718" => DATA <= x"D2";
when x"719" => DATA <= x"CC";
when x"71A" => DATA <= x"F7";
when x"71B" => DATA <= x"CD";
when x"71C" => DATA <= x"77";
when x"71D" => DATA <= x"F8";
when x"71E" => DATA <= x"18";
when x"71F" => DATA <= x"03";
when x"720" => DATA <= x"CD";
when x"721" => DATA <= x"76";
when x"722" => DATA <= x"F8";
when x"723" => DATA <= x"CD";
when x"724" => DATA <= x"B3";
when x"725" => DATA <= x"FF";
when x"726" => DATA <= x"0D";
when x"727" => DATA <= x"5A";
when x"728" => DATA <= x"38";
when x"729" => DATA <= x"30";
when x"72A" => DATA <= x"20";
when x"72B" => DATA <= x"54";
when x"72C" => DATA <= x"55";
when x"72D" => DATA <= x"42";
when x"72E" => DATA <= x"45";
when x"72F" => DATA <= x"20";
when x"730" => DATA <= x"31";
when x"731" => DATA <= x"2E";
when x"732" => DATA <= x"32";
when x"733" => DATA <= x"31";
when x"734" => DATA <= x"0D";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"4F";
when x"737" => DATA <= x"3A";
when x"738" => DATA <= x"A3";
when x"739" => DATA <= x"FC";
when x"73A" => DATA <= x"B7";
when x"73B" => DATA <= x"79";
when x"73C" => DATA <= x"C2";
when x"73D" => DATA <= x"CC";
when x"73E" => DATA <= x"F7";
when x"73F" => DATA <= x"FE";
when x"740" => DATA <= x"0D";
when x"741" => DATA <= x"28";
when x"742" => DATA <= x"29";
when x"743" => DATA <= x"E6";
when x"744" => DATA <= x"DF";
when x"745" => DATA <= x"FE";
when x"746" => DATA <= x"4D";
when x"747" => DATA <= x"28";
when x"748" => DATA <= x"09";
when x"749" => DATA <= x"FE";
when x"74A" => DATA <= x"0D";
when x"74B" => DATA <= x"CA";
when x"74C" => DATA <= x"CC";
when x"74D" => DATA <= x"F7";
when x"74E" => DATA <= x"13";
when x"74F" => DATA <= x"1A";
when x"750" => DATA <= x"18";
when x"751" => DATA <= x"F1";
when x"752" => DATA <= x"13";
when x"753" => DATA <= x"1A";
when x"754" => DATA <= x"E6";
when x"755" => DATA <= x"DF";
when x"756" => DATA <= x"FE";
when x"757" => DATA <= x"4F";
when x"758" => DATA <= x"20";
when x"759" => DATA <= x"F4";
when x"75A" => DATA <= x"13";
when x"75B" => DATA <= x"1A";
when x"75C" => DATA <= x"E6";
when x"75D" => DATA <= x"DF";
when x"75E" => DATA <= x"FE";
when x"75F" => DATA <= x"4E";
when x"760" => DATA <= x"20";
when x"761" => DATA <= x"EC";
when x"762" => DATA <= x"13";
when x"763" => DATA <= x"1A";
when x"764" => DATA <= x"CD";
when x"765" => DATA <= x"6D";
when x"766" => DATA <= x"F8";
when x"767" => DATA <= x"D2";
when x"768" => DATA <= x"4E";
when x"769" => DATA <= x"F7";
when x"76A" => DATA <= x"18";
when x"76B" => DATA <= x"0C";
when x"76C" => DATA <= x"CD";
when x"76D" => DATA <= x"0E";
when x"76E" => DATA <= x"F6";
when x"76F" => DATA <= x"20";
when x"770" => DATA <= x"20";
when x"771" => DATA <= x"4D";
when x"772" => DATA <= x"4F";
when x"773" => DATA <= x"4E";
when x"774" => DATA <= x"0D";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"18";
when x"777" => DATA <= x"54";
when x"778" => DATA <= x"CD";
when x"779" => DATA <= x"0E";
when x"77A" => DATA <= x"F6";
when x"77B" => DATA <= x"20";
when x"77C" => DATA <= x"20";
when x"77D" => DATA <= x"43";
when x"77E" => DATA <= x"50";
when x"77F" => DATA <= x"4D";
when x"780" => DATA <= x"0D";
when x"781" => DATA <= x"20";
when x"782" => DATA <= x"20";
when x"783" => DATA <= x"44";
when x"784" => DATA <= x"75";
when x"785" => DATA <= x"6D";
when x"786" => DATA <= x"70";
when x"787" => DATA <= x"20";
when x"788" => DATA <= x"3C";
when x"789" => DATA <= x"73";
when x"78A" => DATA <= x"74";
when x"78B" => DATA <= x"61";
when x"78C" => DATA <= x"72";
when x"78D" => DATA <= x"74";
when x"78E" => DATA <= x"20";
when x"78F" => DATA <= x"61";
when x"790" => DATA <= x"64";
when x"791" => DATA <= x"64";
when x"792" => DATA <= x"72";
when x"793" => DATA <= x"65";
when x"794" => DATA <= x"73";
when x"795" => DATA <= x"73";
when x"796" => DATA <= x"3E";
when x"797" => DATA <= x"20";
when x"798" => DATA <= x"3C";
when x"799" => DATA <= x"65";
when x"79A" => DATA <= x"6E";
when x"79B" => DATA <= x"64";
when x"79C" => DATA <= x"20";
when x"79D" => DATA <= x"61";
when x"79E" => DATA <= x"64";
when x"79F" => DATA <= x"64";
when x"7A0" => DATA <= x"72";
when x"7A1" => DATA <= x"65";
when x"7A2" => DATA <= x"73";
when x"7A3" => DATA <= x"73";
when x"7A4" => DATA <= x"3E";
when x"7A5" => DATA <= x"0D";
when x"7A6" => DATA <= x"20";
when x"7A7" => DATA <= x"20";
when x"7A8" => DATA <= x"47";
when x"7A9" => DATA <= x"4F";
when x"7AA" => DATA <= x"20";
when x"7AB" => DATA <= x"3C";
when x"7AC" => DATA <= x"61";
when x"7AD" => DATA <= x"64";
when x"7AE" => DATA <= x"64";
when x"7AF" => DATA <= x"72";
when x"7B0" => DATA <= x"65";
when x"7B1" => DATA <= x"73";
when x"7B2" => DATA <= x"73";
when x"7B3" => DATA <= x"3E";
when x"7B4" => DATA <= x"0D";
when x"7B5" => DATA <= x"20";
when x"7B6" => DATA <= x"20";
when x"7B7" => DATA <= x"53";
when x"7B8" => DATA <= x"65";
when x"7B9" => DATA <= x"74";
when x"7BA" => DATA <= x"20";
when x"7BB" => DATA <= x"3C";
when x"7BC" => DATA <= x"73";
when x"7BD" => DATA <= x"74";
when x"7BE" => DATA <= x"61";
when x"7BF" => DATA <= x"72";
when x"7C0" => DATA <= x"74";
when x"7C1" => DATA <= x"20";
when x"7C2" => DATA <= x"61";
when x"7C3" => DATA <= x"64";
when x"7C4" => DATA <= x"64";
when x"7C5" => DATA <= x"72";
when x"7C6" => DATA <= x"65";
when x"7C7" => DATA <= x"73";
when x"7C8" => DATA <= x"73";
when x"7C9" => DATA <= x"3E";
when x"7CA" => DATA <= x"0D";
when x"7CB" => DATA <= x"00";
when x"7CC" => DATA <= x"3E";
when x"7CD" => DATA <= x"02";
when x"7CE" => DATA <= x"CD";
when x"7CF" => DATA <= x"A3";
when x"7D0" => DATA <= x"F6";
when x"7D1" => DATA <= x"CD";
when x"7D2" => DATA <= x"84";
when x"7D3" => DATA <= x"F8";
when x"7D4" => DATA <= x"CD";
when x"7D5" => DATA <= x"9A";
when x"7D6" => DATA <= x"F6";
when x"7D7" => DATA <= x"FE";
when x"7D8" => DATA <= x"80";
when x"7D9" => DATA <= x"28";
when x"7DA" => DATA <= x"04";
when x"7DB" => DATA <= x"D1";
when x"7DC" => DATA <= x"C1";
when x"7DD" => DATA <= x"F1";
when x"7DE" => DATA <= x"C9";
when x"7DF" => DATA <= x"3E";
when x"7E0" => DATA <= x"01";
when x"7E1" => DATA <= x"32";
when x"7E2" => DATA <= x"AF";
when x"7E3" => DATA <= x"FC";
when x"7E4" => DATA <= x"CD";
when x"7E5" => DATA <= x"EB";
when x"7E6" => DATA <= x"F7";
when x"7E7" => DATA <= x"D1";
when x"7E8" => DATA <= x"C1";
when x"7E9" => DATA <= x"F1";
when x"7EA" => DATA <= x"C9";
when x"7EB" => DATA <= x"2A";
when x"7EC" => DATA <= x"A8";
when x"7ED" => DATA <= x"FC";
when x"7EE" => DATA <= x"11";
when x"7EF" => DATA <= x"07";
when x"7F0" => DATA <= x"00";
when x"7F1" => DATA <= x"19";
when x"7F2" => DATA <= x"E5";
when x"7F3" => DATA <= x"7E";
when x"7F4" => DATA <= x"2A";
when x"7F5" => DATA <= x"A8";
when x"7F6" => DATA <= x"FC";
when x"7F7" => DATA <= x"5F";
when x"7F8" => DATA <= x"19";
when x"7F9" => DATA <= x"22";
when x"7FA" => DATA <= x"82";
when x"7FB" => DATA <= x"FF";
when x"7FC" => DATA <= x"7E";
when x"7FD" => DATA <= x"11";
when x"7FE" => DATA <= x"22";
when x"7FF" => DATA <= x"FF";
when x"800" => DATA <= x"06";
when x"801" => DATA <= x"04";
when x"802" => DATA <= x"1A";
when x"803" => DATA <= x"BE";
when x"804" => DATA <= x"20";
when x"805" => DATA <= x"20";
when x"806" => DATA <= x"23";
when x"807" => DATA <= x"13";
when x"808" => DATA <= x"10";
when x"809" => DATA <= x"F8";
when x"80A" => DATA <= x"E1";
when x"80B" => DATA <= x"2B";
when x"80C" => DATA <= x"3A";
when x"80D" => DATA <= x"AF";
when x"80E" => DATA <= x"FC";
when x"80F" => DATA <= x"B7";
when x"810" => DATA <= x"20";
when x"811" => DATA <= x"17";
when x"812" => DATA <= x"7E";
when x"813" => DATA <= x"E6";
when x"814" => DATA <= x"4F";
when x"815" => DATA <= x"FE";
when x"816" => DATA <= x"40";
when x"817" => DATA <= x"38";
when x"818" => DATA <= x"09";
when x"819" => DATA <= x"FE";
when x"81A" => DATA <= x"48";
when x"81B" => DATA <= x"20";
when x"81C" => DATA <= x"05";
when x"81D" => DATA <= x"BF";
when x"81E" => DATA <= x"2A";
when x"81F" => DATA <= x"A8";
when x"820" => DATA <= x"FC";
when x"821" => DATA <= x"E9";
when x"822" => DATA <= x"BF";
when x"823" => DATA <= x"C3";
when x"824" => DATA <= x"A9";
when x"825" => DATA <= x"F4";
when x"826" => DATA <= x"E1";
when x"827" => DATA <= x"18";
when x"828" => DATA <= x"F4";
when x"829" => DATA <= x"AF";
when x"82A" => DATA <= x"32";
when x"82B" => DATA <= x"AF";
when x"82C" => DATA <= x"FC";
when x"82D" => DATA <= x"7E";
when x"82E" => DATA <= x"E6";
when x"82F" => DATA <= x"4F";
when x"830" => DATA <= x"FE";
when x"831" => DATA <= x"40";
when x"832" => DATA <= x"38";
when x"833" => DATA <= x"09";
when x"834" => DATA <= x"FE";
when x"835" => DATA <= x"48";
when x"836" => DATA <= x"20";
when x"837" => DATA <= x"1E";
when x"838" => DATA <= x"3E";
when x"839" => DATA <= x"01";
when x"83A" => DATA <= x"18";
when x"83B" => DATA <= x"E1";
when x"83C" => DATA <= x"00";
when x"83D" => DATA <= x"FF";
when x"83E" => DATA <= x"F9";
when x"83F" => DATA <= x"54";
when x"840" => DATA <= x"68";
when x"841" => DATA <= x"69";
when x"842" => DATA <= x"73";
when x"843" => DATA <= x"20";
when x"844" => DATA <= x"69";
when x"845" => DATA <= x"73";
when x"846" => DATA <= x"20";
when x"847" => DATA <= x"6E";
when x"848" => DATA <= x"6F";
when x"849" => DATA <= x"74";
when x"84A" => DATA <= x"20";
when x"84B" => DATA <= x"61";
when x"84C" => DATA <= x"20";
when x"84D" => DATA <= x"6C";
when x"84E" => DATA <= x"61";
when x"84F" => DATA <= x"6E";
when x"850" => DATA <= x"67";
when x"851" => DATA <= x"75";
when x"852" => DATA <= x"61";
when x"853" => DATA <= x"67";
when x"854" => DATA <= x"65";
when x"855" => DATA <= x"00";
when x"856" => DATA <= x"FF";
when x"857" => DATA <= x"F9";
when x"858" => DATA <= x"54";
when x"859" => DATA <= x"68";
when x"85A" => DATA <= x"69";
when x"85B" => DATA <= x"73";
when x"85C" => DATA <= x"20";
when x"85D" => DATA <= x"69";
when x"85E" => DATA <= x"73";
when x"85F" => DATA <= x"20";
when x"860" => DATA <= x"6E";
when x"861" => DATA <= x"6F";
when x"862" => DATA <= x"74";
when x"863" => DATA <= x"20";
when x"864" => DATA <= x"5A";
when x"865" => DATA <= x"38";
when x"866" => DATA <= x"30";
when x"867" => DATA <= x"20";
when x"868" => DATA <= x"63";
when x"869" => DATA <= x"6F";
when x"86A" => DATA <= x"64";
when x"86B" => DATA <= x"65";
when x"86C" => DATA <= x"00";
when x"86D" => DATA <= x"E6";
when x"86E" => DATA <= x"DF";
when x"86F" => DATA <= x"FE";
when x"870" => DATA <= x"41";
when x"871" => DATA <= x"D8";
when x"872" => DATA <= x"FE";
when x"873" => DATA <= x"5B";
when x"874" => DATA <= x"3F";
when x"875" => DATA <= x"C9";
when x"876" => DATA <= x"13";
when x"877" => DATA <= x"1A";
when x"878" => DATA <= x"FE";
when x"879" => DATA <= x"20";
when x"87A" => DATA <= x"28";
when x"87B" => DATA <= x"FA";
when x"87C" => DATA <= x"C9";
when x"87D" => DATA <= x"13";
when x"87E" => DATA <= x"1A";
when x"87F" => DATA <= x"FE";
when x"880" => DATA <= x"2A";
when x"881" => DATA <= x"28";
when x"882" => DATA <= x"FA";
when x"883" => DATA <= x"C9";
when x"884" => DATA <= x"7E";
when x"885" => DATA <= x"CD";
when x"886" => DATA <= x"A3";
when x"887" => DATA <= x"F6";
when x"888" => DATA <= x"23";
when x"889" => DATA <= x"FE";
when x"88A" => DATA <= x"0D";
when x"88B" => DATA <= x"20";
when x"88C" => DATA <= x"F7";
when x"88D" => DATA <= x"C9";
when x"88E" => DATA <= x"FE";
when x"88F" => DATA <= x"80";
when x"890" => DATA <= x"30";
when x"891" => DATA <= x"15";
when x"892" => DATA <= x"F5";
when x"893" => DATA <= x"3E";
when x"894" => DATA <= x"04";
when x"895" => DATA <= x"CD";
when x"896" => DATA <= x"A3";
when x"897" => DATA <= x"F6";
when x"898" => DATA <= x"7D";
when x"899" => DATA <= x"CD";
when x"89A" => DATA <= x"A3";
when x"89B" => DATA <= x"F6";
when x"89C" => DATA <= x"F1";
when x"89D" => DATA <= x"F5";
when x"89E" => DATA <= x"CD";
when x"89F" => DATA <= x"A3";
when x"8A0" => DATA <= x"F6";
when x"8A1" => DATA <= x"CD";
when x"8A2" => DATA <= x"9A";
when x"8A3" => DATA <= x"F6";
when x"8A4" => DATA <= x"6F";
when x"8A5" => DATA <= x"F1";
when x"8A6" => DATA <= x"C9";
when x"8A7" => DATA <= x"FE";
when x"8A8" => DATA <= x"82";
when x"8A9" => DATA <= x"28";
when x"8AA" => DATA <= x"31";
when x"8AB" => DATA <= x"FE";
when x"8AC" => DATA <= x"83";
when x"8AD" => DATA <= x"28";
when x"8AE" => DATA <= x"31";
when x"8AF" => DATA <= x"FE";
when x"8B0" => DATA <= x"84";
when x"8B1" => DATA <= x"28";
when x"8B2" => DATA <= x"31";
when x"8B3" => DATA <= x"F5";
when x"8B4" => DATA <= x"3E";
when x"8B5" => DATA <= x"06";
when x"8B6" => DATA <= x"CD";
when x"8B7" => DATA <= x"A3";
when x"8B8" => DATA <= x"F6";
when x"8B9" => DATA <= x"7D";
when x"8BA" => DATA <= x"CD";
when x"8BB" => DATA <= x"A3";
when x"8BC" => DATA <= x"F6";
when x"8BD" => DATA <= x"7C";
when x"8BE" => DATA <= x"CD";
when x"8BF" => DATA <= x"A3";
when x"8C0" => DATA <= x"F6";
when x"8C1" => DATA <= x"F1";
when x"8C2" => DATA <= x"F5";
when x"8C3" => DATA <= x"CD";
when x"8C4" => DATA <= x"A3";
when x"8C5" => DATA <= x"F6";
when x"8C6" => DATA <= x"FE";
when x"8C7" => DATA <= x"9D";
when x"8C8" => DATA <= x"28";
when x"8C9" => DATA <= x"10";
when x"8CA" => DATA <= x"CD";
when x"8CB" => DATA <= x"9A";
when x"8CC" => DATA <= x"F6";
when x"8CD" => DATA <= x"6F";
when x"8CE" => DATA <= x"F1";
when x"8CF" => DATA <= x"CB";
when x"8D0" => DATA <= x"25";
when x"8D1" => DATA <= x"F5";
when x"8D2" => DATA <= x"CD";
when x"8D3" => DATA <= x"9A";
when x"8D4" => DATA <= x"F6";
when x"8D5" => DATA <= x"67";
when x"8D6" => DATA <= x"CD";
when x"8D7" => DATA <= x"9A";
when x"8D8" => DATA <= x"F6";
when x"8D9" => DATA <= x"6F";
when x"8DA" => DATA <= x"F1";
when x"8DB" => DATA <= x"C9";
when x"8DC" => DATA <= x"21";
when x"8DD" => DATA <= x"00";
when x"8DE" => DATA <= x"00";
when x"8DF" => DATA <= x"C9";
when x"8E0" => DATA <= x"21";
when x"8E1" => DATA <= x"03";
when x"8E2" => DATA <= x"3B";
when x"8E3" => DATA <= x"C9";
when x"8E4" => DATA <= x"21";
when x"8E5" => DATA <= x"00";
when x"8E6" => DATA <= x"DC";
when x"8E7" => DATA <= x"C9";
when x"8E8" => DATA <= x"F5";
when x"8E9" => DATA <= x"3E";
when x"8EA" => DATA <= x"01";
when x"8EB" => DATA <= x"32";
when x"8EC" => DATA <= x"A4";
when x"8ED" => DATA <= x"FC";
when x"8EE" => DATA <= x"F1";
when x"8EF" => DATA <= x"B7";
when x"8F0" => DATA <= x"28";
when x"8F1" => DATA <= x"6B";
when x"8F2" => DATA <= x"C5";
when x"8F3" => DATA <= x"E5";
when x"8F4" => DATA <= x"DD";
when x"8F5" => DATA <= x"E5";
when x"8F6" => DATA <= x"F5";
when x"8F7" => DATA <= x"3E";
when x"8F8" => DATA <= x"08";
when x"8F9" => DATA <= x"CD";
when x"8FA" => DATA <= x"A3";
when x"8FB" => DATA <= x"F6";
when x"8FC" => DATA <= x"F1";
when x"8FD" => DATA <= x"F5";
when x"8FE" => DATA <= x"CD";
when x"8FF" => DATA <= x"A3";
when x"900" => DATA <= x"F6";
when x"901" => DATA <= x"06";
when x"902" => DATA <= x"00";
when x"903" => DATA <= x"4F";
when x"904" => DATA <= x"FE";
when x"905" => DATA <= x"80";
when x"906" => DATA <= x"38";
when x"907" => DATA <= x"06";
when x"908" => DATA <= x"46";
when x"909" => DATA <= x"23";
when x"90A" => DATA <= x"4E";
when x"90B" => DATA <= x"2B";
when x"90C" => DATA <= x"18";
when x"90D" => DATA <= x"15";
when x"90E" => DATA <= x"FE";
when x"90F" => DATA <= x"15";
when x"910" => DATA <= x"38";
when x"911" => DATA <= x"05";
when x"912" => DATA <= x"01";
when x"913" => DATA <= x"10";
when x"914" => DATA <= x"10";
when x"915" => DATA <= x"18";
when x"916" => DATA <= x"0C";
when x"917" => DATA <= x"DD";
when x"918" => DATA <= x"21";
when x"919" => DATA <= x"75";
when x"91A" => DATA <= x"FC";
when x"91B" => DATA <= x"DD";
when x"91C" => DATA <= x"09";
when x"91D" => DATA <= x"DD";
when x"91E" => DATA <= x"46";
when x"91F" => DATA <= x"FF";
when x"920" => DATA <= x"DD";
when x"921" => DATA <= x"4E";
when x"922" => DATA <= x"13";
when x"923" => DATA <= x"E5";
when x"924" => DATA <= x"C5";
when x"925" => DATA <= x"48";
when x"926" => DATA <= x"06";
when x"927" => DATA <= x"00";
when x"928" => DATA <= x"09";
when x"929" => DATA <= x"C1";
when x"92A" => DATA <= x"78";
when x"92B" => DATA <= x"CD";
when x"92C" => DATA <= x"A3";
when x"92D" => DATA <= x"F6";
when x"92E" => DATA <= x"B7";
when x"92F" => DATA <= x"28";
when x"930" => DATA <= x"07";
when x"931" => DATA <= x"2B";
when x"932" => DATA <= x"7E";
when x"933" => DATA <= x"CD";
when x"934" => DATA <= x"A3";
when x"935" => DATA <= x"F6";
when x"936" => DATA <= x"10";
when x"937" => DATA <= x"F9";
when x"938" => DATA <= x"79";
when x"939" => DATA <= x"CD";
when x"93A" => DATA <= x"A3";
when x"93B" => DATA <= x"F6";
when x"93C" => DATA <= x"E1";
when x"93D" => DATA <= x"F5";
when x"93E" => DATA <= x"3A";
when x"93F" => DATA <= x"A4";
when x"940" => DATA <= x"FC";
when x"941" => DATA <= x"B7";
when x"942" => DATA <= x"28";
when x"943" => DATA <= x"06";
when x"944" => DATA <= x"62";
when x"945" => DATA <= x"6B";
when x"946" => DATA <= x"AF";
when x"947" => DATA <= x"32";
when x"948" => DATA <= x"A4";
when x"949" => DATA <= x"FC";
when x"94A" => DATA <= x"F1";
when x"94B" => DATA <= x"B7";
when x"94C" => DATA <= x"28";
when x"94D" => DATA <= x"09";
when x"94E" => DATA <= x"09";
when x"94F" => DATA <= x"41";
when x"950" => DATA <= x"2B";
when x"951" => DATA <= x"CD";
when x"952" => DATA <= x"9A";
when x"953" => DATA <= x"F6";
when x"954" => DATA <= x"77";
when x"955" => DATA <= x"10";
when x"956" => DATA <= x"F9";
when x"957" => DATA <= x"F1";
when x"958" => DATA <= x"DD";
when x"959" => DATA <= x"E1";
when x"95A" => DATA <= x"E1";
when x"95B" => DATA <= x"C1";
when x"95C" => DATA <= x"C9";
when x"95D" => DATA <= x"C5";
when x"95E" => DATA <= x"F5";
when x"95F" => DATA <= x"3E";
when x"960" => DATA <= x"0A";
when x"961" => DATA <= x"CD";
when x"962" => DATA <= x"A3";
when x"963" => DATA <= x"F6";
when x"964" => DATA <= x"23";
when x"965" => DATA <= x"23";
when x"966" => DATA <= x"23";
when x"967" => DATA <= x"23";
when x"968" => DATA <= x"06";
when x"969" => DATA <= x"03";
when x"96A" => DATA <= x"7E";
when x"96B" => DATA <= x"CD";
when x"96C" => DATA <= x"A3";
when x"96D" => DATA <= x"F6";
when x"96E" => DATA <= x"2B";
when x"96F" => DATA <= x"10";
when x"970" => DATA <= x"F9";
when x"971" => DATA <= x"3E";
when x"972" => DATA <= x"07";
when x"973" => DATA <= x"CD";
when x"974" => DATA <= x"A3";
when x"975" => DATA <= x"F6";
when x"976" => DATA <= x"97";
when x"977" => DATA <= x"CD";
when x"978" => DATA <= x"A3";
when x"979" => DATA <= x"F6";
when x"97A" => DATA <= x"CD";
when x"97B" => DATA <= x"9A";
when x"97C" => DATA <= x"F6";
when x"97D" => DATA <= x"07";
when x"97E" => DATA <= x"38";
when x"97F" => DATA <= x"18";
when x"980" => DATA <= x"7E";
when x"981" => DATA <= x"2B";
when x"982" => DATA <= x"6E";
when x"983" => DATA <= x"67";
when x"984" => DATA <= x"06";
when x"985" => DATA <= x"FF";
when x"986" => DATA <= x"CD";
when x"987" => DATA <= x"9A";
when x"988" => DATA <= x"F6";
when x"989" => DATA <= x"77";
when x"98A" => DATA <= x"23";
when x"98B" => DATA <= x"04";
when x"98C" => DATA <= x"FE";
when x"98D" => DATA <= x"0D";
when x"98E" => DATA <= x"20";
when x"98F" => DATA <= x"F6";
when x"990" => DATA <= x"2E";
when x"991" => DATA <= x"00";
when x"992" => DATA <= x"60";
when x"993" => DATA <= x"F1";
when x"994" => DATA <= x"C1";
when x"995" => DATA <= x"37";
when x"996" => DATA <= x"3F";
when x"997" => DATA <= x"C9";
when x"998" => DATA <= x"21";
when x"999" => DATA <= x"FF";
when x"99A" => DATA <= x"00";
when x"99B" => DATA <= x"F1";
when x"99C" => DATA <= x"C1";
when x"99D" => DATA <= x"37";
when x"99E" => DATA <= x"C9";
when x"99F" => DATA <= x"E5";
when x"9A0" => DATA <= x"D5";
when x"9A1" => DATA <= x"C5";
when x"9A2" => DATA <= x"F5";
when x"9A3" => DATA <= x"3E";
when x"9A4" => DATA <= x"0C";
when x"9A5" => DATA <= x"CD";
when x"9A6" => DATA <= x"A3";
when x"9A7" => DATA <= x"F6";
when x"9A8" => DATA <= x"7B";
when x"9A9" => DATA <= x"CD";
when x"9AA" => DATA <= x"A3";
when x"9AB" => DATA <= x"F6";
when x"9AC" => DATA <= x"23";
when x"9AD" => DATA <= x"23";
when x"9AE" => DATA <= x"23";
when x"9AF" => DATA <= x"06";
when x"9B0" => DATA <= x"04";
when x"9B1" => DATA <= x"7E";
when x"9B2" => DATA <= x"CD";
when x"9B3" => DATA <= x"A3";
when x"9B4" => DATA <= x"F6";
when x"9B5" => DATA <= x"2B";
when x"9B6" => DATA <= x"10";
when x"9B7" => DATA <= x"F9";
when x"9B8" => DATA <= x"23";
when x"9B9" => DATA <= x"F1";
when x"9BA" => DATA <= x"CD";
when x"9BB" => DATA <= x"A3";
when x"9BC" => DATA <= x"F6";
when x"9BD" => DATA <= x"CD";
when x"9BE" => DATA <= x"9A";
when x"9BF" => DATA <= x"F6";
when x"9C0" => DATA <= x"F5";
when x"9C1" => DATA <= x"23";
when x"9C2" => DATA <= x"23";
when x"9C3" => DATA <= x"23";
when x"9C4" => DATA <= x"06";
when x"9C5" => DATA <= x"04";
when x"9C6" => DATA <= x"CD";
when x"9C7" => DATA <= x"9A";
when x"9C8" => DATA <= x"F6";
when x"9C9" => DATA <= x"77";
when x"9CA" => DATA <= x"2B";
when x"9CB" => DATA <= x"10";
when x"9CC" => DATA <= x"F9";
when x"9CD" => DATA <= x"F1";
when x"9CE" => DATA <= x"C1";
when x"9CF" => DATA <= x"D1";
when x"9D0" => DATA <= x"E1";
when x"9D1" => DATA <= x"C9";
when x"9D2" => DATA <= x"F5";
when x"9D3" => DATA <= x"3E";
when x"9D4" => DATA <= x"12";
when x"9D5" => DATA <= x"CD";
when x"9D6" => DATA <= x"A3";
when x"9D7" => DATA <= x"F6";
when x"9D8" => DATA <= x"F1";
when x"9D9" => DATA <= x"CD";
when x"9DA" => DATA <= x"A3";
when x"9DB" => DATA <= x"F6";
when x"9DC" => DATA <= x"FE";
when x"9DD" => DATA <= x"00";
when x"9DE" => DATA <= x"20";
when x"9DF" => DATA <= x"0A";
when x"9E0" => DATA <= x"F5";
when x"9E1" => DATA <= x"7C";
when x"9E2" => DATA <= x"CD";
when x"9E3" => DATA <= x"A3";
when x"9E4" => DATA <= x"F6";
when x"9E5" => DATA <= x"CD";
when x"9E6" => DATA <= x"9A";
when x"9E7" => DATA <= x"F6";
when x"9E8" => DATA <= x"F1";
when x"9E9" => DATA <= x"C9";
when x"9EA" => DATA <= x"CD";
when x"9EB" => DATA <= x"84";
when x"9EC" => DATA <= x"F8";
when x"9ED" => DATA <= x"C3";
when x"9EE" => DATA <= x"9A";
when x"9EF" => DATA <= x"F6";
when x"9F0" => DATA <= x"3E";
when x"9F1" => DATA <= x"0E";
when x"9F2" => DATA <= x"CD";
when x"9F3" => DATA <= x"A3";
when x"9F4" => DATA <= x"F6";
when x"9F5" => DATA <= x"7C";
when x"9F6" => DATA <= x"CD";
when x"9F7" => DATA <= x"A3";
when x"9F8" => DATA <= x"F6";
when x"9F9" => DATA <= x"C3";
when x"9FA" => DATA <= x"95";
when x"9FB" => DATA <= x"F6";
when x"9FC" => DATA <= x"F5";
when x"9FD" => DATA <= x"3E";
when x"9FE" => DATA <= x"10";
when x"9FF" => DATA <= x"CD";
when x"A00" => DATA <= x"A3";
when x"A01" => DATA <= x"F6";
when x"A02" => DATA <= x"7C";
when x"A03" => DATA <= x"CD";
when x"A04" => DATA <= x"A3";
when x"A05" => DATA <= x"F6";
when x"A06" => DATA <= x"F1";
when x"A07" => DATA <= x"CD";
when x"A08" => DATA <= x"A3";
when x"A09" => DATA <= x"F6";
when x"A0A" => DATA <= x"F5";
when x"A0B" => DATA <= x"CD";
when x"A0C" => DATA <= x"9A";
when x"A0D" => DATA <= x"F6";
when x"A0E" => DATA <= x"F1";
when x"A0F" => DATA <= x"C9";
when x"A10" => DATA <= x"C5";
when x"A11" => DATA <= x"F5";
when x"A12" => DATA <= x"22";
when x"A13" => DATA <= x"AC";
when x"A14" => DATA <= x"FC";
when x"A15" => DATA <= x"3E";
when x"A16" => DATA <= x"14";
when x"A17" => DATA <= x"CD";
when x"A18" => DATA <= x"A3";
when x"A19" => DATA <= x"F6";
when x"A1A" => DATA <= x"01";
when x"A1B" => DATA <= x"11";
when x"A1C" => DATA <= x"00";
when x"A1D" => DATA <= x"09";
when x"A1E" => DATA <= x"06";
when x"A1F" => DATA <= x"10";
when x"A20" => DATA <= x"7E";
when x"A21" => DATA <= x"CD";
when x"A22" => DATA <= x"A3";
when x"A23" => DATA <= x"F6";
when x"A24" => DATA <= x"2B";
when x"A25" => DATA <= x"10";
when x"A26" => DATA <= x"F9";
when x"A27" => DATA <= x"7E";
when x"A28" => DATA <= x"2B";
when x"A29" => DATA <= x"6E";
when x"A2A" => DATA <= x"67";
when x"A2B" => DATA <= x"CD";
when x"A2C" => DATA <= x"84";
when x"A2D" => DATA <= x"F8";
when x"A2E" => DATA <= x"F1";
when x"A2F" => DATA <= x"CD";
when x"A30" => DATA <= x"A3";
when x"A31" => DATA <= x"F6";
when x"A32" => DATA <= x"CD";
when x"A33" => DATA <= x"9A";
when x"A34" => DATA <= x"F6";
when x"A35" => DATA <= x"E6";
when x"A36" => DATA <= x"FF";
when x"A37" => DATA <= x"F5";
when x"A38" => DATA <= x"2A";
when x"A39" => DATA <= x"AC";
when x"A3A" => DATA <= x"FC";
when x"A3B" => DATA <= x"01";
when x"A3C" => DATA <= x"11";
when x"A3D" => DATA <= x"00";
when x"A3E" => DATA <= x"09";
when x"A3F" => DATA <= x"06";
when x"A40" => DATA <= x"10";
when x"A41" => DATA <= x"CD";
when x"A42" => DATA <= x"9A";
when x"A43" => DATA <= x"F6";
when x"A44" => DATA <= x"77";
when x"A45" => DATA <= x"2B";
when x"A46" => DATA <= x"10";
when x"A47" => DATA <= x"F9";
when x"A48" => DATA <= x"2A";
when x"A49" => DATA <= x"AC";
when x"A4A" => DATA <= x"FC";
when x"A4B" => DATA <= x"F1";
when x"A4C" => DATA <= x"C1";
when x"A4D" => DATA <= x"C9";
when x"A4E" => DATA <= x"C5";
when x"A4F" => DATA <= x"F5";
when x"A50" => DATA <= x"22";
when x"A51" => DATA <= x"AC";
when x"A52" => DATA <= x"FC";
when x"A53" => DATA <= x"3E";
when x"A54" => DATA <= x"16";
when x"A55" => DATA <= x"CD";
when x"A56" => DATA <= x"A3";
when x"A57" => DATA <= x"F6";
when x"A58" => DATA <= x"01";
when x"A59" => DATA <= x"0C";
when x"A5A" => DATA <= x"00";
when x"A5B" => DATA <= x"09";
when x"A5C" => DATA <= x"06";
when x"A5D" => DATA <= x"0D";
when x"A5E" => DATA <= x"7E";
when x"A5F" => DATA <= x"CD";
when x"A60" => DATA <= x"A3";
when x"A61" => DATA <= x"F6";
when x"A62" => DATA <= x"2B";
when x"A63" => DATA <= x"10";
when x"A64" => DATA <= x"F9";
when x"A65" => DATA <= x"F1";
when x"A66" => DATA <= x"CD";
when x"A67" => DATA <= x"A3";
when x"A68" => DATA <= x"F6";
when x"A69" => DATA <= x"2A";
when x"A6A" => DATA <= x"AC";
when x"A6B" => DATA <= x"FC";
when x"A6C" => DATA <= x"01";
when x"A6D" => DATA <= x"0C";
when x"A6E" => DATA <= x"00";
when x"A6F" => DATA <= x"09";
when x"A70" => DATA <= x"06";
when x"A71" => DATA <= x"0D";
when x"A72" => DATA <= x"CD";
when x"A73" => DATA <= x"9A";
when x"A74" => DATA <= x"F6";
when x"A75" => DATA <= x"77";
when x"A76" => DATA <= x"2B";
when x"A77" => DATA <= x"10";
when x"A78" => DATA <= x"F9";
when x"A79" => DATA <= x"2A";
when x"A7A" => DATA <= x"AC";
when x"A7B" => DATA <= x"FC";
when x"A7C" => DATA <= x"C1";
when x"A7D" => DATA <= x"C3";
when x"A7E" => DATA <= x"95";
when x"A7F" => DATA <= x"F6";
when x"A80" => DATA <= x"00";
when x"A81" => DATA <= x"00";
when x"A82" => DATA <= x"ED";
when x"A83" => DATA <= x"73";
when x"A84" => DATA <= x"80";
when x"A85" => DATA <= x"FA";
when x"A86" => DATA <= x"31";
when x"A87" => DATA <= x"60";
when x"A88" => DATA <= x"FF";
when x"A89" => DATA <= x"CD";
when x"A8A" => DATA <= x"93";
when x"A8B" => DATA <= x"FA";
when x"A8C" => DATA <= x"ED";
when x"A8D" => DATA <= x"7B";
when x"A8E" => DATA <= x"80";
when x"A8F" => DATA <= x"FA";
when x"A90" => DATA <= x"FB";
when x"A91" => DATA <= x"ED";
when x"A92" => DATA <= x"4D";
when x"A93" => DATA <= x"F5";
when x"A94" => DATA <= x"DB";
when x"A95" => DATA <= x"06";
when x"A96" => DATA <= x"CB";
when x"A97" => DATA <= x"7F";
when x"A98" => DATA <= x"20";
when x"A99" => DATA <= x"71";
when x"A9A" => DATA <= x"DB";
when x"A9B" => DATA <= x"00";
when x"A9C" => DATA <= x"CB";
when x"A9D" => DATA <= x"7F";
when x"A9E" => DATA <= x"20";
when x"A9F" => DATA <= x"39";
when x"AA0" => DATA <= x"F1";
when x"AA1" => DATA <= x"C3";
when x"AA2" => DATA <= x"B0";
when x"AA3" => DATA <= x"FF";
when x"AA4" => DATA <= x"E1";
when x"AA5" => DATA <= x"22";
when x"AA6" => DATA <= x"82";
when x"AA7" => DATA <= x"FF";
when x"AA8" => DATA <= x"2A";
when x"AA9" => DATA <= x"FA";
when x"AAA" => DATA <= x"FF";
when x"AAB" => DATA <= x"E9";
when x"AAC" => DATA <= x"CD";
when x"AAD" => DATA <= x"C6";
when x"AAE" => DATA <= x"FA";
when x"AAF" => DATA <= x"C3";
when x"AB0" => DATA <= x"CB";
when x"AB1" => DATA <= x"F2";
when x"AB2" => DATA <= x"3E";
when x"AB3" => DATA <= x"03";
when x"AB4" => DATA <= x"2E";
when x"AB5" => DATA <= x"00";
when x"AB6" => DATA <= x"CD";
when x"AB7" => DATA <= x"8E";
when x"AB8" => DATA <= x"F8";
when x"AB9" => DATA <= x"3E";
when x"ABA" => DATA <= x"02";
when x"ABB" => DATA <= x"2E";
when x"ABC" => DATA <= x"02";
when x"ABD" => DATA <= x"CD";
when x"ABE" => DATA <= x"8E";
when x"ABF" => DATA <= x"F8";
when x"AC0" => DATA <= x"CD";
when x"AC1" => DATA <= x"C6";
when x"AC2" => DATA <= x"FA";
when x"AC3" => DATA <= x"C3";
when x"AC4" => DATA <= x"00";
when x"AC5" => DATA <= x"00";
when x"AC6" => DATA <= x"2A";
when x"AC7" => DATA <= x"82";
when x"AC8" => DATA <= x"FF";
when x"AC9" => DATA <= x"3E";
when x"ACA" => DATA <= x"0D";
when x"ACB" => DATA <= x"CD";
when x"ACC" => DATA <= x"71";
when x"ACD" => DATA <= x"F6";
when x"ACE" => DATA <= x"3E";
when x"ACF" => DATA <= x"0A";
when x"AD0" => DATA <= x"CD";
when x"AD1" => DATA <= x"71";
when x"AD2" => DATA <= x"F6";
when x"AD3" => DATA <= x"23";
when x"AD4" => DATA <= x"7E";
when x"AD5" => DATA <= x"B7";
when x"AD6" => DATA <= x"20";
when x"AD7" => DATA <= x"F8";
when x"AD8" => DATA <= x"C9";
when x"AD9" => DATA <= x"DB";
when x"ADA" => DATA <= x"01";
when x"ADB" => DATA <= x"CB";
when x"ADC" => DATA <= x"7F";
when x"ADD" => DATA <= x"20";
when x"ADE" => DATA <= x"25";
when x"ADF" => DATA <= x"3E";
when x"AE0" => DATA <= x"01";
when x"AE1" => DATA <= x"32";
when x"AE2" => DATA <= x"A2";
when x"AE3" => DATA <= x"FC";
when x"AE4" => DATA <= x"E5";
when x"AE5" => DATA <= x"DD";
when x"AE6" => DATA <= x"E5";
when x"AE7" => DATA <= x"CD";
when x"AE8" => DATA <= x"7C";
when x"AE9" => DATA <= x"F6";
when x"AEA" => DATA <= x"67";
when x"AEB" => DATA <= x"CD";
when x"AEC" => DATA <= x"7C";
when x"AED" => DATA <= x"F6";
when x"AEE" => DATA <= x"6F";
when x"AEF" => DATA <= x"CD";
when x"AF0" => DATA <= x"7C";
when x"AF1" => DATA <= x"F6";
when x"AF2" => DATA <= x"CD";
when x"AF3" => DATA <= x"FE";
when x"AF4" => DATA <= x"FA";
when x"AF5" => DATA <= x"AF";
when x"AF6" => DATA <= x"32";
when x"AF7" => DATA <= x"A2";
when x"AF8" => DATA <= x"FC";
when x"AF9" => DATA <= x"DD";
when x"AFA" => DATA <= x"E1";
when x"AFB" => DATA <= x"E1";
when x"AFC" => DATA <= x"F1";
when x"AFD" => DATA <= x"C9";
when x"AFE" => DATA <= x"DD";
when x"AFF" => DATA <= x"2A";
when x"B00" => DATA <= x"FC";
when x"B01" => DATA <= x"FF";
when x"B02" => DATA <= x"DD";
when x"B03" => DATA <= x"E9";
when x"B04" => DATA <= x"CB";
when x"B05" => DATA <= x"27";
when x"B06" => DATA <= x"32";
when x"B07" => DATA <= x"80";
when x"B08" => DATA <= x"FF";
when x"B09" => DATA <= x"F1";
when x"B0A" => DATA <= x"C9";
when x"B0B" => DATA <= x"DB";
when x"B0C" => DATA <= x"07";
when x"B0D" => DATA <= x"CB";
when x"B0E" => DATA <= x"7F";
when x"B0F" => DATA <= x"28";
when x"B10" => DATA <= x"45";
when x"B11" => DATA <= x"DB";
when x"B12" => DATA <= x"02";
when x"B13" => DATA <= x"CB";
when x"B14" => DATA <= x"7F";
when x"B15" => DATA <= x"28";
when x"B16" => DATA <= x"FA";
when x"B17" => DATA <= x"DB";
when x"B18" => DATA <= x"03";
when x"B19" => DATA <= x"FB";
when x"B1A" => DATA <= x"21";
when x"B1B" => DATA <= x"B0";
when x"B1C" => DATA <= x"FC";
when x"B1D" => DATA <= x"36";
when x"B1E" => DATA <= x"CD";
when x"B1F" => DATA <= x"23";
when x"B20" => DATA <= x"3A";
when x"B21" => DATA <= x"BD";
when x"B22" => DATA <= x"FF";
when x"B23" => DATA <= x"77";
when x"B24" => DATA <= x"23";
when x"B25" => DATA <= x"3A";
when x"B26" => DATA <= x"BE";
when x"B27" => DATA <= x"FF";
when x"B28" => DATA <= x"77";
when x"B29" => DATA <= x"23";
when x"B2A" => DATA <= x"CD";
when x"B2B" => DATA <= x"9A";
when x"B2C" => DATA <= x"F6";
when x"B2D" => DATA <= x"77";
when x"B2E" => DATA <= x"B7";
when x"B2F" => DATA <= x"20";
when x"B30" => DATA <= x"1A";
when x"B31" => DATA <= x"CD";
when x"B32" => DATA <= x"0E";
when x"B33" => DATA <= x"F6";
when x"B34" => DATA <= x"0D";
when x"B35" => DATA <= x"46";
when x"B36" => DATA <= x"61";
when x"B37" => DATA <= x"74";
when x"B38" => DATA <= x"61";
when x"B39" => DATA <= x"6C";
when x"B3A" => DATA <= x"20";
when x"B3B" => DATA <= x"65";
when x"B3C" => DATA <= x"72";
when x"B3D" => DATA <= x"72";
when x"B3E" => DATA <= x"6F";
when x"B3F" => DATA <= x"72";
when x"B40" => DATA <= x"00";
when x"B41" => DATA <= x"3A";
when x"B42" => DATA <= x"A3";
when x"B43" => DATA <= x"FC";
when x"B44" => DATA <= x"B7";
when x"B45" => DATA <= x"C2";
when x"B46" => DATA <= x"00";
when x"B47" => DATA <= x"00";
when x"B48" => DATA <= x"C3";
when x"B49" => DATA <= x"CB";
when x"B4A" => DATA <= x"F2";
when x"B4B" => DATA <= x"23";
when x"B4C" => DATA <= x"CD";
when x"B4D" => DATA <= x"9A";
when x"B4E" => DATA <= x"F6";
when x"B4F" => DATA <= x"77";
when x"B50" => DATA <= x"B7";
when x"B51" => DATA <= x"20";
when x"B52" => DATA <= x"F8";
when x"B53" => DATA <= x"C3";
when x"B54" => DATA <= x"B0";
when x"B55" => DATA <= x"FC";
when x"B56" => DATA <= x"C5";
when x"B57" => DATA <= x"D5";
when x"B58" => DATA <= x"E5";
when x"B59" => DATA <= x"F5";
when x"B5A" => DATA <= x"07";
when x"B5B" => DATA <= x"5F";
when x"B5C" => DATA <= x"07";
when x"B5D" => DATA <= x"07";
when x"B5E" => DATA <= x"83";
when x"B5F" => DATA <= x"07";
when x"B60" => DATA <= x"5F";
when x"B61" => DATA <= x"16";
when x"B62" => DATA <= x"00";
when x"B63" => DATA <= x"21";
when x"B64" => DATA <= x"C1";
when x"B65" => DATA <= x"FB";
when x"B66" => DATA <= x"19";
when x"B67" => DATA <= x"11";
when x"B68" => DATA <= x"61";
when x"B69" => DATA <= x"FC";
when x"B6A" => DATA <= x"01";
when x"B6B" => DATA <= x"14";
when x"B6C" => DATA <= x"00";
when x"B6D" => DATA <= x"ED";
when x"B6E" => DATA <= x"B0";
when x"B6F" => DATA <= x"CD";
when x"B70" => DATA <= x"AE";
when x"B71" => DATA <= x"F6";
when x"B72" => DATA <= x"F1";
when x"B73" => DATA <= x"FE";
when x"B74" => DATA <= x"05";
when x"B75" => DATA <= x"28";
when x"B76" => DATA <= x"33";
when x"B77" => DATA <= x"F5";
when x"B78" => DATA <= x"CD";
when x"B79" => DATA <= x"AE";
when x"B7A" => DATA <= x"F6";
when x"B7B" => DATA <= x"CD";
when x"B7C" => DATA <= x"AE";
when x"B7D" => DATA <= x"F6";
when x"B7E" => DATA <= x"CD";
when x"B7F" => DATA <= x"AE";
when x"B80" => DATA <= x"F6";
when x"B81" => DATA <= x"67";
when x"B82" => DATA <= x"CD";
when x"B83" => DATA <= x"AE";
when x"B84" => DATA <= x"F6";
when x"B85" => DATA <= x"6F";
when x"B86" => DATA <= x"22";
when x"B87" => DATA <= x"A8";
when x"B88" => DATA <= x"FC";
when x"B89" => DATA <= x"0E";
when x"B8A" => DATA <= x"05";
when x"B8B" => DATA <= x"06";
when x"B8C" => DATA <= x"00";
when x"B8D" => DATA <= x"CD";
when x"B8E" => DATA <= x"AE";
when x"B8F" => DATA <= x"F6";
when x"B90" => DATA <= x"F1";
when x"B91" => DATA <= x"FE";
when x"B92" => DATA <= x"06";
when x"B93" => DATA <= x"38";
when x"B94" => DATA <= x"15";
when x"B95" => DATA <= x"20";
when x"B96" => DATA <= x"1D";
when x"B97" => DATA <= x"DB";
when x"B98" => DATA <= x"04";
when x"B99" => DATA <= x"B7";
when x"B9A" => DATA <= x"F2";
when x"B9B" => DATA <= x"97";
when x"B9C" => DATA <= x"FB";
when x"B9D" => DATA <= x"ED";
when x"B9E" => DATA <= x"A3";
when x"B9F" => DATA <= x"C2";
when x"BA0" => DATA <= x"97";
when x"BA1" => DATA <= x"FB";
when x"BA2" => DATA <= x"DB";
when x"BA3" => DATA <= x"04";
when x"BA4" => DATA <= x"B7";
when x"BA5" => DATA <= x"F2";
when x"BA6" => DATA <= x"A2";
when x"BA7" => DATA <= x"FB";
when x"BA8" => DATA <= x"D3";
when x"BA9" => DATA <= x"05";
when x"BAA" => DATA <= x"E1";
when x"BAB" => DATA <= x"D1";
when x"BAC" => DATA <= x"C1";
when x"BAD" => DATA <= x"3A";
when x"BAE" => DATA <= x"A2";
when x"BAF" => DATA <= x"FC";
when x"BB0" => DATA <= x"B7";
when x"BB1" => DATA <= x"C0";
when x"BB2" => DATA <= x"F1";
when x"BB3" => DATA <= x"C9";
when x"BB4" => DATA <= x"DB";
when x"BB5" => DATA <= x"04";
when x"BB6" => DATA <= x"B7";
when x"BB7" => DATA <= x"F2";
when x"BB8" => DATA <= x"B4";
when x"BB9" => DATA <= x"FB";
when x"BBA" => DATA <= x"ED";
when x"BBB" => DATA <= x"A2";
when x"BBC" => DATA <= x"C2";
when x"BBD" => DATA <= x"B4";
when x"BBE" => DATA <= x"FB";
when x"BBF" => DATA <= x"18";
when x"BC0" => DATA <= x"E9";
when x"BC1" => DATA <= x"E5";
when x"BC2" => DATA <= x"F5";
when x"BC3" => DATA <= x"2A";
when x"BC4" => DATA <= x"A8";
when x"BC5" => DATA <= x"FC";
when x"BC6" => DATA <= x"7E";
when x"BC7" => DATA <= x"D3";
when x"BC8" => DATA <= x"05";
when x"BC9" => DATA <= x"23";
when x"BCA" => DATA <= x"22";
when x"BCB" => DATA <= x"A8";
when x"BCC" => DATA <= x"FC";
when x"BCD" => DATA <= x"F1";
when x"BCE" => DATA <= x"E1";
when x"BCF" => DATA <= x"ED";
when x"BD0" => DATA <= x"45";
when x"BD1" => DATA <= x"3A";
when x"BD2" => DATA <= x"12";
when x"BD3" => DATA <= x"3B";
when x"BD4" => DATA <= x"B7";
when x"BD5" => DATA <= x"E5";
when x"BD6" => DATA <= x"F5";
when x"BD7" => DATA <= x"DB";
when x"BD8" => DATA <= x"05";
when x"BD9" => DATA <= x"2A";
when x"BDA" => DATA <= x"A8";
when x"BDB" => DATA <= x"FC";
when x"BDC" => DATA <= x"77";
when x"BDD" => DATA <= x"23";
when x"BDE" => DATA <= x"22";
when x"BDF" => DATA <= x"A8";
when x"BE0" => DATA <= x"FC";
when x"BE1" => DATA <= x"F1";
when x"BE2" => DATA <= x"E1";
when x"BE3" => DATA <= x"ED";
when x"BE4" => DATA <= x"45";
when x"BE5" => DATA <= x"01";
when x"BE6" => DATA <= x"3B";
when x"BE7" => DATA <= x"EB";
when x"BE8" => DATA <= x"CD";
when x"BE9" => DATA <= x"E5";
when x"BEA" => DATA <= x"F5";
when x"BEB" => DATA <= x"2A";
when x"BEC" => DATA <= x"A8";
when x"BED" => DATA <= x"FC";
when x"BEE" => DATA <= x"7E";
when x"BEF" => DATA <= x"D3";
when x"BF0" => DATA <= x"05";
when x"BF1" => DATA <= x"23";
when x"BF2" => DATA <= x"7E";
when x"BF3" => DATA <= x"D3";
when x"BF4" => DATA <= x"05";
when x"BF5" => DATA <= x"23";
when x"BF6" => DATA <= x"22";
when x"BF7" => DATA <= x"A8";
when x"BF8" => DATA <= x"FC";
when x"BF9" => DATA <= x"F1";
when x"BFA" => DATA <= x"E1";
when x"BFB" => DATA <= x"ED";
when x"BFC" => DATA <= x"45";
when x"BFD" => DATA <= x"E5";
when x"BFE" => DATA <= x"F5";
when x"BFF" => DATA <= x"DB";
when x"C00" => DATA <= x"05";
when x"C01" => DATA <= x"2A";
when x"C02" => DATA <= x"A8";
when x"C03" => DATA <= x"FC";
when x"C04" => DATA <= x"77";
when x"C05" => DATA <= x"23";
when x"C06" => DATA <= x"DB";
when x"C07" => DATA <= x"05";
when x"C08" => DATA <= x"77";
when x"C09" => DATA <= x"23";
when x"C0A" => DATA <= x"22";
when x"C0B" => DATA <= x"A8";
when x"C0C" => DATA <= x"FC";
when x"C0D" => DATA <= x"F1";
when x"C0E" => DATA <= x"E1";
when x"C0F" => DATA <= x"ED";
when x"C10" => DATA <= x"45";
when x"C11" => DATA <= x"D3";
when x"C12" => DATA <= x"05";
when x"C13" => DATA <= x"ED";
when x"C14" => DATA <= x"45";
when x"C15" => DATA <= x"23";
when x"C16" => DATA <= x"56";
when x"C17" => DATA <= x"2B";
when x"C18" => DATA <= x"C9";
when x"C19" => DATA <= x"2A";
when x"C1A" => DATA <= x"A0";
when x"C1B" => DATA <= x"3C";
when x"C1C" => DATA <= x"19";
when x"C1D" => DATA <= x"23";
when x"C1E" => DATA <= x"23";
when x"C1F" => DATA <= x"5E";
when x"C20" => DATA <= x"23";
when x"C21" => DATA <= x"56";
when x"C22" => DATA <= x"2B";
when x"C23" => DATA <= x"C9";
when x"C24" => DATA <= x"2A";
when x"C25" => DATA <= x"D3";
when x"C26" => DATA <= x"05";
when x"C27" => DATA <= x"ED";
when x"C28" => DATA <= x"45";
when x"C29" => DATA <= x"CA";
when x"C2A" => DATA <= x"0D";
when x"C2B" => DATA <= x"37";
when x"C2C" => DATA <= x"EB";
when x"C2D" => DATA <= x"D5";
when x"C2E" => DATA <= x"CD";
when x"C2F" => DATA <= x"ED";
when x"C30" => DATA <= x"36";
when x"C31" => DATA <= x"EB";
when x"C32" => DATA <= x"22";
when x"C33" => DATA <= x"A4";
when x"C34" => DATA <= x"3C";
when x"C35" => DATA <= x"D1";
when x"C36" => DATA <= x"C3";
when x"C37" => DATA <= x"39";
when x"C38" => DATA <= x"37";
when x"C39" => DATA <= x"D3";
when x"C3A" => DATA <= x"05";
when x"C3B" => DATA <= x"ED";
when x"C3C" => DATA <= x"45";
when x"C3D" => DATA <= x"20";
when x"C3E" => DATA <= x"00";
when x"C3F" => DATA <= x"EB";
when x"C40" => DATA <= x"19";
when x"C41" => DATA <= x"22";
when x"C42" => DATA <= x"A2";
when x"C43" => DATA <= x"3C";
when x"C44" => DATA <= x"D5";
when x"C45" => DATA <= x"EB";
when x"C46" => DATA <= x"2A";
when x"C47" => DATA <= x"AC";
when x"C48" => DATA <= x"3C";
when x"C49" => DATA <= x"CD";
when x"C4A" => DATA <= x"82";
when x"C4B" => DATA <= x"0D";
when x"C4C" => DATA <= x"D1";
when x"C4D" => DATA <= x"D3";
when x"C4E" => DATA <= x"05";
when x"C4F" => DATA <= x"ED";
when x"C50" => DATA <= x"45";
when x"C51" => DATA <= x"7B";
when x"C52" => DATA <= x"3C";
when x"C53" => DATA <= x"25";
when x"C54" => DATA <= x"3A";
when x"C55" => DATA <= x"7D";
when x"C56" => DATA <= x"3C";
when x"C57" => DATA <= x"B7";
when x"C58" => DATA <= x"CD";
when x"C59" => DATA <= x"82";
when x"C5A" => DATA <= x"0D";
when x"C5B" => DATA <= x"DA";
when x"C5C" => DATA <= x"87";
when x"C5D" => DATA <= x"38";
when x"C5E" => DATA <= x"2A";
when x"C5F" => DATA <= x"A0";
when x"C60" => DATA <= x"3C";
when x"C61" => DATA <= x"D3";
when x"C62" => DATA <= x"05";
when x"C63" => DATA <= x"ED";
when x"C64" => DATA <= x"45";
when x"C65" => DATA <= x"D5";
when x"C66" => DATA <= x"CD";
when x"C67" => DATA <= x"E4";
when x"C68" => DATA <= x"36";
when x"C69" => DATA <= x"EB";
when x"C6A" => DATA <= x"2A";
when x"C6B" => DATA <= x"A8";
when x"C6C" => DATA <= x"3C";
when x"C6D" => DATA <= x"EB";
when x"C6E" => DATA <= x"7B";
when x"C6F" => DATA <= x"E6";
when x"C70" => DATA <= x"E0";
when x"C71" => DATA <= x"5F";
when x"C72" => DATA <= x"7B";
when x"C73" => DATA <= x"B2";
when x"C74" => DATA <= x"C2";
when x"C75" => DATA <= x"00";
when x"C76" => DATA <= x"05";
when x"C77" => DATA <= x"00";
when x"C78" => DATA <= x"05";
when x"C79" => DATA <= x"04";
when x"C7A" => DATA <= x"05";
when x"C7B" => DATA <= x"08";
when x"C7C" => DATA <= x"0E";
when x"C7D" => DATA <= x"04";
when x"C7E" => DATA <= x"01";
when x"C7F" => DATA <= x"01";
when x"C80" => DATA <= x"05";
when x"C81" => DATA <= x"00";
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when x"C83" => DATA <= x"20";
when x"C84" => DATA <= x"10";
when x"C85" => DATA <= x"0D";
when x"C86" => DATA <= x"00";
when x"C87" => DATA <= x"08";
when x"C88" => DATA <= x"80";
when x"C89" => DATA <= x"05";
when x"C8A" => DATA <= x"00";
when x"C8B" => DATA <= x"05";
when x"C8C" => DATA <= x"00";
when x"C8D" => DATA <= x"05";
when x"C8E" => DATA <= x"00";
when x"C8F" => DATA <= x"00";
when x"C90" => DATA <= x"00";
when x"C91" => DATA <= x"05";
when x"C92" => DATA <= x"09";
when x"C93" => DATA <= x"05";
when x"C94" => DATA <= x"00";
when x"C95" => DATA <= x"08";
when x"C96" => DATA <= x"20";
when x"C97" => DATA <= x"10";
when x"C98" => DATA <= x"01";
when x"C99" => DATA <= x"0D";
when x"C9A" => DATA <= x"80";
when x"C9B" => DATA <= x"08";
when x"C9C" => DATA <= x"80";
when x"C9D" => DATA <= x"B0";
when x"C9E" => DATA <= x"FC";
when x"C9F" => DATA <= x"80";
when x"CA0" => DATA <= x"20";
when x"CA1" => DATA <= x"FF";
when x"CA2" => DATA <= x"00";
when x"CA3" => DATA <= x"00";
when x"CA4" => DATA <= x"00";
when x"CA5" => DATA <= x"D5";
when x"CA6" => DATA <= x"F5";
when x"CA7" => DATA <= x"2A";
when x"CA8" => DATA <= x"A8";
when x"CA9" => DATA <= x"FC";
when x"CAA" => DATA <= x"00";
when x"CAB" => DATA <= x"00";
when x"CAC" => DATA <= x"B0";
when x"CAD" => DATA <= x"FC";
when x"CAE" => DATA <= x"00";
when x"CAF" => DATA <= x"00";
when x"CB0" => DATA <= x"36";
when x"CB1" => DATA <= x"2A";
when x"CB2" => DATA <= x"A0";
when x"CB3" => DATA <= x"3C";
when x"CB4" => DATA <= x"19";
when x"CB5" => DATA <= x"F1";
when x"CB6" => DATA <= x"F5";
when x"CB7" => DATA <= x"77";
when x"CB8" => DATA <= x"7B";
when x"CB9" => DATA <= x"E6";
when x"CBA" => DATA <= x"1F";
when x"CBB" => DATA <= x"FE";
when x"CBC" => DATA <= x"1F";
when x"CBD" => DATA <= x"CA";
when x"CBE" => DATA <= x"95";
when x"CBF" => DATA <= x"37";
when x"CC0" => DATA <= x"13";
when x"CC1" => DATA <= x"CC";
when x"CC2" => DATA <= x"9F";
when x"CC3" => DATA <= x"37";
when x"CC4" => DATA <= x"EB";
when x"CC5" => DATA <= x"22";
when x"CC6" => DATA <= x"A8";
when x"CC7" => DATA <= x"3C";
when x"CC8" => DATA <= x"F1";
when x"CC9" => DATA <= x"D1";
when x"CCA" => DATA <= x"C9";
when x"CCB" => DATA <= x"7B";
when x"CCC" => DATA <= x"E6";
when x"CCD" => DATA <= x"E0";
when x"CCE" => DATA <= x"5F";
when x"CCF" => DATA <= x"CD";
when x"CD0" => DATA <= x"ED";
when x"CD1" => DATA <= x"36";
when x"CD2" => DATA <= x"7A";
when x"CD3" => DATA <= x"B3";
when x"CD4" => DATA <= x"CA";
when x"CD5" => DATA <= x"F8";
when x"CD6" => DATA <= x"36";
when x"CD7" => DATA <= x"13";
when x"CD8" => DATA <= x"13";
when x"CD9" => DATA <= x"13";
when x"CDA" => DATA <= x"13";
when x"CDB" => DATA <= x"C9";
when x"CDC" => DATA <= x"D5";
when x"CDD" => DATA <= x"EB";
when x"CDE" => DATA <= x"2A";
when x"CDF" => DATA <= x"A0";
when x"CE0" => DATA <= x"3C";
when x"CE1" => DATA <= x"EB";
when x"CE2" => DATA <= x"7D";
when x"CE3" => DATA <= x"E6";
when x"CE4" => DATA <= x"1F";
when x"CE5" => DATA <= x"C2";
when x"CE6" => DATA <= x"C0";
when x"CE7" => DATA <= x"37";
when x"CE8" => DATA <= x"7D";
when x"CE9" => DATA <= x"F6";
when x"CEA" => DATA <= x"04";
when x"CEB" => DATA <= x"6F";
when x"CEC" => DATA <= x"EB";
when x"CED" => DATA <= x"19";
when x"CEE" => DATA <= x"7E";
when x"CEF" => DATA <= x"EB";
when x"CF0" => DATA <= x"D1";
when x"CF1" => DATA <= x"C9";
when x"CF2" => DATA <= x"CD";
when x"CF3" => DATA <= x"B0";
when x"CF4" => DATA <= x"37";
when x"CF5" => DATA <= x"F5";
when x"CF6" => DATA <= x"D5";
when x"CF7" => DATA <= x"EB";
when x"CF8" => DATA <= x"7B";
when x"CF9" => DATA <= x"E6";
when x"CFA" => DATA <= x"1F";
when x"CFB" => DATA <= x"FE";
when x"CFC" => DATA <= x"1F";
when x"CFD" => DATA <= x"CA";
when x"CFE" => DATA <= x"D5";
when x"CFF" => DATA <= x"37";
when x"D00" => DATA <= x"13";
when x"D01" => DATA <= x"CC";
when x"D02" => DATA <= x"9F";
when x"D03" => DATA <= x"37";
when x"D04" => DATA <= x"EB";
when x"D05" => DATA <= x"D1";
when x"D06" => DATA <= x"F1";
when x"D07" => DATA <= x"C9";
when x"D08" => DATA <= x"EB";
when x"D09" => DATA <= x"7B";
when x"D0A" => DATA <= x"E6";
when x"D0B" => DATA <= x"E0";
when x"D0C" => DATA <= x"5F";
when x"D0D" => DATA <= x"D5";
when x"D0E" => DATA <= x"CD";
when x"D0F" => DATA <= x"ED";
when x"D10" => DATA <= x"36";
when x"D11" => DATA <= x"7B";
when x"D12" => DATA <= x"B2";
when x"D13" => DATA <= x"C1";
when x"D14" => DATA <= x"C8";
when x"D15" => DATA <= x"AF";
when x"D16" => DATA <= x"77";
when x"D17" => DATA <= x"23";
when x"D18" => DATA <= x"77";
when x"D19" => DATA <= x"2A";
when x"D1A" => DATA <= x"A0";
when x"D1B" => DATA <= x"3C";
when x"D1C" => DATA <= x"19";
when x"D1D" => DATA <= x"73";
when x"D1E" => DATA <= x"23";
when x"D1F" => DATA <= x"72";
when x"D20" => DATA <= x"C5";
when x"D21" => DATA <= x"CD";
when x"D22" => DATA <= x"D2";
when x"D23" => DATA <= x"36";
when x"D24" => DATA <= x"C1";
when x"D25" => DATA <= x"2A";
when x"D26" => DATA <= x"A6";
when x"D27" => DATA <= x"3C";
when x"D28" => DATA <= x"EB";
when x"D29" => DATA <= x"CD";
when x"D2A" => DATA <= x"E4";
when x"D2B" => DATA <= x"36";
when x"D2C" => DATA <= x"71";
when x"D2D" => DATA <= x"23";
when x"D2E" => DATA <= x"70";
when x"D2F" => DATA <= x"C9";
when x"D30" => DATA <= x"4C";
when x"D31" => DATA <= x"05";
when x"D32" => DATA <= x"25";
when x"D33" => DATA <= x"10";
when x"D34" => DATA <= x"E3";
when x"D35" => DATA <= x"C9";
when x"D36" => DATA <= x"FF";
when x"D37" => DATA <= x"F0";
when x"D38" => DATA <= x"03";
when x"D39" => DATA <= x"6C";
when x"D3A" => DATA <= x"03";
when x"D3B" => DATA <= x"25";
when x"D3C" => DATA <= x"86";
when x"D3D" => DATA <= x"70";
when x"D3E" => DATA <= x"84";
when x"D3F" => DATA <= x"71";
when x"D40" => DATA <= x"85";
when x"D41" => DATA <= x"72";
when x"D42" => DATA <= x"A0";
when x"D43" => DATA <= x"02";
when x"D44" => DATA <= x"B1";
when x"D45" => DATA <= x"70";
when x"D46" => DATA <= x"85";
when x"D47" => DATA <= x"74";
when x"D48" => DATA <= x"C8";
when x"D49" => DATA <= x"B1";
when x"D4A" => DATA <= x"70";
when x"D4B" => DATA <= x"85";
when x"D4C" => DATA <= x"75";
when x"D4D" => DATA <= x"20";
when x"D4E" => DATA <= x"9C";
when x"D4F" => DATA <= x"25";
when x"D50" => DATA <= x"A0";
when x"D51" => DATA <= x"0C";
when x"D52" => DATA <= x"B1";
when x"D53" => DATA <= x"70";
when x"D54" => DATA <= x"48";
when x"D55" => DATA <= x"A5";
when x"D56" => DATA <= x"70";
when x"D57" => DATA <= x"18";
when x"D58" => DATA <= x"69";
when x"D59" => DATA <= x"06";
when x"D5A" => DATA <= x"AA";
when x"D5B" => DATA <= x"A9";
when x"D5C" => DATA <= x"00";
when x"D5D" => DATA <= x"65";
when x"D5E" => DATA <= x"71";
when x"D5F" => DATA <= x"A8";
when x"D60" => DATA <= x"68";
when x"D61" => DATA <= x"48";
when x"D62" => DATA <= x"20";
when x"D63" => DATA <= x"06";
when x"D64" => DATA <= x"04";
when x"D65" => DATA <= x"A0";
when x"D66" => DATA <= x"0A";
when x"D67" => DATA <= x"B1";
when x"D68" => DATA <= x"70";
when x"D69" => DATA <= x"AA";
when x"D6A" => DATA <= x"C8";
when x"D6B" => DATA <= x"B1";
when x"D6C" => DATA <= x"70";
when x"D6D" => DATA <= x"85";
when x"D6E" => DATA <= x"76";
when x"D6F" => DATA <= x"D0";
when x"D70" => DATA <= x"03";
when x"D71" => DATA <= x"8A";
when x"D72" => DATA <= x"F0";
when x"D73" => DATA <= x"4E";
when x"D74" => DATA <= x"8A";
when x"D75" => DATA <= x"F0";
when x"D76" => DATA <= x"02";
when x"D77" => DATA <= x"E6";
when x"D78" => DATA <= x"76";
when x"D79" => DATA <= x"68";
when x"D7A" => DATA <= x"6A";
when x"D7B" => DATA <= x"B0";
when x"D7C" => DATA <= x"28";
when x"D7D" => DATA <= x"20";
when x"D7E" => DATA <= x"9B";
when x"D7F" => DATA <= x"25";
when x"D80" => DATA <= x"20";
when x"D81" => DATA <= x"9B";
when x"D82" => DATA <= x"25";
when x"D83" => DATA <= x"20";
when x"D84" => DATA <= x"9B";
when x"D85" => DATA <= x"25";
when x"D86" => DATA <= x"A0";
when x"D87" => DATA <= x"00";
when x"D88" => DATA <= x"AD";
when x"D89" => DATA <= x"E5";
when x"D8A" => DATA <= x"FE";
when x"D8B" => DATA <= x"91";
when x"D8C" => DATA <= x"74";
when x"D8D" => DATA <= x"20";
when x"D8E" => DATA <= x"9B";
when x"D8F" => DATA <= x"25";
when x"D90" => DATA <= x"20";
when x"D91" => DATA <= x"9B";
when x"D92" => DATA <= x"25";
when x"D93" => DATA <= x"20";
when x"D94" => DATA <= x"9B";
when x"D95" => DATA <= x"25";
when x"D96" => DATA <= x"E6";
when x"D97" => DATA <= x"74";
when x"D98" => DATA <= x"D0";
when x"D99" => DATA <= x"02";
when x"D9A" => DATA <= x"E6";
when x"D9B" => DATA <= x"75";
when x"D9C" => DATA <= x"CA";
when x"D9D" => DATA <= x"D0";
when x"D9E" => DATA <= x"E9";
when x"D9F" => DATA <= x"C6";
when x"DA0" => DATA <= x"76";
when x"DA1" => DATA <= x"D0";
when x"DA2" => DATA <= x"E5";
when x"DA3" => DATA <= x"F0";
when x"DA4" => DATA <= x"1D";
when x"DA5" => DATA <= x"A0";
when x"DA6" => DATA <= x"00";
when x"DA7" => DATA <= x"B1";
when x"DA8" => DATA <= x"74";
when x"DA9" => DATA <= x"8D";
when x"DAA" => DATA <= x"E5";
when x"DAB" => DATA <= x"FE";
when x"DAC" => DATA <= x"20";
when x"DAD" => DATA <= x"9B";
when x"DAE" => DATA <= x"25";
when x"DAF" => DATA <= x"20";
when x"DB0" => DATA <= x"9B";
when x"DB1" => DATA <= x"25";
when x"DB2" => DATA <= x"20";
when x"DB3" => DATA <= x"9B";
when x"DB4" => DATA <= x"25";
when x"DB5" => DATA <= x"E6";
when x"DB6" => DATA <= x"74";
when x"DB7" => DATA <= x"D0";
when x"DB8" => DATA <= x"02";
when x"DB9" => DATA <= x"E6";
when x"DBA" => DATA <= x"75";
when x"DBB" => DATA <= x"CA";
when x"DBC" => DATA <= x"D0";
when x"DBD" => DATA <= x"E9";
when x"DBE" => DATA <= x"C6";
when x"DBF" => DATA <= x"76";
when x"DC0" => DATA <= x"D0";
when x"DC1" => DATA <= x"E5";
when x"DC2" => DATA <= x"20";
when x"DC3" => DATA <= x"A4";
when x"DC4" => DATA <= x"25";
when x"DC5" => DATA <= x"A6";
when x"DC6" => DATA <= x"70";
when x"DC7" => DATA <= x"A4";
when x"DC8" => DATA <= x"71";
when x"DC9" => DATA <= x"A5";
when x"DCA" => DATA <= x"72";
when x"DCB" => DATA <= x"60";
when x"DCC" => DATA <= x"A9";
when x"DCD" => DATA <= x"C7";
when x"DCE" => DATA <= x"20";
when x"DCF" => DATA <= x"06";
when x"DD0" => DATA <= x"04";
when x"DD1" => DATA <= x"90";
when x"DD2" => DATA <= x"F9";
when x"DD3" => DATA <= x"60";
when x"DD4" => DATA <= x"A9";
when x"DD5" => DATA <= x"87";
when x"DD6" => DATA <= x"20";
when x"DD7" => DATA <= x"06";
when x"DD8" => DATA <= x"04";
when x"DD9" => DATA <= x"60";
when x"DDA" => DATA <= x"00";
when x"DDB" => DATA <= x"25";
when x"DDC" => DATA <= x"36";
when x"DDD" => DATA <= x"42";
when x"DDE" => DATA <= x"FE";
when x"DDF" => DATA <= x"02";
when x"DE0" => DATA <= x"30";
when x"DE1" => DATA <= x"22";
when x"DE2" => DATA <= x"F5";
when x"DE3" => DATA <= x"3A";
when x"DE4" => DATA <= x"81";
when x"DE5" => DATA <= x"FF";
when x"DE6" => DATA <= x"E6";
when x"DE7" => DATA <= x"01";
when x"DE8" => DATA <= x"32";
when x"DE9" => DATA <= x"AA";
when x"DEA" => DATA <= x"FC";
when x"DEB" => DATA <= x"F1";
when x"DEC" => DATA <= x"32";
when x"DED" => DATA <= x"81";
when x"DEE" => DATA <= x"FF";
when x"DEF" => DATA <= x"B7";
when x"DF0" => DATA <= x"20";
when x"DF1" => DATA <= x"08";
when x"DF2" => DATA <= x"21";
when x"DF3" => DATA <= x"71";
when x"DF4" => DATA <= x"F6";
when x"DF5" => DATA <= x"22";
when x"DF6" => DATA <= x"9F";
when x"DF7" => DATA <= x"FF";
when x"DF8" => DATA <= x"18";
when x"DF9" => DATA <= x"06";
when x"DFA" => DATA <= x"21";
when x"DFB" => DATA <= x"0D";
when x"DFC" => DATA <= x"FE";
when x"DFD" => DATA <= x"22";
when x"DFE" => DATA <= x"9F";
when x"DFF" => DATA <= x"FF";
when x"E00" => DATA <= x"3A";
when x"E01" => DATA <= x"AA";
when x"E02" => DATA <= x"FC";
when x"E03" => DATA <= x"C9";
when x"E04" => DATA <= x"FE";
when x"E05" => DATA <= x"FF";
when x"E06" => DATA <= x"C0";
when x"E07" => DATA <= x"3A";
when x"E08" => DATA <= x"81";
when x"E09" => DATA <= x"FF";
when x"E0A" => DATA <= x"E6";
when x"E0B" => DATA <= x"01";
when x"E0C" => DATA <= x"C9";
when x"E0D" => DATA <= x"4F";
when x"E0E" => DATA <= x"3A";
when x"E0F" => DATA <= x"81";
when x"E10" => DATA <= x"FF";
when x"E11" => DATA <= x"CB";
when x"E12" => DATA <= x"7F";
when x"E13" => DATA <= x"20";
when x"E14" => DATA <= x"12";
when x"E15" => DATA <= x"79";
when x"E16" => DATA <= x"FE";
when x"E17" => DATA <= x"1B";
when x"E18" => DATA <= x"28";
when x"E19" => DATA <= x"04";
when x"E1A" => DATA <= x"CD";
when x"E1B" => DATA <= x"71";
when x"E1C" => DATA <= x"F6";
when x"E1D" => DATA <= x"C9";
when x"E1E" => DATA <= x"3A";
when x"E1F" => DATA <= x"81";
when x"E20" => DATA <= x"FF";
when x"E21" => DATA <= x"CB";
when x"E22" => DATA <= x"FF";
when x"E23" => DATA <= x"32";
when x"E24" => DATA <= x"81";
when x"E25" => DATA <= x"FF";
when x"E26" => DATA <= x"C9";
when x"E27" => DATA <= x"CB";
when x"E28" => DATA <= x"77";
when x"E29" => DATA <= x"C2";
when x"E2A" => DATA <= x"A6";
when x"E2B" => DATA <= x"FE";
when x"E2C" => DATA <= x"CB";
when x"E2D" => DATA <= x"6F";
when x"E2E" => DATA <= x"C2";
when x"E2F" => DATA <= x"D9";
when x"E30" => DATA <= x"FE";
when x"E31" => DATA <= x"79";
when x"E32" => DATA <= x"FE";
when x"E33" => DATA <= x"3D";
when x"E34" => DATA <= x"28";
when x"E35" => DATA <= x"15";
when x"E36" => DATA <= x"FE";
when x"E37" => DATA <= x"3E";
when x"E38" => DATA <= x"28";
when x"E39" => DATA <= x"1A";
when x"E3A" => DATA <= x"FE";
when x"E3B" => DATA <= x"3F";
when x"E3C" => DATA <= x"28";
when x"E3D" => DATA <= x"1F";
when x"E3E" => DATA <= x"FE";
when x"E3F" => DATA <= x"40";
when x"E40" => DATA <= x"28";
when x"E41" => DATA <= x"3E";
when x"E42" => DATA <= x"3A";
when x"E43" => DATA <= x"81";
when x"E44" => DATA <= x"FF";
when x"E45" => DATA <= x"CB";
when x"E46" => DATA <= x"BF";
when x"E47" => DATA <= x"32";
when x"E48" => DATA <= x"81";
when x"E49" => DATA <= x"FF";
when x"E4A" => DATA <= x"C9";
when x"E4B" => DATA <= x"3A";
when x"E4C" => DATA <= x"81";
when x"E4D" => DATA <= x"FF";
when x"E4E" => DATA <= x"CB";
when x"E4F" => DATA <= x"F7";
when x"E50" => DATA <= x"32";
when x"E51" => DATA <= x"81";
when x"E52" => DATA <= x"FF";
when x"E53" => DATA <= x"C9";
when x"E54" => DATA <= x"3A";
when x"E55" => DATA <= x"81";
when x"E56" => DATA <= x"FF";
when x"E57" => DATA <= x"CB";
when x"E58" => DATA <= x"EF";
when x"E59" => DATA <= x"32";
when x"E5A" => DATA <= x"81";
when x"E5B" => DATA <= x"FF";
when x"E5C" => DATA <= x"C9";
when x"E5D" => DATA <= x"CD";
when x"E5E" => DATA <= x"EC";
when x"E5F" => DATA <= x"FE";
when x"E60" => DATA <= x"28";
when x"E61" => DATA <= x"08";
when x"E62" => DATA <= x"FE";
when x"E63" => DATA <= x"00";
when x"E64" => DATA <= x"20";
when x"E65" => DATA <= x"DC";
when x"E66" => DATA <= x"3E";
when x"E67" => DATA <= x"1F";
when x"E68" => DATA <= x"18";
when x"E69" => DATA <= x"02";
when x"E6A" => DATA <= x"3E";
when x"E6B" => DATA <= x"18";
when x"E6C" => DATA <= x"32";
when x"E6D" => DATA <= x"18";
when x"E6E" => DATA <= x"FF";
when x"E6F" => DATA <= x"CD";
when x"E70" => DATA <= x"F5";
when x"E71" => DATA <= x"FE";
when x"E72" => DATA <= x"06";
when x"E73" => DATA <= x"10";
when x"E74" => DATA <= x"21";
when x"E75" => DATA <= x"10";
when x"E76" => DATA <= x"FF";
when x"E77" => DATA <= x"7E";
when x"E78" => DATA <= x"CD";
when x"E79" => DATA <= x"71";
when x"E7A" => DATA <= x"F6";
when x"E7B" => DATA <= x"23";
when x"E7C" => DATA <= x"10";
when x"E7D" => DATA <= x"F9";
when x"E7E" => DATA <= x"18";
when x"E7F" => DATA <= x"C2";
when x"E80" => DATA <= x"CD";
when x"E81" => DATA <= x"EC";
when x"E82" => DATA <= x"FE";
when x"E83" => DATA <= x"28";
when x"E84" => DATA <= x"04";
when x"E85" => DATA <= x"FE";
when x"E86" => DATA <= x"00";
when x"E87" => DATA <= x"20";
when x"E88" => DATA <= x"B9";
when x"E89" => DATA <= x"CD";
when x"E8A" => DATA <= x"F5";
when x"E8B" => DATA <= x"FE";
when x"E8C" => DATA <= x"06";
when x"E8D" => DATA <= x"06";
when x"E8E" => DATA <= x"21";
when x"E8F" => DATA <= x"10";
when x"E90" => DATA <= x"FF";
when x"E91" => DATA <= x"7E";
when x"E92" => DATA <= x"CD";
when x"E93" => DATA <= x"71";
when x"E94" => DATA <= x"F6";
when x"E95" => DATA <= x"23";
when x"E96" => DATA <= x"10";
when x"E97" => DATA <= x"F9";
when x"E98" => DATA <= x"06";
when x"E99" => DATA <= x"05";
when x"E9A" => DATA <= x"21";
when x"E9B" => DATA <= x"1B";
when x"E9C" => DATA <= x"FF";
when x"E9D" => DATA <= x"7E";
when x"E9E" => DATA <= x"CD";
when x"E9F" => DATA <= x"71";
when x"EA0" => DATA <= x"F6";
when x"EA1" => DATA <= x"23";
when x"EA2" => DATA <= x"10";
when x"EA3" => DATA <= x"F9";
when x"EA4" => DATA <= x"18";
when x"EA5" => DATA <= x"9C";
when x"EA6" => DATA <= x"CB";
when x"EA7" => DATA <= x"67";
when x"EA8" => DATA <= x"20";
when x"EA9" => DATA <= x"0F";
when x"EAA" => DATA <= x"79";
when x"EAB" => DATA <= x"D6";
when x"EAC" => DATA <= x"20";
when x"EAD" => DATA <= x"32";
when x"EAE" => DATA <= x"21";
when x"EAF" => DATA <= x"FF";
when x"EB0" => DATA <= x"3A";
when x"EB1" => DATA <= x"81";
when x"EB2" => DATA <= x"FF";
when x"EB3" => DATA <= x"CB";
when x"EB4" => DATA <= x"E7";
when x"EB5" => DATA <= x"32";
when x"EB6" => DATA <= x"81";
when x"EB7" => DATA <= x"FF";
when x"EB8" => DATA <= x"C9";
when x"EB9" => DATA <= x"79";
when x"EBA" => DATA <= x"D6";
when x"EBB" => DATA <= x"20";
when x"EBC" => DATA <= x"32";
when x"EBD" => DATA <= x"20";
when x"EBE" => DATA <= x"FF";
when x"EBF" => DATA <= x"3E";
when x"EC0" => DATA <= x"1F";
when x"EC1" => DATA <= x"CD";
when x"EC2" => DATA <= x"71";
when x"EC3" => DATA <= x"F6";
when x"EC4" => DATA <= x"3A";
when x"EC5" => DATA <= x"20";
when x"EC6" => DATA <= x"FF";
when x"EC7" => DATA <= x"CD";
when x"EC8" => DATA <= x"71";
when x"EC9" => DATA <= x"F6";
when x"ECA" => DATA <= x"3A";
when x"ECB" => DATA <= x"21";
when x"ECC" => DATA <= x"FF";
when x"ECD" => DATA <= x"CD";
when x"ECE" => DATA <= x"71";
when x"ECF" => DATA <= x"F6";
when x"ED0" => DATA <= x"3A";
when x"ED1" => DATA <= x"81";
when x"ED2" => DATA <= x"FF";
when x"ED3" => DATA <= x"E6";
when x"ED4" => DATA <= x"01";
when x"ED5" => DATA <= x"32";
when x"ED6" => DATA <= x"81";
when x"ED7" => DATA <= x"FF";
when x"ED8" => DATA <= x"C9";
when x"ED9" => DATA <= x"79";
when x"EDA" => DATA <= x"B7";
when x"EDB" => DATA <= x"28";
when x"EDC" => DATA <= x"06";
when x"EDD" => DATA <= x"D6";
when x"EDE" => DATA <= x"20";
when x"EDF" => DATA <= x"CD";
when x"EE0" => DATA <= x"71";
when x"EE1" => DATA <= x"F6";
when x"EE2" => DATA <= x"C9";
when x"EE3" => DATA <= x"3A";
when x"EE4" => DATA <= x"81";
when x"EE5" => DATA <= x"FF";
when x"EE6" => DATA <= x"E6";
when x"EE7" => DATA <= x"01";
when x"EE8" => DATA <= x"32";
when x"EE9" => DATA <= x"81";
when x"EEA" => DATA <= x"FF";
when x"EEB" => DATA <= x"C9";
when x"EEC" => DATA <= x"3E";
when x"EED" => DATA <= x"87";
when x"EEE" => DATA <= x"CD";
when x"EEF" => DATA <= x"8E";
when x"EF0" => DATA <= x"F8";
when x"EF1" => DATA <= x"7C";
when x"EF2" => DATA <= x"FE";
when x"EF3" => DATA <= x"03";
when x"EF4" => DATA <= x"C9";
when x"EF5" => DATA <= x"3E";
when x"EF6" => DATA <= x"86";
when x"EF7" => DATA <= x"CD";
when x"EF8" => DATA <= x"8E";
when x"EF9" => DATA <= x"F8";
when x"EFA" => DATA <= x"7D";
when x"EFB" => DATA <= x"32";
when x"EFC" => DATA <= x"11";
when x"EFD" => DATA <= x"FF";
when x"EFE" => DATA <= x"32";
when x"EFF" => DATA <= x"1E";
when x"F00" => DATA <= x"FF";
when x"F01" => DATA <= x"7C";
when x"F02" => DATA <= x"32";
when x"F03" => DATA <= x"12";
when x"F04" => DATA <= x"FF";
when x"F05" => DATA <= x"32";
when x"F06" => DATA <= x"14";
when x"F07" => DATA <= x"FF";
when x"F08" => DATA <= x"32";
when x"F09" => DATA <= x"1F";
when x"F0A" => DATA <= x"FF";
when x"F0B" => DATA <= x"3C";
when x"F0C" => DATA <= x"32";
when x"F0D" => DATA <= x"1A";
when x"F0E" => DATA <= x"FF";
when x"F0F" => DATA <= x"C9";
when x"F10" => DATA <= x"1C";
when x"F11" => DATA <= x"C4";
when x"F12" => DATA <= x"48";
when x"F13" => DATA <= x"4F";
when x"F14" => DATA <= x"C1";
when x"F15" => DATA <= x"0C";
when x"F16" => DATA <= x"1C";
when x"F17" => DATA <= x"00";
when x"F18" => DATA <= x"1F";
when x"F19" => DATA <= x"4F";
when x"F1A" => DATA <= x"48";
when x"F1B" => DATA <= x"0C";
when x"F1C" => DATA <= x"1A";
when x"F1D" => DATA <= x"1F";
when x"F1E" => DATA <= x"22";
when x"F1F" => DATA <= x"28";
when x"F20" => DATA <= x"00";
when x"F21" => DATA <= x"00";
when x"F22" => DATA <= x"00";
when x"F23" => DATA <= x"28";
when x"F24" => DATA <= x"43";
when x"F25" => DATA <= x"29";
when x"F26" => DATA <= x"3B";
when x"F27" => DATA <= x"36";
when x"F28" => DATA <= x"00";
when x"F29" => DATA <= x"21";
when x"F2A" => DATA <= x"2A";
when x"F2B" => DATA <= x"3B";
when x"F2C" => DATA <= x"C3";
when x"F2D" => DATA <= x"77";
when x"F2E" => DATA <= x"19";
when x"F2F" => DATA <= x"C5";
when x"F30" => DATA <= x"E5";
when x"F31" => DATA <= x"7E";
when x"F32" => DATA <= x"E6";
when x"F33" => DATA <= x"03";
when x"F34" => DATA <= x"47";
when x"F35" => DATA <= x"0E";
when x"F36" => DATA <= x"06";
when x"F37" => DATA <= x"23";
when x"F38" => DATA <= x"5E";
when x"F39" => DATA <= x"23";
when x"F3A" => DATA <= x"56";
when x"F3B" => DATA <= x"CD";
when x"F3C" => DATA <= x"48";
when x"F3D" => DATA <= x"1A";
when x"F3E" => DATA <= x"E1";
when x"F3F" => DATA <= x"C1";
when x"F40" => DATA <= x"C9";
when x"F41" => DATA <= x"53";
when x"F42" => DATA <= x"00";
when x"F43" => DATA <= x"00";
when x"F44" => DATA <= x"00";
when x"F45" => DATA <= x"00";
when x"F46" => DATA <= x"00";
when x"F47" => DATA <= x"02";
when x"F48" => DATA <= x"00";
when x"F49" => DATA <= x"00";
when x"F4A" => DATA <= x"00";
when x"F4B" => DATA <= x"00";
when x"F4C" => DATA <= x"0A";
when x"F4D" => DATA <= x"00";
when x"F4E" => DATA <= x"00";
when x"F4F" => DATA <= x"00";
when x"F50" => DATA <= x"00";
when x"F51" => DATA <= x"00";
when x"F52" => DATA <= x"00";
when x"F53" => DATA <= x"00";
when x"F54" => DATA <= x"00";
when x"F55" => DATA <= x"00";
when x"F56" => DATA <= x"00";
when x"F57" => DATA <= x"00";
when x"F58" => DATA <= x"00";
when x"F59" => DATA <= x"00";
when x"F5A" => DATA <= x"00";
when x"F5B" => DATA <= x"00";
when x"F5C" => DATA <= x"00";
when x"F5D" => DATA <= x"00";
when x"F5E" => DATA <= x"00";
when x"F5F" => DATA <= x"00";
when x"F60" => DATA <= x"00";
when x"F61" => DATA <= x"00";
when x"F62" => DATA <= x"00";
when x"F63" => DATA <= x"00";
when x"F64" => DATA <= x"00";
when x"F65" => DATA <= x"00";
when x"F66" => DATA <= x"00";
when x"F67" => DATA <= x"00";
when x"F68" => DATA <= x"00";
when x"F69" => DATA <= x"00";
when x"F6A" => DATA <= x"00";
when x"F6B" => DATA <= x"00";
when x"F6C" => DATA <= x"00";
when x"F6D" => DATA <= x"00";
when x"F6E" => DATA <= x"00";
when x"F6F" => DATA <= x"00";
when x"F70" => DATA <= x"00";
when x"F71" => DATA <= x"00";
when x"F72" => DATA <= x"00";
when x"F73" => DATA <= x"00";
when x"F74" => DATA <= x"00";
when x"F75" => DATA <= x"00";
when x"F76" => DATA <= x"00";
when x"F77" => DATA <= x"00";
when x"F78" => DATA <= x"00";
when x"F79" => DATA <= x"00";
when x"F7A" => DATA <= x"00";
when x"F7B" => DATA <= x"00";
when x"F7C" => DATA <= x"00";
when x"F7D" => DATA <= x"00";
when x"F7E" => DATA <= x"00";
when x"F7F" => DATA <= x"00";
when x"F80" => DATA <= x"00";
when x"F81" => DATA <= x"00";
when x"F82" => DATA <= x"00";
when x"F83" => DATA <= x"01";
when x"F84" => DATA <= x"B2";
when x"F85" => DATA <= x"FA";
when x"F86" => DATA <= x"02";
when x"F87" => DATA <= x"14";
when x"F88" => DATA <= x"95";
when x"F89" => DATA <= x"00";
when x"F8A" => DATA <= x"01";
when x"F8B" => DATA <= x"00";
when x"F8C" => DATA <= x"00";
when x"F8D" => DATA <= x"3C";
when x"F8E" => DATA <= x"1A";
when x"F8F" => DATA <= x"FF";
when x"F90" => DATA <= x"FF";
when x"F91" => DATA <= x"01";
when x"F92" => DATA <= x"00";
when x"F93" => DATA <= x"00";
when x"F94" => DATA <= x"00";
when x"F95" => DATA <= x"00";
when x"F96" => DATA <= x"00";
when x"F97" => DATA <= x"00";
when x"F98" => DATA <= x"00";
when x"F99" => DATA <= x"00";
when x"F9A" => DATA <= x"74";
when x"F9B" => DATA <= x"4C";
when x"F9C" => DATA <= x"D6";
when x"F9D" => DATA <= x"5E";
when x"F9E" => DATA <= x"C3";
when x"F9F" => DATA <= x"71";
when x"FA0" => DATA <= x"F6";
when x"FA1" => DATA <= x"C3";
when x"FA2" => DATA <= x"AE";
when x"FA3" => DATA <= x"F5";
when x"FA4" => DATA <= x"C3";
when x"FA5" => DATA <= x"5C";
when x"FA6" => DATA <= x"F5";
when x"FA7" => DATA <= x"C3";
when x"FA8" => DATA <= x"3B";
when x"FA9" => DATA <= x"F5";
when x"FAA" => DATA <= x"C3";
when x"FAB" => DATA <= x"76";
when x"FAC" => DATA <= x"F4";
when x"FAD" => DATA <= x"C3";
when x"FAE" => DATA <= x"71";
when x"FAF" => DATA <= x"F4";
when x"FB0" => DATA <= x"C3";
when x"FB1" => DATA <= x"FD";
when x"FB2" => DATA <= x"FA";
when x"FB3" => DATA <= x"C3";
when x"FB4" => DATA <= x"0E";
when x"FB5" => DATA <= x"F6";
when x"FB6" => DATA <= x"C3";
when x"FB7" => DATA <= x"0E";
when x"FB8" => DATA <= x"FE";
when x"FB9" => DATA <= x"C3";
when x"FBA" => DATA <= x"CE";
when x"FBB" => DATA <= x"F2";
when x"FBC" => DATA <= x"C3";
when x"FBD" => DATA <= x"A4";
when x"FBE" => DATA <= x"FA";
when x"FBF" => DATA <= x"C3";
when x"FC0" => DATA <= x"5E";
when x"FC1" => DATA <= x"F6";
when x"FC2" => DATA <= x"C3";
when x"FC3" => DATA <= x"1B";
when x"FC4" => DATA <= x"F6";
when x"FC5" => DATA <= x"C3";
when x"FC6" => DATA <= x"3F";
when x"FC7" => DATA <= x"F6";
when x"FC8" => DATA <= x"C3";
when x"FC9" => DATA <= x"DE";
when x"FCA" => DATA <= x"FD";
when x"FCB" => DATA <= x"C3";
when x"FCC" => DATA <= x"E8";
when x"FCD" => DATA <= x"F8";
when x"FCE" => DATA <= x"C3";
when x"FCF" => DATA <= x"D2";
when x"FD0" => DATA <= x"F9";
when x"FD1" => DATA <= x"C3";
when x"FD2" => DATA <= x"4E";
when x"FD3" => DATA <= x"FA";
when x"FD4" => DATA <= x"C3";
when x"FD5" => DATA <= x"FC";
when x"FD6" => DATA <= x"F9";
when x"FD7" => DATA <= x"C3";
when x"FD8" => DATA <= x"F0";
when x"FD9" => DATA <= x"F9";
when x"FDA" => DATA <= x"C3";
when x"FDB" => DATA <= x"9F";
when x"FDC" => DATA <= x"F9";
when x"FDD" => DATA <= x"C3";
when x"FDE" => DATA <= x"10";
when x"FDF" => DATA <= x"FA";
when x"FE0" => DATA <= x"C3";
when x"FE1" => DATA <= x"90";
when x"FE2" => DATA <= x"F6";
when x"FE3" => DATA <= x"FE";
when x"FE4" => DATA <= x"0D";
when x"FE5" => DATA <= x"20";
when x"FE6" => DATA <= x"07";
when x"FE7" => DATA <= x"3E";
when x"FE8" => DATA <= x"0A";
when x"FE9" => DATA <= x"CD";
when x"FEA" => DATA <= x"EE";
when x"FEB" => DATA <= x"FF";
when x"FEC" => DATA <= x"3E";
when x"FED" => DATA <= x"0D";
when x"FEE" => DATA <= x"C3";
when x"FEF" => DATA <= x"71";
when x"FF0" => DATA <= x"F6";
when x"FF1" => DATA <= x"C3";
when x"FF2" => DATA <= x"EF";
when x"FF3" => DATA <= x"F8";
when x"FF4" => DATA <= x"C3";
when x"FF5" => DATA <= x"8E";
when x"FF6" => DATA <= x"F8";
when x"FF7" => DATA <= x"C3";
when x"FF8" => DATA <= x"B7";
when x"FF9" => DATA <= x"F6";
when x"FFA" => DATA <= x"AC";
when x"FFB" => DATA <= x"FA";
when x"FFC" => DATA <= x"70";
when x"FFD" => DATA <= x"F6";
when x"FFE" => DATA <= x"82";
when x"FFF" => DATA <= x"FA";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_rnd;
architecture behaviour of ex3_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101";
constant s2: std_logic_vector(3 downto 0) := "0010";
constant s4: std_logic_vector(3 downto 0) := "1011";
constant s3: std_logic_vector(3 downto 0) := "1110";
constant s0: std_logic_vector(3 downto 0) := "1111";
constant s7: std_logic_vector(3 downto 0) := "0001";
constant s8: std_logic_vector(3 downto 0) := "0110";
constant s6: std_logic_vector(3 downto 0) := "0000";
constant s5: std_logic_vector(3 downto 0) := "1010";
constant s9: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer := 50000000;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:23:59 06/15/2015
-- Design Name:
-- Module Name: CU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--convertaddr
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
entity convertaddr is
Port ( op : in STD_LOGIC_VECTOR (4 downto 0);
op_add : out STD_LOGIC_VECTOR (4 downto 0));
end convertaddr;
architecture Behavioral of convertaddr is
begin
process(op)
begin
op_add <= op(3 downto 0) & '0';
end process;
end Behavioral;
--MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
entity MUX is
PORT(
mode:IN STD_LOGIC;
next_add:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
op_addr :IN STD_LOGIC_VECTOR(4 DOWNTO 0);
out_add :OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
end MUX;
architecture Behavioral of MUX is
begin
process(mode,next_add,op_addr)
begin
case mode is
when'0' => out_add<=next_add;
when others => out_add<=op_addr;
end case;
end process;
end Behavioral;
--ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
entity ROM is
Port ( add : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (0 to 23));
end ROM;
architecture Behavioral of ROM is
type microcode_array is array(28 downto 0) of std_logic_vector(0 to 23);
constant code : microcode_array:=(
0=> "110000000000000000000001", 1=> "001100000000000000000010", 2=> "0000100000000000001UUUUU", 4=> "000001000000000000000000",
6=> "000000100000000000000000", 8=> "000000010000000000000000", 10=> "000000001000000000000000", 12=> "000000000100000000000000",
14=> "010000000010000000001111", 15=> "001000000000000000010000", 16=> "000000000001000000000000",18=> "000000000010100000010011",
19=> "000000000000010000010100",20=> "000000000000001000000000", 22=> "010000000010000000010111", 23=> "001000000000000000011000",
24=> "000000000000000100000000", 26=> "000000000000000010000000", 28=> "000000000000000001000000",others=>"000000000000000000000000");
begin
data_out <= code(conv_integer(add));
end Behavioral;
--Splitcode
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Splitcode is
Port (
clock : IN Std_logic;
u_op : in STD_LOGIC_VECTOR (0 TO 23);
control : out STD_LOGIC_VECTOR (0 TO 17);
mode_sel: out STD_LOGIC;
next_add : out STD_LOGIC_VECTOR (4 DOWNTO 0));
end Splitcode;
architecture Behavioral of Splitcode is
SIGNAL int_reg : Std_logic_vector(0 TO 23);
BEGIN
main_proc : PROCESS
BEGIN
WAIT UNTIL falling_edge(clock);
int_reg <= u_op;
END PROCESS;
control <= int_reg(0 TO 17);
mode_sel<= int_reg(18);
next_add <= int_reg(19 TO 23);
end Behavioral;
--CU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CU is
Port ( clk : in STD_LOGIC;
op_code : in STD_LOGIC_VECTOR (4 downto 0);
ctrl_signal : out STD_LOGIC_VECTOR (17 downto 0));end CU;
architecture Behavioral of CU is
component Splitcode
Port (
clock : IN Std_logic;
u_op : in STD_LOGIC_VECTOR (0 TO 23);
control : out STD_LOGIC_VECTOR (0 TO 17);
mode_sel: out STD_LOGIC;
next_add : out STD_LOGIC_VECTOR (4 DOWNTO 0));
end component;
component convertaddr
Port (
op : in STD_LOGIC_VECTOR (4 downto 0);
op_add : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component MUX
PORT(
mode:IN STD_LOGIC;
next_add:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
op_addr :IN STD_LOGIC_VECTOR(4 DOWNTO 0);
out_add :OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
end component;
component ROM
Port (
add : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (0 to 23));
end component;
signal op_add_MUX:std_logic_vector(4 downto 0);
signal mode_MUX :std_logic;
signal next_add_MUX:std_logic_vector(4 downto 0);
signal MUX_CM :std_logic_vector(4 downto 0);
signal CM_CMAR :std_logic_vector(0 to 23);
begin
unit1:convertaddr port map(op_code, op_add_MUX);
unit2:MUX port map(mode_MUX, next_add_MUX, op_add_MUX, MUX_CM);
unit3:ROM port map(MUX_CM, CM_CMAR);
unit4:Splitcode port map(clk, CM_CMAR, ctrl_signal, mode_MUX, next_add_MUX);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FileName: vga_controller.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 05/10/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 208; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 336; --horiztonal back porch width in pixels
h_pixels : INTEGER := 1920; --horiztonal display width in pixels
h_fp : INTEGER := 128; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 3; --vertical sync pulse width in rows
v_bp : INTEGER := 38; --vertical back porch width in rows
v_pixels : INTEGER := 1200; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT INTEGER; --horizontal pixel coordinate
row : OUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= 0; --reset column pixel coordinate
row <= 0; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= v_count; --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior; |
--------------------------------------------------------------------------------
--
-- FileName: vga_controller.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 05/10/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 208; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 336; --horiztonal back porch width in pixels
h_pixels : INTEGER := 1920; --horiztonal display width in pixels
h_fp : INTEGER := 128; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 3; --vertical sync pulse width in rows
v_bp : INTEGER := 38; --vertical back porch width in rows
v_pixels : INTEGER := 1200; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT INTEGER; --horizontal pixel coordinate
row : OUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= 0; --reset column pixel coordinate
row <= 0; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= v_count; --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior; |
entity test is
type t;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 17:53:12 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => Q(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 2) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(1 downto 0) => B"00",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => dout(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg_0(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gcc0.gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
D(11 downto 0) <= \^d\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(3),
O => \gc0.count[0]_i_2_n_0\
);
\gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(2),
O => \gc0.count[0]_i_3_n_0\
);
\gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(1),
O => \gc0.count[0]_i_4_n_0\
);
\gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^d\(0),
O => \gc0.count[0]_i_5_n_0\
);
\gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(7),
O => \gc0.count[4]_i_2_n_0\
);
\gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(6),
O => \gc0.count[4]_i_3_n_0\
);
\gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(5),
O => \gc0.count[4]_i_4_n_0\
);
\gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(4),
O => \gc0.count[4]_i_5_n_0\
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(11),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(10),
O => \gc0.count[8]_i_3_n_0\
);
\gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(9),
O => \gc0.count[8]_i_4_n_0\
);
\gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(8),
O => \gc0.count[8]_i_5_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(0),
Q => Q(0),
R => srst
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(10),
Q => Q(10),
R => srst
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(11),
Q => Q(11),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(1),
Q => Q(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(2),
Q => Q(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(3),
Q => Q(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(4),
Q => Q(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(5),
Q => Q(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(6),
Q => Q(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(7),
Q => Q(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(8),
Q => Q(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(9),
Q => Q(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_7\,
Q => \^d\(0),
S => srst
);
\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gc0.count_reg[0]_i_1_n_4\,
O(2) => \gc0.count_reg[0]_i_1_n_5\,
O(1) => \gc0.count_reg[0]_i_1_n_6\,
O(0) => \gc0.count_reg[0]_i_1_n_7\,
S(3) => \gc0.count[0]_i_2_n_0\,
S(2) => \gc0.count[0]_i_3_n_0\,
S(1) => \gc0.count[0]_i_4_n_0\,
S(0) => \gc0.count[0]_i_5_n_0\
);
\gc0.count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_5\,
Q => \^d\(10),
R => srst
);
\gc0.count_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_4\,
Q => \^d\(11),
R => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_6\,
Q => \^d\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_5\,
Q => \^d\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_4\,
Q => \^d\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_7\,
Q => \^d\(4),
R => srst
);
\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[4]_i_1_n_4\,
O(2) => \gc0.count_reg[4]_i_1_n_5\,
O(1) => \gc0.count_reg[4]_i_1_n_6\,
O(0) => \gc0.count_reg[4]_i_1_n_7\,
S(3) => \gc0.count[4]_i_2_n_0\,
S(2) => \gc0.count[4]_i_3_n_0\,
S(1) => \gc0.count[4]_i_4_n_0\,
S(0) => \gc0.count[4]_i_5_n_0\
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_6\,
Q => \^d\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_5\,
Q => \^d\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_4\,
Q => \^d\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_7\,
Q => \^d\(8),
R => srst
);
\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[8]_i_1_n_4\,
O(2) => \gc0.count_reg[8]_i_1_n_5\,
O(1) => \gc0.count_reg[8]_i_1_n_6\,
O(0) => \gc0.count_reg[8]_i_1_n_7\,
S(3) => \gc0.count[8]_i_2_n_0\,
S(2) => \gc0.count[8]_i_3_n_0\,
S(1) => \gc0.count[8]_i_4_n_0\,
S(0) => \gc0.count[8]_i_5_n_0\
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_6\,
Q => \^d\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
srst : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gcc0.gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\gcc0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(3),
O => \gcc0.gc0.count[0]_i_2_n_0\
);
\gcc0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(2),
O => \gcc0.gc0.count[0]_i_3_n_0\
);
\gcc0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(1),
O => \gcc0.gc0.count[0]_i_4_n_0\
);
\gcc0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(7),
O => \gcc0.gc0.count[4]_i_2_n_0\
);
\gcc0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(6),
O => \gcc0.gc0.count[4]_i_3_n_0\
);
\gcc0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(5),
O => \gcc0.gc0.count[4]_i_4_n_0\
);
\gcc0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(4),
O => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(11),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(10),
O => \gcc0.gc0.count[8]_i_3_n_0\
);
\gcc0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(9),
O => \gcc0.gc0.count[8]_i_4_n_0\
);
\gcc0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(8),
O => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(10),
Q => \^q\(10),
R => srst
);
\gcc0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(11),
Q => \^q\(11),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_7\,
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gcc0.gc0.count_reg[0]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[0]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[0]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[0]_i_1_n_7\,
S(3) => \gcc0.gc0.count[0]_i_2_n_0\,
S(2) => \gcc0.gc0.count[0]_i_3_n_0\,
S(1) => \gcc0.gc0.count[0]_i_4_n_0\,
S(0) => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_5\,
Q => p_12_out(10),
R => srst
);
\gcc0.gc0.count_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_4\,
Q => p_12_out(11),
R => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_6\,
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_5\,
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_4\,
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_7\,
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[4]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[4]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[4]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[4]_i_1_n_7\,
S(3) => \gcc0.gc0.count[4]_i_2_n_0\,
S(2) => \gcc0.gc0.count[4]_i_3_n_0\,
S(1) => \gcc0.gc0.count[4]_i_4_n_0\,
S(0) => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_6\,
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_5\,
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_4\,
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_7\,
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gcc0.gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[8]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[8]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[8]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[8]_i_1_n_7\,
S(3) => \gcc0.gc0.count[8]_i_2_n_0\,
S(2) => \gcc0.gc0.count[8]_i_3_n_0\,
S(1) => \gcc0.gc0.count[8]_i_4_n_0\,
S(0) => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_6\,
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => D(0),
I2 => \^q\(1),
I3 => D(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => D(2),
I2 => \^q\(3),
I3 => D(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => D(4),
I2 => \^q\(5),
I3 => D(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => D(6),
I2 => \^q\(7),
I3 => D(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => D(8),
I2 => \^q\(9),
I3 => D(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => ram_empty_i_reg_3
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_0(5)
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => D(10),
I2 => \^q\(11),
I3 => D(11),
O => v1_reg(5)
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => p_12_out(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_1(5)
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => ram_empty_i_reg_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => srst,
I1 => ram_empty_fb_i,
I2 => rd_en,
O => tmp_ram_rd_en
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2
port map (
comp1 => comp1,
v1_reg(5 downto 0) => v1_reg(5 downto 0)
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => \gcc0.gc0.count_d1_reg[11]\
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0
port map (
comp1 => comp1,
v1_reg_0(5 downto 0) => v1_reg_0(5 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(12 downto 4),
dout(8 downto 0) => dout(12 downto 4),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(21 downto 13),
dout(8 downto 0) => dout(21 downto 13),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(30 downto 22),
dout(8 downto 0) => dout(30 downto 22),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(39 downto 31),
dout(8 downto 0) => dout(39 downto 31),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(48 downto 40),
dout(8 downto 0) => dout(48 downto 40),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(57 downto 49),
dout(8 downto 0) => dout(57 downto 49),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(63 downto 58),
dout(5 downto 0) => dout(63 downto 58),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \grss.rsts_n_2\ : STD_LOGIC;
begin
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
E(0) => \grss.rsts_n_2\,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
E(0) => \grss.rsts_n_2\,
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[11]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[11]\ <= \^gcc0.gc0.count_d1_reg[11]\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
clk => clk,
full => full,
\gcc0.gc0.count_d1_reg[11]\ => \^gcc0.gc0.count_d1_reg[11]\,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_0(5 downto 0) => \c1/v1_reg\(5 downto 0),
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
ram_empty_i_reg_4 => ram_empty_i_reg_4,
ram_full_fb_i_reg => \^gcc0.gc0.count_d1_reg[11]\,
srst => srst,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
v1_reg_0(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_1(5 downto 0) => \c1/v1_reg\(5 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
Q(11 downto 0) => p_0_out(11 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_26\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_25\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\gcc0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_24\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_25\,
ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_26\,
rd_en => rd_en,
srst => srst,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11 downto 0) => B"000000000000",
prog_empty_thresh_assert(11 downto 0) => B"000000000000",
prog_empty_thresh_negate(11 downto 0) => B"000000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11 downto 0) => B"000000000000",
prog_full_thresh_assert(11 downto 0) => B"000000000000",
prog_full_thresh_negate(11 downto 0) => B"000000000000",
rd_clk => '0',
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
context c1, c1a, c1b;
context C2, C2A, C2B;
context Con3, cOn3a;
context lib1.C1;
context LIB1.c1;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05400_good.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of internal tristate: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_05400_good is
port (
i_A : in std_logic_vector(3 downto 0); -- Input data of tristate block
i_Sel : in std_logic_vector(3 downto 0); -- Mux select
o_B : out std_logic -- Single module output
);
end STD_05400_good;
architecture Behavioral of STD_05400_good is
signal B : std_logic; -- Module output
begin
-- Simple Mux asynchronous process, output depends on Mux select
P_Mux:process(i_A, i_Sel)
begin
if (i_Sel="00") then
B <= i_A(0);
elsif (i_Sel="01") then
B <= i_A(1);
elsif (i_Sel="10") then
B <= i_A(2);
else
B <= i_A(3);
end if;
end process;
o_B <= B;
end Behavioral;
--CODE |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc169.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00169ent IS
END c04s03b03x00p01n01i00169ent;
ARCHITECTURE c04s03b03x00p01n01i00169arch OF c04s03b03x00p01n01i00169ent IS
BEGIN
TESTING: PROCESS
variable V2 : STRING(1 to 5) := "Hello";
alias a3 : STRING(1 to 5) is V2; -- composite alias of composite
alias a2 : STRING(4 downto 1) is V2(1 to 4);
alias a4 : CHARACTER is V2(4); -- scalar alias of composite
BEGIN
assert V2 = "Hello";
assert A2 = "Hell";
assert V2(1) = 'H';
assert A2(4) = 'H';
assert V2(2) = 'e';
assert A2(3) = 'e';
assert A3 = "Hello";
assert A4 = 'l';
wait for 5 ns;
assert NOT( V2 = "Hello" and
A2 = "Hell" and
V2(1) = 'H' and
A2(4) = 'H' and
V2(2) = 'e' and
A2(3) = 'e' and
A3 = "Hello" and
A4 = 'l' )
report "***PASSED TEST: c04s03b03x00p01n01i00169"
severity NOTE;
assert ( V2 = "Hello" and
A2 = "Hell" and
V2(1) = 'H' and
A2(4) = 'H' and
V2(2) = 'e' and
A2(3) = 'e' and
A3 = "Hello" and
A4 = 'l' )
report "***FAILED TEST: c04s03b03x00p01n01i00169 - Alias of alias composite type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00169arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc169.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00169ent IS
END c04s03b03x00p01n01i00169ent;
ARCHITECTURE c04s03b03x00p01n01i00169arch OF c04s03b03x00p01n01i00169ent IS
BEGIN
TESTING: PROCESS
variable V2 : STRING(1 to 5) := "Hello";
alias a3 : STRING(1 to 5) is V2; -- composite alias of composite
alias a2 : STRING(4 downto 1) is V2(1 to 4);
alias a4 : CHARACTER is V2(4); -- scalar alias of composite
BEGIN
assert V2 = "Hello";
assert A2 = "Hell";
assert V2(1) = 'H';
assert A2(4) = 'H';
assert V2(2) = 'e';
assert A2(3) = 'e';
assert A3 = "Hello";
assert A4 = 'l';
wait for 5 ns;
assert NOT( V2 = "Hello" and
A2 = "Hell" and
V2(1) = 'H' and
A2(4) = 'H' and
V2(2) = 'e' and
A2(3) = 'e' and
A3 = "Hello" and
A4 = 'l' )
report "***PASSED TEST: c04s03b03x00p01n01i00169"
severity NOTE;
assert ( V2 = "Hello" and
A2 = "Hell" and
V2(1) = 'H' and
A2(4) = 'H' and
V2(2) = 'e' and
A2(3) = 'e' and
A3 = "Hello" and
A4 = 'l' )
report "***FAILED TEST: c04s03b03x00p01n01i00169 - Alias of alias composite type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00169arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc169.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00169ent IS
END c04s03b03x00p01n01i00169ent;
ARCHITECTURE c04s03b03x00p01n01i00169arch OF c04s03b03x00p01n01i00169ent IS
BEGIN
TESTING: PROCESS
variable V2 : STRING(1 to 5) := "Hello";
alias a3 : STRING(1 to 5) is V2; -- composite alias of composite
alias a2 : STRING(4 downto 1) is V2(1 to 4);
alias a4 : CHARACTER is V2(4); -- scalar alias of composite
BEGIN
assert V2 = "Hello";
assert A2 = "Hell";
assert V2(1) = 'H';
assert A2(4) = 'H';
assert V2(2) = 'e';
assert A2(3) = 'e';
assert A3 = "Hello";
assert A4 = 'l';
wait for 5 ns;
assert NOT( V2 = "Hello" and
A2 = "Hell" and
V2(1) = 'H' and
A2(4) = 'H' and
V2(2) = 'e' and
A2(3) = 'e' and
A3 = "Hello" and
A4 = 'l' )
report "***PASSED TEST: c04s03b03x00p01n01i00169"
severity NOTE;
assert ( V2 = "Hello" and
A2 = "Hell" and
V2(1) = 'H' and
A2(4) = 'H' and
V2(2) = 'e' and
A2(3) = 'e' and
A3 = "Hello" and
A4 = 'l' )
report "***FAILED TEST: c04s03b03x00p01n01i00169 - Alias of alias composite type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00169arch;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 26-02-2017
-- Module Name: 4-bit-adder.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity four_bit_adder is
port (a, b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
sum : out std_logic_vector(3 downto 0);
c_out : out std_logic);
end entity;
architecture arch_four_bit_adder of four_bit_adder is
component fulladdr is
port (a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end component fulladdr;
signal c : std_logic_vector(4 downto 0);
for all:fulladdr use entity work.fulladdr(arch_fulladdr);
begin
c(0) <= c_in;
c_out <= c(4);
fa0 : fulladdr port map (a(0), b(0), c(0), sum(0), c(1));
fa1 : fulladdr port map (a(1), b(1), c(1), sum(1), c(2));
fa2 : fulladdr port map (a(2), b(2), c(2), sum(2), c(3));
fa3 : fulladdr port map (a(3), b(3), c(3), sum(3), c(4));
end architecture arch_four_bit_adder;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:34 03/28/2016
-- Design Name:
-- Module Name: logical_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logical_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
LOG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end logical_unit;
architecture Combinational of logical_unit is
signal result : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal zro : STD_LOGIC := '0';
begin
with OP select
result <=
RA or RB when "011", -- OR
RA and RB when "010", -- AND
RA and RB when "110", -- ANDI
RB when "100", -- MOV
RA or RB when OTHERS; -- SAFE (I guess)
zro <= '1' when result(15 downto 0) = x"00000000" else '1'; -- Zero
LOG_OUT <= result;
SREG_OUT(2) <= zro;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:30:19 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_iROM - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The instruction ROM for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_iROM is
Port ( addr : in STD_LOGIC_VECTOR (10 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0));
end TestCPU1_iROM;
architecture Behavioral of TestCPU1_iROM is
begin
iROM: process (addr) is
type iROM_array is array (2047 downto 0) of
STD_LOGIC_VECTOR (15 downto 0);
variable iROM: iROM_array := (0 => "0000000000000000", --null
1 => "0001001000011001", --addi r2, r0, 25 --loading r2 with value
2 => "0000001001001000", --add r2, r2, r2
3 => "0000001001001000", --add r2, r2, r2
4 => "0000001001001000", --add r2, r2, r2
5 => "0000001001001000", --add r2, r2, r2
6 => "0000001001001000", --add r2, r2, r2
7 => "0001001001010001", --addi r2, r2,17
8 => "0000001001001000", --add r2, r2, r2
9 => "0000001001001000", --add r2, r2, r2
10 => "0000001001001000", --add r2, r2, r2
11 => "0001001100001111", --addi r3, r0, 15 --loading r3 with value
12 => "0001010000011001", --addi r4, r0, 25 --loading r4 with value
13 => "0000010010010000", --add r4, r4, r4
14 => "0000010010010000", --add r4, r4, r4
15 => "0000010010010000", --add r4, r4, r4
16 => "0000010010010000", --add r4, r4, r4
17 => "0001010110100001", --addi r5, r5, 1 --begin waiting for 20ms
18 => "0010000010101000", --cp r5, r2
19 => "0100000000010101", --bz r0, 21
20 => "0100100000010001", --jp 17
21 => "1000000000000001", --opin 0, 1 --RS = '0' (r1 = 0) sending set function
22 => "1000000000000010", --opin 0, 2 --RW = '0' //leaving at '0' for the rest
23 => "1000000000100000", --opin 1, 0 --E = '1'
24 => "1000000000100011", --opin 1, 3 --DBe = '1'
25 => "1000000000000000", --opin 0, 0 --E = '0'
26 => "1000000000000011", --opin 0, 3 --DBe = '0'
27 => "0001011011000001", --addi r6, r6, 1 --begin waiting for 40us
28 => "0010000011001100", --cp r6, r3
29 => "0100000000011111", --bz r0, 31
30 => "0100100000011011", --jp 27
31 => "0001000100100001", --addi r1, r1 --increment message ROM address
32 => "1000000000100000", --opin 1, 0 --E = '1' (r1 = 1) sending display set
33 => "1000000000100011", --opin 1, 3 --DBe = '1'
34 => "1000000000000000", --opin 0, 0 --E = '0'
35 => "1000000000000011", --opin 0, 3 --DBe = '0'
36 => "0001011111100001", --addi r7, r7, 1 --begin waiting for 40us
37 => "0010000011101100", --cp r7, r3
38 => "0100000000101000", --bz r0, 40
39 => "0100100000100100", --jp 36
40 => "0001000100100001", --addi r1, r1 --increment message ROM address
41 => "1000000000100000", --opin 1, 0 --E = '1' (r1 = 2) sending display clear
42 => "1000000000100011", --opin 1, 3 --DBe = '1'
43 => "1000000000000000", --opin 0, 0 --E = '0'
44 => "1000000000000011", --opin 0, 3 --DBe = '0'
45 => "0001011100000000", --addi r7, r0, 0 --reset r7
46 => "0001011111100001", --addi r7, r7, 1 --begin waiting for 1.60ms
47 => "0010000011110000", --cp r7, r4
48 => "0100000000110010", --bz r0, 50
49 => "0100100000101110", --jp 46
50 => "1000000000100001", --opin 1, 1 --RS = '1' begin writing, leave RS = 1
51 => "0001011100001110", --addi r7, r0, 14
52 => "0001000100100001", --addi r1, r1 --increment message ROM address //begin writing message
53 => "1000000000100000", --opin 1, 0 --E = '1'
54 => "1000000000100011", --opin 1, 3 --DBe = '1'
55 => "1000000000000000", --opin 0, 0 --E = '0'
56 => "1000000000000011", --opin 0, 3 --DBe = '0'
57 => "0001011000000000", --addi r6, r0, 0 --reset r6
58 => "0001011011000001", --addi r6, r6, 1 --pause for 40us
59 => "0010000011001100", --cp r6, r3
60 => "0100000000111110", --bz r0, 62
61 => "0100100000111010", --jp 58 --end pause
62 => "0010000011100100", --cp r1, r7
63 => "0100000001000001", --bz 65
64 => "0100100000110100", --jp 52 --loop until r1 = 14
65 => "0100100001000010", --jp 66 --loop forever
66 => "0100100001000001", --jp 65
others => "0000000000000000");
begin
data_out <= iROM(conv_integer(unsigned(addr)));
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mmb
-- File: ahbtrace_mmb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus and
-- select between several trace buses.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
entity ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1)
);
end;
architecture rtl of ahbtrace_mmb is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32;
constant FILTEN : boolean := ahbfilt /= 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS-1 downto 0);
data : std_logic_vector(255 downto 0);
enable : std_logic;
write : std_logic_vector(7 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(255 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
thaddr : std_logic_vector(31 downto 0);
thwrite : std_logic;
thtrans : std_logic_vector(1 downto 0);
thsize : std_logic_vector(2 downto 0);
thburst : std_logic_vector(2 downto 0);
thmaster : std_logic_vector(3 downto 0);
thmastlock : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TIMEBITS-1 downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
hsel : std_logic;
hwrite : std_logic;
haddr : std_logic_vector(TBUFABITS+4 downto 2);
hrdata : std_logic_vector(31 downto 0);
regacc : std_logic;
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
type fregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
rf : std_ulogic; -- Retry filtering
end record;
type bregtype is record
bsel : std_logic_vector(log2(ntrace) downto 0);
end record;
function ahb_filt_hit (
r : regtype;
rf : fregtype;
hresp : std_logic_vector(1 downto 0)) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((rf.fw and r.thwrite) or (rf.fr and not r.thwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) /= zero32(29 downto 0)) then
if rf.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in rf.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(r.thmaster) and rf.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in rf.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (rf.shsel(i) and rf.smask(i)) /= '0' then
hit := true;
end if;
end loop;
-- Filter on retry response
if (rf.rf = '1' and hresp = HRESP_RETRY) then
hit := true;
end if;
return hit;
end function ahb_filt_hit;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
signal rf, rfin : fregtype;
signal rb, rbin : bregtype;
begin
ctrl : process(rst, ahbsi, tahbmiv, tahbsiv, r, rf, rb, tbo)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable wdata, rdata : std_logic_vector(127 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable tahbmi : ahb_mst_in_type;
variable tahbsi : ahb_slv_in_type;
variable vf : fregtype;
variable vb : bregtype;
variable regaddr : std_logic_vector(4 downto 2);
variable tbaddr : std_logic_vector(3 downto 2);
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
hirq := (others => '0'); hirq(irq) := r.bhit;
vf := rf; vb := rb;
if ntrace = 1 then
tahbmi := tahbmiv(0); tahbsi := tahbsiv(0);
else
tahbmi := tahbmiv(conv_integer(rb.bsel));
tahbsi := tahbsiv(conv_integer(rb.bsel));
end if;
regaddr := r.haddr(4 downto 2); --tbaddr := r.haddr(3 downto 2);
-- trace buffer index and delay counters
if r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (tahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.thaddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.thwrite) or (r.tbreg1.write and r.thwrite)) = '1'))
or ((((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.thwrite) or (r.tbreg2.write and r.thwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1'; bphit := '1';
--else bphit := '1'; v.enable := '0'; end if;
elsif (r.enable = '1') and (r.dcnten = '0') then bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "00000000";
wdata(AHBDW-1 downto 0) := tahbsi.hwdata;
rdata(AHBDW-1 downto 0) := tahbmi.hrdata;
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := r.timer;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := tahbmi.hirq(15 downto 1);
vabufi.data(79) := r.thwrite;
vabufi.data(78 downto 77) := r.thtrans;
vabufi.data(76 downto 74) := r.thsize;
vabufi.data(73 downto 71) := r.thburst;
vabufi.data(70 downto 67) := r.thmaster;
vabufi.data(66) := r.thmastlock;
vabufi.data(65 downto 64) := tahbmi.hresp;
if r.thwrite = '1' then
vabufi.data(63 downto 32) := wdata(31 downto 0);
vabufi.data(223 downto 128) := wdata(127 downto 32);
else
vabufi.data(63 downto 32) := rdata(31 downto 0);
vabufi.data(223 downto 128) := rdata(127 downto 32);
end if;
vabufi.data(31 downto 0) := r.thaddr;
else
if bwidth = 32 then
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+4 downto 5);
end if;
-- Note: HWDATA from register i/f
vabufi.data := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and tahbsi.hready) = '1' then
if not (FILTEN and ahb_filt_hit(r, rf, tahbmi.hresp)) then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "11111111";
end if;
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') and (r.ahbactive and tahbsi.hready) = '1' then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- save AHB transfer parameters
if (tahbsi.hready = '1' ) then
v.thaddr := tahbsi.haddr; v.thwrite := tahbsi.hwrite; v.thtrans := tahbsi.htrans;
v.thsize := tahbsi.hsize; v.thburst := tahbsi.hburst;
v.thmaster := tahbsi.hmaster; v.thmastlock := tahbsi.hmastlock;
v.ahbactive := tahbsi.htrans(1);
if FILTEN then vf.shsel := tahbsi.hsel; end if;
end if;
-- AHB transfer parameters for register accesses
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr(TBUFABITS+4 downto 2); v.hwrite := ahbsi.hwrite;
v.regacc := ahbsi.haddr(16);
v.hsel := ahbsi.htrans(1) and ahbsi.hsel(hindex);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.regacc = '0' then -- registers
v.hready := '1';
case regaddr is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
if ntrace /= 1 then
regsd(15) := '1';
regsd(log2(ntrace)+12 downto 12) := vb.bsel;
end if;
regsd(7 downto 6) := conv_std_logic_vector(log2(bwidth/32), 2);
if FILTEN then
regsd(5) := rf.rf;
regsd(4) := rf.af;
regsd(3) := rf.fr;
regsd(2) := rf.fw;
end if;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
if ntrace /= 1 then
vb.bsel := ahbsi.hwdata(log2(ntrace)+12 downto 12);
end if;
if FILTEN then
vf.rf := ahbsi.hwdata(5);
vf.af := ahbsi.hwdata(4);
vf.fr := ahbsi.hwdata(3);
vf.fw := ahbsi.hwdata(2);
end if;
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd((TIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
end if;
when "011" =>
if FILTEN then
regsd(31 downto 0) := rf.smask & rf.mmask;
if r.hwrite = '1' then
vf.smask := ahbsi.hwdata(31 downto 16);
vf.mmask := ahbsi.hwdata(15 downto 0);
end if;
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hrdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
case regaddr is
when "000" =>
v.hrdata := tbo.data(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "001" =>
v.hrdata := tbo.data(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "010" =>
v.hrdata := tbo.data(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when "011" =>
v.hrdata := tbo.data(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
when "100" =>
if bwidth > 32 then
v.hrdata := tbo.data(159 downto 128);
if r.hwrite = '1' then
vabufi.write(7) := vabufi.enable;
end if;
else
v.hrdata := tbo.data(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
end if;
when "101" =>
if bwidth > 32 then
if bwidth > 64 then
v.hrdata := tbo.data(223 downto 192);
if r.hwrite = '1' then
vabufi.write(6) := vabufi.enable;
end if;
else v.hrdata := zero32; end if;
else
v.hrdata := tbo.data(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
end if;
when "110" =>
if bwidth > 32 then
if bwidth > 64 then
v.hrdata := tbo.data(191 downto 160);
if r.hwrite = '1' then
vabufi.write(5) := vabufi.enable;
end if;
else v.hrdata := zero32; end if;
else
v.hrdata := tbo.data(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
end if;
when others =>
if bwidth > 32 then
v.hrdata := zero32;
else
v.hrdata := tbo.data(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.regacc := '0'; v.hready := '1';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
if FILTEN then
vf.smask := (others => '0'); vf.mmask := (others => '0');
end if;
if ntrace /= 1 then vb.bsel := (others => '0'); end if;
end if;
tbi <= vabufi;
rin <= v; rfin <= vf; rbin <= vb;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hrdata <= ahbdrivedata(r.hrdata);
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
fregs : if FILTEN generate
regs : process(clk)
begin if rising_edge(clk) then rf <= rfin; end if; end process;
end generate;
nofregs : if not FILTEN generate
rf.shsel <= (others => '0');
rf.af <= '0';
rf.fr <= '0';
rf.fw <= '0';
rf.smask <= (others => '0');
rf.mmask <= (others => '0');
rf.rf <= '0';
end generate;
bregs : if ntrace /= 1 generate
regs : process(clk)
begin if rising_edge(clk) then rb <= rbin; end if; end process;
end generate;
nobregs : if ntrace = 1 generate
rb.bsel <= (others => '0');
end generate;
enable <= tbi.enable & tbi.enable;
mem32 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
end generate;
mem64 : if bwidth > 32 generate -- extra data buffer for 64-bit bus
ram0 : syncram generic map (tech => tech, abits => TBUFABITS, dbits => 32)
port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+31) downto 128),
tbo.data((128+31) downto 128), tbi.enable, tbi.write(7));
end generate;
mem128 : if bwidth > 64 generate -- extra data buffer for 128-bit bus
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+95) downto (128+32)),
tbo.data((128+95) downto (128+32)), enable, tbi.write(6 downto 5));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- Access channel
avalid_in : in std_logic;
aready_out : out std_logic;
aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
awren_in : in std_logic;
astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
rvalid_out : out std_logic;
rready_in : in std_logic;
rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_blockram;
architecture rtl of xilinx_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
signal ram_addr : unsigned(addrw_g-1 downto 0);
signal ram_write_data : std_logic_vector(dataw_padded_c-1 downto 0);
signal ram_read_data_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal ram_enable : std_logic;
signal ram_strb : std_logic_vector(astrb_width_c-1 downto 0);
constant adata_padding : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal adata_padded : std_logic_vector(dataw_padded_c-1 downto 0);
signal aready_r : std_logic;
signal live_read : std_logic;
signal live_read_r : std_logic;
signal read_data_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal read_data_valid_r : std_logic;
signal rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
signal RAM_ARR : ram_type;
begin
control_comb : process(aaddr_in, avalid_in, aready_r, awren_in, astrb_in,
live_read_r, read_data_valid_r)
begin
if avalid_in = '1' and aready_r = '1' then
ram_enable <= '1';
if awren_in = '1' then
ram_strb <= astrb_in;
live_read <= '0';
else
ram_strb <= (others => '0');
live_read <= '1';
end if;
else
ram_strb <= (others => '0');
ram_enable <= '0';
live_read <= '0';
end if;
ram_addr <= unsigned(aaddr_in);
rvalid <= live_read_r or read_data_valid_r;
end process;
control_sync : process(clk, rstx)
begin
if rstx = '0' then
live_read_r <= '0';
aready_r <= '0';
read_data_valid_r <= '0';
read_data_r <= (others => '0');
elsif rising_edge(clk) then
if rvalid = '1' and rready_in = '1' then
read_data_valid_r <= '0';
end if;
if rvalid = '1' and rready_in = '0' then
aready_r <= '0';
else
aready_r <= '1';
end if;
live_read_r <= live_read or live_read_r;
if live_read_r = '1' and (rready_in = '1' or read_data_valid_r = '0') then
live_read_r <= live_read;
if rready_in = '0' or read_data_valid_r = '1' then
read_data_valid_r <= '1';
read_data_r <= ram_read_data_r;
end if;
end if;
end if;
end process;
adata_padded <= adata_padding & adata_in;
RAM : process(clk)
begin
if rising_edge(clk) then
if ram_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if ram_strb(i) = '1' then
RAM_ARR(to_integer(ram_addr))((i+1)*8-1 downto i*8)
<= adata_padded((i+1)*8-1 downto i*8);
end if;
end loop;
ram_read_data_r <= RAM_ARR(to_integer(ram_addr));
end if;
end if;
end process;
rdata_out <= ram_read_data_r(rdata_out'range) when read_data_valid_r = '0'
else read_data_r(rdata_out'range);
rvalid_out <= rvalid;
aready_out <= aready_r;
end rtl;
|
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- Access channel
avalid_in : in std_logic;
aready_out : out std_logic;
aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
awren_in : in std_logic;
astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
rvalid_out : out std_logic;
rready_in : in std_logic;
rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_blockram;
architecture rtl of xilinx_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
signal ram_addr : unsigned(addrw_g-1 downto 0);
signal ram_write_data : std_logic_vector(dataw_padded_c-1 downto 0);
signal ram_read_data_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal ram_enable : std_logic;
signal ram_strb : std_logic_vector(astrb_width_c-1 downto 0);
constant adata_padding : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal adata_padded : std_logic_vector(dataw_padded_c-1 downto 0);
signal aready_r : std_logic;
signal live_read : std_logic;
signal live_read_r : std_logic;
signal read_data_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal read_data_valid_r : std_logic;
signal rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
signal RAM_ARR : ram_type;
begin
control_comb : process(aaddr_in, avalid_in, aready_r, awren_in, astrb_in,
live_read_r, read_data_valid_r)
begin
if avalid_in = '1' and aready_r = '1' then
ram_enable <= '1';
if awren_in = '1' then
ram_strb <= astrb_in;
live_read <= '0';
else
ram_strb <= (others => '0');
live_read <= '1';
end if;
else
ram_strb <= (others => '0');
ram_enable <= '0';
live_read <= '0';
end if;
ram_addr <= unsigned(aaddr_in);
rvalid <= live_read_r or read_data_valid_r;
end process;
control_sync : process(clk, rstx)
begin
if rstx = '0' then
live_read_r <= '0';
aready_r <= '0';
read_data_valid_r <= '0';
read_data_r <= (others => '0');
elsif rising_edge(clk) then
if rvalid = '1' and rready_in = '1' then
read_data_valid_r <= '0';
end if;
if rvalid = '1' and rready_in = '0' then
aready_r <= '0';
else
aready_r <= '1';
end if;
live_read_r <= live_read or live_read_r;
if live_read_r = '1' and (rready_in = '1' or read_data_valid_r = '0') then
live_read_r <= live_read;
if rready_in = '0' or read_data_valid_r = '1' then
read_data_valid_r <= '1';
read_data_r <= ram_read_data_r;
end if;
end if;
end if;
end process;
adata_padded <= adata_padding & adata_in;
RAM : process(clk)
begin
if rising_edge(clk) then
if ram_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if ram_strb(i) = '1' then
RAM_ARR(to_integer(ram_addr))((i+1)*8-1 downto i*8)
<= adata_padded((i+1)*8-1 downto i*8);
end if;
end loop;
ram_read_data_r <= RAM_ARR(to_integer(ram_addr));
end if;
end if;
end process;
rdata_out <= ram_read_data_r(rdata_out'range) when read_data_valid_r = '0'
else read_data_r(rdata_out'range);
rvalid_out <= rvalid;
aready_out <= aready_r;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_fir_generic_transposed_filter is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type SIGNED is array (INTEGER range <>) of std_logic;
end CONV_PACK_fir_generic_transposed_filter;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_fir_generic_transposed_filter.all;
entity fir_generic_transposed_filter is
port( clk, rst, valid_x_in : in std_logic; ready_x_out : out std_logic;
valid_h_in : in std_logic; ready_h_out, valid_out : out std_logic;
ready_in : in std_logic; x_data_in, h_data_in : in SIGNED (15 downto
0); y_data_out : out SIGNED (32 downto 0));
end fir_generic_transposed_filter;
architecture SYN_fir_rtl_arch of fir_generic_transposed_filter is
component inv
port( inb : in std_logic; outb : out std_logic);
end component;
component xor2
port( a, b : in std_logic; outb : out std_logic);
end component;
component nand2
port( a, b : in std_logic; outb : out std_logic);
end component;
component oai22
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component aoi22
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component nor2
port( a, b : in std_logic; outb : out std_logic);
end component;
component oai12
port( b, c, a : in std_logic; outb : out std_logic);
end component;
component aoi12
port( b, c, a : in std_logic; outb : out std_logic);
end component;
component dff
port( d, gclk, rnot : in std_logic; q : out std_logic);
end component;
component dff_asyncprehh
port( d, gclk, asyncprehh : in std_logic; q : out std_logic);
end component;
component dff_asyncrsthl
port( d, gclk, asyncrsthl : in std_logic; q : out std_logic);
end component;
signal ready_x_out_port, ready_h_out_port, valid_out_port,
coefficient_mem_array_0_15_port, coefficient_mem_array_0_14_port,
coefficient_mem_array_0_13_port, coefficient_mem_array_0_12_port,
coefficient_mem_array_0_11_port, coefficient_mem_array_0_10_port,
coefficient_mem_array_0_9_port, coefficient_mem_array_0_8_port,
coefficient_mem_array_0_7_port, coefficient_mem_array_0_6_port,
coefficient_mem_array_0_5_port, coefficient_mem_array_0_4_port,
coefficient_mem_array_0_3_port, coefficient_mem_array_0_2_port,
coefficient_mem_array_0_1_port, coefficient_mem_array_0_0_port,
coefficient_mem_array_1_15_port, coefficient_mem_array_1_14_port,
coefficient_mem_array_1_13_port, coefficient_mem_array_1_12_port,
coefficient_mem_array_1_11_port, coefficient_mem_array_1_10_port,
coefficient_mem_array_1_9_port, coefficient_mem_array_1_8_port,
coefficient_mem_array_1_7_port, coefficient_mem_array_1_6_port,
coefficient_mem_array_1_5_port, coefficient_mem_array_1_4_port,
coefficient_mem_array_1_3_port, coefficient_mem_array_1_2_port,
coefficient_mem_array_1_1_port, coefficient_mem_array_1_0_port,
coefficient_mem_array_2_15_port, coefficient_mem_array_2_14_port,
coefficient_mem_array_2_13_port, coefficient_mem_array_2_12_port,
coefficient_mem_array_2_11_port, coefficient_mem_array_2_10_port,
coefficient_mem_array_2_9_port, coefficient_mem_array_2_8_port,
coefficient_mem_array_2_7_port, coefficient_mem_array_2_6_port,
coefficient_mem_array_2_5_port, coefficient_mem_array_2_4_port,
coefficient_mem_array_2_3_port, coefficient_mem_array_2_2_port,
coefficient_mem_array_2_1_port, coefficient_mem_array_2_0_port,
coefficient_mem_array_3_15_port, coefficient_mem_array_3_14_port,
coefficient_mem_array_3_13_port, coefficient_mem_array_3_12_port,
coefficient_mem_array_3_11_port, coefficient_mem_array_3_10_port,
coefficient_mem_array_3_9_port, coefficient_mem_array_3_8_port,
coefficient_mem_array_3_7_port, coefficient_mem_array_3_6_port,
coefficient_mem_array_3_5_port, coefficient_mem_array_3_4_port,
coefficient_mem_array_3_3_port, coefficient_mem_array_3_2_port,
coefficient_mem_array_3_1_port, coefficient_mem_array_3_0_port,
input_sample_mem_15_port, input_sample_mem_14_port,
input_sample_mem_13_port, input_sample_mem_12_port,
input_sample_mem_11_port, input_sample_mem_10_port,
input_sample_mem_9_port, input_sample_mem_8_port, input_sample_mem_7_port
, input_sample_mem_6_port, input_sample_mem_5_port,
input_sample_mem_4_port, input_sample_mem_3_port, input_sample_mem_2_port
, input_sample_mem_1_port, input_sample_mem_0_port,
adder_mem_array_0_32_port, adder_mem_array_0_31_port,
adder_mem_array_0_30_port, adder_mem_array_0_29_port,
adder_mem_array_0_28_port, adder_mem_array_0_27_port,
adder_mem_array_0_26_port, adder_mem_array_0_25_port,
adder_mem_array_0_24_port, adder_mem_array_0_23_port,
adder_mem_array_0_22_port, adder_mem_array_0_21_port,
adder_mem_array_0_20_port, adder_mem_array_0_19_port,
adder_mem_array_0_18_port, adder_mem_array_0_17_port,
adder_mem_array_0_16_port, adder_mem_array_0_15_port,
adder_mem_array_0_14_port, adder_mem_array_0_13_port,
adder_mem_array_0_12_port, adder_mem_array_0_11_port,
adder_mem_array_0_10_port, adder_mem_array_0_9_port,
adder_mem_array_0_8_port, adder_mem_array_0_7_port,
adder_mem_array_0_6_port, adder_mem_array_0_5_port,
adder_mem_array_0_4_port, adder_mem_array_0_3_port,
adder_mem_array_0_2_port, adder_mem_array_0_1_port,
adder_mem_array_0_0_port, adder_mem_array_1_32_port,
adder_mem_array_1_31_port, adder_mem_array_1_30_port,
adder_mem_array_1_29_port, adder_mem_array_1_28_port,
adder_mem_array_1_27_port, adder_mem_array_1_26_port,
adder_mem_array_1_25_port, adder_mem_array_1_24_port,
adder_mem_array_1_23_port, adder_mem_array_1_22_port,
adder_mem_array_1_21_port, adder_mem_array_1_20_port,
adder_mem_array_1_19_port, adder_mem_array_1_18_port,
adder_mem_array_1_17_port, adder_mem_array_1_16_port,
adder_mem_array_1_15_port, adder_mem_array_1_14_port,
adder_mem_array_1_13_port, adder_mem_array_1_12_port,
adder_mem_array_1_11_port, adder_mem_array_1_10_port,
adder_mem_array_1_9_port, adder_mem_array_1_8_port,
adder_mem_array_1_7_port, adder_mem_array_1_6_port,
adder_mem_array_1_5_port, adder_mem_array_1_4_port,
adder_mem_array_1_3_port, adder_mem_array_1_2_port,
adder_mem_array_1_1_port, adder_mem_array_1_0_port,
adder_mem_array_2_32_port, adder_mem_array_2_31_port,
adder_mem_array_2_30_port, adder_mem_array_2_29_port,
adder_mem_array_2_28_port, adder_mem_array_2_27_port,
adder_mem_array_2_26_port, adder_mem_array_2_25_port,
adder_mem_array_2_24_port, adder_mem_array_2_23_port,
adder_mem_array_2_22_port, adder_mem_array_2_21_port,
adder_mem_array_2_20_port, adder_mem_array_2_19_port,
adder_mem_array_2_18_port, adder_mem_array_2_17_port,
adder_mem_array_2_16_port, adder_mem_array_2_15_port,
adder_mem_array_2_14_port, adder_mem_array_2_13_port,
adder_mem_array_2_12_port, adder_mem_array_2_11_port,
adder_mem_array_2_10_port, adder_mem_array_2_9_port,
adder_mem_array_2_8_port, adder_mem_array_2_7_port,
adder_mem_array_2_6_port, adder_mem_array_2_5_port,
adder_mem_array_2_4_port, adder_mem_array_2_3_port,
adder_mem_array_2_2_port, adder_mem_array_2_1_port,
adder_mem_array_2_0_port, adder_mem_array_3_32_port,
adder_mem_array_3_31_port, adder_mem_array_3_30_port,
adder_mem_array_3_29_port, adder_mem_array_3_28_port,
adder_mem_array_3_27_port, adder_mem_array_3_26_port,
adder_mem_array_3_25_port, adder_mem_array_3_24_port,
adder_mem_array_3_23_port, adder_mem_array_3_22_port,
adder_mem_array_3_21_port, adder_mem_array_3_20_port,
adder_mem_array_3_19_port, adder_mem_array_3_18_port,
adder_mem_array_3_17_port, adder_mem_array_3_16_port,
adder_mem_array_3_15_port, adder_mem_array_3_14_port,
adder_mem_array_3_13_port, adder_mem_array_3_12_port,
adder_mem_array_3_11_port, adder_mem_array_3_10_port,
adder_mem_array_3_9_port, adder_mem_array_3_8_port,
adder_mem_array_3_7_port, adder_mem_array_3_6_port,
adder_mem_array_3_5_port, adder_mem_array_3_4_port,
adder_mem_array_3_3_port, adder_mem_array_3_2_port,
adder_mem_array_3_1_port, adder_mem_array_3_0_port,
multiplier_sigs_0_31_port, multiplier_sigs_0_30_port,
multiplier_sigs_0_29_port, multiplier_sigs_0_28_port,
multiplier_sigs_0_27_port, multiplier_sigs_0_26_port,
multiplier_sigs_0_25_port, multiplier_sigs_0_24_port,
multiplier_sigs_0_23_port, multiplier_sigs_0_22_port,
multiplier_sigs_0_21_port, multiplier_sigs_0_20_port,
multiplier_sigs_0_19_port, multiplier_sigs_0_18_port,
multiplier_sigs_0_17_port, multiplier_sigs_0_16_port,
multiplier_sigs_0_15_port, multiplier_sigs_0_14_port,
multiplier_sigs_0_13_port, multiplier_sigs_0_12_port,
multiplier_sigs_0_11_port, multiplier_sigs_0_10_port,
multiplier_sigs_0_9_port, multiplier_sigs_0_8_port,
multiplier_sigs_0_7_port, multiplier_sigs_0_6_port,
multiplier_sigs_0_5_port, multiplier_sigs_0_4_port,
multiplier_sigs_0_3_port, multiplier_sigs_0_2_port,
multiplier_sigs_0_0_port, multiplier_sigs_1_31_port,
multiplier_sigs_1_30_port, multiplier_sigs_1_29_port,
multiplier_sigs_1_28_port, multiplier_sigs_1_27_port,
multiplier_sigs_1_26_port, multiplier_sigs_1_25_port,
multiplier_sigs_1_24_port, multiplier_sigs_1_23_port,
multiplier_sigs_1_22_port, multiplier_sigs_1_21_port,
multiplier_sigs_1_20_port, multiplier_sigs_1_19_port,
multiplier_sigs_1_18_port, multiplier_sigs_1_17_port,
multiplier_sigs_1_16_port, multiplier_sigs_1_15_port,
multiplier_sigs_1_14_port, multiplier_sigs_1_13_port,
multiplier_sigs_1_12_port, multiplier_sigs_1_11_port,
multiplier_sigs_1_10_port, multiplier_sigs_1_9_port,
multiplier_sigs_1_8_port, multiplier_sigs_1_7_port,
multiplier_sigs_1_6_port, multiplier_sigs_1_5_port,
multiplier_sigs_1_4_port, multiplier_sigs_1_3_port,
multiplier_sigs_1_2_port, multiplier_sigs_1_0_port,
multiplier_sigs_2_31_port, multiplier_sigs_2_30_port,
multiplier_sigs_2_29_port, multiplier_sigs_2_28_port,
multiplier_sigs_2_27_port, multiplier_sigs_2_26_port,
multiplier_sigs_2_25_port, multiplier_sigs_2_24_port,
multiplier_sigs_2_23_port, multiplier_sigs_2_22_port,
multiplier_sigs_2_21_port, multiplier_sigs_2_20_port,
multiplier_sigs_2_19_port, multiplier_sigs_2_18_port,
multiplier_sigs_2_17_port, multiplier_sigs_2_16_port,
multiplier_sigs_2_15_port, multiplier_sigs_2_14_port,
multiplier_sigs_2_13_port, multiplier_sigs_2_12_port,
multiplier_sigs_2_11_port, multiplier_sigs_2_10_port,
multiplier_sigs_2_9_port, multiplier_sigs_2_8_port,
multiplier_sigs_2_7_port, multiplier_sigs_2_6_port,
multiplier_sigs_2_5_port, multiplier_sigs_2_4_port,
multiplier_sigs_2_3_port, multiplier_sigs_2_2_port,
multiplier_sigs_2_0_port, multiplier_sigs_3_31_port,
multiplier_sigs_3_30_port, multiplier_sigs_3_29_port,
multiplier_sigs_3_28_port, multiplier_sigs_3_27_port,
multiplier_sigs_3_26_port, multiplier_sigs_3_25_port,
multiplier_sigs_3_24_port, multiplier_sigs_3_23_port,
multiplier_sigs_3_22_port, multiplier_sigs_3_21_port,
multiplier_sigs_3_20_port, multiplier_sigs_3_19_port,
multiplier_sigs_3_18_port, multiplier_sigs_3_17_port,
multiplier_sigs_3_16_port, multiplier_sigs_3_15_port,
multiplier_sigs_3_14_port, multiplier_sigs_3_13_port,
multiplier_sigs_3_12_port, multiplier_sigs_3_11_port,
multiplier_sigs_3_10_port, multiplier_sigs_3_9_port,
multiplier_sigs_3_8_port, multiplier_sigs_3_7_port,
multiplier_sigs_3_6_port, multiplier_sigs_3_5_port,
multiplier_sigs_3_4_port, multiplier_sigs_3_3_port,
multiplier_sigs_3_2_port, multiplier_sigs_3_1_port,
multiplier_sigs_3_0_port, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15,
N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30
, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44,
N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59
, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70, N71, N72, N73,
N74, N75, N76, N77, N78, N79, N80, N81, N82, N83, N84, N85, N86, N87, N88
, N89, N90, N91, N92, N93, N94, N95, N96, N97, N98, N99, N100, N101, N102
, N103, N104, coeff_cnt_1_port, coeff_cnt_0_port, n16_port, n17_port,
n18_port, n19_port, n20_port, n21_port, n22_port, n23_port, n24_port,
n25_port, n26_port, n27_port, n28_port, n29_port, n30_port, n31_port,
n32_port, n33_port, n34_port, n35_port, n36_port, n37_port, n38_port,
n39_port, n40_port, n41_port, n42_port, n43_port, n44_port, n45_port,
n46_port, n47_port, n48_port, n49_port, n50_port, n51_port, n52_port,
n53_port, n54_port, n55_port, n56_port, n57_port, n58_port, n59_port,
n60_port, n61_port, n62_port, n63_port, n64_port, n65_port, n66_port,
n67_port, n68_port, n69_port, n70_port, n71_port, n72_port, n73_port,
n74_port, n75_port, n76_port, n77_port, n78_port, n79_port, n80_port,
n81_port, n82_port, n83_port, n84_port, n85_port, n86_port, n87_port,
n88_port, n89_port, n90_port, n91_port, n92_port, n93_port, n94_port,
n95_port, n96_port, n97_port, n98_port, n99_port, n100_port, n101_port,
n102_port, n103_port, n104_port, n105, n106, n107, n108, n109, n110, n111
, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239,
mult_125_G3_FS_1_C_1_3_3_port, mult_125_G3_FS_1_C_1_4_0_port,
mult_125_G3_FS_1_C_1_4_1_port, mult_125_G3_FS_1_C_1_4_2_port,
mult_125_G3_FS_1_C_1_4_3_port, mult_125_G3_FS_1_C_1_5_0_port,
mult_125_G3_FS_1_C_1_5_1_port, mult_125_G3_FS_1_C_1_5_2_port,
mult_125_G3_FS_1_C_1_5_3_port, mult_125_G3_FS_1_C_1_6_0_port,
mult_125_G3_FS_1_C_1_6_1_port, mult_125_G3_FS_1_C_1_6_2_port,
mult_125_G3_FS_1_C_1_6_3_port, mult_125_G3_FS_1_C_1_7_0_port,
mult_125_G3_FS_1_C_1_7_1_port, mult_125_G3_FS_1_P_0_0_1_port,
mult_125_G3_FS_1_P_0_0_2_port, mult_125_G3_FS_1_P_0_0_3_port,
mult_125_G3_FS_1_P_0_1_1_port, mult_125_G3_FS_1_P_0_1_2_port,
mult_125_G3_FS_1_P_0_1_3_port, mult_125_G3_FS_1_P_0_2_1_port,
mult_125_G3_FS_1_P_0_2_2_port, mult_125_G3_FS_1_P_0_2_3_port,
mult_125_G3_FS_1_P_0_3_1_port, mult_125_G3_FS_1_P_0_3_2_port,
mult_125_G3_FS_1_P_0_3_3_port, mult_125_G3_FS_1_P_0_4_1_port,
mult_125_G3_FS_1_P_0_4_2_port, mult_125_G3_FS_1_P_0_4_3_port,
mult_125_G3_FS_1_P_0_5_1_port, mult_125_G3_FS_1_P_0_5_2_port,
mult_125_G3_FS_1_P_0_5_3_port, mult_125_G3_FS_1_P_0_6_1_port,
mult_125_G3_FS_1_P_0_6_2_port, mult_125_G3_FS_1_P_0_6_3_port,
mult_125_G3_FS_1_P_0_7_1_port, mult_125_G3_FS_1_TEMP_P_0_0_0_port,
mult_125_G3_FS_1_TEMP_P_0_1_0_port, mult_125_G3_FS_1_TEMP_P_0_2_0_port,
mult_125_G3_FS_1_TEMP_P_0_3_0_port, mult_125_G3_FS_1_TEMP_P_0_4_0_port,
mult_125_G3_FS_1_TEMP_P_0_4_1_port, mult_125_G3_FS_1_TEMP_P_0_4_2_port,
mult_125_G3_FS_1_TEMP_P_0_5_0_port, mult_125_G3_FS_1_TEMP_P_0_5_1_port,
mult_125_G3_FS_1_TEMP_P_0_5_2_port, mult_125_G3_FS_1_TEMP_P_0_6_0_port,
mult_125_G3_FS_1_TEMP_P_0_6_1_port, mult_125_G3_FS_1_TEMP_P_0_6_2_port,
mult_125_G3_FS_1_TEMP_P_0_7_0_port, mult_125_G3_FS_1_G_1_0_3_port,
mult_125_G3_FS_1_G_1_1_0_port, mult_125_G3_FS_1_G_1_1_1_port,
mult_125_G3_FS_1_G_1_1_2_port, mult_125_G3_FS_1_G_2_0_0_port,
mult_125_G3_FS_1_TEMP_G_0_3_2_port, mult_125_G3_FS_1_TEMP_G_0_4_1_port,
mult_125_G3_FS_1_TEMP_G_0_4_2_port, mult_125_G3_FS_1_TEMP_G_0_5_1_port,
mult_125_G3_FS_1_TEMP_G_0_5_2_port, mult_125_G3_FS_1_TEMP_G_0_6_1_port,
mult_125_G3_FS_1_TEMP_G_0_6_2_port, mult_125_G3_FS_1_G_n_int_0_3_2_port,
mult_125_G3_FS_1_G_n_int_0_3_3_port, mult_125_G3_FS_1_G_n_int_0_4_0_port,
mult_125_G3_FS_1_G_n_int_0_4_1_port, mult_125_G3_FS_1_G_n_int_0_4_2_port,
mult_125_G3_FS_1_G_n_int_0_4_3_port, mult_125_G3_FS_1_G_n_int_0_5_0_port,
mult_125_G3_FS_1_G_n_int_0_5_1_port, mult_125_G3_FS_1_G_n_int_0_5_2_port,
mult_125_G3_FS_1_G_n_int_0_5_3_port, mult_125_G3_FS_1_G_n_int_0_6_0_port,
mult_125_G3_FS_1_G_n_int_0_6_1_port, mult_125_G3_FS_1_G_n_int_0_6_2_port,
mult_125_G3_FS_1_G_n_int_0_6_3_port, mult_125_G3_FS_1_G_n_int_0_7_0_port,
mult_125_G3_FS_1_G_n_int_0_7_1_port, mult_125_G3_FS_1_PG_int_0_3_3_port,
mult_125_G3_FS_1_PG_int_0_4_0_port, mult_125_G3_FS_1_PG_int_0_4_1_port,
mult_125_G3_FS_1_PG_int_0_4_2_port, mult_125_G3_FS_1_PG_int_0_4_3_port,
mult_125_G3_FS_1_PG_int_0_5_0_port, mult_125_G3_FS_1_PG_int_0_5_1_port,
mult_125_G3_FS_1_PG_int_0_5_2_port, mult_125_G3_FS_1_PG_int_0_5_3_port,
mult_125_G3_FS_1_PG_int_0_6_0_port, mult_125_G3_FS_1_PG_int_0_6_1_port,
mult_125_G3_FS_1_PG_int_0_6_2_port, mult_125_G3_FS_1_PG_int_0_6_3_port,
mult_125_G3_FS_1_PG_int_0_7_0_port, mult_125_G3_FS_1_PG_int_0_7_1_port,
mult_125_G3_A2_14_port, mult_125_G3_A2_15_port, mult_125_G3_A2_16_port,
mult_125_G3_A2_17_port, mult_125_G3_A2_18_port, mult_125_G3_A2_19_port,
mult_125_G3_A2_20_port, mult_125_G3_A2_21_port, mult_125_G3_A2_22_port,
mult_125_G3_A2_23_port, mult_125_G3_A2_24_port, mult_125_G3_A2_25_port,
mult_125_G3_A2_26_port, mult_125_G3_A2_27_port, mult_125_G3_A2_28_port,
mult_125_G3_A2_29_port, mult_125_G3_A1_0_port, mult_125_G3_A1_1_port,
mult_125_G3_A1_2_port, mult_125_G3_A1_3_port, mult_125_G3_A1_4_port,
mult_125_G3_A1_5_port, mult_125_G3_A1_6_port, mult_125_G3_A1_7_port,
mult_125_G3_A1_8_port, mult_125_G3_A1_9_port, mult_125_G3_A1_10_port,
mult_125_G3_A1_11_port, mult_125_G3_A1_12_port, mult_125_G3_A1_13_port,
mult_125_G3_A1_14_port, mult_125_G3_A1_15_port, mult_125_G3_A1_16_port,
mult_125_G3_A1_17_port, mult_125_G3_A1_18_port, mult_125_G3_A1_19_port,
mult_125_G3_A1_20_port, mult_125_G3_A1_21_port, mult_125_G3_A1_22_port,
mult_125_G3_A1_23_port, mult_125_G3_A1_24_port, mult_125_G3_A1_25_port,
mult_125_G3_A1_26_port, mult_125_G3_A1_27_port, mult_125_G3_A1_28_port,
mult_125_G3_A1_29_port, mult_125_G3_ZB, mult_125_G3_ZA, mult_125_G3_QB,
mult_125_G3_QA, mult_125_G3_A_notx_0_port, mult_125_G3_A_notx_1_port,
mult_125_G3_A_notx_2_port, mult_125_G3_A_notx_3_port,
mult_125_G3_A_notx_4_port, mult_125_G3_A_notx_5_port,
mult_125_G3_A_notx_6_port, mult_125_G3_A_notx_7_port,
mult_125_G3_A_notx_8_port, mult_125_G3_A_notx_9_port,
mult_125_G3_A_notx_10_port, mult_125_G3_A_notx_11_port,
mult_125_G3_A_notx_12_port, mult_125_G3_A_notx_13_port,
mult_125_G3_A_notx_14_port, mult_125_G3_B_notx_0_port,
mult_125_G3_B_notx_1_port, mult_125_G3_B_notx_2_port,
mult_125_G3_B_notx_3_port, mult_125_G3_B_notx_4_port,
mult_125_G3_B_notx_5_port, mult_125_G3_B_notx_6_port,
mult_125_G3_B_notx_7_port, mult_125_G3_B_notx_8_port,
mult_125_G3_B_notx_9_port, mult_125_G3_B_notx_10_port,
mult_125_G3_B_notx_11_port, mult_125_G3_B_notx_12_port,
mult_125_G3_B_notx_13_port, mult_125_G3_B_notx_14_port,
mult_125_G3_ab_0_1_port, mult_125_G3_ab_0_2_port, mult_125_G3_ab_0_3_port
, mult_125_G3_ab_0_4_port, mult_125_G3_ab_0_5_port,
mult_125_G3_ab_0_6_port, mult_125_G3_ab_0_7_port, mult_125_G3_ab_0_8_port
, mult_125_G3_ab_0_9_port, mult_125_G3_ab_0_10_port,
mult_125_G3_ab_0_11_port, mult_125_G3_ab_0_12_port,
mult_125_G3_ab_0_13_port, mult_125_G3_ab_0_14_port,
mult_125_G3_ab_0_15_port, mult_125_G3_ab_1_0_port,
mult_125_G3_ab_1_1_port, mult_125_G3_ab_1_2_port, mult_125_G3_ab_1_3_port
, mult_125_G3_ab_1_4_port, mult_125_G3_ab_1_5_port,
mult_125_G3_ab_1_6_port, mult_125_G3_ab_1_7_port, mult_125_G3_ab_1_8_port
, mult_125_G3_ab_1_9_port, mult_125_G3_ab_1_10_port,
mult_125_G3_ab_1_11_port, mult_125_G3_ab_1_12_port,
mult_125_G3_ab_1_13_port, mult_125_G3_ab_1_14_port,
mult_125_G3_ab_1_15_port, mult_125_G3_ab_2_0_port,
mult_125_G3_ab_2_1_port, mult_125_G3_ab_2_2_port, mult_125_G3_ab_2_3_port
, mult_125_G3_ab_2_4_port, mult_125_G3_ab_2_5_port,
mult_125_G3_ab_2_6_port, mult_125_G3_ab_2_7_port, mult_125_G3_ab_2_8_port
, mult_125_G3_ab_2_9_port, mult_125_G3_ab_2_10_port,
mult_125_G3_ab_2_11_port, mult_125_G3_ab_2_12_port,
mult_125_G3_ab_2_13_port, mult_125_G3_ab_2_14_port,
mult_125_G3_ab_2_15_port, mult_125_G3_ab_3_0_port,
mult_125_G3_ab_3_1_port, mult_125_G3_ab_3_2_port, mult_125_G3_ab_3_3_port
, mult_125_G3_ab_3_4_port, mult_125_G3_ab_3_5_port,
mult_125_G3_ab_3_6_port, mult_125_G3_ab_3_7_port, mult_125_G3_ab_3_8_port
, mult_125_G3_ab_3_9_port, mult_125_G3_ab_3_10_port,
mult_125_G3_ab_3_11_port, mult_125_G3_ab_3_12_port,
mult_125_G3_ab_3_13_port, mult_125_G3_ab_3_14_port,
mult_125_G3_ab_3_15_port, mult_125_G3_ab_4_0_port,
mult_125_G3_ab_4_1_port, mult_125_G3_ab_4_2_port, mult_125_G3_ab_4_3_port
, mult_125_G3_ab_4_4_port, mult_125_G3_ab_4_5_port,
mult_125_G3_ab_4_6_port, mult_125_G3_ab_4_7_port, mult_125_G3_ab_4_8_port
, mult_125_G3_ab_4_9_port, mult_125_G3_ab_4_10_port,
mult_125_G3_ab_4_11_port, mult_125_G3_ab_4_12_port,
mult_125_G3_ab_4_13_port, mult_125_G3_ab_4_14_port,
mult_125_G3_ab_4_15_port, mult_125_G3_ab_5_0_port,
mult_125_G3_ab_5_1_port, mult_125_G3_ab_5_2_port, mult_125_G3_ab_5_3_port
, mult_125_G3_ab_5_4_port, mult_125_G3_ab_5_5_port,
mult_125_G3_ab_5_6_port, mult_125_G3_ab_5_7_port, mult_125_G3_ab_5_8_port
, mult_125_G3_ab_5_9_port, mult_125_G3_ab_5_10_port,
mult_125_G3_ab_5_11_port, mult_125_G3_ab_5_12_port,
mult_125_G3_ab_5_13_port, mult_125_G3_ab_5_14_port,
mult_125_G3_ab_5_15_port, mult_125_G3_ab_6_0_port,
mult_125_G3_ab_6_1_port, mult_125_G3_ab_6_2_port, mult_125_G3_ab_6_3_port
, mult_125_G3_ab_6_4_port, mult_125_G3_ab_6_5_port,
mult_125_G3_ab_6_6_port, mult_125_G3_ab_6_7_port, mult_125_G3_ab_6_8_port
, mult_125_G3_ab_6_9_port, mult_125_G3_ab_6_10_port,
mult_125_G3_ab_6_11_port, mult_125_G3_ab_6_12_port,
mult_125_G3_ab_6_13_port, mult_125_G3_ab_6_14_port,
mult_125_G3_ab_6_15_port, mult_125_G3_ab_7_0_port,
mult_125_G3_ab_7_1_port, mult_125_G3_ab_7_2_port, mult_125_G3_ab_7_3_port
, mult_125_G3_ab_7_4_port, mult_125_G3_ab_7_5_port,
mult_125_G3_ab_7_6_port, mult_125_G3_ab_7_7_port, mult_125_G3_ab_7_8_port
, mult_125_G3_ab_7_9_port, mult_125_G3_ab_7_10_port,
mult_125_G3_ab_7_11_port, mult_125_G3_ab_7_12_port,
mult_125_G3_ab_7_13_port, mult_125_G3_ab_7_14_port,
mult_125_G3_ab_7_15_port, mult_125_G3_ab_8_0_port,
mult_125_G3_ab_8_1_port, mult_125_G3_ab_8_2_port, mult_125_G3_ab_8_3_port
, mult_125_G3_ab_8_4_port, mult_125_G3_ab_8_5_port,
mult_125_G3_ab_8_6_port, mult_125_G3_ab_8_7_port, mult_125_G3_ab_8_8_port
, mult_125_G3_ab_8_9_port, mult_125_G3_ab_8_10_port,
mult_125_G3_ab_8_11_port, mult_125_G3_ab_8_12_port,
mult_125_G3_ab_8_13_port, mult_125_G3_ab_8_14_port,
mult_125_G3_ab_8_15_port, mult_125_G3_ab_9_0_port,
mult_125_G3_ab_9_1_port, mult_125_G3_ab_9_2_port, mult_125_G3_ab_9_3_port
, mult_125_G3_ab_9_4_port, mult_125_G3_ab_9_5_port,
mult_125_G3_ab_9_6_port, mult_125_G3_ab_9_7_port, mult_125_G3_ab_9_8_port
, mult_125_G3_ab_9_9_port, mult_125_G3_ab_9_10_port,
mult_125_G3_ab_9_11_port, mult_125_G3_ab_9_12_port,
mult_125_G3_ab_9_13_port, mult_125_G3_ab_9_14_port,
mult_125_G3_ab_9_15_port, mult_125_G3_ab_10_0_port,
mult_125_G3_ab_10_1_port, mult_125_G3_ab_10_2_port,
mult_125_G3_ab_10_3_port, mult_125_G3_ab_10_4_port,
mult_125_G3_ab_10_5_port, mult_125_G3_ab_10_6_port,
mult_125_G3_ab_10_7_port, mult_125_G3_ab_10_8_port,
mult_125_G3_ab_10_9_port, mult_125_G3_ab_10_10_port,
mult_125_G3_ab_10_11_port, mult_125_G3_ab_10_12_port,
mult_125_G3_ab_10_13_port, mult_125_G3_ab_10_14_port,
mult_125_G3_ab_10_15_port, mult_125_G3_ab_11_0_port,
mult_125_G3_ab_11_1_port, mult_125_G3_ab_11_2_port,
mult_125_G3_ab_11_3_port, mult_125_G3_ab_11_4_port,
mult_125_G3_ab_11_5_port, mult_125_G3_ab_11_6_port,
mult_125_G3_ab_11_7_port, mult_125_G3_ab_11_8_port,
mult_125_G3_ab_11_9_port, mult_125_G3_ab_11_10_port,
mult_125_G3_ab_11_11_port, mult_125_G3_ab_11_12_port,
mult_125_G3_ab_11_13_port, mult_125_G3_ab_11_14_port,
mult_125_G3_ab_11_15_port, mult_125_G3_ab_12_0_port,
mult_125_G3_ab_12_1_port, mult_125_G3_ab_12_2_port,
mult_125_G3_ab_12_3_port, mult_125_G3_ab_12_4_port,
mult_125_G3_ab_12_5_port, mult_125_G3_ab_12_6_port,
mult_125_G3_ab_12_7_port, mult_125_G3_ab_12_8_port,
mult_125_G3_ab_12_9_port, mult_125_G3_ab_12_10_port,
mult_125_G3_ab_12_11_port, mult_125_G3_ab_12_12_port,
mult_125_G3_ab_12_13_port, mult_125_G3_ab_12_14_port,
mult_125_G3_ab_12_15_port, mult_125_G3_ab_13_0_port,
mult_125_G3_ab_13_1_port, mult_125_G3_ab_13_2_port,
mult_125_G3_ab_13_3_port, mult_125_G3_ab_13_4_port,
mult_125_G3_ab_13_5_port, mult_125_G3_ab_13_6_port,
mult_125_G3_ab_13_7_port, mult_125_G3_ab_13_8_port,
mult_125_G3_ab_13_9_port, mult_125_G3_ab_13_10_port,
mult_125_G3_ab_13_11_port, mult_125_G3_ab_13_12_port,
mult_125_G3_ab_13_13_port, mult_125_G3_ab_13_14_port,
mult_125_G3_ab_13_15_port, mult_125_G3_ab_14_0_port,
mult_125_G3_ab_14_1_port, mult_125_G3_ab_14_2_port,
mult_125_G3_ab_14_3_port, mult_125_G3_ab_14_4_port,
mult_125_G3_ab_14_5_port, mult_125_G3_ab_14_6_port,
mult_125_G3_ab_14_7_port, mult_125_G3_ab_14_8_port,
mult_125_G3_ab_14_9_port, mult_125_G3_ab_14_10_port,
mult_125_G3_ab_14_11_port, mult_125_G3_ab_14_12_port,
mult_125_G3_ab_14_13_port, mult_125_G3_ab_14_14_port,
mult_125_G3_ab_14_15_port, mult_125_G3_ab_15_0_port,
mult_125_G3_ab_15_1_port, mult_125_G3_ab_15_2_port,
mult_125_G3_ab_15_3_port, mult_125_G3_ab_15_4_port,
mult_125_G3_ab_15_5_port, mult_125_G3_ab_15_6_port,
mult_125_G3_ab_15_7_port, mult_125_G3_ab_15_8_port,
mult_125_G3_ab_15_9_port, mult_125_G3_ab_15_10_port,
mult_125_G3_ab_15_11_port, mult_125_G3_ab_15_12_port,
mult_125_G3_ab_15_13_port, mult_125_G3_ab_15_14_port,
mult_125_G3_ab_15_15_port, mult_125_G3_B_not_0_port,
mult_125_G3_B_not_1_port, mult_125_G3_B_not_2_port,
mult_125_G3_B_not_3_port, mult_125_G3_B_not_4_port,
mult_125_G3_B_not_5_port, mult_125_G3_B_not_6_port,
mult_125_G3_B_not_7_port, mult_125_G3_B_not_8_port,
mult_125_G3_B_not_9_port, mult_125_G3_B_not_10_port,
mult_125_G3_B_not_11_port, mult_125_G3_B_not_12_port,
mult_125_G3_B_not_13_port, mult_125_G3_B_not_14_port,
mult_125_G3_B_not_15_port, mult_125_G3_A_not_0_port,
mult_125_G3_A_not_1_port, mult_125_G3_A_not_2_port,
mult_125_G3_A_not_3_port, mult_125_G3_A_not_4_port,
mult_125_G3_A_not_5_port, mult_125_G3_A_not_6_port,
mult_125_G3_A_not_7_port, mult_125_G3_A_not_8_port,
mult_125_G3_A_not_9_port, mult_125_G3_A_not_10_port,
mult_125_G3_A_not_11_port, mult_125_G3_A_not_12_port,
mult_125_G3_A_not_13_port, mult_125_G3_A_not_14_port,
mult_125_G3_A_not_15_port, mult_125_G2_FS_1_C_1_3_3_port,
mult_125_G2_FS_1_C_1_4_0_port, mult_125_G2_FS_1_C_1_4_1_port,
mult_125_G2_FS_1_C_1_4_2_port, mult_125_G2_FS_1_C_1_4_3_port,
mult_125_G2_FS_1_C_1_5_0_port, mult_125_G2_FS_1_C_1_5_1_port,
mult_125_G2_FS_1_C_1_5_2_port, mult_125_G2_FS_1_C_1_5_3_port,
mult_125_G2_FS_1_C_1_6_0_port, mult_125_G2_FS_1_C_1_6_1_port,
mult_125_G2_FS_1_C_1_6_2_port, mult_125_G2_FS_1_C_1_6_3_port,
mult_125_G2_FS_1_C_1_7_0_port, mult_125_G2_FS_1_C_1_7_1_port,
mult_125_G2_FS_1_P_0_0_1_port, mult_125_G2_FS_1_P_0_0_2_port,
mult_125_G2_FS_1_P_0_0_3_port, mult_125_G2_FS_1_P_0_1_1_port,
mult_125_G2_FS_1_P_0_1_2_port, mult_125_G2_FS_1_P_0_1_3_port,
mult_125_G2_FS_1_P_0_2_1_port, mult_125_G2_FS_1_P_0_2_2_port,
mult_125_G2_FS_1_P_0_2_3_port, mult_125_G2_FS_1_P_0_3_1_port,
mult_125_G2_FS_1_P_0_3_2_port, mult_125_G2_FS_1_P_0_3_3_port,
mult_125_G2_FS_1_P_0_4_1_port, mult_125_G2_FS_1_P_0_4_2_port,
mult_125_G2_FS_1_P_0_4_3_port, mult_125_G2_FS_1_P_0_5_1_port,
mult_125_G2_FS_1_P_0_5_2_port, mult_125_G2_FS_1_P_0_5_3_port,
mult_125_G2_FS_1_P_0_6_1_port, mult_125_G2_FS_1_P_0_6_2_port,
mult_125_G2_FS_1_P_0_6_3_port, mult_125_G2_FS_1_P_0_7_1_port,
mult_125_G2_FS_1_TEMP_P_0_0_0_port, mult_125_G2_FS_1_TEMP_P_0_1_0_port,
mult_125_G2_FS_1_TEMP_P_0_2_0_port, mult_125_G2_FS_1_TEMP_P_0_3_0_port,
mult_125_G2_FS_1_TEMP_P_0_4_0_port, mult_125_G2_FS_1_TEMP_P_0_4_1_port,
mult_125_G2_FS_1_TEMP_P_0_4_2_port, mult_125_G2_FS_1_TEMP_P_0_5_0_port,
mult_125_G2_FS_1_TEMP_P_0_5_1_port, mult_125_G2_FS_1_TEMP_P_0_5_2_port,
mult_125_G2_FS_1_TEMP_P_0_6_0_port, mult_125_G2_FS_1_TEMP_P_0_6_1_port,
mult_125_G2_FS_1_TEMP_P_0_6_2_port, mult_125_G2_FS_1_TEMP_P_0_7_0_port,
mult_125_G2_FS_1_G_1_0_3_port, mult_125_G2_FS_1_G_1_1_0_port,
mult_125_G2_FS_1_G_1_1_1_port, mult_125_G2_FS_1_G_1_1_2_port,
mult_125_G2_FS_1_G_2_0_0_port, mult_125_G2_FS_1_TEMP_G_0_3_2_port,
mult_125_G2_FS_1_TEMP_G_0_4_1_port, mult_125_G2_FS_1_TEMP_G_0_4_2_port,
mult_125_G2_FS_1_TEMP_G_0_5_1_port, mult_125_G2_FS_1_TEMP_G_0_5_2_port,
mult_125_G2_FS_1_TEMP_G_0_6_1_port, mult_125_G2_FS_1_TEMP_G_0_6_2_port,
mult_125_G2_FS_1_G_n_int_0_3_2_port, mult_125_G2_FS_1_G_n_int_0_3_3_port,
mult_125_G2_FS_1_G_n_int_0_4_0_port, mult_125_G2_FS_1_G_n_int_0_4_1_port,
mult_125_G2_FS_1_G_n_int_0_4_2_port, mult_125_G2_FS_1_G_n_int_0_4_3_port,
mult_125_G2_FS_1_G_n_int_0_5_0_port, mult_125_G2_FS_1_G_n_int_0_5_1_port,
mult_125_G2_FS_1_G_n_int_0_5_2_port, mult_125_G2_FS_1_G_n_int_0_5_3_port,
mult_125_G2_FS_1_G_n_int_0_6_0_port, mult_125_G2_FS_1_G_n_int_0_6_1_port,
mult_125_G2_FS_1_G_n_int_0_6_2_port, mult_125_G2_FS_1_G_n_int_0_6_3_port,
mult_125_G2_FS_1_G_n_int_0_7_0_port, mult_125_G2_FS_1_G_n_int_0_7_1_port,
mult_125_G2_FS_1_PG_int_0_3_3_port, mult_125_G2_FS_1_PG_int_0_4_0_port,
mult_125_G2_FS_1_PG_int_0_4_1_port, mult_125_G2_FS_1_PG_int_0_4_2_port,
mult_125_G2_FS_1_PG_int_0_4_3_port, mult_125_G2_FS_1_PG_int_0_5_0_port,
mult_125_G2_FS_1_PG_int_0_5_1_port, mult_125_G2_FS_1_PG_int_0_5_2_port,
mult_125_G2_FS_1_PG_int_0_5_3_port, mult_125_G2_FS_1_PG_int_0_6_0_port,
mult_125_G2_FS_1_PG_int_0_6_1_port, mult_125_G2_FS_1_PG_int_0_6_2_port,
mult_125_G2_FS_1_PG_int_0_6_3_port, mult_125_G2_FS_1_PG_int_0_7_0_port,
mult_125_G2_FS_1_PG_int_0_7_1_port, mult_125_G2_A2_14_port,
mult_125_G2_A2_15_port, mult_125_G2_A2_16_port, mult_125_G2_A2_17_port,
mult_125_G2_A2_18_port, mult_125_G2_A2_19_port, mult_125_G2_A2_20_port,
mult_125_G2_A2_21_port, mult_125_G2_A2_22_port, mult_125_G2_A2_23_port,
mult_125_G2_A2_24_port, mult_125_G2_A2_25_port, mult_125_G2_A2_26_port,
mult_125_G2_A2_27_port, mult_125_G2_A2_28_port, mult_125_G2_A2_29_port,
mult_125_G2_A1_0_port, mult_125_G2_A1_1_port, mult_125_G2_A1_2_port,
mult_125_G2_A1_3_port, mult_125_G2_A1_4_port, mult_125_G2_A1_5_port,
mult_125_G2_A1_6_port, mult_125_G2_A1_7_port, mult_125_G2_A1_8_port,
mult_125_G2_A1_9_port, mult_125_G2_A1_10_port, mult_125_G2_A1_11_port,
mult_125_G2_A1_12_port, mult_125_G2_A1_13_port, mult_125_G2_A1_14_port,
mult_125_G2_A1_15_port, mult_125_G2_A1_16_port, mult_125_G2_A1_17_port,
mult_125_G2_A1_18_port, mult_125_G2_A1_19_port, mult_125_G2_A1_20_port,
mult_125_G2_A1_21_port, mult_125_G2_A1_22_port, mult_125_G2_A1_23_port,
mult_125_G2_A1_24_port, mult_125_G2_A1_25_port, mult_125_G2_A1_26_port,
mult_125_G2_A1_27_port, mult_125_G2_A1_28_port, mult_125_G2_A1_29_port,
mult_125_G2_ZB, mult_125_G2_ZA, mult_125_G2_QB, mult_125_G2_QA,
mult_125_G2_A_notx_0_port, mult_125_G2_A_notx_1_port,
mult_125_G2_A_notx_2_port, mult_125_G2_A_notx_3_port,
mult_125_G2_A_notx_4_port, mult_125_G2_A_notx_5_port,
mult_125_G2_A_notx_6_port, mult_125_G2_A_notx_7_port,
mult_125_G2_A_notx_8_port, mult_125_G2_A_notx_9_port,
mult_125_G2_A_notx_10_port, mult_125_G2_A_notx_11_port,
mult_125_G2_A_notx_12_port, mult_125_G2_A_notx_13_port,
mult_125_G2_A_notx_14_port, mult_125_G2_B_notx_0_port,
mult_125_G2_B_notx_1_port, mult_125_G2_B_notx_2_port,
mult_125_G2_B_notx_3_port, mult_125_G2_B_notx_4_port,
mult_125_G2_B_notx_5_port, mult_125_G2_B_notx_6_port,
mult_125_G2_B_notx_7_port, mult_125_G2_B_notx_8_port,
mult_125_G2_B_notx_9_port, mult_125_G2_B_notx_10_port,
mult_125_G2_B_notx_11_port, mult_125_G2_B_notx_12_port,
mult_125_G2_B_notx_13_port, mult_125_G2_B_notx_14_port,
mult_125_G2_ab_0_1_port, mult_125_G2_ab_0_2_port, mult_125_G2_ab_0_3_port
, mult_125_G2_ab_0_4_port, mult_125_G2_ab_0_5_port,
mult_125_G2_ab_0_6_port, mult_125_G2_ab_0_7_port, mult_125_G2_ab_0_8_port
, mult_125_G2_ab_0_9_port, mult_125_G2_ab_0_10_port,
mult_125_G2_ab_0_11_port, mult_125_G2_ab_0_12_port,
mult_125_G2_ab_0_13_port, mult_125_G2_ab_0_14_port,
mult_125_G2_ab_0_15_port, mult_125_G2_ab_1_0_port,
mult_125_G2_ab_1_1_port, mult_125_G2_ab_1_2_port, mult_125_G2_ab_1_3_port
, mult_125_G2_ab_1_4_port, mult_125_G2_ab_1_5_port,
mult_125_G2_ab_1_6_port, mult_125_G2_ab_1_7_port, mult_125_G2_ab_1_8_port
, mult_125_G2_ab_1_9_port, mult_125_G2_ab_1_10_port,
mult_125_G2_ab_1_11_port, mult_125_G2_ab_1_12_port,
mult_125_G2_ab_1_13_port, mult_125_G2_ab_1_14_port,
mult_125_G2_ab_1_15_port, mult_125_G2_ab_2_0_port,
mult_125_G2_ab_2_1_port, mult_125_G2_ab_2_2_port, mult_125_G2_ab_2_3_port
, mult_125_G2_ab_2_4_port, mult_125_G2_ab_2_5_port,
mult_125_G2_ab_2_6_port, mult_125_G2_ab_2_7_port, mult_125_G2_ab_2_8_port
, mult_125_G2_ab_2_9_port, mult_125_G2_ab_2_10_port,
mult_125_G2_ab_2_11_port, mult_125_G2_ab_2_12_port,
mult_125_G2_ab_2_13_port, mult_125_G2_ab_2_14_port,
mult_125_G2_ab_2_15_port, mult_125_G2_ab_3_0_port,
mult_125_G2_ab_3_1_port, mult_125_G2_ab_3_2_port, mult_125_G2_ab_3_3_port
, mult_125_G2_ab_3_4_port, mult_125_G2_ab_3_5_port,
mult_125_G2_ab_3_6_port, mult_125_G2_ab_3_7_port, mult_125_G2_ab_3_8_port
, mult_125_G2_ab_3_9_port, mult_125_G2_ab_3_10_port,
mult_125_G2_ab_3_11_port, mult_125_G2_ab_3_12_port,
mult_125_G2_ab_3_13_port, mult_125_G2_ab_3_14_port,
mult_125_G2_ab_3_15_port, mult_125_G2_ab_4_0_port,
mult_125_G2_ab_4_1_port, mult_125_G2_ab_4_2_port, mult_125_G2_ab_4_3_port
, mult_125_G2_ab_4_4_port, mult_125_G2_ab_4_5_port,
mult_125_G2_ab_4_6_port, mult_125_G2_ab_4_7_port, mult_125_G2_ab_4_8_port
, mult_125_G2_ab_4_9_port, mult_125_G2_ab_4_10_port,
mult_125_G2_ab_4_11_port, mult_125_G2_ab_4_12_port,
mult_125_G2_ab_4_13_port, mult_125_G2_ab_4_14_port,
mult_125_G2_ab_4_15_port, mult_125_G2_ab_5_0_port,
mult_125_G2_ab_5_1_port, mult_125_G2_ab_5_2_port, mult_125_G2_ab_5_3_port
, mult_125_G2_ab_5_4_port, mult_125_G2_ab_5_5_port,
mult_125_G2_ab_5_6_port, mult_125_G2_ab_5_7_port, mult_125_G2_ab_5_8_port
, mult_125_G2_ab_5_9_port, mult_125_G2_ab_5_10_port,
mult_125_G2_ab_5_11_port, mult_125_G2_ab_5_12_port,
mult_125_G2_ab_5_13_port, mult_125_G2_ab_5_14_port,
mult_125_G2_ab_5_15_port, mult_125_G2_ab_6_0_port,
mult_125_G2_ab_6_1_port, mult_125_G2_ab_6_2_port, mult_125_G2_ab_6_3_port
, mult_125_G2_ab_6_4_port, mult_125_G2_ab_6_5_port,
mult_125_G2_ab_6_6_port, mult_125_G2_ab_6_7_port, mult_125_G2_ab_6_8_port
, mult_125_G2_ab_6_9_port, mult_125_G2_ab_6_10_port,
mult_125_G2_ab_6_11_port, mult_125_G2_ab_6_12_port,
mult_125_G2_ab_6_13_port, mult_125_G2_ab_6_14_port,
mult_125_G2_ab_6_15_port, mult_125_G2_ab_7_0_port,
mult_125_G2_ab_7_1_port, mult_125_G2_ab_7_2_port, mult_125_G2_ab_7_3_port
, mult_125_G2_ab_7_4_port, mult_125_G2_ab_7_5_port,
mult_125_G2_ab_7_6_port, mult_125_G2_ab_7_7_port, mult_125_G2_ab_7_8_port
, mult_125_G2_ab_7_9_port, mult_125_G2_ab_7_10_port,
mult_125_G2_ab_7_11_port, mult_125_G2_ab_7_12_port,
mult_125_G2_ab_7_13_port, mult_125_G2_ab_7_14_port,
mult_125_G2_ab_7_15_port, mult_125_G2_ab_8_0_port,
mult_125_G2_ab_8_1_port, mult_125_G2_ab_8_2_port, mult_125_G2_ab_8_3_port
, mult_125_G2_ab_8_4_port, mult_125_G2_ab_8_5_port,
mult_125_G2_ab_8_6_port, mult_125_G2_ab_8_7_port, mult_125_G2_ab_8_8_port
, mult_125_G2_ab_8_9_port, mult_125_G2_ab_8_10_port,
mult_125_G2_ab_8_11_port, mult_125_G2_ab_8_12_port,
mult_125_G2_ab_8_13_port, mult_125_G2_ab_8_14_port,
mult_125_G2_ab_8_15_port, mult_125_G2_ab_9_0_port,
mult_125_G2_ab_9_1_port, mult_125_G2_ab_9_2_port, mult_125_G2_ab_9_3_port
, mult_125_G2_ab_9_4_port, mult_125_G2_ab_9_5_port,
mult_125_G2_ab_9_6_port, mult_125_G2_ab_9_7_port, mult_125_G2_ab_9_8_port
, mult_125_G2_ab_9_9_port, mult_125_G2_ab_9_10_port,
mult_125_G2_ab_9_11_port, mult_125_G2_ab_9_12_port,
mult_125_G2_ab_9_13_port, mult_125_G2_ab_9_14_port,
mult_125_G2_ab_9_15_port, mult_125_G2_ab_10_0_port,
mult_125_G2_ab_10_1_port, mult_125_G2_ab_10_2_port,
mult_125_G2_ab_10_3_port, mult_125_G2_ab_10_4_port,
mult_125_G2_ab_10_5_port, mult_125_G2_ab_10_6_port,
mult_125_G2_ab_10_7_port, mult_125_G2_ab_10_8_port,
mult_125_G2_ab_10_9_port, mult_125_G2_ab_10_10_port,
mult_125_G2_ab_10_11_port, mult_125_G2_ab_10_12_port,
mult_125_G2_ab_10_13_port, mult_125_G2_ab_10_14_port,
mult_125_G2_ab_10_15_port, mult_125_G2_ab_11_0_port,
mult_125_G2_ab_11_1_port, mult_125_G2_ab_11_2_port,
mult_125_G2_ab_11_3_port, mult_125_G2_ab_11_4_port,
mult_125_G2_ab_11_5_port, mult_125_G2_ab_11_6_port,
mult_125_G2_ab_11_7_port, mult_125_G2_ab_11_8_port,
mult_125_G2_ab_11_9_port, mult_125_G2_ab_11_10_port,
mult_125_G2_ab_11_11_port, mult_125_G2_ab_11_12_port,
mult_125_G2_ab_11_13_port, mult_125_G2_ab_11_14_port,
mult_125_G2_ab_11_15_port, mult_125_G2_ab_12_0_port,
mult_125_G2_ab_12_1_port, mult_125_G2_ab_12_2_port,
mult_125_G2_ab_12_3_port, mult_125_G2_ab_12_4_port,
mult_125_G2_ab_12_5_port, mult_125_G2_ab_12_6_port,
mult_125_G2_ab_12_7_port, mult_125_G2_ab_12_8_port,
mult_125_G2_ab_12_9_port, mult_125_G2_ab_12_10_port,
mult_125_G2_ab_12_11_port, mult_125_G2_ab_12_12_port,
mult_125_G2_ab_12_13_port, mult_125_G2_ab_12_14_port,
mult_125_G2_ab_12_15_port, mult_125_G2_ab_13_0_port,
mult_125_G2_ab_13_1_port, mult_125_G2_ab_13_2_port,
mult_125_G2_ab_13_3_port, mult_125_G2_ab_13_4_port,
mult_125_G2_ab_13_5_port, mult_125_G2_ab_13_6_port,
mult_125_G2_ab_13_7_port, mult_125_G2_ab_13_8_port,
mult_125_G2_ab_13_9_port, mult_125_G2_ab_13_10_port,
mult_125_G2_ab_13_11_port, mult_125_G2_ab_13_12_port,
mult_125_G2_ab_13_13_port, mult_125_G2_ab_13_14_port,
mult_125_G2_ab_13_15_port, mult_125_G2_ab_14_0_port,
mult_125_G2_ab_14_1_port, mult_125_G2_ab_14_2_port,
mult_125_G2_ab_14_3_port, mult_125_G2_ab_14_4_port,
mult_125_G2_ab_14_5_port, mult_125_G2_ab_14_6_port,
mult_125_G2_ab_14_7_port, mult_125_G2_ab_14_8_port,
mult_125_G2_ab_14_9_port, mult_125_G2_ab_14_10_port,
mult_125_G2_ab_14_11_port, mult_125_G2_ab_14_12_port,
mult_125_G2_ab_14_13_port, mult_125_G2_ab_14_14_port,
mult_125_G2_ab_14_15_port, mult_125_G2_ab_15_0_port,
mult_125_G2_ab_15_1_port, mult_125_G2_ab_15_2_port,
mult_125_G2_ab_15_3_port, mult_125_G2_ab_15_4_port,
mult_125_G2_ab_15_5_port, mult_125_G2_ab_15_6_port,
mult_125_G2_ab_15_7_port, mult_125_G2_ab_15_8_port,
mult_125_G2_ab_15_9_port, mult_125_G2_ab_15_10_port,
mult_125_G2_ab_15_11_port, mult_125_G2_ab_15_12_port,
mult_125_G2_ab_15_13_port, mult_125_G2_ab_15_14_port,
mult_125_G2_ab_15_15_port, mult_125_G2_B_not_0_port,
mult_125_G2_B_not_1_port, mult_125_G2_B_not_2_port,
mult_125_G2_B_not_3_port, mult_125_G2_B_not_4_port,
mult_125_G2_B_not_5_port, mult_125_G2_B_not_6_port,
mult_125_G2_B_not_7_port, mult_125_G2_B_not_8_port,
mult_125_G2_B_not_9_port, mult_125_G2_B_not_10_port,
mult_125_G2_B_not_11_port, mult_125_G2_B_not_12_port,
mult_125_G2_B_not_13_port, mult_125_G2_B_not_14_port,
mult_125_G2_B_not_15_port, mult_125_G2_A_not_0_port,
mult_125_G2_A_not_1_port, mult_125_G2_A_not_2_port,
mult_125_G2_A_not_3_port, mult_125_G2_A_not_4_port,
mult_125_G2_A_not_5_port, mult_125_G2_A_not_6_port,
mult_125_G2_A_not_7_port, mult_125_G2_A_not_8_port,
mult_125_G2_A_not_9_port, mult_125_G2_A_not_10_port,
mult_125_G2_A_not_11_port, mult_125_G2_A_not_12_port,
mult_125_G2_A_not_13_port, mult_125_G2_A_not_14_port,
mult_125_G2_A_not_15_port, mult_125_FS_1_C_1_3_3_port,
mult_125_FS_1_C_1_4_0_port, mult_125_FS_1_C_1_4_1_port,
mult_125_FS_1_C_1_4_2_port, mult_125_FS_1_C_1_4_3_port,
mult_125_FS_1_C_1_5_0_port, mult_125_FS_1_C_1_5_1_port,
mult_125_FS_1_C_1_5_2_port, mult_125_FS_1_C_1_5_3_port,
mult_125_FS_1_C_1_6_0_port, mult_125_FS_1_C_1_6_1_port,
mult_125_FS_1_C_1_6_2_port, mult_125_FS_1_C_1_6_3_port,
mult_125_FS_1_C_1_7_0_port, mult_125_FS_1_C_1_7_1_port,
mult_125_FS_1_P_0_0_1_port, mult_125_FS_1_P_0_0_2_port,
mult_125_FS_1_P_0_0_3_port, mult_125_FS_1_P_0_1_1_port,
mult_125_FS_1_P_0_1_2_port, mult_125_FS_1_P_0_1_3_port,
mult_125_FS_1_P_0_2_1_port, mult_125_FS_1_P_0_2_2_port,
mult_125_FS_1_P_0_2_3_port, mult_125_FS_1_P_0_3_1_port,
mult_125_FS_1_P_0_3_2_port, mult_125_FS_1_P_0_3_3_port,
mult_125_FS_1_P_0_4_1_port, mult_125_FS_1_P_0_4_2_port,
mult_125_FS_1_P_0_4_3_port, mult_125_FS_1_P_0_5_1_port,
mult_125_FS_1_P_0_5_2_port, mult_125_FS_1_P_0_5_3_port,
mult_125_FS_1_P_0_6_1_port, mult_125_FS_1_P_0_6_2_port,
mult_125_FS_1_P_0_6_3_port, mult_125_FS_1_P_0_7_1_port,
mult_125_FS_1_TEMP_P_0_0_0_port, mult_125_FS_1_TEMP_P_0_1_0_port,
mult_125_FS_1_TEMP_P_0_2_0_port, mult_125_FS_1_TEMP_P_0_3_0_port,
mult_125_FS_1_TEMP_P_0_4_0_port, mult_125_FS_1_TEMP_P_0_4_1_port,
mult_125_FS_1_TEMP_P_0_4_2_port, mult_125_FS_1_TEMP_P_0_5_0_port,
mult_125_FS_1_TEMP_P_0_5_1_port, mult_125_FS_1_TEMP_P_0_5_2_port,
mult_125_FS_1_TEMP_P_0_6_0_port, mult_125_FS_1_TEMP_P_0_6_1_port,
mult_125_FS_1_TEMP_P_0_6_2_port, mult_125_FS_1_TEMP_P_0_7_0_port,
mult_125_FS_1_G_1_0_3_port, mult_125_FS_1_G_1_1_0_port,
mult_125_FS_1_G_1_1_1_port, mult_125_FS_1_G_1_1_2_port,
mult_125_FS_1_G_2_0_0_port, mult_125_FS_1_TEMP_G_0_3_2_port,
mult_125_FS_1_TEMP_G_0_4_1_port, mult_125_FS_1_TEMP_G_0_4_2_port,
mult_125_FS_1_TEMP_G_0_5_1_port, mult_125_FS_1_TEMP_G_0_5_2_port,
mult_125_FS_1_TEMP_G_0_6_1_port, mult_125_FS_1_TEMP_G_0_6_2_port,
mult_125_FS_1_G_n_int_0_3_2_port, mult_125_FS_1_G_n_int_0_3_3_port,
mult_125_FS_1_G_n_int_0_4_0_port, mult_125_FS_1_G_n_int_0_4_1_port,
mult_125_FS_1_G_n_int_0_4_2_port, mult_125_FS_1_G_n_int_0_4_3_port,
mult_125_FS_1_G_n_int_0_5_0_port, mult_125_FS_1_G_n_int_0_5_1_port,
mult_125_FS_1_G_n_int_0_5_2_port, mult_125_FS_1_G_n_int_0_5_3_port,
mult_125_FS_1_G_n_int_0_6_0_port, mult_125_FS_1_G_n_int_0_6_1_port,
mult_125_FS_1_G_n_int_0_6_2_port, mult_125_FS_1_G_n_int_0_6_3_port,
mult_125_FS_1_G_n_int_0_7_0_port, mult_125_FS_1_G_n_int_0_7_1_port,
mult_125_FS_1_PG_int_0_3_3_port, mult_125_FS_1_PG_int_0_4_0_port,
mult_125_FS_1_PG_int_0_4_1_port, mult_125_FS_1_PG_int_0_4_2_port,
mult_125_FS_1_PG_int_0_4_3_port, mult_125_FS_1_PG_int_0_5_0_port,
mult_125_FS_1_PG_int_0_5_1_port, mult_125_FS_1_PG_int_0_5_2_port,
mult_125_FS_1_PG_int_0_5_3_port, mult_125_FS_1_PG_int_0_6_0_port,
mult_125_FS_1_PG_int_0_6_1_port, mult_125_FS_1_PG_int_0_6_2_port,
mult_125_FS_1_PG_int_0_6_3_port, mult_125_FS_1_PG_int_0_7_0_port,
mult_125_FS_1_PG_int_0_7_1_port, mult_125_A2_14_port, mult_125_A2_15_port
, mult_125_A2_16_port, mult_125_A2_17_port, mult_125_A2_18_port,
mult_125_A2_19_port, mult_125_A2_20_port, mult_125_A2_21_port,
mult_125_A2_22_port, mult_125_A2_23_port, mult_125_A2_24_port,
mult_125_A2_25_port, mult_125_A2_26_port, mult_125_A2_27_port,
mult_125_A2_28_port, mult_125_A2_29_port, mult_125_A1_0_port,
mult_125_A1_1_port, mult_125_A1_2_port, mult_125_A1_3_port,
mult_125_A1_4_port, mult_125_A1_5_port, mult_125_A1_6_port,
mult_125_A1_7_port, mult_125_A1_8_port, mult_125_A1_9_port,
mult_125_A1_10_port, mult_125_A1_11_port, mult_125_A1_12_port,
mult_125_A1_13_port, mult_125_A1_14_port, mult_125_A1_15_port,
mult_125_A1_16_port, mult_125_A1_17_port, mult_125_A1_18_port,
mult_125_A1_19_port, mult_125_A1_20_port, mult_125_A1_21_port,
mult_125_A1_22_port, mult_125_A1_23_port, mult_125_A1_24_port,
mult_125_A1_25_port, mult_125_A1_26_port, mult_125_A1_27_port,
mult_125_A1_28_port, mult_125_A1_29_port, mult_125_ZB, mult_125_ZA,
mult_125_QB, mult_125_QA, mult_125_A_notx_0_port, mult_125_A_notx_1_port,
mult_125_A_notx_2_port, mult_125_A_notx_3_port, mult_125_A_notx_4_port,
mult_125_A_notx_5_port, mult_125_A_notx_6_port, mult_125_A_notx_7_port,
mult_125_A_notx_8_port, mult_125_A_notx_9_port, mult_125_A_notx_10_port,
mult_125_A_notx_11_port, mult_125_A_notx_12_port, mult_125_A_notx_13_port
, mult_125_A_notx_14_port, mult_125_B_notx_0_port, mult_125_B_notx_1_port
, mult_125_B_notx_2_port, mult_125_B_notx_3_port, mult_125_B_notx_4_port,
mult_125_B_notx_5_port, mult_125_B_notx_6_port, mult_125_B_notx_7_port,
mult_125_B_notx_8_port, mult_125_B_notx_9_port, mult_125_B_notx_10_port,
mult_125_B_notx_11_port, mult_125_B_notx_12_port, mult_125_B_notx_13_port
, mult_125_B_notx_14_port, mult_125_ab_0_1_port, mult_125_ab_0_2_port,
mult_125_ab_0_3_port, mult_125_ab_0_4_port, mult_125_ab_0_5_port,
mult_125_ab_0_6_port, mult_125_ab_0_7_port, mult_125_ab_0_8_port,
mult_125_ab_0_9_port, mult_125_ab_0_10_port, mult_125_ab_0_11_port,
mult_125_ab_0_12_port, mult_125_ab_0_13_port, mult_125_ab_0_14_port,
mult_125_ab_0_15_port, mult_125_ab_1_0_port, mult_125_ab_1_1_port,
mult_125_ab_1_2_port, mult_125_ab_1_3_port, mult_125_ab_1_4_port,
mult_125_ab_1_5_port, mult_125_ab_1_6_port, mult_125_ab_1_7_port,
mult_125_ab_1_8_port, mult_125_ab_1_9_port, mult_125_ab_1_10_port,
mult_125_ab_1_11_port, mult_125_ab_1_12_port, mult_125_ab_1_13_port,
mult_125_ab_1_14_port, mult_125_ab_1_15_port, mult_125_ab_2_0_port,
mult_125_ab_2_1_port, mult_125_ab_2_2_port, mult_125_ab_2_3_port,
mult_125_ab_2_4_port, mult_125_ab_2_5_port, mult_125_ab_2_6_port,
mult_125_ab_2_7_port, mult_125_ab_2_8_port, mult_125_ab_2_9_port,
mult_125_ab_2_10_port, mult_125_ab_2_11_port, mult_125_ab_2_12_port,
mult_125_ab_2_13_port, mult_125_ab_2_14_port, mult_125_ab_2_15_port,
mult_125_ab_3_0_port, mult_125_ab_3_1_port, mult_125_ab_3_2_port,
mult_125_ab_3_3_port, mult_125_ab_3_4_port, mult_125_ab_3_5_port,
mult_125_ab_3_6_port, mult_125_ab_3_7_port, mult_125_ab_3_8_port,
mult_125_ab_3_9_port, mult_125_ab_3_10_port, mult_125_ab_3_11_port,
mult_125_ab_3_12_port, mult_125_ab_3_13_port, mult_125_ab_3_14_port,
mult_125_ab_3_15_port, mult_125_ab_4_0_port, mult_125_ab_4_1_port,
mult_125_ab_4_2_port, mult_125_ab_4_3_port, mult_125_ab_4_4_port,
mult_125_ab_4_5_port, mult_125_ab_4_6_port, mult_125_ab_4_7_port,
mult_125_ab_4_8_port, mult_125_ab_4_9_port, mult_125_ab_4_10_port,
mult_125_ab_4_11_port, mult_125_ab_4_12_port, mult_125_ab_4_13_port,
mult_125_ab_4_14_port, mult_125_ab_4_15_port, mult_125_ab_5_0_port,
mult_125_ab_5_1_port, mult_125_ab_5_2_port, mult_125_ab_5_3_port,
mult_125_ab_5_4_port, mult_125_ab_5_5_port, mult_125_ab_5_6_port,
mult_125_ab_5_7_port, mult_125_ab_5_8_port, mult_125_ab_5_9_port,
mult_125_ab_5_10_port, mult_125_ab_5_11_port, mult_125_ab_5_12_port,
mult_125_ab_5_13_port, mult_125_ab_5_14_port, mult_125_ab_5_15_port,
mult_125_ab_6_0_port, mult_125_ab_6_1_port, mult_125_ab_6_2_port,
mult_125_ab_6_3_port, mult_125_ab_6_4_port, mult_125_ab_6_5_port,
mult_125_ab_6_6_port, mult_125_ab_6_7_port, mult_125_ab_6_8_port,
mult_125_ab_6_9_port, mult_125_ab_6_10_port, mult_125_ab_6_11_port,
mult_125_ab_6_12_port, mult_125_ab_6_13_port, mult_125_ab_6_14_port,
mult_125_ab_6_15_port, mult_125_ab_7_0_port, mult_125_ab_7_1_port,
mult_125_ab_7_2_port, mult_125_ab_7_3_port, mult_125_ab_7_4_port,
mult_125_ab_7_5_port, mult_125_ab_7_6_port, mult_125_ab_7_7_port,
mult_125_ab_7_8_port, mult_125_ab_7_9_port, mult_125_ab_7_10_port,
mult_125_ab_7_11_port, mult_125_ab_7_12_port, mult_125_ab_7_13_port,
mult_125_ab_7_14_port, mult_125_ab_7_15_port, mult_125_ab_8_0_port,
mult_125_ab_8_1_port, mult_125_ab_8_2_port, mult_125_ab_8_3_port,
mult_125_ab_8_4_port, mult_125_ab_8_5_port, mult_125_ab_8_6_port,
mult_125_ab_8_7_port, mult_125_ab_8_8_port, mult_125_ab_8_9_port,
mult_125_ab_8_10_port, mult_125_ab_8_11_port, mult_125_ab_8_12_port,
mult_125_ab_8_13_port, mult_125_ab_8_14_port, mult_125_ab_8_15_port,
mult_125_ab_9_0_port, mult_125_ab_9_1_port, mult_125_ab_9_2_port,
mult_125_ab_9_3_port, mult_125_ab_9_4_port, mult_125_ab_9_5_port,
mult_125_ab_9_6_port, mult_125_ab_9_7_port, mult_125_ab_9_8_port,
mult_125_ab_9_9_port, mult_125_ab_9_10_port, mult_125_ab_9_11_port,
mult_125_ab_9_12_port, mult_125_ab_9_13_port, mult_125_ab_9_14_port,
mult_125_ab_9_15_port, mult_125_ab_10_0_port, mult_125_ab_10_1_port,
mult_125_ab_10_2_port, mult_125_ab_10_3_port, mult_125_ab_10_4_port,
mult_125_ab_10_5_port, mult_125_ab_10_6_port, mult_125_ab_10_7_port,
mult_125_ab_10_8_port, mult_125_ab_10_9_port, mult_125_ab_10_10_port,
mult_125_ab_10_11_port, mult_125_ab_10_12_port, mult_125_ab_10_13_port,
mult_125_ab_10_14_port, mult_125_ab_10_15_port, mult_125_ab_11_0_port,
mult_125_ab_11_1_port, mult_125_ab_11_2_port, mult_125_ab_11_3_port,
mult_125_ab_11_4_port, mult_125_ab_11_5_port, mult_125_ab_11_6_port,
mult_125_ab_11_7_port, mult_125_ab_11_8_port, mult_125_ab_11_9_port,
mult_125_ab_11_10_port, mult_125_ab_11_11_port, mult_125_ab_11_12_port,
mult_125_ab_11_13_port, mult_125_ab_11_14_port, mult_125_ab_11_15_port,
mult_125_ab_12_0_port, mult_125_ab_12_1_port, mult_125_ab_12_2_port,
mult_125_ab_12_3_port, mult_125_ab_12_4_port, mult_125_ab_12_5_port,
mult_125_ab_12_6_port, mult_125_ab_12_7_port, mult_125_ab_12_8_port,
mult_125_ab_12_9_port, mult_125_ab_12_10_port, mult_125_ab_12_11_port,
mult_125_ab_12_12_port, mult_125_ab_12_13_port, mult_125_ab_12_14_port,
mult_125_ab_12_15_port, mult_125_ab_13_0_port, mult_125_ab_13_1_port,
mult_125_ab_13_2_port, mult_125_ab_13_3_port, mult_125_ab_13_4_port,
mult_125_ab_13_5_port, mult_125_ab_13_6_port, mult_125_ab_13_7_port,
mult_125_ab_13_8_port, mult_125_ab_13_9_port, mult_125_ab_13_10_port,
mult_125_ab_13_11_port, mult_125_ab_13_12_port, mult_125_ab_13_13_port,
mult_125_ab_13_14_port, mult_125_ab_13_15_port, mult_125_ab_14_0_port,
mult_125_ab_14_1_port, mult_125_ab_14_2_port, mult_125_ab_14_3_port,
mult_125_ab_14_4_port, mult_125_ab_14_5_port, mult_125_ab_14_6_port,
mult_125_ab_14_7_port, mult_125_ab_14_8_port, mult_125_ab_14_9_port,
mult_125_ab_14_10_port, mult_125_ab_14_11_port, mult_125_ab_14_12_port,
mult_125_ab_14_13_port, mult_125_ab_14_14_port, mult_125_ab_14_15_port,
mult_125_ab_15_0_port, mult_125_ab_15_1_port, mult_125_ab_15_2_port,
mult_125_ab_15_3_port, mult_125_ab_15_4_port, mult_125_ab_15_5_port,
mult_125_ab_15_6_port, mult_125_ab_15_7_port, mult_125_ab_15_8_port,
mult_125_ab_15_9_port, mult_125_ab_15_10_port, mult_125_ab_15_11_port,
mult_125_ab_15_12_port, mult_125_ab_15_13_port, mult_125_ab_15_14_port,
mult_125_ab_15_15_port, mult_125_B_not_0_port, mult_125_B_not_1_port,
mult_125_B_not_2_port, mult_125_B_not_3_port, mult_125_B_not_4_port,
mult_125_B_not_5_port, mult_125_B_not_6_port, mult_125_B_not_7_port,
mult_125_B_not_8_port, mult_125_B_not_9_port, mult_125_B_not_10_port,
mult_125_B_not_11_port, mult_125_B_not_12_port, mult_125_B_not_13_port,
mult_125_B_not_14_port, mult_125_B_not_15_port, mult_125_A_not_0_port,
mult_125_A_not_1_port, mult_125_A_not_2_port, mult_125_A_not_3_port,
mult_125_A_not_4_port, mult_125_A_not_5_port, mult_125_A_not_6_port,
mult_125_A_not_7_port, mult_125_A_not_8_port, mult_125_A_not_9_port,
mult_125_A_not_10_port, mult_125_A_not_11_port, mult_125_A_not_12_port,
mult_125_A_not_13_port, mult_125_A_not_14_port, mult_125_A_not_15_port,
mult_125_G4_FS_1_C_1_3_3_port, mult_125_G4_FS_1_C_1_4_0_port,
mult_125_G4_FS_1_C_1_4_1_port, mult_125_G4_FS_1_C_1_4_2_port,
mult_125_G4_FS_1_C_1_4_3_port, mult_125_G4_FS_1_C_1_5_0_port,
mult_125_G4_FS_1_C_1_5_1_port, mult_125_G4_FS_1_C_1_5_2_port,
mult_125_G4_FS_1_C_1_5_3_port, mult_125_G4_FS_1_C_1_6_0_port,
mult_125_G4_FS_1_C_1_6_1_port, mult_125_G4_FS_1_C_1_6_2_port,
mult_125_G4_FS_1_C_1_6_3_port, mult_125_G4_FS_1_C_1_7_0_port,
mult_125_G4_FS_1_C_1_7_1_port, mult_125_G4_FS_1_P_0_0_1_port,
mult_125_G4_FS_1_P_0_0_2_port, mult_125_G4_FS_1_P_0_0_3_port,
mult_125_G4_FS_1_P_0_1_1_port, mult_125_G4_FS_1_P_0_1_2_port,
mult_125_G4_FS_1_P_0_1_3_port, mult_125_G4_FS_1_P_0_2_1_port,
mult_125_G4_FS_1_P_0_2_2_port, mult_125_G4_FS_1_P_0_2_3_port,
mult_125_G4_FS_1_P_0_3_1_port, mult_125_G4_FS_1_P_0_3_2_port,
mult_125_G4_FS_1_P_0_3_3_port, mult_125_G4_FS_1_P_0_4_1_port,
mult_125_G4_FS_1_P_0_4_2_port, mult_125_G4_FS_1_P_0_4_3_port,
mult_125_G4_FS_1_P_0_5_1_port, mult_125_G4_FS_1_P_0_5_2_port,
mult_125_G4_FS_1_P_0_5_3_port, mult_125_G4_FS_1_P_0_6_1_port,
mult_125_G4_FS_1_P_0_6_2_port, mult_125_G4_FS_1_P_0_6_3_port,
mult_125_G4_FS_1_P_0_7_1_port, mult_125_G4_FS_1_TEMP_P_0_0_0_port,
mult_125_G4_FS_1_TEMP_P_0_1_0_port, mult_125_G4_FS_1_TEMP_P_0_2_0_port,
mult_125_G4_FS_1_TEMP_P_0_3_0_port, mult_125_G4_FS_1_TEMP_P_0_4_0_port,
mult_125_G4_FS_1_TEMP_P_0_4_1_port, mult_125_G4_FS_1_TEMP_P_0_4_2_port,
mult_125_G4_FS_1_TEMP_P_0_5_0_port, mult_125_G4_FS_1_TEMP_P_0_5_1_port,
mult_125_G4_FS_1_TEMP_P_0_5_2_port, mult_125_G4_FS_1_TEMP_P_0_6_0_port,
mult_125_G4_FS_1_TEMP_P_0_6_1_port, mult_125_G4_FS_1_TEMP_P_0_6_2_port,
mult_125_G4_FS_1_TEMP_P_0_7_0_port, mult_125_G4_FS_1_G_1_0_3_port,
mult_125_G4_FS_1_G_1_1_0_port, mult_125_G4_FS_1_G_1_1_1_port,
mult_125_G4_FS_1_G_1_1_2_port, mult_125_G4_FS_1_G_2_0_0_port,
mult_125_G4_FS_1_TEMP_G_0_3_2_port, mult_125_G4_FS_1_TEMP_G_0_4_1_port,
mult_125_G4_FS_1_TEMP_G_0_4_2_port, mult_125_G4_FS_1_TEMP_G_0_5_1_port,
mult_125_G4_FS_1_TEMP_G_0_5_2_port, mult_125_G4_FS_1_TEMP_G_0_6_1_port,
mult_125_G4_FS_1_TEMP_G_0_6_2_port, mult_125_G4_FS_1_G_n_int_0_3_2_port,
mult_125_G4_FS_1_G_n_int_0_3_3_port, mult_125_G4_FS_1_G_n_int_0_4_0_port,
mult_125_G4_FS_1_G_n_int_0_4_1_port, mult_125_G4_FS_1_G_n_int_0_4_2_port,
mult_125_G4_FS_1_G_n_int_0_4_3_port, mult_125_G4_FS_1_G_n_int_0_5_0_port,
mult_125_G4_FS_1_G_n_int_0_5_1_port, mult_125_G4_FS_1_G_n_int_0_5_2_port,
mult_125_G4_FS_1_G_n_int_0_5_3_port, mult_125_G4_FS_1_G_n_int_0_6_0_port,
mult_125_G4_FS_1_G_n_int_0_6_1_port, mult_125_G4_FS_1_G_n_int_0_6_2_port,
mult_125_G4_FS_1_G_n_int_0_6_3_port, mult_125_G4_FS_1_G_n_int_0_7_0_port,
mult_125_G4_FS_1_G_n_int_0_7_1_port, mult_125_G4_FS_1_PG_int_0_3_3_port,
mult_125_G4_FS_1_PG_int_0_4_0_port, mult_125_G4_FS_1_PG_int_0_4_1_port,
mult_125_G4_FS_1_PG_int_0_4_2_port, mult_125_G4_FS_1_PG_int_0_4_3_port,
mult_125_G4_FS_1_PG_int_0_5_0_port, mult_125_G4_FS_1_PG_int_0_5_1_port,
mult_125_G4_FS_1_PG_int_0_5_2_port, mult_125_G4_FS_1_PG_int_0_5_3_port,
mult_125_G4_FS_1_PG_int_0_6_0_port, mult_125_G4_FS_1_PG_int_0_6_1_port,
mult_125_G4_FS_1_PG_int_0_6_2_port, mult_125_G4_FS_1_PG_int_0_6_3_port,
mult_125_G4_FS_1_PG_int_0_7_0_port, mult_125_G4_FS_1_PG_int_0_7_1_port,
mult_125_G4_A2_14_port, mult_125_G4_A2_15_port, mult_125_G4_A2_16_port,
mult_125_G4_A2_17_port, mult_125_G4_A2_18_port, mult_125_G4_A2_19_port,
mult_125_G4_A2_20_port, mult_125_G4_A2_21_port, mult_125_G4_A2_22_port,
mult_125_G4_A2_23_port, mult_125_G4_A2_24_port, mult_125_G4_A2_25_port,
mult_125_G4_A2_26_port, mult_125_G4_A2_27_port, mult_125_G4_A2_28_port,
mult_125_G4_A2_29_port, mult_125_G4_A1_0_port, mult_125_G4_A1_1_port,
mult_125_G4_A1_2_port, mult_125_G4_A1_3_port, mult_125_G4_A1_4_port,
mult_125_G4_A1_5_port, mult_125_G4_A1_6_port, mult_125_G4_A1_7_port,
mult_125_G4_A1_8_port, mult_125_G4_A1_9_port, mult_125_G4_A1_10_port,
mult_125_G4_A1_11_port, mult_125_G4_A1_12_port, mult_125_G4_A1_13_port,
mult_125_G4_A1_14_port, mult_125_G4_A1_15_port, mult_125_G4_A1_16_port,
mult_125_G4_A1_17_port, mult_125_G4_A1_18_port, mult_125_G4_A1_19_port,
mult_125_G4_A1_20_port, mult_125_G4_A1_21_port, mult_125_G4_A1_22_port,
mult_125_G4_A1_23_port, mult_125_G4_A1_24_port, mult_125_G4_A1_25_port,
mult_125_G4_A1_26_port, mult_125_G4_A1_27_port, mult_125_G4_A1_28_port,
mult_125_G4_A1_29_port, mult_125_G4_ZB, mult_125_G4_ZA, mult_125_G4_QB,
mult_125_G4_QA, mult_125_G4_A_notx_0_port, mult_125_G4_A_notx_1_port,
mult_125_G4_A_notx_2_port, mult_125_G4_A_notx_3_port,
mult_125_G4_A_notx_4_port, mult_125_G4_A_notx_5_port,
mult_125_G4_A_notx_6_port, mult_125_G4_A_notx_7_port,
mult_125_G4_A_notx_8_port, mult_125_G4_A_notx_9_port,
mult_125_G4_A_notx_10_port, mult_125_G4_A_notx_11_port,
mult_125_G4_A_notx_12_port, mult_125_G4_A_notx_13_port,
mult_125_G4_A_notx_14_port, mult_125_G4_B_notx_0_port,
mult_125_G4_B_notx_1_port, mult_125_G4_B_notx_2_port,
mult_125_G4_B_notx_3_port, mult_125_G4_B_notx_4_port,
mult_125_G4_B_notx_5_port, mult_125_G4_B_notx_6_port,
mult_125_G4_B_notx_7_port, mult_125_G4_B_notx_8_port,
mult_125_G4_B_notx_9_port, mult_125_G4_B_notx_10_port,
mult_125_G4_B_notx_11_port, mult_125_G4_B_notx_12_port,
mult_125_G4_B_notx_13_port, mult_125_G4_B_notx_14_port,
mult_125_G4_ab_0_1_port, mult_125_G4_ab_0_2_port, mult_125_G4_ab_0_3_port
, mult_125_G4_ab_0_4_port, mult_125_G4_ab_0_5_port,
mult_125_G4_ab_0_6_port, mult_125_G4_ab_0_7_port, mult_125_G4_ab_0_8_port
, mult_125_G4_ab_0_9_port, mult_125_G4_ab_0_10_port,
mult_125_G4_ab_0_11_port, mult_125_G4_ab_0_12_port,
mult_125_G4_ab_0_13_port, mult_125_G4_ab_0_14_port,
mult_125_G4_ab_0_15_port, mult_125_G4_ab_1_0_port,
mult_125_G4_ab_1_1_port, mult_125_G4_ab_1_2_port, mult_125_G4_ab_1_3_port
, mult_125_G4_ab_1_4_port, mult_125_G4_ab_1_5_port,
mult_125_G4_ab_1_6_port, mult_125_G4_ab_1_7_port, mult_125_G4_ab_1_8_port
, mult_125_G4_ab_1_9_port, mult_125_G4_ab_1_10_port,
mult_125_G4_ab_1_11_port, mult_125_G4_ab_1_12_port,
mult_125_G4_ab_1_13_port, mult_125_G4_ab_1_14_port,
mult_125_G4_ab_1_15_port, mult_125_G4_ab_2_0_port,
mult_125_G4_ab_2_1_port, mult_125_G4_ab_2_2_port, mult_125_G4_ab_2_3_port
, mult_125_G4_ab_2_4_port, mult_125_G4_ab_2_5_port,
mult_125_G4_ab_2_6_port, mult_125_G4_ab_2_7_port, mult_125_G4_ab_2_8_port
, mult_125_G4_ab_2_9_port, mult_125_G4_ab_2_10_port,
mult_125_G4_ab_2_11_port, mult_125_G4_ab_2_12_port,
mult_125_G4_ab_2_13_port, mult_125_G4_ab_2_14_port,
mult_125_G4_ab_2_15_port, mult_125_G4_ab_3_0_port,
mult_125_G4_ab_3_1_port, mult_125_G4_ab_3_2_port, mult_125_G4_ab_3_3_port
, mult_125_G4_ab_3_4_port, mult_125_G4_ab_3_5_port,
mult_125_G4_ab_3_6_port, mult_125_G4_ab_3_7_port, mult_125_G4_ab_3_8_port
, mult_125_G4_ab_3_9_port, mult_125_G4_ab_3_10_port,
mult_125_G4_ab_3_11_port, mult_125_G4_ab_3_12_port,
mult_125_G4_ab_3_13_port, mult_125_G4_ab_3_14_port,
mult_125_G4_ab_3_15_port, mult_125_G4_ab_4_0_port,
mult_125_G4_ab_4_1_port, mult_125_G4_ab_4_2_port, mult_125_G4_ab_4_3_port
, mult_125_G4_ab_4_4_port, mult_125_G4_ab_4_5_port,
mult_125_G4_ab_4_6_port, mult_125_G4_ab_4_7_port, mult_125_G4_ab_4_8_port
, mult_125_G4_ab_4_9_port, mult_125_G4_ab_4_10_port,
mult_125_G4_ab_4_11_port, mult_125_G4_ab_4_12_port,
mult_125_G4_ab_4_13_port, mult_125_G4_ab_4_14_port,
mult_125_G4_ab_4_15_port, mult_125_G4_ab_5_0_port,
mult_125_G4_ab_5_1_port, mult_125_G4_ab_5_2_port, mult_125_G4_ab_5_3_port
, mult_125_G4_ab_5_4_port, mult_125_G4_ab_5_5_port,
mult_125_G4_ab_5_6_port, mult_125_G4_ab_5_7_port, mult_125_G4_ab_5_8_port
, mult_125_G4_ab_5_9_port, mult_125_G4_ab_5_10_port,
mult_125_G4_ab_5_11_port, mult_125_G4_ab_5_12_port,
mult_125_G4_ab_5_13_port, mult_125_G4_ab_5_14_port,
mult_125_G4_ab_5_15_port, mult_125_G4_ab_6_0_port,
mult_125_G4_ab_6_1_port, mult_125_G4_ab_6_2_port, mult_125_G4_ab_6_3_port
, mult_125_G4_ab_6_4_port, mult_125_G4_ab_6_5_port,
mult_125_G4_ab_6_6_port, mult_125_G4_ab_6_7_port, mult_125_G4_ab_6_8_port
, mult_125_G4_ab_6_9_port, mult_125_G4_ab_6_10_port,
mult_125_G4_ab_6_11_port, mult_125_G4_ab_6_12_port,
mult_125_G4_ab_6_13_port, mult_125_G4_ab_6_14_port,
mult_125_G4_ab_6_15_port, mult_125_G4_ab_7_0_port,
mult_125_G4_ab_7_1_port, mult_125_G4_ab_7_2_port, mult_125_G4_ab_7_3_port
, mult_125_G4_ab_7_4_port, mult_125_G4_ab_7_5_port,
mult_125_G4_ab_7_6_port, mult_125_G4_ab_7_7_port, mult_125_G4_ab_7_8_port
, mult_125_G4_ab_7_9_port, mult_125_G4_ab_7_10_port,
mult_125_G4_ab_7_11_port, mult_125_G4_ab_7_12_port,
mult_125_G4_ab_7_13_port, mult_125_G4_ab_7_14_port,
mult_125_G4_ab_7_15_port, mult_125_G4_ab_8_0_port,
mult_125_G4_ab_8_1_port, mult_125_G4_ab_8_2_port, mult_125_G4_ab_8_3_port
, mult_125_G4_ab_8_4_port, mult_125_G4_ab_8_5_port,
mult_125_G4_ab_8_6_port, mult_125_G4_ab_8_7_port, mult_125_G4_ab_8_8_port
, mult_125_G4_ab_8_9_port, mult_125_G4_ab_8_10_port,
mult_125_G4_ab_8_11_port, mult_125_G4_ab_8_12_port,
mult_125_G4_ab_8_13_port, mult_125_G4_ab_8_14_port,
mult_125_G4_ab_8_15_port, mult_125_G4_ab_9_0_port,
mult_125_G4_ab_9_1_port, mult_125_G4_ab_9_2_port, mult_125_G4_ab_9_3_port
, mult_125_G4_ab_9_4_port, mult_125_G4_ab_9_5_port,
mult_125_G4_ab_9_6_port, mult_125_G4_ab_9_7_port, mult_125_G4_ab_9_8_port
, mult_125_G4_ab_9_9_port, mult_125_G4_ab_9_10_port,
mult_125_G4_ab_9_11_port, mult_125_G4_ab_9_12_port,
mult_125_G4_ab_9_13_port, mult_125_G4_ab_9_14_port,
mult_125_G4_ab_9_15_port, mult_125_G4_ab_10_0_port,
mult_125_G4_ab_10_1_port, mult_125_G4_ab_10_2_port,
mult_125_G4_ab_10_3_port, mult_125_G4_ab_10_4_port,
mult_125_G4_ab_10_5_port, mult_125_G4_ab_10_6_port,
mult_125_G4_ab_10_7_port, mult_125_G4_ab_10_8_port,
mult_125_G4_ab_10_9_port, mult_125_G4_ab_10_10_port,
mult_125_G4_ab_10_11_port, mult_125_G4_ab_10_12_port,
mult_125_G4_ab_10_13_port, mult_125_G4_ab_10_14_port,
mult_125_G4_ab_10_15_port, mult_125_G4_ab_11_0_port,
mult_125_G4_ab_11_1_port, mult_125_G4_ab_11_2_port,
mult_125_G4_ab_11_3_port, mult_125_G4_ab_11_4_port,
mult_125_G4_ab_11_5_port, mult_125_G4_ab_11_6_port,
mult_125_G4_ab_11_7_port, mult_125_G4_ab_11_8_port,
mult_125_G4_ab_11_9_port, mult_125_G4_ab_11_10_port,
mult_125_G4_ab_11_11_port, mult_125_G4_ab_11_12_port,
mult_125_G4_ab_11_13_port, mult_125_G4_ab_11_14_port,
mult_125_G4_ab_11_15_port, mult_125_G4_ab_12_0_port,
mult_125_G4_ab_12_1_port, mult_125_G4_ab_12_2_port,
mult_125_G4_ab_12_3_port, mult_125_G4_ab_12_4_port,
mult_125_G4_ab_12_5_port, mult_125_G4_ab_12_6_port,
mult_125_G4_ab_12_7_port, mult_125_G4_ab_12_8_port,
mult_125_G4_ab_12_9_port, mult_125_G4_ab_12_10_port,
mult_125_G4_ab_12_11_port, mult_125_G4_ab_12_12_port,
mult_125_G4_ab_12_13_port, mult_125_G4_ab_12_14_port,
mult_125_G4_ab_12_15_port, mult_125_G4_ab_13_0_port,
mult_125_G4_ab_13_1_port, mult_125_G4_ab_13_2_port,
mult_125_G4_ab_13_3_port, mult_125_G4_ab_13_4_port,
mult_125_G4_ab_13_5_port, mult_125_G4_ab_13_6_port,
mult_125_G4_ab_13_7_port, mult_125_G4_ab_13_8_port,
mult_125_G4_ab_13_9_port, mult_125_G4_ab_13_10_port,
mult_125_G4_ab_13_11_port, mult_125_G4_ab_13_12_port,
mult_125_G4_ab_13_13_port, mult_125_G4_ab_13_14_port,
mult_125_G4_ab_13_15_port, mult_125_G4_ab_14_0_port,
mult_125_G4_ab_14_1_port, mult_125_G4_ab_14_2_port,
mult_125_G4_ab_14_3_port, mult_125_G4_ab_14_4_port,
mult_125_G4_ab_14_5_port, mult_125_G4_ab_14_6_port,
mult_125_G4_ab_14_7_port, mult_125_G4_ab_14_8_port,
mult_125_G4_ab_14_9_port, mult_125_G4_ab_14_10_port,
mult_125_G4_ab_14_11_port, mult_125_G4_ab_14_12_port,
mult_125_G4_ab_14_13_port, mult_125_G4_ab_14_14_port,
mult_125_G4_ab_14_15_port, mult_125_G4_ab_15_0_port,
mult_125_G4_ab_15_1_port, mult_125_G4_ab_15_2_port,
mult_125_G4_ab_15_3_port, mult_125_G4_ab_15_4_port,
mult_125_G4_ab_15_5_port, mult_125_G4_ab_15_6_port,
mult_125_G4_ab_15_7_port, mult_125_G4_ab_15_8_port,
mult_125_G4_ab_15_9_port, mult_125_G4_ab_15_10_port,
mult_125_G4_ab_15_11_port, mult_125_G4_ab_15_12_port,
mult_125_G4_ab_15_13_port, mult_125_G4_ab_15_14_port,
mult_125_G4_ab_15_15_port, mult_125_G4_B_not_0_port,
mult_125_G4_B_not_1_port, mult_125_G4_B_not_2_port,
mult_125_G4_B_not_3_port, mult_125_G4_B_not_4_port,
mult_125_G4_B_not_5_port, mult_125_G4_B_not_6_port,
mult_125_G4_B_not_7_port, mult_125_G4_B_not_8_port,
mult_125_G4_B_not_9_port, mult_125_G4_B_not_10_port,
mult_125_G4_B_not_11_port, mult_125_G4_B_not_12_port,
mult_125_G4_B_not_13_port, mult_125_G4_B_not_14_port,
mult_125_G4_B_not_15_port, mult_125_G4_A_not_0_port,
mult_125_G4_A_not_1_port, mult_125_G4_A_not_2_port,
mult_125_G4_A_not_3_port, mult_125_G4_A_not_4_port,
mult_125_G4_A_not_5_port, mult_125_G4_A_not_6_port,
mult_125_G4_A_not_7_port, mult_125_G4_A_not_8_port,
mult_125_G4_A_not_9_port, mult_125_G4_A_not_10_port,
mult_125_G4_A_not_11_port, mult_125_G4_A_not_12_port,
mult_125_G4_A_not_13_port, mult_125_G4_A_not_14_port,
mult_125_G4_A_not_15_port, n240, n241, n242, n243, n244, n245, n246, n247
, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259,
n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319,
n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355,
n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391,
n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451,
n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498, n499,
n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619,
n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751,
n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883,
n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102,
n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112,
n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122,
n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132,
n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142,
n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362,
n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372,
n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012,
n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722,
n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732,
n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742,
n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752,
n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762,
n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772,
n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782,
n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792,
n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802,
n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812,
n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822,
n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832,
n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842,
n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852,
n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862,
n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872,
n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882,
n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892,
n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902,
n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912,
n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922,
n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932,
n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942,
n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952,
n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962,
n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972,
n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982,
n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992,
n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002,
n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012,
n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022,
n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032,
n6033, n6034, n6035 : std_logic;
begin
ready_x_out <= ready_x_out_port;
ready_h_out <= ready_h_out_port;
valid_out <= valid_out_port;
adder_mem_array_reg_3_0_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_0_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_0_port);
adder_mem_array_reg_3_1_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_1_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_1_port);
adder_mem_array_reg_3_2_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_2_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_2_port);
adder_mem_array_reg_3_3_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_3_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_3_port);
adder_mem_array_reg_3_4_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_4_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_4_port);
adder_mem_array_reg_3_5_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_5_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_5_port);
adder_mem_array_reg_3_6_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_6_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_6_port);
adder_mem_array_reg_3_7_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_7_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_7_port);
adder_mem_array_reg_3_8_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_8_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_8_port);
adder_mem_array_reg_3_9_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_9_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_9_port);
adder_mem_array_reg_3_10_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_10_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_10_port);
adder_mem_array_reg_3_11_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_11_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_11_port);
adder_mem_array_reg_3_12_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_12_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_12_port);
adder_mem_array_reg_3_13_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_13_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_13_port);
adder_mem_array_reg_3_14_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_14_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_14_port);
adder_mem_array_reg_3_15_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_15_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_15_port);
adder_mem_array_reg_3_16_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_16_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_16_port);
adder_mem_array_reg_3_17_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_17_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_17_port);
adder_mem_array_reg_3_18_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_18_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_18_port);
adder_mem_array_reg_3_19_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_19_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_19_port);
adder_mem_array_reg_3_20_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_20_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_20_port);
adder_mem_array_reg_3_21_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_21_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_21_port);
adder_mem_array_reg_3_22_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_22_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_22_port);
adder_mem_array_reg_3_23_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_23_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_23_port);
adder_mem_array_reg_3_24_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_24_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_24_port);
adder_mem_array_reg_3_25_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_25_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_25_port);
adder_mem_array_reg_3_26_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_26_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_26_port);
adder_mem_array_reg_3_27_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_27_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_27_port);
adder_mem_array_reg_3_28_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_28_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_28_port);
adder_mem_array_reg_3_29_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_29_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_29_port);
adder_mem_array_reg_3_30_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_30_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_30_port);
adder_mem_array_reg_3_32_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_31_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_32_port);
adder_mem_array_reg_3_31_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_31_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_31_port);
adder_mem_array_reg_2_0_inst : dff_asyncrsthl port map( d => N72, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_0_port);
adder_mem_array_reg_2_1_inst : dff_asyncrsthl port map( d => N73, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_1_port);
adder_mem_array_reg_2_2_inst : dff_asyncrsthl port map( d => N74, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_2_port);
adder_mem_array_reg_2_3_inst : dff_asyncrsthl port map( d => N75, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_3_port);
adder_mem_array_reg_2_4_inst : dff_asyncrsthl port map( d => N76, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_4_port);
adder_mem_array_reg_2_5_inst : dff_asyncrsthl port map( d => N77, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_5_port);
adder_mem_array_reg_2_6_inst : dff_asyncrsthl port map( d => N78, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_6_port);
adder_mem_array_reg_2_7_inst : dff_asyncrsthl port map( d => N79, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_7_port);
adder_mem_array_reg_2_8_inst : dff_asyncrsthl port map( d => N80, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_8_port);
adder_mem_array_reg_2_9_inst : dff_asyncrsthl port map( d => N81, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_9_port);
adder_mem_array_reg_2_10_inst : dff_asyncrsthl port map( d => N82, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_10_port);
adder_mem_array_reg_2_11_inst : dff_asyncrsthl port map( d => N83, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_11_port);
adder_mem_array_reg_2_12_inst : dff_asyncrsthl port map( d => N84, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_12_port);
adder_mem_array_reg_2_13_inst : dff_asyncrsthl port map( d => N85, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_13_port);
adder_mem_array_reg_2_14_inst : dff_asyncrsthl port map( d => N86, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_14_port);
adder_mem_array_reg_2_15_inst : dff_asyncrsthl port map( d => N87, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_15_port);
adder_mem_array_reg_2_16_inst : dff_asyncrsthl port map( d => N88, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_16_port);
adder_mem_array_reg_2_17_inst : dff_asyncrsthl port map( d => N89, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_17_port);
adder_mem_array_reg_2_18_inst : dff_asyncrsthl port map( d => N90, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_18_port);
adder_mem_array_reg_2_19_inst : dff_asyncrsthl port map( d => N91, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_19_port);
adder_mem_array_reg_2_20_inst : dff_asyncrsthl port map( d => N92, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_20_port);
adder_mem_array_reg_2_21_inst : dff_asyncrsthl port map( d => N93, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_21_port);
adder_mem_array_reg_2_22_inst : dff_asyncrsthl port map( d => N94, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_22_port);
adder_mem_array_reg_2_23_inst : dff_asyncrsthl port map( d => N95, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_23_port);
adder_mem_array_reg_2_24_inst : dff_asyncrsthl port map( d => N96, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_24_port);
adder_mem_array_reg_2_25_inst : dff_asyncrsthl port map( d => N97, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_25_port);
adder_mem_array_reg_2_26_inst : dff_asyncrsthl port map( d => N98, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_26_port);
adder_mem_array_reg_2_27_inst : dff_asyncrsthl port map( d => N99, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_27_port);
adder_mem_array_reg_2_28_inst : dff_asyncrsthl port map( d => N100, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_28_port);
adder_mem_array_reg_2_29_inst : dff_asyncrsthl port map( d => N101, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_29_port);
adder_mem_array_reg_2_30_inst : dff_asyncrsthl port map( d => N102, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_30_port);
adder_mem_array_reg_2_31_inst : dff_asyncrsthl port map( d => N103, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_31_port);
adder_mem_array_reg_2_32_inst : dff_asyncrsthl port map( d => N104, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_32_port);
adder_mem_array_reg_1_0_inst : dff_asyncrsthl port map( d => N39, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_0_port);
adder_mem_array_reg_1_1_inst : dff_asyncrsthl port map( d => N40, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_1_port);
adder_mem_array_reg_1_2_inst : dff_asyncrsthl port map( d => N41, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_2_port);
adder_mem_array_reg_1_3_inst : dff_asyncrsthl port map( d => N42, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_3_port);
adder_mem_array_reg_1_4_inst : dff_asyncrsthl port map( d => N43, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_4_port);
adder_mem_array_reg_1_5_inst : dff_asyncrsthl port map( d => N44, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_5_port);
adder_mem_array_reg_1_6_inst : dff_asyncrsthl port map( d => N45, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_6_port);
adder_mem_array_reg_1_7_inst : dff_asyncrsthl port map( d => N46, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_7_port);
adder_mem_array_reg_1_8_inst : dff_asyncrsthl port map( d => N47, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_8_port);
adder_mem_array_reg_1_9_inst : dff_asyncrsthl port map( d => N48, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_9_port);
adder_mem_array_reg_1_10_inst : dff_asyncrsthl port map( d => N49, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_10_port);
adder_mem_array_reg_1_11_inst : dff_asyncrsthl port map( d => N50, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_11_port);
adder_mem_array_reg_1_12_inst : dff_asyncrsthl port map( d => N51, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_12_port);
adder_mem_array_reg_1_13_inst : dff_asyncrsthl port map( d => N52, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_13_port);
adder_mem_array_reg_1_14_inst : dff_asyncrsthl port map( d => N53, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_14_port);
adder_mem_array_reg_1_15_inst : dff_asyncrsthl port map( d => N54, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_15_port);
adder_mem_array_reg_1_16_inst : dff_asyncrsthl port map( d => N55, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_16_port);
adder_mem_array_reg_1_17_inst : dff_asyncrsthl port map( d => N56, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_17_port);
adder_mem_array_reg_1_18_inst : dff_asyncrsthl port map( d => N57, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_18_port);
adder_mem_array_reg_1_19_inst : dff_asyncrsthl port map( d => N58, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_19_port);
adder_mem_array_reg_1_20_inst : dff_asyncrsthl port map( d => N59, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_20_port);
adder_mem_array_reg_1_21_inst : dff_asyncrsthl port map( d => N60, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_21_port);
adder_mem_array_reg_1_22_inst : dff_asyncrsthl port map( d => N61, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_22_port);
adder_mem_array_reg_1_23_inst : dff_asyncrsthl port map( d => N62, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_23_port);
adder_mem_array_reg_1_24_inst : dff_asyncrsthl port map( d => N63, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_24_port);
adder_mem_array_reg_1_25_inst : dff_asyncrsthl port map( d => N64, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_25_port);
adder_mem_array_reg_1_26_inst : dff_asyncrsthl port map( d => N65, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_26_port);
adder_mem_array_reg_1_27_inst : dff_asyncrsthl port map( d => N66, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_27_port);
adder_mem_array_reg_1_28_inst : dff_asyncrsthl port map( d => N67, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_28_port);
adder_mem_array_reg_1_29_inst : dff_asyncrsthl port map( d => N68, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_29_port);
adder_mem_array_reg_1_30_inst : dff_asyncrsthl port map( d => N69, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_30_port);
adder_mem_array_reg_1_31_inst : dff_asyncrsthl port map( d => N70, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_31_port);
adder_mem_array_reg_1_32_inst : dff_asyncrsthl port map( d => N71, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_32_port);
adder_mem_array_reg_0_0_inst : dff_asyncrsthl port map( d => N6, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_0_port);
adder_mem_array_reg_0_1_inst : dff_asyncrsthl port map( d => N7, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_1_port);
adder_mem_array_reg_0_2_inst : dff_asyncrsthl port map( d => N8, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_2_port);
adder_mem_array_reg_0_3_inst : dff_asyncrsthl port map( d => N9, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_3_port);
adder_mem_array_reg_0_4_inst : dff_asyncrsthl port map( d => N10, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_4_port);
adder_mem_array_reg_0_5_inst : dff_asyncrsthl port map( d => N11, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_5_port);
adder_mem_array_reg_0_6_inst : dff_asyncrsthl port map( d => N12, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_6_port);
adder_mem_array_reg_0_7_inst : dff_asyncrsthl port map( d => N13, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_7_port);
adder_mem_array_reg_0_8_inst : dff_asyncrsthl port map( d => N14, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_8_port);
adder_mem_array_reg_0_9_inst : dff_asyncrsthl port map( d => N15, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_9_port);
adder_mem_array_reg_0_10_inst : dff_asyncrsthl port map( d => N16, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_10_port);
adder_mem_array_reg_0_11_inst : dff_asyncrsthl port map( d => N17, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_11_port);
adder_mem_array_reg_0_12_inst : dff_asyncrsthl port map( d => N18, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_12_port);
adder_mem_array_reg_0_13_inst : dff_asyncrsthl port map( d => N19, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_13_port);
adder_mem_array_reg_0_14_inst : dff_asyncrsthl port map( d => N20, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_14_port);
adder_mem_array_reg_0_15_inst : dff_asyncrsthl port map( d => N21, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_15_port);
adder_mem_array_reg_0_16_inst : dff_asyncrsthl port map( d => N22, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_16_port);
adder_mem_array_reg_0_17_inst : dff_asyncrsthl port map( d => N23, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_17_port);
adder_mem_array_reg_0_18_inst : dff_asyncrsthl port map( d => N24, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_18_port);
adder_mem_array_reg_0_19_inst : dff_asyncrsthl port map( d => N25, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_19_port);
adder_mem_array_reg_0_20_inst : dff_asyncrsthl port map( d => N26, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_20_port);
adder_mem_array_reg_0_21_inst : dff_asyncrsthl port map( d => N27, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_21_port);
adder_mem_array_reg_0_22_inst : dff_asyncrsthl port map( d => N28, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_22_port);
adder_mem_array_reg_0_23_inst : dff_asyncrsthl port map( d => N29, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_23_port);
adder_mem_array_reg_0_24_inst : dff_asyncrsthl port map( d => N30, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_24_port);
adder_mem_array_reg_0_25_inst : dff_asyncrsthl port map( d => N31, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_25_port);
adder_mem_array_reg_0_26_inst : dff_asyncrsthl port map( d => N32, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_26_port);
adder_mem_array_reg_0_27_inst : dff_asyncrsthl port map( d => N33, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_27_port);
adder_mem_array_reg_0_28_inst : dff_asyncrsthl port map( d => N34, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_28_port);
adder_mem_array_reg_0_29_inst : dff_asyncrsthl port map( d => N35, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_29_port);
adder_mem_array_reg_0_30_inst : dff_asyncrsthl port map( d => N36, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_30_port);
adder_mem_array_reg_0_31_inst : dff_asyncrsthl port map( d => N37, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_31_port);
adder_mem_array_reg_0_32_inst : dff_asyncrsthl port map( d => N38, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_32_port);
coeff_cnt_reg_0_inst : dff port map( d => n206, gclk => clk, rnot => n121, q
=> coeff_cnt_0_port);
ready_h_out_reg_reg : dff_asyncprehh port map( d => n205, gclk => clk,
asyncprehh => rst, q => ready_h_out_port);
coeff_cnt_reg_1_inst : dff port map( d => n204, gclk => clk, rnot => n121, q
=> coeff_cnt_1_port);
coefficient_mem_array_reg_3_0_inst : dff port map( d => n203, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_0_port);
coefficient_mem_array_reg_2_0_inst : dff port map( d => n202, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_0_port);
coefficient_mem_array_reg_1_0_inst : dff port map( d => n201, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_0_port);
coefficient_mem_array_reg_0_0_inst : dff port map( d => n200, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_0_port);
coefficient_mem_array_reg_3_15_inst : dff port map( d => n199, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_15_port);
coefficient_mem_array_reg_2_15_inst : dff port map( d => n198, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_15_port);
coefficient_mem_array_reg_1_15_inst : dff port map( d => n197, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_15_port);
coefficient_mem_array_reg_0_15_inst : dff port map( d => n196, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_15_port);
coefficient_mem_array_reg_3_14_inst : dff port map( d => n195, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_14_port);
coefficient_mem_array_reg_2_14_inst : dff port map( d => n194, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_14_port);
coefficient_mem_array_reg_1_14_inst : dff port map( d => n193, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_14_port);
coefficient_mem_array_reg_0_14_inst : dff port map( d => n192, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_14_port);
coefficient_mem_array_reg_3_13_inst : dff port map( d => n191, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_13_port);
coefficient_mem_array_reg_2_13_inst : dff port map( d => n190, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_13_port);
coefficient_mem_array_reg_1_13_inst : dff port map( d => n189, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_13_port);
coefficient_mem_array_reg_0_13_inst : dff port map( d => n188, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_13_port);
coefficient_mem_array_reg_3_12_inst : dff port map( d => n187, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_12_port);
coefficient_mem_array_reg_2_12_inst : dff port map( d => n186, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_12_port);
coefficient_mem_array_reg_1_12_inst : dff port map( d => n185, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_12_port);
coefficient_mem_array_reg_0_12_inst : dff port map( d => n184, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_12_port);
coefficient_mem_array_reg_3_11_inst : dff port map( d => n183, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_11_port);
coefficient_mem_array_reg_2_11_inst : dff port map( d => n182, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_11_port);
coefficient_mem_array_reg_1_11_inst : dff port map( d => n181, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_11_port);
coefficient_mem_array_reg_0_11_inst : dff port map( d => n180, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_11_port);
coefficient_mem_array_reg_3_10_inst : dff port map( d => n179, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_10_port);
coefficient_mem_array_reg_2_10_inst : dff port map( d => n178, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_10_port);
coefficient_mem_array_reg_1_10_inst : dff port map( d => n177, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_10_port);
coefficient_mem_array_reg_0_10_inst : dff port map( d => n176, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_10_port);
coefficient_mem_array_reg_3_9_inst : dff port map( d => n175, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_9_port);
coefficient_mem_array_reg_2_9_inst : dff port map( d => n174, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_9_port);
coefficient_mem_array_reg_1_9_inst : dff port map( d => n173, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_9_port);
coefficient_mem_array_reg_0_9_inst : dff port map( d => n172, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_9_port);
coefficient_mem_array_reg_3_8_inst : dff port map( d => n171, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_8_port);
coefficient_mem_array_reg_2_8_inst : dff port map( d => n170, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_8_port);
coefficient_mem_array_reg_1_8_inst : dff port map( d => n169, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_8_port);
coefficient_mem_array_reg_0_8_inst : dff port map( d => n168, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_8_port);
coefficient_mem_array_reg_3_7_inst : dff port map( d => n167, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_7_port);
coefficient_mem_array_reg_2_7_inst : dff port map( d => n166, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_7_port);
coefficient_mem_array_reg_1_7_inst : dff port map( d => n165, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_7_port);
coefficient_mem_array_reg_0_7_inst : dff port map( d => n164, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_7_port);
coefficient_mem_array_reg_3_6_inst : dff port map( d => n163, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_6_port);
coefficient_mem_array_reg_2_6_inst : dff port map( d => n162, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_6_port);
coefficient_mem_array_reg_1_6_inst : dff port map( d => n161, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_6_port);
coefficient_mem_array_reg_0_6_inst : dff port map( d => n160, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_6_port);
coefficient_mem_array_reg_3_5_inst : dff port map( d => n159, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_5_port);
coefficient_mem_array_reg_2_5_inst : dff port map( d => n158, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_5_port);
coefficient_mem_array_reg_1_5_inst : dff port map( d => n157, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_5_port);
coefficient_mem_array_reg_0_5_inst : dff port map( d => n156, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_5_port);
coefficient_mem_array_reg_3_4_inst : dff port map( d => n155, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_4_port);
coefficient_mem_array_reg_2_4_inst : dff port map( d => n154, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_4_port);
coefficient_mem_array_reg_1_4_inst : dff port map( d => n153, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_4_port);
coefficient_mem_array_reg_0_4_inst : dff port map( d => n152, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_4_port);
coefficient_mem_array_reg_3_3_inst : dff port map( d => n151, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_3_port);
coefficient_mem_array_reg_2_3_inst : dff port map( d => n150, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_3_port);
coefficient_mem_array_reg_1_3_inst : dff port map( d => n149, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_3_port);
coefficient_mem_array_reg_0_3_inst : dff port map( d => n148, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_3_port);
coefficient_mem_array_reg_3_2_inst : dff port map( d => n147, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_2_port);
coefficient_mem_array_reg_2_2_inst : dff port map( d => n146, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_2_port);
coefficient_mem_array_reg_1_2_inst : dff port map( d => n145, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_2_port);
coefficient_mem_array_reg_0_2_inst : dff port map( d => n144, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_2_port);
coefficient_mem_array_reg_3_1_inst : dff port map( d => n143, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_1_port);
coefficient_mem_array_reg_2_1_inst : dff port map( d => n142, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_1_port);
coefficient_mem_array_reg_1_1_inst : dff port map( d => n141, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_1_port);
coefficient_mem_array_reg_0_1_inst : dff port map( d => n140, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_1_port);
valid_out_reg_reg : dff port map( d => n139, gclk => clk, rnot => n121, q =>
valid_out_port);
ready_x_out_reg_reg : dff port map( d => n138, gclk => clk, rnot => n121, q
=> ready_x_out_port);
input_sample_mem_reg_0_inst : dff port map( d => n137, gclk => clk, rnot =>
n121, q => input_sample_mem_0_port);
input_sample_mem_reg_15_inst : dff port map( d => n136, gclk => clk, rnot =>
n121, q => input_sample_mem_15_port);
input_sample_mem_reg_14_inst : dff port map( d => n135, gclk => clk, rnot =>
n121, q => input_sample_mem_14_port);
input_sample_mem_reg_13_inst : dff port map( d => n134, gclk => clk, rnot =>
n121, q => input_sample_mem_13_port);
input_sample_mem_reg_12_inst : dff port map( d => n133, gclk => clk, rnot =>
n121, q => input_sample_mem_12_port);
input_sample_mem_reg_11_inst : dff port map( d => n132, gclk => clk, rnot =>
n121, q => input_sample_mem_11_port);
input_sample_mem_reg_10_inst : dff port map( d => n131, gclk => clk, rnot =>
n121, q => input_sample_mem_10_port);
input_sample_mem_reg_9_inst : dff port map( d => n130, gclk => clk, rnot =>
n121, q => input_sample_mem_9_port);
input_sample_mem_reg_8_inst : dff port map( d => n129, gclk => clk, rnot =>
n121, q => input_sample_mem_8_port);
input_sample_mem_reg_7_inst : dff port map( d => n128, gclk => clk, rnot =>
n121, q => input_sample_mem_7_port);
input_sample_mem_reg_6_inst : dff port map( d => n127, gclk => clk, rnot =>
n121, q => input_sample_mem_6_port);
input_sample_mem_reg_5_inst : dff port map( d => n126, gclk => clk, rnot =>
n121, q => input_sample_mem_5_port);
input_sample_mem_reg_4_inst : dff port map( d => n125, gclk => clk, rnot =>
n121, q => input_sample_mem_4_port);
input_sample_mem_reg_3_inst : dff port map( d => n124, gclk => clk, rnot =>
n121, q => input_sample_mem_3_port);
input_sample_mem_reg_2_inst : dff port map( d => n123, gclk => clk, rnot =>
n121, q => input_sample_mem_2_port);
input_sample_mem_reg_1_inst : dff port map( d => n122, gclk => clk, rnot =>
n121, q => input_sample_mem_1_port);
U3 : inv port map( inb => n16_port, outb => n139);
U4 : aoi12 port map( b => coeff_cnt_0_port, c => coeff_cnt_1_port, a =>
valid_out_port, outb => n16_port);
U12 : inv port map( inb => n17_port, outb => n138);
U13 : aoi12 port map( b => coeff_cnt_0_port, c => coeff_cnt_1_port, a =>
ready_x_out_port, outb => n17_port);
U14 : aoi12 port map( b => coeff_cnt_1_port, c => coeff_cnt_0_port, a =>
n18_port, outb => n205);
U15 : inv port map( inb => ready_h_out_port, outb => n18_port);
U16 : inv port map( inb => n19_port, outb => n130);
U17 : aoi22 port map( a => x_data_in(9), b => n20_port, c =>
input_sample_mem_9_port, d => n21_port, outb =>
n19_port);
U18 : inv port map( inb => n22_port, outb => n129);
U19 : aoi22 port map( a => x_data_in(8), b => n20_port, c =>
input_sample_mem_8_port, d => n21_port, outb =>
n22_port);
U20 : inv port map( inb => n23_port, outb => n128);
U21 : aoi22 port map( a => x_data_in(7), b => n20_port, c =>
input_sample_mem_7_port, d => n21_port, outb =>
n23_port);
U22 : inv port map( inb => n24_port, outb => n127);
U23 : aoi22 port map( a => x_data_in(6), b => n20_port, c =>
input_sample_mem_6_port, d => n21_port, outb =>
n24_port);
U24 : inv port map( inb => n25_port, outb => n126);
U25 : aoi22 port map( a => x_data_in(5), b => n20_port, c =>
input_sample_mem_5_port, d => n21_port, outb =>
n25_port);
U26 : inv port map( inb => n26_port, outb => n125);
U27 : aoi22 port map( a => x_data_in(4), b => n20_port, c =>
input_sample_mem_4_port, d => n21_port, outb =>
n26_port);
U28 : inv port map( inb => n27_port, outb => n124);
U29 : aoi22 port map( a => x_data_in(3), b => n20_port, c =>
input_sample_mem_3_port, d => n21_port, outb =>
n27_port);
U30 : inv port map( inb => n28_port, outb => n123);
U31 : aoi22 port map( a => x_data_in(2), b => n20_port, c =>
input_sample_mem_2_port, d => n21_port, outb =>
n28_port);
U32 : inv port map( inb => n29_port, outb => n122);
U33 : aoi22 port map( a => x_data_in(1), b => n20_port, c =>
input_sample_mem_1_port, d => n21_port, outb =>
n29_port);
U34 : inv port map( inb => n30_port, outb => n136);
U35 : aoi22 port map( a => x_data_in(15), b => n20_port, c =>
input_sample_mem_15_port, d => n21_port, outb =>
n30_port);
U36 : inv port map( inb => n31_port, outb => n135);
U37 : aoi22 port map( a => x_data_in(14), b => n20_port, c =>
input_sample_mem_14_port, d => n21_port, outb =>
n31_port);
U38 : inv port map( inb => n32_port, outb => n134);
U39 : aoi22 port map( a => x_data_in(13), b => n20_port, c =>
input_sample_mem_13_port, d => n21_port, outb =>
n32_port);
U40 : inv port map( inb => n33_port, outb => n133);
U41 : aoi22 port map( a => x_data_in(12), b => n20_port, c =>
input_sample_mem_12_port, d => n21_port, outb =>
n33_port);
U42 : inv port map( inb => n34_port, outb => n132);
U43 : aoi22 port map( a => x_data_in(11), b => n20_port, c =>
input_sample_mem_11_port, d => n21_port, outb =>
n34_port);
U44 : inv port map( inb => n35_port, outb => n131);
U45 : aoi22 port map( a => x_data_in(10), b => n20_port, c =>
input_sample_mem_10_port, d => n21_port, outb =>
n35_port);
U46 : inv port map( inb => n36_port, outb => n137);
U47 : aoi22 port map( a => x_data_in(0), b => n20_port, c =>
input_sample_mem_0_port, d => n21_port, outb =>
n36_port);
U48 : inv port map( inb => n21_port, outb => n20_port);
U49 : nand2 port map( a => valid_x_in, b => ready_x_out_port, outb =>
n21_port);
U50 : inv port map( inb => n37_port, outb => n175);
U51 : aoi22 port map( a => n38_port, b => h_data_in(9), c => n39_port, d =>
coefficient_mem_array_3_9_port, outb => n37_port);
U52 : inv port map( inb => n40_port, outb => n171);
U53 : aoi22 port map( a => n38_port, b => h_data_in(8), c => n39_port, d =>
coefficient_mem_array_3_8_port, outb => n40_port);
U54 : inv port map( inb => n41_port, outb => n167);
U55 : aoi22 port map( a => n38_port, b => h_data_in(7), c => n39_port, d =>
coefficient_mem_array_3_7_port, outb => n41_port);
U56 : inv port map( inb => n42_port, outb => n163);
U57 : aoi22 port map( a => n38_port, b => h_data_in(6), c => n39_port, d =>
coefficient_mem_array_3_6_port, outb => n42_port);
U58 : inv port map( inb => n43_port, outb => n159);
U59 : aoi22 port map( a => n38_port, b => h_data_in(5), c => n39_port, d =>
coefficient_mem_array_3_5_port, outb => n43_port);
U60 : inv port map( inb => n44_port, outb => n155);
U61 : aoi22 port map( a => n38_port, b => h_data_in(4), c => n39_port, d =>
coefficient_mem_array_3_4_port, outb => n44_port);
U62 : inv port map( inb => n45_port, outb => n151);
U63 : aoi22 port map( a => n38_port, b => h_data_in(3), c => n39_port, d =>
coefficient_mem_array_3_3_port, outb => n45_port);
U64 : inv port map( inb => n46_port, outb => n147);
U65 : aoi22 port map( a => n38_port, b => h_data_in(2), c => n39_port, d =>
coefficient_mem_array_3_2_port, outb => n46_port);
U66 : inv port map( inb => n47_port, outb => n143);
U67 : aoi22 port map( a => n38_port, b => h_data_in(1), c => n39_port, d =>
coefficient_mem_array_3_1_port, outb => n47_port);
U68 : inv port map( inb => n48_port, outb => n199);
U69 : aoi22 port map( a => n38_port, b => h_data_in(15), c => n39_port, d =>
coefficient_mem_array_3_15_port, outb => n48_port);
U70 : inv port map( inb => n49_port, outb => n195);
U71 : aoi22 port map( a => n38_port, b => h_data_in(14), c => n39_port, d =>
coefficient_mem_array_3_14_port, outb => n49_port);
U72 : inv port map( inb => n50_port, outb => n191);
U73 : aoi22 port map( a => n38_port, b => h_data_in(13), c => n39_port, d =>
coefficient_mem_array_3_13_port, outb => n50_port);
U74 : inv port map( inb => n51_port, outb => n187);
U75 : aoi22 port map( a => n38_port, b => h_data_in(12), c => n39_port, d =>
coefficient_mem_array_3_12_port, outb => n51_port);
U76 : inv port map( inb => n52_port, outb => n183);
U77 : aoi22 port map( a => n38_port, b => h_data_in(11), c => n39_port, d =>
coefficient_mem_array_3_11_port, outb => n52_port);
U78 : inv port map( inb => n53_port, outb => n179);
U79 : aoi22 port map( a => n38_port, b => h_data_in(10), c => n39_port, d =>
coefficient_mem_array_3_10_port, outb => n53_port);
U80 : inv port map( inb => n54_port, outb => n203);
U81 : aoi22 port map( a => n38_port, b => h_data_in(0), c => n39_port, d =>
coefficient_mem_array_3_0_port, outb => n54_port);
U82 : oai22 port map( a => n55_port, b => n39_port, c => n38_port, d =>
n56_port, outb => n174);
U83 : inv port map( inb => coefficient_mem_array_3_9_port, outb => n55_port)
;
U84 : oai22 port map( a => n39_port, b => n57_port, c => n38_port, d =>
n58_port, outb => n170);
U85 : inv port map( inb => coefficient_mem_array_3_8_port, outb => n57_port)
;
U86 : oai22 port map( a => n39_port, b => n59_port, c => n38_port, d =>
n60_port, outb => n166);
U87 : inv port map( inb => coefficient_mem_array_3_7_port, outb => n59_port)
;
U88 : oai22 port map( a => n39_port, b => n61_port, c => n38_port, d =>
n62_port, outb => n162);
U89 : inv port map( inb => coefficient_mem_array_3_6_port, outb => n61_port)
;
U90 : oai22 port map( a => n39_port, b => n63_port, c => n38_port, d =>
n64_port, outb => n158);
U91 : inv port map( inb => coefficient_mem_array_3_5_port, outb => n63_port)
;
U92 : oai22 port map( a => n39_port, b => n65_port, c => n38_port, d =>
n66_port, outb => n154);
U93 : inv port map( inb => coefficient_mem_array_3_4_port, outb => n65_port)
;
U94 : oai22 port map( a => n39_port, b => n67_port, c => n38_port, d =>
n68_port, outb => n150);
U95 : inv port map( inb => coefficient_mem_array_3_3_port, outb => n67_port)
;
U96 : oai22 port map( a => n39_port, b => n69_port, c => n38_port, d =>
n70_port, outb => n146);
U97 : inv port map( inb => coefficient_mem_array_3_2_port, outb => n69_port)
;
U98 : oai22 port map( a => n39_port, b => n71_port, c => n38_port, d =>
n72_port, outb => n142);
U99 : inv port map( inb => coefficient_mem_array_3_1_port, outb => n71_port)
;
U100 : oai22 port map( a => n39_port, b => n73_port, c => n38_port, d =>
n74_port, outb => n198);
U101 : inv port map( inb => coefficient_mem_array_3_15_port, outb =>
n73_port);
U102 : oai22 port map( a => n39_port, b => n75_port, c => n38_port, d =>
n76_port, outb => n194);
U103 : inv port map( inb => coefficient_mem_array_3_14_port, outb =>
n75_port);
U104 : oai22 port map( a => n39_port, b => n77_port, c => n38_port, d =>
n78_port, outb => n190);
U105 : inv port map( inb => coefficient_mem_array_3_13_port, outb =>
n77_port);
U106 : oai22 port map( a => n39_port, b => n79_port, c => n38_port, d =>
n80_port, outb => n186);
U107 : inv port map( inb => coefficient_mem_array_3_12_port, outb =>
n79_port);
U108 : oai22 port map( a => n39_port, b => n81_port, c => n38_port, d =>
n82_port, outb => n182);
U109 : inv port map( inb => coefficient_mem_array_3_11_port, outb =>
n81_port);
U110 : oai22 port map( a => n39_port, b => n83_port, c => n38_port, d =>
n84_port, outb => n178);
U111 : inv port map( inb => coefficient_mem_array_3_10_port, outb =>
n83_port);
U112 : oai22 port map( a => n39_port, b => n85_port, c => n38_port, d =>
n86_port, outb => n202);
U113 : inv port map( inb => coefficient_mem_array_3_0_port, outb => n85_port
);
U114 : oai22 port map( a => n39_port, b => n56_port, c => n38_port, d =>
n87_port, outb => n173);
U115 : inv port map( inb => coefficient_mem_array_2_9_port, outb => n56_port
);
U116 : oai22 port map( a => n39_port, b => n58_port, c => n38_port, d =>
n88_port, outb => n169);
U117 : inv port map( inb => coefficient_mem_array_2_8_port, outb => n58_port
);
U118 : oai22 port map( a => n39_port, b => n60_port, c => n38_port, d =>
n89_port, outb => n165);
U119 : inv port map( inb => coefficient_mem_array_2_7_port, outb => n60_port
);
U120 : oai22 port map( a => n39_port, b => n62_port, c => n38_port, d =>
n90_port, outb => n161);
U121 : inv port map( inb => coefficient_mem_array_2_6_port, outb => n62_port
);
U122 : oai22 port map( a => n39_port, b => n64_port, c => n38_port, d =>
n91_port, outb => n157);
U123 : inv port map( inb => coefficient_mem_array_2_5_port, outb => n64_port
);
U124 : oai22 port map( a => n39_port, b => n66_port, c => n38_port, d =>
n92_port, outb => n153);
U125 : inv port map( inb => coefficient_mem_array_2_4_port, outb => n66_port
);
U126 : oai22 port map( a => n39_port, b => n68_port, c => n38_port, d =>
n93_port, outb => n149);
U127 : inv port map( inb => coefficient_mem_array_2_3_port, outb => n68_port
);
U128 : oai22 port map( a => n39_port, b => n70_port, c => n38_port, d =>
n94_port, outb => n145);
U129 : inv port map( inb => coefficient_mem_array_2_2_port, outb => n70_port
);
U130 : oai22 port map( a => n39_port, b => n72_port, c => n38_port, d =>
n95_port, outb => n141);
U131 : inv port map( inb => coefficient_mem_array_2_1_port, outb => n72_port
);
U132 : oai22 port map( a => n39_port, b => n74_port, c => n38_port, d =>
n96_port, outb => n197);
U133 : inv port map( inb => coefficient_mem_array_2_15_port, outb =>
n74_port);
U134 : oai22 port map( a => n39_port, b => n76_port, c => n38_port, d =>
n97_port, outb => n193);
U135 : inv port map( inb => coefficient_mem_array_2_14_port, outb =>
n76_port);
U136 : oai22 port map( a => n39_port, b => n78_port, c => n38_port, d =>
n98_port, outb => n189);
U137 : inv port map( inb => coefficient_mem_array_2_13_port, outb =>
n78_port);
U138 : oai22 port map( a => n39_port, b => n80_port, c => n38_port, d =>
n99_port, outb => n185);
U139 : inv port map( inb => coefficient_mem_array_2_12_port, outb =>
n80_port);
U140 : oai22 port map( a => n39_port, b => n82_port, c => n38_port, d =>
n100_port, outb => n181);
U141 : inv port map( inb => coefficient_mem_array_2_11_port, outb =>
n82_port);
U142 : oai22 port map( a => n39_port, b => n84_port, c => n38_port, d =>
n101_port, outb => n177);
U143 : inv port map( inb => coefficient_mem_array_2_10_port, outb =>
n84_port);
U144 : oai22 port map( a => n39_port, b => n86_port, c => n38_port, d =>
n102_port, outb => n201);
U145 : inv port map( inb => coefficient_mem_array_2_0_port, outb => n86_port
);
U146 : oai12 port map( b => n39_port, c => n87_port, a => n103_port, outb =>
n172);
U147 : nand2 port map( a => coefficient_mem_array_0_9_port, b => n39_port,
outb => n103_port);
U148 : inv port map( inb => coefficient_mem_array_1_9_port, outb => n87_port
);
U149 : oai12 port map( b => n39_port, c => n88_port, a => n104_port, outb =>
n168);
U150 : nand2 port map( a => coefficient_mem_array_0_8_port, b => n39_port,
outb => n104_port);
U151 : inv port map( inb => coefficient_mem_array_1_8_port, outb => n88_port
);
U152 : oai12 port map( b => n39_port, c => n89_port, a => n105, outb => n164
);
U153 : nand2 port map( a => coefficient_mem_array_0_7_port, b => n39_port,
outb => n105);
U154 : inv port map( inb => coefficient_mem_array_1_7_port, outb => n89_port
);
U155 : oai12 port map( b => n39_port, c => n90_port, a => n106, outb => n160
);
U156 : nand2 port map( a => coefficient_mem_array_0_6_port, b => n39_port,
outb => n106);
U157 : inv port map( inb => coefficient_mem_array_1_6_port, outb => n90_port
);
U158 : oai12 port map( b => n39_port, c => n91_port, a => n107, outb => n156
);
U159 : nand2 port map( a => coefficient_mem_array_0_5_port, b => n39_port,
outb => n107);
U160 : inv port map( inb => coefficient_mem_array_1_5_port, outb => n91_port
);
U161 : oai12 port map( b => n39_port, c => n92_port, a => n108, outb => n152
);
U162 : nand2 port map( a => coefficient_mem_array_0_4_port, b => n39_port,
outb => n108);
U163 : inv port map( inb => coefficient_mem_array_1_4_port, outb => n92_port
);
U164 : oai12 port map( b => n39_port, c => n93_port, a => n109, outb => n148
);
U165 : nand2 port map( a => coefficient_mem_array_0_3_port, b => n39_port,
outb => n109);
U166 : inv port map( inb => coefficient_mem_array_1_3_port, outb => n93_port
);
U167 : oai12 port map( b => n39_port, c => n94_port, a => n110, outb => n144
);
U168 : nand2 port map( a => coefficient_mem_array_0_2_port, b => n39_port,
outb => n110);
U169 : inv port map( inb => coefficient_mem_array_1_2_port, outb => n94_port
);
U170 : oai12 port map( b => n39_port, c => n95_port, a => n111, outb => n140
);
U171 : nand2 port map( a => coefficient_mem_array_0_1_port, b => n39_port,
outb => n111);
U172 : inv port map( inb => coefficient_mem_array_1_1_port, outb => n95_port
);
U173 : oai12 port map( b => n39_port, c => n96_port, a => n112, outb => n196
);
U174 : nand2 port map( a => coefficient_mem_array_0_15_port, b => n39_port,
outb => n112);
U175 : inv port map( inb => coefficient_mem_array_1_15_port, outb =>
n96_port);
U176 : oai12 port map( b => n39_port, c => n97_port, a => n113, outb => n192
);
U177 : nand2 port map( a => coefficient_mem_array_0_14_port, b => n39_port,
outb => n113);
U178 : inv port map( inb => coefficient_mem_array_1_14_port, outb =>
n97_port);
U179 : oai12 port map( b => n39_port, c => n98_port, a => n114, outb => n188
);
U180 : nand2 port map( a => coefficient_mem_array_0_13_port, b => n39_port,
outb => n114);
U181 : inv port map( inb => coefficient_mem_array_1_13_port, outb =>
n98_port);
U182 : oai12 port map( b => n39_port, c => n99_port, a => n115, outb => n184
);
U183 : nand2 port map( a => coefficient_mem_array_0_12_port, b => n39_port,
outb => n115);
U184 : inv port map( inb => coefficient_mem_array_1_12_port, outb =>
n99_port);
U185 : oai12 port map( b => n39_port, c => n100_port, a => n116, outb =>
n180);
U186 : nand2 port map( a => coefficient_mem_array_0_11_port, b => n39_port,
outb => n116);
U187 : inv port map( inb => coefficient_mem_array_1_11_port, outb =>
n100_port);
U188 : oai12 port map( b => n39_port, c => n101_port, a => n117, outb =>
n176);
U189 : nand2 port map( a => coefficient_mem_array_0_10_port, b => n39_port,
outb => n117);
U190 : inv port map( inb => coefficient_mem_array_1_10_port, outb =>
n101_port);
U191 : oai12 port map( b => n39_port, c => n102_port, a => n118, outb =>
n200);
U192 : nand2 port map( a => coefficient_mem_array_0_0_port, b => n39_port,
outb => n118);
U193 : inv port map( inb => coefficient_mem_array_1_0_port, outb =>
n102_port);
U194 : xor2 port map( a => n119, b => n120, outb => n204);
U195 : nand2 port map( a => coeff_cnt_0_port, b => n38_port, outb => n120);
U196 : inv port map( inb => coeff_cnt_1_port, outb => n119);
U197 : inv port map( inb => rst, outb => n121);
U198 : xor2 port map( a => coeff_cnt_0_port, b => n38_port, outb => n206);
U199 : inv port map( inb => n39_port, outb => n38_port);
U200 : nand2 port map( a => valid_h_in, b => ready_h_out_port, outb =>
n39_port);
U201 : inv port map( inb => n207, outb => y_data_out(9));
U202 : nand2 port map( a => valid_out_port, b => adder_mem_array_0_9_port,
outb => n207);
U203 : inv port map( inb => n208, outb => y_data_out(8));
U204 : nand2 port map( a => adder_mem_array_0_8_port, b => valid_out_port,
outb => n208);
U205 : inv port map( inb => n209, outb => y_data_out(7));
U206 : nand2 port map( a => adder_mem_array_0_7_port, b => valid_out_port,
outb => n209);
U207 : inv port map( inb => n210, outb => y_data_out(6));
U208 : nand2 port map( a => adder_mem_array_0_6_port, b => valid_out_port,
outb => n210);
U209 : inv port map( inb => n211, outb => y_data_out(5));
U210 : nand2 port map( a => adder_mem_array_0_5_port, b => valid_out_port,
outb => n211);
U211 : inv port map( inb => n212, outb => y_data_out(4));
U212 : nand2 port map( a => adder_mem_array_0_4_port, b => valid_out_port,
outb => n212);
U213 : inv port map( inb => n213, outb => y_data_out(3));
U214 : nand2 port map( a => adder_mem_array_0_3_port, b => valid_out_port,
outb => n213);
U215 : inv port map( inb => n214, outb => y_data_out(32));
U216 : nand2 port map( a => adder_mem_array_0_32_port, b => valid_out_port,
outb => n214);
U217 : inv port map( inb => n215, outb => y_data_out(31));
U218 : nand2 port map( a => adder_mem_array_0_31_port, b => valid_out_port,
outb => n215);
U219 : inv port map( inb => n216, outb => y_data_out(30));
U220 : nand2 port map( a => adder_mem_array_0_30_port, b => valid_out_port,
outb => n216);
U221 : inv port map( inb => n217, outb => y_data_out(2));
U222 : nand2 port map( a => adder_mem_array_0_2_port, b => valid_out_port,
outb => n217);
U223 : inv port map( inb => n218, outb => y_data_out(29));
U224 : nand2 port map( a => adder_mem_array_0_29_port, b => valid_out_port,
outb => n218);
U225 : inv port map( inb => n219, outb => y_data_out(28));
U226 : nand2 port map( a => adder_mem_array_0_28_port, b => valid_out_port,
outb => n219);
U227 : inv port map( inb => n220, outb => y_data_out(27));
U228 : nand2 port map( a => adder_mem_array_0_27_port, b => valid_out_port,
outb => n220);
U229 : inv port map( inb => n221, outb => y_data_out(26));
U230 : nand2 port map( a => adder_mem_array_0_26_port, b => valid_out_port,
outb => n221);
U231 : inv port map( inb => n222, outb => y_data_out(25));
U232 : nand2 port map( a => adder_mem_array_0_25_port, b => valid_out_port,
outb => n222);
U233 : inv port map( inb => n223, outb => y_data_out(24));
U234 : nand2 port map( a => adder_mem_array_0_24_port, b => valid_out_port,
outb => n223);
U235 : inv port map( inb => n224, outb => y_data_out(23));
U236 : nand2 port map( a => adder_mem_array_0_23_port, b => valid_out_port,
outb => n224);
U237 : inv port map( inb => n225, outb => y_data_out(22));
U238 : nand2 port map( a => adder_mem_array_0_22_port, b => valid_out_port,
outb => n225);
U239 : inv port map( inb => n226, outb => y_data_out(21));
U240 : nand2 port map( a => adder_mem_array_0_21_port, b => valid_out_port,
outb => n226);
U241 : inv port map( inb => n227, outb => y_data_out(20));
U242 : nand2 port map( a => adder_mem_array_0_20_port, b => valid_out_port,
outb => n227);
U243 : inv port map( inb => n228, outb => y_data_out(1));
U244 : nand2 port map( a => adder_mem_array_0_1_port, b => valid_out_port,
outb => n228);
U245 : inv port map( inb => n229, outb => y_data_out(19));
U246 : nand2 port map( a => adder_mem_array_0_19_port, b => valid_out_port,
outb => n229);
U247 : inv port map( inb => n230, outb => y_data_out(18));
U248 : nand2 port map( a => adder_mem_array_0_18_port, b => valid_out_port,
outb => n230);
U249 : inv port map( inb => n231, outb => y_data_out(17));
U250 : nand2 port map( a => adder_mem_array_0_17_port, b => valid_out_port,
outb => n231);
U251 : inv port map( inb => n232, outb => y_data_out(16));
U252 : nand2 port map( a => adder_mem_array_0_16_port, b => valid_out_port,
outb => n232);
U253 : inv port map( inb => n233, outb => y_data_out(15));
U254 : nand2 port map( a => adder_mem_array_0_15_port, b => valid_out_port,
outb => n233);
U255 : inv port map( inb => n234, outb => y_data_out(14));
U256 : nand2 port map( a => adder_mem_array_0_14_port, b => valid_out_port,
outb => n234);
U257 : inv port map( inb => n235, outb => y_data_out(13));
U258 : nand2 port map( a => adder_mem_array_0_13_port, b => valid_out_port,
outb => n235);
U259 : inv port map( inb => n236, outb => y_data_out(12));
U260 : nand2 port map( a => adder_mem_array_0_12_port, b => valid_out_port,
outb => n236);
U261 : inv port map( inb => n237, outb => y_data_out(11));
U262 : nand2 port map( a => adder_mem_array_0_11_port, b => valid_out_port,
outb => n237);
U263 : inv port map( inb => n238, outb => y_data_out(10));
U264 : nand2 port map( a => adder_mem_array_0_10_port, b => valid_out_port,
outb => n238);
U265 : inv port map( inb => n239, outb => y_data_out(0));
U266 : nand2 port map( a => adder_mem_array_0_0_port, b => valid_out_port,
outb => n239);
mult_125_G3_FS_1_U6_1_1_3 : oai12 port map( b => n6032, c => n6033, a =>
n6034, outb => mult_125_G3_FS_1_C_1_7_0_port);
mult_125_G3_FS_1_U6_1_1_2 : oai12 port map( b => n6029, c => n6030, a =>
n6031, outb => mult_125_G3_FS_1_C_1_6_0_port);
mult_125_G3_FS_1_U6_1_1_1 : oai12 port map( b => n6026, c => n6027, a =>
n6028, outb => mult_125_G3_FS_1_C_1_5_0_port);
mult_125_G3_FS_1_U6_0_7_1 : oai12 port map( b => n6023, c => n6024, a =>
mult_125_G3_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_G3_FS_1_C_1_7_1_port);
mult_125_G3_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_7_1_port, b =>
mult_125_G3_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_2_31_port);
mult_125_G3_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_7_1_port, b =>
mult_125_G3_FS_1_P_0_7_1_port, outb => n6022);
mult_125_G3_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_G3_A1_29_port, b
=> mult_125_G3_A2_29_port, outb =>
mult_125_G3_FS_1_G_n_int_0_7_1_port);
mult_125_G3_FS_1_U1_0_7_1 : nand2 port map( a => n6020, b => n6021, outb =>
mult_125_G3_FS_1_P_0_7_1_port);
mult_125_G3_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_7_0_port, b =>
mult_125_G3_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_2_30_port);
mult_125_G3_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_7_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_7_0_port, outb => n6019);
mult_125_G3_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_G3_A1_28_port, b
=> mult_125_G3_A2_28_port, outb =>
mult_125_G3_FS_1_G_n_int_0_7_0_port);
mult_125_G3_FS_1_U1_0_7_0 : nand2 port map( a => n6017, b => n6018, outb =>
mult_125_G3_FS_1_TEMP_P_0_7_0_port);
mult_125_G3_FS_1_U6_0_6_3 : oai12 port map( b => n6015, c => n6016, a =>
mult_125_G3_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G3_FS_1_C_1_6_3_port);
mult_125_G3_FS_1_U5_0_6_3 : oai12 port map( b => n6013, c => n6014, a =>
mult_125_G3_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_G3_FS_1_G_1_1_2_port);
mult_125_G3_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_G3_FS_1_P_0_6_3_port, outb => n6033);
mult_125_G3_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_3_port, b =>
mult_125_G3_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_2_29_port);
mult_125_G3_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_3_port, b =>
mult_125_G3_FS_1_P_0_6_3_port, outb => n6012);
mult_125_G3_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_G3_A1_27_port, b
=> mult_125_G3_A2_27_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_3_port);
mult_125_G3_FS_1_U1_0_6_3 : nand2 port map( a => n6010, b => n6011, outb =>
mult_125_G3_FS_1_P_0_6_3_port);
mult_125_G3_FS_1_U6_0_6_2 : oai12 port map( b => n6008, c => n6009, a =>
mult_125_G3_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G3_FS_1_C_1_6_2_port);
mult_125_G3_FS_1_U5_0_6_2 : oai12 port map( b => n6007, c => n6016, a =>
mult_125_G3_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_6_2_port);
mult_125_G3_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_G3_FS_1_P_0_6_2_port, outb => n6006);
mult_125_G3_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_2_port, b =>
mult_125_G3_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_2_28_port);
mult_125_G3_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_2_port, b =>
mult_125_G3_FS_1_P_0_6_2_port, outb => n6005);
mult_125_G3_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_G3_A1_26_port, b
=> mult_125_G3_A2_26_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_2_port);
mult_125_G3_FS_1_U1_0_6_2 : nand2 port map( a => n6003, b => n6004, outb =>
mult_125_G3_FS_1_P_0_6_2_port);
mult_125_G3_FS_1_U6_0_6_1 : oai12 port map( b => n6032, c => n6002, a =>
mult_125_G3_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_G3_FS_1_C_1_6_1_port);
mult_125_G3_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_G3_FS_1_G_n_int_0_6_0_port, c => n6009, a
=> mult_125_G3_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_6_1_port);
mult_125_G3_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_G3_FS_1_P_0_6_1_port, outb => n6001);
mult_125_G3_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_1_port, b =>
mult_125_G3_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_2_27_port);
mult_125_G3_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_1_port, b =>
mult_125_G3_FS_1_P_0_6_1_port, outb => n6000);
mult_125_G3_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_G3_A1_25_port, b
=> mult_125_G3_A2_25_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_1_port);
mult_125_G3_FS_1_U1_0_6_1 : nand2 port map( a => n5998, b => n5999, outb =>
mult_125_G3_FS_1_P_0_6_1_port);
mult_125_G3_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_0_port, b =>
mult_125_G3_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_2_26_port);
mult_125_G3_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_6_0_port, outb => n5997);
mult_125_G3_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_G3_A1_24_port, b
=> mult_125_G3_A2_24_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_0_port);
mult_125_G3_FS_1_U1_0_6_0 : nand2 port map( a => n5995, b => n5996, outb =>
mult_125_G3_FS_1_TEMP_P_0_6_0_port);
mult_125_G3_FS_1_U6_0_5_3 : oai12 port map( b => n5993, c => n5994, a =>
mult_125_G3_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G3_FS_1_C_1_5_3_port);
mult_125_G3_FS_1_U5_0_5_3 : oai12 port map( b => n5991, c => n5992, a =>
mult_125_G3_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_G3_FS_1_G_1_1_1_port);
mult_125_G3_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_G3_FS_1_P_0_5_3_port, outb => n6030);
mult_125_G3_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_3_port, b =>
mult_125_G3_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_2_25_port);
mult_125_G3_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_3_port, b =>
mult_125_G3_FS_1_P_0_5_3_port, outb => n5990);
mult_125_G3_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_G3_A1_23_port, b
=> mult_125_G3_A2_23_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_3_port);
mult_125_G3_FS_1_U1_0_5_3 : nand2 port map( a => n5988, b => n5989, outb =>
mult_125_G3_FS_1_P_0_5_3_port);
mult_125_G3_FS_1_U6_0_5_2 : oai12 port map( b => n5986, c => n5987, a =>
mult_125_G3_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G3_FS_1_C_1_5_2_port);
mult_125_G3_FS_1_U5_0_5_2 : oai12 port map( b => n5985, c => n5994, a =>
mult_125_G3_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_5_2_port);
mult_125_G3_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_G3_FS_1_P_0_5_2_port, outb => n5984);
mult_125_G3_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_2_port, b =>
mult_125_G3_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_2_24_port);
mult_125_G3_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_2_port, b =>
mult_125_G3_FS_1_P_0_5_2_port, outb => n5983);
mult_125_G3_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_G3_A1_22_port, b
=> mult_125_G3_A2_22_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_2_port);
mult_125_G3_FS_1_U1_0_5_2 : nand2 port map( a => n5981, b => n5982, outb =>
mult_125_G3_FS_1_P_0_5_2_port);
mult_125_G3_FS_1_U6_0_5_1 : oai12 port map( b => n6029, c => n5980, a =>
mult_125_G3_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_G3_FS_1_C_1_5_1_port);
mult_125_G3_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_G3_FS_1_G_n_int_0_5_0_port, c => n5987, a
=> mult_125_G3_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_5_1_port);
mult_125_G3_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_G3_FS_1_P_0_5_1_port, outb => n5979);
mult_125_G3_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_1_port, b =>
mult_125_G3_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_2_23_port);
mult_125_G3_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_1_port, b =>
mult_125_G3_FS_1_P_0_5_1_port, outb => n5978);
mult_125_G3_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_G3_A1_21_port, b
=> mult_125_G3_A2_21_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_1_port);
mult_125_G3_FS_1_U1_0_5_1 : nand2 port map( a => n5976, b => n5977, outb =>
mult_125_G3_FS_1_P_0_5_1_port);
mult_125_G3_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_0_port, b =>
mult_125_G3_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_2_22_port);
mult_125_G3_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_5_0_port, outb => n5975);
mult_125_G3_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_G3_A1_20_port, b
=> mult_125_G3_A2_20_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_0_port);
mult_125_G3_FS_1_U1_0_5_0 : nand2 port map( a => n5973, b => n5974, outb =>
mult_125_G3_FS_1_TEMP_P_0_5_0_port);
mult_125_G3_FS_1_U6_0_4_3 : oai12 port map( b => n5971, c => n5972, a =>
mult_125_G3_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G3_FS_1_C_1_4_3_port);
mult_125_G3_FS_1_U5_0_4_3 : oai12 port map( b => n5969, c => n5970, a =>
mult_125_G3_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_G3_FS_1_G_1_1_0_port);
mult_125_G3_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_G3_FS_1_P_0_4_3_port, outb => n6027);
mult_125_G3_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_3_port, b =>
mult_125_G3_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_2_21_port);
mult_125_G3_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_3_port, b =>
mult_125_G3_FS_1_P_0_4_3_port, outb => n5968);
mult_125_G3_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_G3_A1_19_port, b
=> mult_125_G3_A2_19_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_3_port);
mult_125_G3_FS_1_U1_0_4_3 : nand2 port map( a => n5966, b => n5967, outb =>
mult_125_G3_FS_1_P_0_4_3_port);
mult_125_G3_FS_1_U6_0_4_2 : oai12 port map( b => n5964, c => n5965, a =>
mult_125_G3_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G3_FS_1_C_1_4_2_port);
mult_125_G3_FS_1_U5_0_4_2 : oai12 port map( b => n5963, c => n5972, a =>
mult_125_G3_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_4_2_port);
mult_125_G3_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_G3_FS_1_P_0_4_2_port, outb => n5962);
mult_125_G3_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_2_port, b =>
mult_125_G3_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_2_20_port);
mult_125_G3_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_2_port, b =>
mult_125_G3_FS_1_P_0_4_2_port, outb => n5961);
mult_125_G3_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_G3_A1_18_port, b
=> mult_125_G3_A2_18_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_2_port);
mult_125_G3_FS_1_U1_0_4_2 : nand2 port map( a => n5959, b => n5960, outb =>
mult_125_G3_FS_1_P_0_4_2_port);
mult_125_G3_FS_1_U6_0_4_1 : oai12 port map( b => n6026, c => n5958, a =>
mult_125_G3_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_G3_FS_1_C_1_4_1_port);
mult_125_G3_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_G3_FS_1_G_n_int_0_4_0_port, c => n5965, a
=> mult_125_G3_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_4_1_port);
mult_125_G3_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_G3_FS_1_P_0_4_1_port, outb => n5957);
mult_125_G3_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_1_port, b =>
mult_125_G3_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_2_19_port);
mult_125_G3_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_1_port, b =>
mult_125_G3_FS_1_P_0_4_1_port, outb => n5956);
mult_125_G3_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_G3_A1_17_port, b
=> mult_125_G3_A2_17_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_1_port);
mult_125_G3_FS_1_U1_0_4_1 : nand2 port map( a => n5954, b => n5955, outb =>
mult_125_G3_FS_1_P_0_4_1_port);
mult_125_G3_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_0_port, b =>
mult_125_G3_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_2_18_port);
mult_125_G3_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_4_0_port, outb => n5953);
mult_125_G3_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_G3_A1_16_port, b
=> mult_125_G3_A2_16_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_0_port);
mult_125_G3_FS_1_U1_0_4_0 : nand2 port map( a => n5951, b => n5952, outb =>
mult_125_G3_FS_1_TEMP_P_0_4_0_port);
mult_125_G3_FS_1_U5_0_3_3 : oai12 port map( b => n5949, c => n5950, a =>
mult_125_G3_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_G3_FS_1_G_1_0_3_port);
mult_125_G3_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_3_3_port, b =>
mult_125_G3_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_2_17_port);
mult_125_G3_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_3_3_port, b =>
mult_125_G3_FS_1_P_0_3_3_port, outb => n5948);
mult_125_G3_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_G3_A1_15_port, b
=> mult_125_G3_A2_15_port, outb =>
mult_125_G3_FS_1_G_n_int_0_3_3_port);
mult_125_G3_FS_1_U1_0_3_3 : nand2 port map( a => n5946, b => n5947, outb =>
mult_125_G3_FS_1_P_0_3_3_port);
mult_125_G3_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_3_2_port, b =>
mult_125_G3_FS_1_P_0_3_2_port, outb => n5945);
mult_125_G3_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_G3_A1_14_port, b
=> mult_125_G3_A2_14_port, outb =>
mult_125_G3_FS_1_G_n_int_0_3_2_port);
mult_125_G3_FS_1_U1_0_3_2 : nand2 port map( a => n5943, b => n5944, outb =>
mult_125_G3_FS_1_P_0_3_2_port);
mult_125_G3_AN1_15 : inv port map( inb => coefficient_mem_array_2_15_port,
outb => mult_125_G3_A_not_15_port);
mult_125_G3_AN1_14 : inv port map( inb => coefficient_mem_array_2_14_port,
outb => mult_125_G3_A_not_14_port);
mult_125_G3_AN1_13 : inv port map( inb => coefficient_mem_array_2_13_port,
outb => mult_125_G3_A_not_13_port);
mult_125_G3_AN1_12 : inv port map( inb => coefficient_mem_array_2_12_port,
outb => mult_125_G3_A_not_12_port);
mult_125_G3_AN1_11 : inv port map( inb => coefficient_mem_array_2_11_port,
outb => mult_125_G3_A_not_11_port);
mult_125_G3_AN1_10 : inv port map( inb => coefficient_mem_array_2_10_port,
outb => mult_125_G3_A_not_10_port);
mult_125_G3_AN1_9 : inv port map( inb => coefficient_mem_array_2_9_port,
outb => mult_125_G3_A_not_9_port);
mult_125_G3_AN1_8 : inv port map( inb => coefficient_mem_array_2_8_port,
outb => mult_125_G3_A_not_8_port);
mult_125_G3_AN1_7 : inv port map( inb => coefficient_mem_array_2_7_port,
outb => mult_125_G3_A_not_7_port);
mult_125_G3_AN1_6 : inv port map( inb => coefficient_mem_array_2_6_port,
outb => mult_125_G3_A_not_6_port);
mult_125_G3_AN1_5 : inv port map( inb => coefficient_mem_array_2_5_port,
outb => mult_125_G3_A_not_5_port);
mult_125_G3_AN1_4 : inv port map( inb => coefficient_mem_array_2_4_port,
outb => mult_125_G3_A_not_4_port);
mult_125_G3_AN1_3 : inv port map( inb => coefficient_mem_array_2_3_port,
outb => mult_125_G3_A_not_3_port);
mult_125_G3_AN1_2 : inv port map( inb => coefficient_mem_array_2_2_port,
outb => mult_125_G3_A_not_2_port);
mult_125_G3_AN1_1 : inv port map( inb => coefficient_mem_array_2_1_port,
outb => mult_125_G3_A_not_1_port);
mult_125_G3_AN1_0 : inv port map( inb => coefficient_mem_array_2_0_port,
outb => mult_125_G3_A_not_0_port);
mult_125_G3_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb
=> mult_125_G3_B_not_15_port);
mult_125_G3_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb
=> mult_125_G3_B_not_14_port);
mult_125_G3_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb
=> mult_125_G3_B_not_13_port);
mult_125_G3_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb
=> mult_125_G3_B_not_12_port);
mult_125_G3_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb
=> mult_125_G3_B_not_11_port);
mult_125_G3_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb
=> mult_125_G3_B_not_10_port);
mult_125_G3_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_G3_B_not_9_port);
mult_125_G3_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_G3_B_not_8_port);
mult_125_G3_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_G3_B_not_7_port);
mult_125_G3_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_G3_B_not_6_port);
mult_125_G3_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_G3_B_not_5_port);
mult_125_G3_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_G3_B_not_4_port);
mult_125_G3_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_G3_B_not_3_port);
mult_125_G3_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_G3_B_not_2_port);
mult_125_G3_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_G3_B_not_1_port);
mult_125_G3_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_G3_B_not_0_port);
mult_125_G3_AN1_15_15 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_15_15_port);
mult_125_G3_AN3_15_14 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_14_port, outb =>
mult_125_G3_ab_15_14_port);
mult_125_G3_AN3_15_13 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_13_port, outb =>
mult_125_G3_ab_15_13_port);
mult_125_G3_AN3_15_12 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_12_port, outb =>
mult_125_G3_ab_15_12_port);
mult_125_G3_AN3_15_11 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_11_port, outb =>
mult_125_G3_ab_15_11_port);
mult_125_G3_AN3_15_10 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_10_port, outb =>
mult_125_G3_ab_15_10_port);
mult_125_G3_AN3_15_9 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_9_port, outb =>
mult_125_G3_ab_15_9_port);
mult_125_G3_AN3_15_8 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_8_port, outb =>
mult_125_G3_ab_15_8_port);
mult_125_G3_AN3_15_7 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_7_port, outb =>
mult_125_G3_ab_15_7_port);
mult_125_G3_AN3_15_6 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_6_port, outb =>
mult_125_G3_ab_15_6_port);
mult_125_G3_AN3_15_5 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_5_port, outb =>
mult_125_G3_ab_15_5_port);
mult_125_G3_AN3_15_4 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_4_port, outb =>
mult_125_G3_ab_15_4_port);
mult_125_G3_AN3_15_3 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_3_port, outb =>
mult_125_G3_ab_15_3_port);
mult_125_G3_AN3_15_2 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_2_port, outb =>
mult_125_G3_ab_15_2_port);
mult_125_G3_AN3_15_1 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_1_port, outb =>
mult_125_G3_ab_15_1_port);
mult_125_G3_AN3_15_0 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_0_port, outb =>
mult_125_G3_ab_15_0_port);
mult_125_G3_AN2_14_15 : nor2 port map( a => mult_125_G3_A_notx_14_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_14_15_port);
mult_125_G3_AN1_14_14 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_14_14_port);
mult_125_G3_AN1_14_13 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_14_13_port);
mult_125_G3_AN1_14_12 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_14_12_port);
mult_125_G3_AN1_14_11 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_14_11_port);
mult_125_G3_AN1_14_10 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_14_10_port);
mult_125_G3_AN1_14_9 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_14_9_port);
mult_125_G3_AN1_14_8 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_14_8_port);
mult_125_G3_AN1_14_7 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_14_7_port);
mult_125_G3_AN1_14_6 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_14_6_port);
mult_125_G3_AN1_14_5 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_14_5_port);
mult_125_G3_AN1_14_4 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_14_4_port);
mult_125_G3_AN1_14_3 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_14_3_port);
mult_125_G3_AN1_14_2 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_14_2_port);
mult_125_G3_AN1_14_1 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_14_1_port);
mult_125_G3_AN1_14_0_0 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_14_0_port);
mult_125_G3_AN2_13_15 : nor2 port map( a => mult_125_G3_A_notx_13_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_13_15_port);
mult_125_G3_AN1_13_14 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_13_14_port);
mult_125_G3_AN1_13_13 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_13_13_port);
mult_125_G3_AN1_13_12 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_13_12_port);
mult_125_G3_AN1_13_11 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_13_11_port);
mult_125_G3_AN1_13_10 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_13_10_port);
mult_125_G3_AN1_13_9 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_13_9_port);
mult_125_G3_AN1_13_8 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_13_8_port);
mult_125_G3_AN1_13_7 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_13_7_port);
mult_125_G3_AN1_13_6 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_13_6_port);
mult_125_G3_AN1_13_5 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_13_5_port);
mult_125_G3_AN1_13_4 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_13_4_port);
mult_125_G3_AN1_13_3 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_13_3_port);
mult_125_G3_AN1_13_2 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_13_2_port);
mult_125_G3_AN1_13_1 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_13_1_port);
mult_125_G3_AN1_13_0_0 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_13_0_port);
mult_125_G3_AN2_12_15 : nor2 port map( a => mult_125_G3_A_notx_12_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_12_15_port);
mult_125_G3_AN1_12_14 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_12_14_port);
mult_125_G3_AN1_12_13 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_12_13_port);
mult_125_G3_AN1_12_12 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_12_12_port);
mult_125_G3_AN1_12_11 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_12_11_port);
mult_125_G3_AN1_12_10 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_12_10_port);
mult_125_G3_AN1_12_9 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_12_9_port);
mult_125_G3_AN1_12_8 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_12_8_port);
mult_125_G3_AN1_12_7 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_12_7_port);
mult_125_G3_AN1_12_6 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_12_6_port);
mult_125_G3_AN1_12_5 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_12_5_port);
mult_125_G3_AN1_12_4 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_12_4_port);
mult_125_G3_AN1_12_3 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_12_3_port);
mult_125_G3_AN1_12_2 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_12_2_port);
mult_125_G3_AN1_12_1 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_12_1_port);
mult_125_G3_AN1_12_0_0 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_12_0_port);
mult_125_G3_AN2_11_15 : nor2 port map( a => mult_125_G3_A_notx_11_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_11_15_port);
mult_125_G3_AN1_11_14 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_11_14_port);
mult_125_G3_AN1_11_13 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_11_13_port);
mult_125_G3_AN1_11_12 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_11_12_port);
mult_125_G3_AN1_11_11 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_11_11_port);
mult_125_G3_AN1_11_10 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_11_10_port);
mult_125_G3_AN1_11_9 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_11_9_port);
mult_125_G3_AN1_11_8 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_11_8_port);
mult_125_G3_AN1_11_7 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_11_7_port);
mult_125_G3_AN1_11_6 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_11_6_port);
mult_125_G3_AN1_11_5 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_11_5_port);
mult_125_G3_AN1_11_4 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_11_4_port);
mult_125_G3_AN1_11_3 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_11_3_port);
mult_125_G3_AN1_11_2 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_11_2_port);
mult_125_G3_AN1_11_1 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_11_1_port);
mult_125_G3_AN1_11_0_0 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_11_0_port);
mult_125_G3_AN2_10_15 : nor2 port map( a => mult_125_G3_A_notx_10_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_10_15_port);
mult_125_G3_AN1_10_14 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_10_14_port);
mult_125_G3_AN1_10_13 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_10_13_port);
mult_125_G3_AN1_10_12 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_10_12_port);
mult_125_G3_AN1_10_11 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_10_11_port);
mult_125_G3_AN1_10_10 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_10_10_port);
mult_125_G3_AN1_10_9 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_10_9_port);
mult_125_G3_AN1_10_8 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_10_8_port);
mult_125_G3_AN1_10_7 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_10_7_port);
mult_125_G3_AN1_10_6 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_10_6_port);
mult_125_G3_AN1_10_5 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_10_5_port);
mult_125_G3_AN1_10_4 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_10_4_port);
mult_125_G3_AN1_10_3 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_10_3_port);
mult_125_G3_AN1_10_2 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_10_2_port);
mult_125_G3_AN1_10_1 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_10_1_port);
mult_125_G3_AN1_10_0_0 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_10_0_port);
mult_125_G3_AN2_9_15 : nor2 port map( a => mult_125_G3_A_notx_9_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_9_15_port);
mult_125_G3_AN1_9_14 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_9_14_port);
mult_125_G3_AN1_9_13 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_9_13_port);
mult_125_G3_AN1_9_12 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_9_12_port);
mult_125_G3_AN1_9_11 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_9_11_port);
mult_125_G3_AN1_9_10 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_9_10_port);
mult_125_G3_AN1_9_9 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_9_9_port);
mult_125_G3_AN1_9_8 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_9_8_port);
mult_125_G3_AN1_9_7 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_9_7_port);
mult_125_G3_AN1_9_6 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_9_6_port);
mult_125_G3_AN1_9_5 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_9_5_port);
mult_125_G3_AN1_9_4 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_9_4_port);
mult_125_G3_AN1_9_3 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_9_3_port);
mult_125_G3_AN1_9_2 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_9_2_port);
mult_125_G3_AN1_9_1 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_9_1_port);
mult_125_G3_AN1_9_0_0 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_9_0_port);
mult_125_G3_AN2_8_15 : nor2 port map( a => mult_125_G3_A_notx_8_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_8_15_port);
mult_125_G3_AN1_8_14 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_8_14_port);
mult_125_G3_AN1_8_13 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_8_13_port);
mult_125_G3_AN1_8_12 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_8_12_port);
mult_125_G3_AN1_8_11 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_8_11_port);
mult_125_G3_AN1_8_10 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_8_10_port);
mult_125_G3_AN1_8_9 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_8_9_port);
mult_125_G3_AN1_8_8 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_8_8_port);
mult_125_G3_AN1_8_7 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_8_7_port);
mult_125_G3_AN1_8_6 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_8_6_port);
mult_125_G3_AN1_8_5 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_8_5_port);
mult_125_G3_AN1_8_4 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_8_4_port);
mult_125_G3_AN1_8_3 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_8_3_port);
mult_125_G3_AN1_8_2 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_8_2_port);
mult_125_G3_AN1_8_1 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_8_1_port);
mult_125_G3_AN1_8_0_0 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_8_0_port);
mult_125_G3_AN2_7_15 : nor2 port map( a => mult_125_G3_A_notx_7_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_7_15_port);
mult_125_G3_AN1_7_14 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_7_14_port);
mult_125_G3_AN1_7_13 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_7_13_port);
mult_125_G3_AN1_7_12 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_7_12_port);
mult_125_G3_AN1_7_11 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_7_11_port);
mult_125_G3_AN1_7_10 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_7_10_port);
mult_125_G3_AN1_7_9 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_7_9_port);
mult_125_G3_AN1_7_8 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_7_8_port);
mult_125_G3_AN1_7_7 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_7_7_port);
mult_125_G3_AN1_7_6 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_7_6_port);
mult_125_G3_AN1_7_5 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_7_5_port);
mult_125_G3_AN1_7_4 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_7_4_port);
mult_125_G3_AN1_7_3 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_7_3_port);
mult_125_G3_AN1_7_2 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_7_2_port);
mult_125_G3_AN1_7_1 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_7_1_port);
mult_125_G3_AN1_7_0_0 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_7_0_port);
mult_125_G3_AN2_6_15 : nor2 port map( a => mult_125_G3_A_notx_6_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_6_15_port);
mult_125_G3_AN1_6_14 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_6_14_port);
mult_125_G3_AN1_6_13 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_6_13_port);
mult_125_G3_AN1_6_12 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_6_12_port);
mult_125_G3_AN1_6_11 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_6_11_port);
mult_125_G3_AN1_6_10 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_6_10_port);
mult_125_G3_AN1_6_9 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_6_9_port);
mult_125_G3_AN1_6_8 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_6_8_port);
mult_125_G3_AN1_6_7 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_6_7_port);
mult_125_G3_AN1_6_6 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_6_6_port);
mult_125_G3_AN1_6_5 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_6_5_port);
mult_125_G3_AN1_6_4 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_6_4_port);
mult_125_G3_AN1_6_3 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_6_3_port);
mult_125_G3_AN1_6_2 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_6_2_port);
mult_125_G3_AN1_6_1 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_6_1_port);
mult_125_G3_AN1_6_0_0 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_6_0_port);
mult_125_G3_AN2_5_15 : nor2 port map( a => mult_125_G3_A_notx_5_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_5_15_port);
mult_125_G3_AN1_5_14 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_5_14_port);
mult_125_G3_AN1_5_13 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_5_13_port);
mult_125_G3_AN1_5_12 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_5_12_port);
mult_125_G3_AN1_5_11 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_5_11_port);
mult_125_G3_AN1_5_10 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_5_10_port);
mult_125_G3_AN1_5_9 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_5_9_port);
mult_125_G3_AN1_5_8 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_5_8_port);
mult_125_G3_AN1_5_7 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_5_7_port);
mult_125_G3_AN1_5_6 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_5_6_port);
mult_125_G3_AN1_5_5 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_5_5_port);
mult_125_G3_AN1_5_4 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_5_4_port);
mult_125_G3_AN1_5_3 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_5_3_port);
mult_125_G3_AN1_5_2 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_5_2_port);
mult_125_G3_AN1_5_1 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_5_1_port);
mult_125_G3_AN1_5_0_0 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_5_0_port);
mult_125_G3_AN2_4_15 : nor2 port map( a => mult_125_G3_A_notx_4_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_4_15_port);
mult_125_G3_AN1_4_14 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_4_14_port);
mult_125_G3_AN1_4_13 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_4_13_port);
mult_125_G3_AN1_4_12 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_4_12_port);
mult_125_G3_AN1_4_11 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_4_11_port);
mult_125_G3_AN1_4_10 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_4_10_port);
mult_125_G3_AN1_4_9 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_4_9_port);
mult_125_G3_AN1_4_8 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_4_8_port);
mult_125_G3_AN1_4_7 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_4_7_port);
mult_125_G3_AN1_4_6 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_4_6_port);
mult_125_G3_AN1_4_5 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_4_5_port);
mult_125_G3_AN1_4_4 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_4_4_port);
mult_125_G3_AN1_4_3 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_4_3_port);
mult_125_G3_AN1_4_2 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_4_2_port);
mult_125_G3_AN1_4_1 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_4_1_port);
mult_125_G3_AN1_4_0_0 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_4_0_port);
mult_125_G3_AN2_3_15 : nor2 port map( a => mult_125_G3_A_notx_3_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_3_15_port);
mult_125_G3_AN1_3_14 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_3_14_port);
mult_125_G3_AN1_3_13 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_3_13_port);
mult_125_G3_AN1_3_12 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_3_12_port);
mult_125_G3_AN1_3_11 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_3_11_port);
mult_125_G3_AN1_3_10 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_3_10_port);
mult_125_G3_AN1_3_9 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_3_9_port);
mult_125_G3_AN1_3_8 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_3_8_port);
mult_125_G3_AN1_3_7 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_3_7_port);
mult_125_G3_AN1_3_6 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_3_6_port);
mult_125_G3_AN1_3_5 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_3_5_port);
mult_125_G3_AN1_3_4 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_3_4_port);
mult_125_G3_AN1_3_3 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_3_3_port);
mult_125_G3_AN1_3_2 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_3_2_port);
mult_125_G3_AN1_3_1 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_3_1_port);
mult_125_G3_AN1_3_0_0 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_3_0_port);
mult_125_G3_AN2_2_15 : nor2 port map( a => mult_125_G3_A_notx_2_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_2_15_port);
mult_125_G3_AN1_2_14 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_2_14_port);
mult_125_G3_AN1_2_13 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_2_13_port);
mult_125_G3_AN1_2_12 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_2_12_port);
mult_125_G3_AN1_2_11 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_2_11_port);
mult_125_G3_AN1_2_10 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_2_10_port);
mult_125_G3_AN1_2_9 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_2_9_port);
mult_125_G3_AN1_2_8 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_2_8_port);
mult_125_G3_AN1_2_7 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_2_7_port);
mult_125_G3_AN1_2_6 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_2_6_port);
mult_125_G3_AN1_2_5 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_2_5_port);
mult_125_G3_AN1_2_4 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_2_4_port);
mult_125_G3_AN1_2_3 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_2_3_port);
mult_125_G3_AN1_2_2 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_2_2_port);
mult_125_G3_AN1_2_1 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_2_1_port);
mult_125_G3_AN1_2_0_0 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_2_0_port);
mult_125_G3_AN2_1_15 : nor2 port map( a => mult_125_G3_A_notx_1_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_1_15_port);
mult_125_G3_AN1_1_14 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_1_14_port);
mult_125_G3_AN1_1_13 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_1_13_port);
mult_125_G3_AN1_1_12 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_1_12_port);
mult_125_G3_AN1_1_11 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_1_11_port);
mult_125_G3_AN1_1_10 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_1_10_port);
mult_125_G3_AN1_1_9 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_1_9_port);
mult_125_G3_AN1_1_8 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_1_8_port);
mult_125_G3_AN1_1_7 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_1_7_port);
mult_125_G3_AN1_1_6 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_1_6_port);
mult_125_G3_AN1_1_5 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_1_5_port);
mult_125_G3_AN1_1_4 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_1_4_port);
mult_125_G3_AN1_1_3 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_1_3_port);
mult_125_G3_AN1_1_2 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_1_2_port);
mult_125_G3_AN1_1_1 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_1_1_port);
mult_125_G3_AN1_1_0_0 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_1_0_port);
mult_125_G3_AN2_0_15 : nor2 port map( a => mult_125_G3_A_notx_0_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_0_15_port);
mult_125_G3_AN1_0_14 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_0_14_port);
mult_125_G3_AN1_0_13 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_0_13_port);
mult_125_G3_AN1_0_12 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_0_12_port);
mult_125_G3_AN1_0_11 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_0_11_port);
mult_125_G3_AN1_0_10 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_0_10_port);
mult_125_G3_AN1_0_9 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_0_9_port);
mult_125_G3_AN1_0_8 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_0_8_port);
mult_125_G3_AN1_0_7 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_0_7_port);
mult_125_G3_AN1_0_6 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_0_6_port);
mult_125_G3_AN1_0_5 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_0_5_port);
mult_125_G3_AN1_0_4 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_0_4_port);
mult_125_G3_AN1_0_3 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_0_3_port);
mult_125_G3_AN1_0_2 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_0_2_port);
mult_125_G3_AN1_0_1 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_0_1_port);
mult_125_G3_AN1_0_0_0 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_0_port, outb =>
multiplier_sigs_2_0_port);
mult_125_G2_FS_1_U6_1_1_3 : oai12 port map( b => n5907, c => n5908, a =>
n5909, outb => mult_125_G2_FS_1_C_1_7_0_port);
mult_125_G2_FS_1_U6_1_1_2 : oai12 port map( b => n5904, c => n5905, a =>
n5906, outb => mult_125_G2_FS_1_C_1_6_0_port);
mult_125_G2_FS_1_U6_1_1_1 : oai12 port map( b => n5901, c => n5902, a =>
n5903, outb => mult_125_G2_FS_1_C_1_5_0_port);
mult_125_G2_FS_1_U6_0_7_1 : oai12 port map( b => n5898, c => n5899, a =>
mult_125_G2_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_G2_FS_1_C_1_7_1_port);
mult_125_G2_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_7_1_port, b =>
mult_125_G2_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_1_31_port);
mult_125_G2_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_7_1_port, b =>
mult_125_G2_FS_1_P_0_7_1_port, outb => n5897);
mult_125_G2_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_G2_A1_29_port, b
=> mult_125_G2_A2_29_port, outb =>
mult_125_G2_FS_1_G_n_int_0_7_1_port);
mult_125_G2_FS_1_U1_0_7_1 : nand2 port map( a => n5895, b => n5896, outb =>
mult_125_G2_FS_1_P_0_7_1_port);
mult_125_G2_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_7_0_port, b =>
mult_125_G2_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_1_30_port);
mult_125_G2_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_7_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_7_0_port, outb => n5894);
mult_125_G2_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_G2_A1_28_port, b
=> mult_125_G2_A2_28_port, outb =>
mult_125_G2_FS_1_G_n_int_0_7_0_port);
mult_125_G2_FS_1_U1_0_7_0 : nand2 port map( a => n5892, b => n5893, outb =>
mult_125_G2_FS_1_TEMP_P_0_7_0_port);
mult_125_G2_FS_1_U6_0_6_3 : oai12 port map( b => n5890, c => n5891, a =>
mult_125_G2_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G2_FS_1_C_1_6_3_port);
mult_125_G2_FS_1_U5_0_6_3 : oai12 port map( b => n5888, c => n5889, a =>
mult_125_G2_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_G2_FS_1_G_1_1_2_port);
mult_125_G2_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_G2_FS_1_P_0_6_3_port, outb => n5908);
mult_125_G2_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_3_port, b =>
mult_125_G2_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_1_29_port);
mult_125_G2_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_3_port, b =>
mult_125_G2_FS_1_P_0_6_3_port, outb => n5887);
mult_125_G2_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_G2_A1_27_port, b
=> mult_125_G2_A2_27_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_3_port);
mult_125_G2_FS_1_U1_0_6_3 : nand2 port map( a => n5885, b => n5886, outb =>
mult_125_G2_FS_1_P_0_6_3_port);
mult_125_G2_FS_1_U6_0_6_2 : oai12 port map( b => n5883, c => n5884, a =>
mult_125_G2_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G2_FS_1_C_1_6_2_port);
mult_125_G2_FS_1_U5_0_6_2 : oai12 port map( b => n5882, c => n5891, a =>
mult_125_G2_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_6_2_port);
mult_125_G2_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_G2_FS_1_P_0_6_2_port, outb => n5881);
mult_125_G2_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_2_port, b =>
mult_125_G2_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_1_28_port);
mult_125_G2_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_2_port, b =>
mult_125_G2_FS_1_P_0_6_2_port, outb => n5880);
mult_125_G2_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_G2_A1_26_port, b
=> mult_125_G2_A2_26_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_2_port);
mult_125_G2_FS_1_U1_0_6_2 : nand2 port map( a => n5878, b => n5879, outb =>
mult_125_G2_FS_1_P_0_6_2_port);
mult_125_G2_FS_1_U6_0_6_1 : oai12 port map( b => n5907, c => n5877, a =>
mult_125_G2_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_G2_FS_1_C_1_6_1_port);
mult_125_G2_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_G2_FS_1_G_n_int_0_6_0_port, c => n5884, a
=> mult_125_G2_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_6_1_port);
mult_125_G2_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_G2_FS_1_P_0_6_1_port, outb => n5876);
mult_125_G2_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_1_port, b =>
mult_125_G2_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_1_27_port);
mult_125_G2_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_1_port, b =>
mult_125_G2_FS_1_P_0_6_1_port, outb => n5875);
mult_125_G2_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_G2_A1_25_port, b
=> mult_125_G2_A2_25_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_1_port);
mult_125_G2_FS_1_U1_0_6_1 : nand2 port map( a => n5873, b => n5874, outb =>
mult_125_G2_FS_1_P_0_6_1_port);
mult_125_G2_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_0_port, b =>
mult_125_G2_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_1_26_port);
mult_125_G2_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_6_0_port, outb => n5872);
mult_125_G2_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_G2_A1_24_port, b
=> mult_125_G2_A2_24_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_0_port);
mult_125_G2_FS_1_U1_0_6_0 : nand2 port map( a => n5870, b => n5871, outb =>
mult_125_G2_FS_1_TEMP_P_0_6_0_port);
mult_125_G2_FS_1_U6_0_5_3 : oai12 port map( b => n5868, c => n5869, a =>
mult_125_G2_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G2_FS_1_C_1_5_3_port);
mult_125_G2_FS_1_U5_0_5_3 : oai12 port map( b => n5866, c => n5867, a =>
mult_125_G2_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_G2_FS_1_G_1_1_1_port);
mult_125_G2_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_G2_FS_1_P_0_5_3_port, outb => n5905);
mult_125_G2_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_3_port, b =>
mult_125_G2_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_1_25_port);
mult_125_G2_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_3_port, b =>
mult_125_G2_FS_1_P_0_5_3_port, outb => n5865);
mult_125_G2_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_G2_A1_23_port, b
=> mult_125_G2_A2_23_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_3_port);
mult_125_G2_FS_1_U1_0_5_3 : nand2 port map( a => n5863, b => n5864, outb =>
mult_125_G2_FS_1_P_0_5_3_port);
mult_125_G2_FS_1_U6_0_5_2 : oai12 port map( b => n5861, c => n5862, a =>
mult_125_G2_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G2_FS_1_C_1_5_2_port);
mult_125_G2_FS_1_U5_0_5_2 : oai12 port map( b => n5860, c => n5869, a =>
mult_125_G2_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_5_2_port);
mult_125_G2_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_G2_FS_1_P_0_5_2_port, outb => n5859);
mult_125_G2_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_2_port, b =>
mult_125_G2_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_1_24_port);
mult_125_G2_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_2_port, b =>
mult_125_G2_FS_1_P_0_5_2_port, outb => n5858);
mult_125_G2_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_G2_A1_22_port, b
=> mult_125_G2_A2_22_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_2_port);
mult_125_G2_FS_1_U1_0_5_2 : nand2 port map( a => n5856, b => n5857, outb =>
mult_125_G2_FS_1_P_0_5_2_port);
mult_125_G2_FS_1_U6_0_5_1 : oai12 port map( b => n5904, c => n5855, a =>
mult_125_G2_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_G2_FS_1_C_1_5_1_port);
mult_125_G2_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_G2_FS_1_G_n_int_0_5_0_port, c => n5862, a
=> mult_125_G2_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_5_1_port);
mult_125_G2_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_G2_FS_1_P_0_5_1_port, outb => n5854);
mult_125_G2_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_1_port, b =>
mult_125_G2_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_1_23_port);
mult_125_G2_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_1_port, b =>
mult_125_G2_FS_1_P_0_5_1_port, outb => n5853);
mult_125_G2_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_G2_A1_21_port, b
=> mult_125_G2_A2_21_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_1_port);
mult_125_G2_FS_1_U1_0_5_1 : nand2 port map( a => n5851, b => n5852, outb =>
mult_125_G2_FS_1_P_0_5_1_port);
mult_125_G2_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_0_port, b =>
mult_125_G2_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_1_22_port);
mult_125_G2_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_5_0_port, outb => n5850);
mult_125_G2_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_G2_A1_20_port, b
=> mult_125_G2_A2_20_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_0_port);
mult_125_G2_FS_1_U1_0_5_0 : nand2 port map( a => n5848, b => n5849, outb =>
mult_125_G2_FS_1_TEMP_P_0_5_0_port);
mult_125_G2_FS_1_U6_0_4_3 : oai12 port map( b => n5846, c => n5847, a =>
mult_125_G2_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G2_FS_1_C_1_4_3_port);
mult_125_G2_FS_1_U5_0_4_3 : oai12 port map( b => n5844, c => n5845, a =>
mult_125_G2_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_G2_FS_1_G_1_1_0_port);
mult_125_G2_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_G2_FS_1_P_0_4_3_port, outb => n5902);
mult_125_G2_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_3_port, b =>
mult_125_G2_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_1_21_port);
mult_125_G2_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_3_port, b =>
mult_125_G2_FS_1_P_0_4_3_port, outb => n5843);
mult_125_G2_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_G2_A1_19_port, b
=> mult_125_G2_A2_19_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_3_port);
mult_125_G2_FS_1_U1_0_4_3 : nand2 port map( a => n5841, b => n5842, outb =>
mult_125_G2_FS_1_P_0_4_3_port);
mult_125_G2_FS_1_U6_0_4_2 : oai12 port map( b => n5839, c => n5840, a =>
mult_125_G2_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G2_FS_1_C_1_4_2_port);
mult_125_G2_FS_1_U5_0_4_2 : oai12 port map( b => n5838, c => n5847, a =>
mult_125_G2_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_4_2_port);
mult_125_G2_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_G2_FS_1_P_0_4_2_port, outb => n5837);
mult_125_G2_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_2_port, b =>
mult_125_G2_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_1_20_port);
mult_125_G2_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_2_port, b =>
mult_125_G2_FS_1_P_0_4_2_port, outb => n5836);
mult_125_G2_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_G2_A1_18_port, b
=> mult_125_G2_A2_18_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_2_port);
mult_125_G2_FS_1_U1_0_4_2 : nand2 port map( a => n5834, b => n5835, outb =>
mult_125_G2_FS_1_P_0_4_2_port);
mult_125_G2_FS_1_U6_0_4_1 : oai12 port map( b => n5901, c => n5833, a =>
mult_125_G2_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_G2_FS_1_C_1_4_1_port);
mult_125_G2_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_G2_FS_1_G_n_int_0_4_0_port, c => n5840, a
=> mult_125_G2_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_4_1_port);
mult_125_G2_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_G2_FS_1_P_0_4_1_port, outb => n5832);
mult_125_G2_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_1_port, b =>
mult_125_G2_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_1_19_port);
mult_125_G2_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_1_port, b =>
mult_125_G2_FS_1_P_0_4_1_port, outb => n5831);
mult_125_G2_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_G2_A1_17_port, b
=> mult_125_G2_A2_17_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_1_port);
mult_125_G2_FS_1_U1_0_4_1 : nand2 port map( a => n5829, b => n5830, outb =>
mult_125_G2_FS_1_P_0_4_1_port);
mult_125_G2_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_0_port, b =>
mult_125_G2_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_1_18_port);
mult_125_G2_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_4_0_port, outb => n5828);
mult_125_G2_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_G2_A1_16_port, b
=> mult_125_G2_A2_16_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_0_port);
mult_125_G2_FS_1_U1_0_4_0 : nand2 port map( a => n5826, b => n5827, outb =>
mult_125_G2_FS_1_TEMP_P_0_4_0_port);
mult_125_G2_FS_1_U5_0_3_3 : oai12 port map( b => n5824, c => n5825, a =>
mult_125_G2_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_G2_FS_1_G_1_0_3_port);
mult_125_G2_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_3_3_port, b =>
mult_125_G2_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_1_17_port);
mult_125_G2_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_3_3_port, b =>
mult_125_G2_FS_1_P_0_3_3_port, outb => n5823);
mult_125_G2_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_G2_A1_15_port, b
=> mult_125_G2_A2_15_port, outb =>
mult_125_G2_FS_1_G_n_int_0_3_3_port);
mult_125_G2_FS_1_U1_0_3_3 : nand2 port map( a => n5821, b => n5822, outb =>
mult_125_G2_FS_1_P_0_3_3_port);
mult_125_G2_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_3_2_port, b =>
mult_125_G2_FS_1_P_0_3_2_port, outb => n5820);
mult_125_G2_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_G2_A1_14_port, b
=> mult_125_G2_A2_14_port, outb =>
mult_125_G2_FS_1_G_n_int_0_3_2_port);
mult_125_G2_FS_1_U1_0_3_2 : nand2 port map( a => n5818, b => n5819, outb =>
mult_125_G2_FS_1_P_0_3_2_port);
mult_125_G2_AN1_15 : inv port map( inb => coefficient_mem_array_1_15_port,
outb => mult_125_G2_A_not_15_port);
mult_125_G2_AN1_14 : inv port map( inb => coefficient_mem_array_1_14_port,
outb => mult_125_G2_A_not_14_port);
mult_125_G2_AN1_13 : inv port map( inb => coefficient_mem_array_1_13_port,
outb => mult_125_G2_A_not_13_port);
mult_125_G2_AN1_12 : inv port map( inb => coefficient_mem_array_1_12_port,
outb => mult_125_G2_A_not_12_port);
mult_125_G2_AN1_11 : inv port map( inb => coefficient_mem_array_1_11_port,
outb => mult_125_G2_A_not_11_port);
mult_125_G2_AN1_10 : inv port map( inb => coefficient_mem_array_1_10_port,
outb => mult_125_G2_A_not_10_port);
mult_125_G2_AN1_9 : inv port map( inb => coefficient_mem_array_1_9_port,
outb => mult_125_G2_A_not_9_port);
mult_125_G2_AN1_8 : inv port map( inb => coefficient_mem_array_1_8_port,
outb => mult_125_G2_A_not_8_port);
mult_125_G2_AN1_7 : inv port map( inb => coefficient_mem_array_1_7_port,
outb => mult_125_G2_A_not_7_port);
mult_125_G2_AN1_6 : inv port map( inb => coefficient_mem_array_1_6_port,
outb => mult_125_G2_A_not_6_port);
mult_125_G2_AN1_5 : inv port map( inb => coefficient_mem_array_1_5_port,
outb => mult_125_G2_A_not_5_port);
mult_125_G2_AN1_4 : inv port map( inb => coefficient_mem_array_1_4_port,
outb => mult_125_G2_A_not_4_port);
mult_125_G2_AN1_3 : inv port map( inb => coefficient_mem_array_1_3_port,
outb => mult_125_G2_A_not_3_port);
mult_125_G2_AN1_2 : inv port map( inb => coefficient_mem_array_1_2_port,
outb => mult_125_G2_A_not_2_port);
mult_125_G2_AN1_1 : inv port map( inb => coefficient_mem_array_1_1_port,
outb => mult_125_G2_A_not_1_port);
mult_125_G2_AN1_0 : inv port map( inb => coefficient_mem_array_1_0_port,
outb => mult_125_G2_A_not_0_port);
mult_125_G2_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb
=> mult_125_G2_B_not_15_port);
mult_125_G2_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb
=> mult_125_G2_B_not_14_port);
mult_125_G2_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb
=> mult_125_G2_B_not_13_port);
mult_125_G2_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb
=> mult_125_G2_B_not_12_port);
mult_125_G2_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb
=> mult_125_G2_B_not_11_port);
mult_125_G2_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb
=> mult_125_G2_B_not_10_port);
mult_125_G2_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_G2_B_not_9_port);
mult_125_G2_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_G2_B_not_8_port);
mult_125_G2_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_G2_B_not_7_port);
mult_125_G2_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_G2_B_not_6_port);
mult_125_G2_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_G2_B_not_5_port);
mult_125_G2_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_G2_B_not_4_port);
mult_125_G2_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_G2_B_not_3_port);
mult_125_G2_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_G2_B_not_2_port);
mult_125_G2_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_G2_B_not_1_port);
mult_125_G2_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_G2_B_not_0_port);
mult_125_G2_AN1_15_15 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_15_15_port);
mult_125_G2_AN3_15_14 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_14_port, outb =>
mult_125_G2_ab_15_14_port);
mult_125_G2_AN3_15_13 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_13_port, outb =>
mult_125_G2_ab_15_13_port);
mult_125_G2_AN3_15_12 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_12_port, outb =>
mult_125_G2_ab_15_12_port);
mult_125_G2_AN3_15_11 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_11_port, outb =>
mult_125_G2_ab_15_11_port);
mult_125_G2_AN3_15_10 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_10_port, outb =>
mult_125_G2_ab_15_10_port);
mult_125_G2_AN3_15_9 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_9_port, outb =>
mult_125_G2_ab_15_9_port);
mult_125_G2_AN3_15_8 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_8_port, outb =>
mult_125_G2_ab_15_8_port);
mult_125_G2_AN3_15_7 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_7_port, outb =>
mult_125_G2_ab_15_7_port);
mult_125_G2_AN3_15_6 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_6_port, outb =>
mult_125_G2_ab_15_6_port);
mult_125_G2_AN3_15_5 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_5_port, outb =>
mult_125_G2_ab_15_5_port);
mult_125_G2_AN3_15_4 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_4_port, outb =>
mult_125_G2_ab_15_4_port);
mult_125_G2_AN3_15_3 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_3_port, outb =>
mult_125_G2_ab_15_3_port);
mult_125_G2_AN3_15_2 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_2_port, outb =>
mult_125_G2_ab_15_2_port);
mult_125_G2_AN3_15_1 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_1_port, outb =>
mult_125_G2_ab_15_1_port);
mult_125_G2_AN3_15_0 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_0_port, outb =>
mult_125_G2_ab_15_0_port);
mult_125_G2_AN2_14_15 : nor2 port map( a => mult_125_G2_A_notx_14_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_14_15_port);
mult_125_G2_AN1_14_14 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_14_14_port);
mult_125_G2_AN1_14_13 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_14_13_port);
mult_125_G2_AN1_14_12 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_14_12_port);
mult_125_G2_AN1_14_11 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_14_11_port);
mult_125_G2_AN1_14_10 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_14_10_port);
mult_125_G2_AN1_14_9 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_14_9_port);
mult_125_G2_AN1_14_8 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_14_8_port);
mult_125_G2_AN1_14_7 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_14_7_port);
mult_125_G2_AN1_14_6 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_14_6_port);
mult_125_G2_AN1_14_5 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_14_5_port);
mult_125_G2_AN1_14_4 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_14_4_port);
mult_125_G2_AN1_14_3 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_14_3_port);
mult_125_G2_AN1_14_2 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_14_2_port);
mult_125_G2_AN1_14_1 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_14_1_port);
mult_125_G2_AN1_14_0_0 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_14_0_port);
mult_125_G2_AN2_13_15 : nor2 port map( a => mult_125_G2_A_notx_13_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_13_15_port);
mult_125_G2_AN1_13_14 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_13_14_port);
mult_125_G2_AN1_13_13 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_13_13_port);
mult_125_G2_AN1_13_12 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_13_12_port);
mult_125_G2_AN1_13_11 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_13_11_port);
mult_125_G2_AN1_13_10 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_13_10_port);
mult_125_G2_AN1_13_9 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_13_9_port);
mult_125_G2_AN1_13_8 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_13_8_port);
mult_125_G2_AN1_13_7 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_13_7_port);
mult_125_G2_AN1_13_6 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_13_6_port);
mult_125_G2_AN1_13_5 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_13_5_port);
mult_125_G2_AN1_13_4 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_13_4_port);
mult_125_G2_AN1_13_3 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_13_3_port);
mult_125_G2_AN1_13_2 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_13_2_port);
mult_125_G2_AN1_13_1 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_13_1_port);
mult_125_G2_AN1_13_0_0 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_13_0_port);
mult_125_G2_AN2_12_15 : nor2 port map( a => mult_125_G2_A_notx_12_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_12_15_port);
mult_125_G2_AN1_12_14 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_12_14_port);
mult_125_G2_AN1_12_13 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_12_13_port);
mult_125_G2_AN1_12_12 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_12_12_port);
mult_125_G2_AN1_12_11 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_12_11_port);
mult_125_G2_AN1_12_10 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_12_10_port);
mult_125_G2_AN1_12_9 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_12_9_port);
mult_125_G2_AN1_12_8 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_12_8_port);
mult_125_G2_AN1_12_7 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_12_7_port);
mult_125_G2_AN1_12_6 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_12_6_port);
mult_125_G2_AN1_12_5 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_12_5_port);
mult_125_G2_AN1_12_4 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_12_4_port);
mult_125_G2_AN1_12_3 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_12_3_port);
mult_125_G2_AN1_12_2 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_12_2_port);
mult_125_G2_AN1_12_1 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_12_1_port);
mult_125_G2_AN1_12_0_0 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_12_0_port);
mult_125_G2_AN2_11_15 : nor2 port map( a => mult_125_G2_A_notx_11_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_11_15_port);
mult_125_G2_AN1_11_14 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_11_14_port);
mult_125_G2_AN1_11_13 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_11_13_port);
mult_125_G2_AN1_11_12 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_11_12_port);
mult_125_G2_AN1_11_11 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_11_11_port);
mult_125_G2_AN1_11_10 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_11_10_port);
mult_125_G2_AN1_11_9 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_11_9_port);
mult_125_G2_AN1_11_8 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_11_8_port);
mult_125_G2_AN1_11_7 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_11_7_port);
mult_125_G2_AN1_11_6 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_11_6_port);
mult_125_G2_AN1_11_5 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_11_5_port);
mult_125_G2_AN1_11_4 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_11_4_port);
mult_125_G2_AN1_11_3 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_11_3_port);
mult_125_G2_AN1_11_2 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_11_2_port);
mult_125_G2_AN1_11_1 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_11_1_port);
mult_125_G2_AN1_11_0_0 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_11_0_port);
mult_125_G2_AN2_10_15 : nor2 port map( a => mult_125_G2_A_notx_10_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_10_15_port);
mult_125_G2_AN1_10_14 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_10_14_port);
mult_125_G2_AN1_10_13 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_10_13_port);
mult_125_G2_AN1_10_12 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_10_12_port);
mult_125_G2_AN1_10_11 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_10_11_port);
mult_125_G2_AN1_10_10 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_10_10_port);
mult_125_G2_AN1_10_9 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_10_9_port);
mult_125_G2_AN1_10_8 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_10_8_port);
mult_125_G2_AN1_10_7 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_10_7_port);
mult_125_G2_AN1_10_6 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_10_6_port);
mult_125_G2_AN1_10_5 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_10_5_port);
mult_125_G2_AN1_10_4 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_10_4_port);
mult_125_G2_AN1_10_3 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_10_3_port);
mult_125_G2_AN1_10_2 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_10_2_port);
mult_125_G2_AN1_10_1 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_10_1_port);
mult_125_G2_AN1_10_0_0 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_10_0_port);
mult_125_G2_AN2_9_15 : nor2 port map( a => mult_125_G2_A_notx_9_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_9_15_port);
mult_125_G2_AN1_9_14 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_9_14_port);
mult_125_G2_AN1_9_13 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_9_13_port);
mult_125_G2_AN1_9_12 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_9_12_port);
mult_125_G2_AN1_9_11 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_9_11_port);
mult_125_G2_AN1_9_10 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_9_10_port);
mult_125_G2_AN1_9_9 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_9_9_port);
mult_125_G2_AN1_9_8 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_9_8_port);
mult_125_G2_AN1_9_7 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_9_7_port);
mult_125_G2_AN1_9_6 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_9_6_port);
mult_125_G2_AN1_9_5 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_9_5_port);
mult_125_G2_AN1_9_4 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_9_4_port);
mult_125_G2_AN1_9_3 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_9_3_port);
mult_125_G2_AN1_9_2 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_9_2_port);
mult_125_G2_AN1_9_1 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_9_1_port);
mult_125_G2_AN1_9_0_0 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_9_0_port);
mult_125_G2_AN2_8_15 : nor2 port map( a => mult_125_G2_A_notx_8_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_8_15_port);
mult_125_G2_AN1_8_14 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_8_14_port);
mult_125_G2_AN1_8_13 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_8_13_port);
mult_125_G2_AN1_8_12 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_8_12_port);
mult_125_G2_AN1_8_11 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_8_11_port);
mult_125_G2_AN1_8_10 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_8_10_port);
mult_125_G2_AN1_8_9 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_8_9_port);
mult_125_G2_AN1_8_8 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_8_8_port);
mult_125_G2_AN1_8_7 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_8_7_port);
mult_125_G2_AN1_8_6 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_8_6_port);
mult_125_G2_AN1_8_5 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_8_5_port);
mult_125_G2_AN1_8_4 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_8_4_port);
mult_125_G2_AN1_8_3 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_8_3_port);
mult_125_G2_AN1_8_2 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_8_2_port);
mult_125_G2_AN1_8_1 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_8_1_port);
mult_125_G2_AN1_8_0_0 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_8_0_port);
mult_125_G2_AN2_7_15 : nor2 port map( a => mult_125_G2_A_notx_7_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_7_15_port);
mult_125_G2_AN1_7_14 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_7_14_port);
mult_125_G2_AN1_7_13 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_7_13_port);
mult_125_G2_AN1_7_12 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_7_12_port);
mult_125_G2_AN1_7_11 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_7_11_port);
mult_125_G2_AN1_7_10 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_7_10_port);
mult_125_G2_AN1_7_9 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_7_9_port);
mult_125_G2_AN1_7_8 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_7_8_port);
mult_125_G2_AN1_7_7 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_7_7_port);
mult_125_G2_AN1_7_6 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_7_6_port);
mult_125_G2_AN1_7_5 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_7_5_port);
mult_125_G2_AN1_7_4 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_7_4_port);
mult_125_G2_AN1_7_3 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_7_3_port);
mult_125_G2_AN1_7_2 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_7_2_port);
mult_125_G2_AN1_7_1 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_7_1_port);
mult_125_G2_AN1_7_0_0 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_7_0_port);
mult_125_G2_AN2_6_15 : nor2 port map( a => mult_125_G2_A_notx_6_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_6_15_port);
mult_125_G2_AN1_6_14 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_6_14_port);
mult_125_G2_AN1_6_13 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_6_13_port);
mult_125_G2_AN1_6_12 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_6_12_port);
mult_125_G2_AN1_6_11 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_6_11_port);
mult_125_G2_AN1_6_10 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_6_10_port);
mult_125_G2_AN1_6_9 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_6_9_port);
mult_125_G2_AN1_6_8 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_6_8_port);
mult_125_G2_AN1_6_7 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_6_7_port);
mult_125_G2_AN1_6_6 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_6_6_port);
mult_125_G2_AN1_6_5 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_6_5_port);
mult_125_G2_AN1_6_4 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_6_4_port);
mult_125_G2_AN1_6_3 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_6_3_port);
mult_125_G2_AN1_6_2 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_6_2_port);
mult_125_G2_AN1_6_1 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_6_1_port);
mult_125_G2_AN1_6_0_0 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_6_0_port);
mult_125_G2_AN2_5_15 : nor2 port map( a => mult_125_G2_A_notx_5_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_5_15_port);
mult_125_G2_AN1_5_14 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_5_14_port);
mult_125_G2_AN1_5_13 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_5_13_port);
mult_125_G2_AN1_5_12 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_5_12_port);
mult_125_G2_AN1_5_11 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_5_11_port);
mult_125_G2_AN1_5_10 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_5_10_port);
mult_125_G2_AN1_5_9 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_5_9_port);
mult_125_G2_AN1_5_8 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_5_8_port);
mult_125_G2_AN1_5_7 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_5_7_port);
mult_125_G2_AN1_5_6 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_5_6_port);
mult_125_G2_AN1_5_5 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_5_5_port);
mult_125_G2_AN1_5_4 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_5_4_port);
mult_125_G2_AN1_5_3 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_5_3_port);
mult_125_G2_AN1_5_2 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_5_2_port);
mult_125_G2_AN1_5_1 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_5_1_port);
mult_125_G2_AN1_5_0_0 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_5_0_port);
mult_125_G2_AN2_4_15 : nor2 port map( a => mult_125_G2_A_notx_4_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_4_15_port);
mult_125_G2_AN1_4_14 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_4_14_port);
mult_125_G2_AN1_4_13 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_4_13_port);
mult_125_G2_AN1_4_12 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_4_12_port);
mult_125_G2_AN1_4_11 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_4_11_port);
mult_125_G2_AN1_4_10 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_4_10_port);
mult_125_G2_AN1_4_9 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_4_9_port);
mult_125_G2_AN1_4_8 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_4_8_port);
mult_125_G2_AN1_4_7 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_4_7_port);
mult_125_G2_AN1_4_6 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_4_6_port);
mult_125_G2_AN1_4_5 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_4_5_port);
mult_125_G2_AN1_4_4 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_4_4_port);
mult_125_G2_AN1_4_3 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_4_3_port);
mult_125_G2_AN1_4_2 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_4_2_port);
mult_125_G2_AN1_4_1 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_4_1_port);
mult_125_G2_AN1_4_0_0 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_4_0_port);
mult_125_G2_AN2_3_15 : nor2 port map( a => mult_125_G2_A_notx_3_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_3_15_port);
mult_125_G2_AN1_3_14 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_3_14_port);
mult_125_G2_AN1_3_13 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_3_13_port);
mult_125_G2_AN1_3_12 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_3_12_port);
mult_125_G2_AN1_3_11 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_3_11_port);
mult_125_G2_AN1_3_10 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_3_10_port);
mult_125_G2_AN1_3_9 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_3_9_port);
mult_125_G2_AN1_3_8 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_3_8_port);
mult_125_G2_AN1_3_7 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_3_7_port);
mult_125_G2_AN1_3_6 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_3_6_port);
mult_125_G2_AN1_3_5 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_3_5_port);
mult_125_G2_AN1_3_4 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_3_4_port);
mult_125_G2_AN1_3_3 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_3_3_port);
mult_125_G2_AN1_3_2 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_3_2_port);
mult_125_G2_AN1_3_1 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_3_1_port);
mult_125_G2_AN1_3_0_0 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_3_0_port);
mult_125_G2_AN2_2_15 : nor2 port map( a => mult_125_G2_A_notx_2_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_2_15_port);
mult_125_G2_AN1_2_14 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_2_14_port);
mult_125_G2_AN1_2_13 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_2_13_port);
mult_125_G2_AN1_2_12 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_2_12_port);
mult_125_G2_AN1_2_11 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_2_11_port);
mult_125_G2_AN1_2_10 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_2_10_port);
mult_125_G2_AN1_2_9 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_2_9_port);
mult_125_G2_AN1_2_8 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_2_8_port);
mult_125_G2_AN1_2_7 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_2_7_port);
mult_125_G2_AN1_2_6 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_2_6_port);
mult_125_G2_AN1_2_5 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_2_5_port);
mult_125_G2_AN1_2_4 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_2_4_port);
mult_125_G2_AN1_2_3 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_2_3_port);
mult_125_G2_AN1_2_2 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_2_2_port);
mult_125_G2_AN1_2_1 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_2_1_port);
mult_125_G2_AN1_2_0_0 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_2_0_port);
mult_125_G2_AN2_1_15 : nor2 port map( a => mult_125_G2_A_notx_1_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_1_15_port);
mult_125_G2_AN1_1_14 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_1_14_port);
mult_125_G2_AN1_1_13 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_1_13_port);
mult_125_G2_AN1_1_12 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_1_12_port);
mult_125_G2_AN1_1_11 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_1_11_port);
mult_125_G2_AN1_1_10 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_1_10_port);
mult_125_G2_AN1_1_9 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_1_9_port);
mult_125_G2_AN1_1_8 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_1_8_port);
mult_125_G2_AN1_1_7 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_1_7_port);
mult_125_G2_AN1_1_6 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_1_6_port);
mult_125_G2_AN1_1_5 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_1_5_port);
mult_125_G2_AN1_1_4 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_1_4_port);
mult_125_G2_AN1_1_3 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_1_3_port);
mult_125_G2_AN1_1_2 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_1_2_port);
mult_125_G2_AN1_1_1 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_1_1_port);
mult_125_G2_AN1_1_0_0 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_1_0_port);
mult_125_G2_AN2_0_15 : nor2 port map( a => mult_125_G2_A_notx_0_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_0_15_port);
mult_125_G2_AN1_0_14 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_0_14_port);
mult_125_G2_AN1_0_13 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_0_13_port);
mult_125_G2_AN1_0_12 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_0_12_port);
mult_125_G2_AN1_0_11 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_0_11_port);
mult_125_G2_AN1_0_10 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_0_10_port);
mult_125_G2_AN1_0_9 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_0_9_port);
mult_125_G2_AN1_0_8 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_0_8_port);
mult_125_G2_AN1_0_7 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_0_7_port);
mult_125_G2_AN1_0_6 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_0_6_port);
mult_125_G2_AN1_0_5 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_0_5_port);
mult_125_G2_AN1_0_4 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_0_4_port);
mult_125_G2_AN1_0_3 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_0_3_port);
mult_125_G2_AN1_0_2 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_0_2_port);
mult_125_G2_AN1_0_1 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_0_1_port);
mult_125_G2_AN1_0_0_0 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_0_port, outb =>
multiplier_sigs_1_0_port);
mult_125_FS_1_U6_1_1_3 : oai12 port map( b => n5782, c => n5783, a => n5784,
outb => mult_125_FS_1_C_1_7_0_port);
mult_125_FS_1_U6_1_1_2 : oai12 port map( b => n5779, c => n5780, a => n5781,
outb => mult_125_FS_1_C_1_6_0_port);
mult_125_FS_1_U6_1_1_1 : oai12 port map( b => n5776, c => n5777, a => n5778,
outb => mult_125_FS_1_C_1_5_0_port);
mult_125_FS_1_U6_0_7_1 : oai12 port map( b => n5773, c => n5774, a =>
mult_125_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_FS_1_C_1_7_1_port);
mult_125_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_7_1_port, b =>
mult_125_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_0_31_port);
mult_125_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_7_1_port, b =>
mult_125_FS_1_P_0_7_1_port, outb => n5772);
mult_125_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_A1_29_port, b =>
mult_125_A2_29_port, outb =>
mult_125_FS_1_G_n_int_0_7_1_port);
mult_125_FS_1_U1_0_7_1 : nand2 port map( a => n5770, b => n5771, outb =>
mult_125_FS_1_P_0_7_1_port);
mult_125_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_7_0_port, b =>
mult_125_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_0_30_port);
mult_125_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_7_0_port, b =>
mult_125_FS_1_TEMP_P_0_7_0_port, outb => n5769);
mult_125_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_A1_28_port, b =>
mult_125_A2_28_port, outb =>
mult_125_FS_1_G_n_int_0_7_0_port);
mult_125_FS_1_U1_0_7_0 : nand2 port map( a => n5767, b => n5768, outb =>
mult_125_FS_1_TEMP_P_0_7_0_port);
mult_125_FS_1_U6_0_6_3 : oai12 port map( b => n5765, c => n5766, a =>
mult_125_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_FS_1_C_1_6_3_port);
mult_125_FS_1_U5_0_6_3 : oai12 port map( b => n5763, c => n5764, a =>
mult_125_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_FS_1_G_1_1_2_port);
mult_125_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_FS_1_P_0_6_3_port, outb => n5783);
mult_125_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_3_port, b =>
mult_125_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_0_29_port);
mult_125_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_3_port, b =>
mult_125_FS_1_P_0_6_3_port, outb => n5762);
mult_125_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_A1_27_port, b =>
mult_125_A2_27_port, outb =>
mult_125_FS_1_G_n_int_0_6_3_port);
mult_125_FS_1_U1_0_6_3 : nand2 port map( a => n5760, b => n5761, outb =>
mult_125_FS_1_P_0_6_3_port);
mult_125_FS_1_U6_0_6_2 : oai12 port map( b => n5758, c => n5759, a =>
mult_125_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_FS_1_C_1_6_2_port);
mult_125_FS_1_U5_0_6_2 : oai12 port map( b => n5757, c => n5766, a =>
mult_125_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_FS_1_TEMP_G_0_6_2_port);
mult_125_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_FS_1_P_0_6_2_port, outb => n5756);
mult_125_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_2_port, b =>
mult_125_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_0_28_port);
mult_125_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_2_port, b =>
mult_125_FS_1_P_0_6_2_port, outb => n5755);
mult_125_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_A1_26_port, b =>
mult_125_A2_26_port, outb =>
mult_125_FS_1_G_n_int_0_6_2_port);
mult_125_FS_1_U1_0_6_2 : nand2 port map( a => n5753, b => n5754, outb =>
mult_125_FS_1_P_0_6_2_port);
mult_125_FS_1_U6_0_6_1 : oai12 port map( b => n5782, c => n5752, a =>
mult_125_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_FS_1_C_1_6_1_port);
mult_125_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_FS_1_G_n_int_0_6_0_port, c => n5759, a =>
mult_125_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_FS_1_TEMP_G_0_6_1_port);
mult_125_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_FS_1_P_0_6_1_port, outb => n5751);
mult_125_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_1_port, b =>
mult_125_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_0_27_port);
mult_125_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_1_port, b =>
mult_125_FS_1_P_0_6_1_port, outb => n5750);
mult_125_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_A1_25_port, b =>
mult_125_A2_25_port, outb =>
mult_125_FS_1_G_n_int_0_6_1_port);
mult_125_FS_1_U1_0_6_1 : nand2 port map( a => n5748, b => n5749, outb =>
mult_125_FS_1_P_0_6_1_port);
mult_125_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_0_port, b =>
mult_125_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_0_26_port);
mult_125_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_0_port, b =>
mult_125_FS_1_TEMP_P_0_6_0_port, outb => n5747);
mult_125_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_A1_24_port, b =>
mult_125_A2_24_port, outb =>
mult_125_FS_1_G_n_int_0_6_0_port);
mult_125_FS_1_U1_0_6_0 : nand2 port map( a => n5745, b => n5746, outb =>
mult_125_FS_1_TEMP_P_0_6_0_port);
mult_125_FS_1_U6_0_5_3 : oai12 port map( b => n5743, c => n5744, a =>
mult_125_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_FS_1_C_1_5_3_port);
mult_125_FS_1_U5_0_5_3 : oai12 port map( b => n5741, c => n5742, a =>
mult_125_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_FS_1_G_1_1_1_port);
mult_125_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_FS_1_P_0_5_3_port, outb => n5780);
mult_125_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_3_port, b =>
mult_125_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_0_25_port);
mult_125_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_3_port, b =>
mult_125_FS_1_P_0_5_3_port, outb => n5740);
mult_125_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_A1_23_port, b =>
mult_125_A2_23_port, outb =>
mult_125_FS_1_G_n_int_0_5_3_port);
mult_125_FS_1_U1_0_5_3 : nand2 port map( a => n5738, b => n5739, outb =>
mult_125_FS_1_P_0_5_3_port);
mult_125_FS_1_U6_0_5_2 : oai12 port map( b => n5736, c => n5737, a =>
mult_125_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_FS_1_C_1_5_2_port);
mult_125_FS_1_U5_0_5_2 : oai12 port map( b => n5735, c => n5744, a =>
mult_125_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_FS_1_TEMP_G_0_5_2_port);
mult_125_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_FS_1_P_0_5_2_port, outb => n5734);
mult_125_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_2_port, b =>
mult_125_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_0_24_port);
mult_125_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_2_port, b =>
mult_125_FS_1_P_0_5_2_port, outb => n5733);
mult_125_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_A1_22_port, b =>
mult_125_A2_22_port, outb =>
mult_125_FS_1_G_n_int_0_5_2_port);
mult_125_FS_1_U1_0_5_2 : nand2 port map( a => n5731, b => n5732, outb =>
mult_125_FS_1_P_0_5_2_port);
mult_125_FS_1_U6_0_5_1 : oai12 port map( b => n5779, c => n5730, a =>
mult_125_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_FS_1_C_1_5_1_port);
mult_125_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_FS_1_G_n_int_0_5_0_port, c => n5737, a =>
mult_125_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_FS_1_TEMP_G_0_5_1_port);
mult_125_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_FS_1_P_0_5_1_port, outb => n5729);
mult_125_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_1_port, b =>
mult_125_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_0_23_port);
mult_125_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_1_port, b =>
mult_125_FS_1_P_0_5_1_port, outb => n5728);
mult_125_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_A1_21_port, b =>
mult_125_A2_21_port, outb =>
mult_125_FS_1_G_n_int_0_5_1_port);
mult_125_FS_1_U1_0_5_1 : nand2 port map( a => n5726, b => n5727, outb =>
mult_125_FS_1_P_0_5_1_port);
mult_125_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_0_port, b =>
mult_125_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_0_22_port);
mult_125_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_0_port, b =>
mult_125_FS_1_TEMP_P_0_5_0_port, outb => n5725);
mult_125_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_A1_20_port, b =>
mult_125_A2_20_port, outb =>
mult_125_FS_1_G_n_int_0_5_0_port);
mult_125_FS_1_U1_0_5_0 : nand2 port map( a => n5723, b => n5724, outb =>
mult_125_FS_1_TEMP_P_0_5_0_port);
mult_125_FS_1_U6_0_4_3 : oai12 port map( b => n5721, c => n5722, a =>
mult_125_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_FS_1_C_1_4_3_port);
mult_125_FS_1_U5_0_4_3 : oai12 port map( b => n5719, c => n5720, a =>
mult_125_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_FS_1_G_1_1_0_port);
mult_125_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_FS_1_P_0_4_3_port, outb => n5777);
mult_125_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_3_port, b =>
mult_125_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_0_21_port);
mult_125_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_3_port, b =>
mult_125_FS_1_P_0_4_3_port, outb => n5718);
mult_125_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_A1_19_port, b =>
mult_125_A2_19_port, outb =>
mult_125_FS_1_G_n_int_0_4_3_port);
mult_125_FS_1_U1_0_4_3 : nand2 port map( a => n5716, b => n5717, outb =>
mult_125_FS_1_P_0_4_3_port);
mult_125_FS_1_U6_0_4_2 : oai12 port map( b => n5714, c => n5715, a =>
mult_125_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_FS_1_C_1_4_2_port);
mult_125_FS_1_U5_0_4_2 : oai12 port map( b => n5713, c => n5722, a =>
mult_125_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_FS_1_TEMP_G_0_4_2_port);
mult_125_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_FS_1_P_0_4_2_port, outb => n5712);
mult_125_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_2_port, b =>
mult_125_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_0_20_port);
mult_125_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_2_port, b =>
mult_125_FS_1_P_0_4_2_port, outb => n5711);
mult_125_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_A1_18_port, b =>
mult_125_A2_18_port, outb =>
mult_125_FS_1_G_n_int_0_4_2_port);
mult_125_FS_1_U1_0_4_2 : nand2 port map( a => n5709, b => n5710, outb =>
mult_125_FS_1_P_0_4_2_port);
mult_125_FS_1_U6_0_4_1 : oai12 port map( b => n5776, c => n5708, a =>
mult_125_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_FS_1_C_1_4_1_port);
mult_125_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_FS_1_G_n_int_0_4_0_port, c => n5715, a =>
mult_125_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_FS_1_TEMP_G_0_4_1_port);
mult_125_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_FS_1_P_0_4_1_port, outb => n5707);
mult_125_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_1_port, b =>
mult_125_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_0_19_port);
mult_125_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_1_port, b =>
mult_125_FS_1_P_0_4_1_port, outb => n5706);
mult_125_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_A1_17_port, b =>
mult_125_A2_17_port, outb =>
mult_125_FS_1_G_n_int_0_4_1_port);
mult_125_FS_1_U1_0_4_1 : nand2 port map( a => n5704, b => n5705, outb =>
mult_125_FS_1_P_0_4_1_port);
mult_125_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_0_port, b =>
mult_125_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_0_18_port);
mult_125_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_0_port, b =>
mult_125_FS_1_TEMP_P_0_4_0_port, outb => n5703);
mult_125_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_A1_16_port, b =>
mult_125_A2_16_port, outb =>
mult_125_FS_1_G_n_int_0_4_0_port);
mult_125_FS_1_U1_0_4_0 : nand2 port map( a => n5701, b => n5702, outb =>
mult_125_FS_1_TEMP_P_0_4_0_port);
mult_125_FS_1_U5_0_3_3 : oai12 port map( b => n5699, c => n5700, a =>
mult_125_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_FS_1_G_1_0_3_port);
mult_125_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_3_3_port, b =>
mult_125_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_0_17_port);
mult_125_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_3_3_port, b =>
mult_125_FS_1_P_0_3_3_port, outb => n5698);
mult_125_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_A1_15_port, b =>
mult_125_A2_15_port, outb =>
mult_125_FS_1_G_n_int_0_3_3_port);
mult_125_FS_1_U1_0_3_3 : nand2 port map( a => n5696, b => n5697, outb =>
mult_125_FS_1_P_0_3_3_port);
mult_125_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_3_2_port, b =>
mult_125_FS_1_P_0_3_2_port, outb => n5695);
mult_125_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_A1_14_port, b =>
mult_125_A2_14_port, outb =>
mult_125_FS_1_G_n_int_0_3_2_port);
mult_125_FS_1_U1_0_3_2 : nand2 port map( a => n5693, b => n5694, outb =>
mult_125_FS_1_P_0_3_2_port);
mult_125_AN1_15 : inv port map( inb => coefficient_mem_array_0_15_port, outb
=> mult_125_A_not_15_port);
mult_125_AN1_14 : inv port map( inb => coefficient_mem_array_0_14_port, outb
=> mult_125_A_not_14_port);
mult_125_AN1_13 : inv port map( inb => coefficient_mem_array_0_13_port, outb
=> mult_125_A_not_13_port);
mult_125_AN1_12 : inv port map( inb => coefficient_mem_array_0_12_port, outb
=> mult_125_A_not_12_port);
mult_125_AN1_11 : inv port map( inb => coefficient_mem_array_0_11_port, outb
=> mult_125_A_not_11_port);
mult_125_AN1_10 : inv port map( inb => coefficient_mem_array_0_10_port, outb
=> mult_125_A_not_10_port);
mult_125_AN1_9 : inv port map( inb => coefficient_mem_array_0_9_port, outb
=> mult_125_A_not_9_port);
mult_125_AN1_8 : inv port map( inb => coefficient_mem_array_0_8_port, outb
=> mult_125_A_not_8_port);
mult_125_AN1_7 : inv port map( inb => coefficient_mem_array_0_7_port, outb
=> mult_125_A_not_7_port);
mult_125_AN1_6 : inv port map( inb => coefficient_mem_array_0_6_port, outb
=> mult_125_A_not_6_port);
mult_125_AN1_5 : inv port map( inb => coefficient_mem_array_0_5_port, outb
=> mult_125_A_not_5_port);
mult_125_AN1_4 : inv port map( inb => coefficient_mem_array_0_4_port, outb
=> mult_125_A_not_4_port);
mult_125_AN1_3 : inv port map( inb => coefficient_mem_array_0_3_port, outb
=> mult_125_A_not_3_port);
mult_125_AN1_2 : inv port map( inb => coefficient_mem_array_0_2_port, outb
=> mult_125_A_not_2_port);
mult_125_AN1_1 : inv port map( inb => coefficient_mem_array_0_1_port, outb
=> mult_125_A_not_1_port);
mult_125_AN1_0 : inv port map( inb => coefficient_mem_array_0_0_port, outb
=> mult_125_A_not_0_port);
mult_125_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb =>
mult_125_B_not_15_port);
mult_125_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb =>
mult_125_B_not_14_port);
mult_125_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb =>
mult_125_B_not_13_port);
mult_125_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb =>
mult_125_B_not_12_port);
mult_125_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb =>
mult_125_B_not_11_port);
mult_125_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb =>
mult_125_B_not_10_port);
mult_125_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_B_not_9_port);
mult_125_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_B_not_8_port);
mult_125_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_B_not_7_port);
mult_125_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_B_not_6_port);
mult_125_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_B_not_5_port);
mult_125_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_B_not_4_port);
mult_125_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_B_not_3_port);
mult_125_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_B_not_2_port);
mult_125_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_B_not_1_port);
mult_125_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_B_not_0_port);
mult_125_AN1_15_15 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_15_15_port);
mult_125_AN3_15_14 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_14_port, outb =>
mult_125_ab_15_14_port);
mult_125_AN3_15_13 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_13_port, outb =>
mult_125_ab_15_13_port);
mult_125_AN3_15_12 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_12_port, outb =>
mult_125_ab_15_12_port);
mult_125_AN3_15_11 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_11_port, outb =>
mult_125_ab_15_11_port);
mult_125_AN3_15_10 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_10_port, outb =>
mult_125_ab_15_10_port);
mult_125_AN3_15_9 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_9_port, outb =>
mult_125_ab_15_9_port);
mult_125_AN3_15_8 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_8_port, outb =>
mult_125_ab_15_8_port);
mult_125_AN3_15_7 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_7_port, outb =>
mult_125_ab_15_7_port);
mult_125_AN3_15_6 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_6_port, outb =>
mult_125_ab_15_6_port);
mult_125_AN3_15_5 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_5_port, outb =>
mult_125_ab_15_5_port);
mult_125_AN3_15_4 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_4_port, outb =>
mult_125_ab_15_4_port);
mult_125_AN3_15_3 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_3_port, outb =>
mult_125_ab_15_3_port);
mult_125_AN3_15_2 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_2_port, outb =>
mult_125_ab_15_2_port);
mult_125_AN3_15_1 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_1_port, outb =>
mult_125_ab_15_1_port);
mult_125_AN3_15_0 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_0_port, outb =>
mult_125_ab_15_0_port);
mult_125_AN2_14_15 : nor2 port map( a => mult_125_A_notx_14_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_14_15_port);
mult_125_AN1_14_14 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_14_14_port);
mult_125_AN1_14_13 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_14_13_port);
mult_125_AN1_14_12 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_14_12_port);
mult_125_AN1_14_11 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_14_11_port);
mult_125_AN1_14_10 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_14_10_port);
mult_125_AN1_14_9 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_14_9_port
);
mult_125_AN1_14_8 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_14_8_port
);
mult_125_AN1_14_7 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_14_7_port
);
mult_125_AN1_14_6 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_14_6_port
);
mult_125_AN1_14_5 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_14_5_port
);
mult_125_AN1_14_4 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_14_4_port
);
mult_125_AN1_14_3 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_14_3_port
);
mult_125_AN1_14_2 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_14_2_port
);
mult_125_AN1_14_1 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_14_1_port
);
mult_125_AN1_14_0_0 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_14_0_port
);
mult_125_AN2_13_15 : nor2 port map( a => mult_125_A_notx_13_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_13_15_port);
mult_125_AN1_13_14 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_13_14_port);
mult_125_AN1_13_13 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_13_13_port);
mult_125_AN1_13_12 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_13_12_port);
mult_125_AN1_13_11 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_13_11_port);
mult_125_AN1_13_10 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_13_10_port);
mult_125_AN1_13_9 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_13_9_port
);
mult_125_AN1_13_8 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_13_8_port
);
mult_125_AN1_13_7 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_13_7_port
);
mult_125_AN1_13_6 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_13_6_port
);
mult_125_AN1_13_5 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_13_5_port
);
mult_125_AN1_13_4 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_13_4_port
);
mult_125_AN1_13_3 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_13_3_port
);
mult_125_AN1_13_2 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_13_2_port
);
mult_125_AN1_13_1 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_13_1_port
);
mult_125_AN1_13_0_0 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_13_0_port
);
mult_125_AN2_12_15 : nor2 port map( a => mult_125_A_notx_12_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_12_15_port);
mult_125_AN1_12_14 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_12_14_port);
mult_125_AN1_12_13 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_12_13_port);
mult_125_AN1_12_12 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_12_12_port);
mult_125_AN1_12_11 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_12_11_port);
mult_125_AN1_12_10 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_12_10_port);
mult_125_AN1_12_9 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_12_9_port
);
mult_125_AN1_12_8 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_12_8_port
);
mult_125_AN1_12_7 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_12_7_port
);
mult_125_AN1_12_6 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_12_6_port
);
mult_125_AN1_12_5 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_12_5_port
);
mult_125_AN1_12_4 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_12_4_port
);
mult_125_AN1_12_3 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_12_3_port
);
mult_125_AN1_12_2 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_12_2_port
);
mult_125_AN1_12_1 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_12_1_port
);
mult_125_AN1_12_0_0 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_12_0_port
);
mult_125_AN2_11_15 : nor2 port map( a => mult_125_A_notx_11_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_11_15_port);
mult_125_AN1_11_14 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_11_14_port);
mult_125_AN1_11_13 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_11_13_port);
mult_125_AN1_11_12 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_11_12_port);
mult_125_AN1_11_11 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_11_11_port);
mult_125_AN1_11_10 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_11_10_port);
mult_125_AN1_11_9 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_11_9_port
);
mult_125_AN1_11_8 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_11_8_port
);
mult_125_AN1_11_7 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_11_7_port
);
mult_125_AN1_11_6 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_11_6_port
);
mult_125_AN1_11_5 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_11_5_port
);
mult_125_AN1_11_4 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_11_4_port
);
mult_125_AN1_11_3 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_11_3_port
);
mult_125_AN1_11_2 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_11_2_port
);
mult_125_AN1_11_1 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_11_1_port
);
mult_125_AN1_11_0_0 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_11_0_port
);
mult_125_AN2_10_15 : nor2 port map( a => mult_125_A_notx_10_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_10_15_port);
mult_125_AN1_10_14 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_10_14_port);
mult_125_AN1_10_13 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_10_13_port);
mult_125_AN1_10_12 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_10_12_port);
mult_125_AN1_10_11 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_10_11_port);
mult_125_AN1_10_10 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_10_10_port);
mult_125_AN1_10_9 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_10_9_port
);
mult_125_AN1_10_8 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_10_8_port
);
mult_125_AN1_10_7 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_10_7_port
);
mult_125_AN1_10_6 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_10_6_port
);
mult_125_AN1_10_5 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_10_5_port
);
mult_125_AN1_10_4 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_10_4_port
);
mult_125_AN1_10_3 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_10_3_port
);
mult_125_AN1_10_2 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_10_2_port
);
mult_125_AN1_10_1 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_10_1_port
);
mult_125_AN1_10_0_0 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_10_0_port
);
mult_125_AN2_9_15 : nor2 port map( a => mult_125_A_notx_9_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_9_15_port);
mult_125_AN1_9_14 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_9_14_port);
mult_125_AN1_9_13 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_9_13_port);
mult_125_AN1_9_12 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_9_12_port);
mult_125_AN1_9_11 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_9_11_port);
mult_125_AN1_9_10 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_9_10_port);
mult_125_AN1_9_9 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_9_9_port)
;
mult_125_AN1_9_8 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_9_8_port)
;
mult_125_AN1_9_7 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_9_7_port)
;
mult_125_AN1_9_6 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_9_6_port)
;
mult_125_AN1_9_5 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_9_5_port)
;
mult_125_AN1_9_4 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_9_4_port)
;
mult_125_AN1_9_3 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_9_3_port)
;
mult_125_AN1_9_2 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_9_2_port)
;
mult_125_AN1_9_1 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_9_1_port)
;
mult_125_AN1_9_0_0 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_9_0_port)
;
mult_125_AN2_8_15 : nor2 port map( a => mult_125_A_notx_8_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_8_15_port);
mult_125_AN1_8_14 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_8_14_port);
mult_125_AN1_8_13 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_8_13_port);
mult_125_AN1_8_12 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_8_12_port);
mult_125_AN1_8_11 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_8_11_port);
mult_125_AN1_8_10 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_8_10_port);
mult_125_AN1_8_9 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_8_9_port)
;
mult_125_AN1_8_8 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_8_8_port)
;
mult_125_AN1_8_7 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_8_7_port)
;
mult_125_AN1_8_6 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_8_6_port)
;
mult_125_AN1_8_5 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_8_5_port)
;
mult_125_AN1_8_4 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_8_4_port)
;
mult_125_AN1_8_3 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_8_3_port)
;
mult_125_AN1_8_2 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_8_2_port)
;
mult_125_AN1_8_1 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_8_1_port)
;
mult_125_AN1_8_0_0 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_8_0_port)
;
mult_125_AN2_7_15 : nor2 port map( a => mult_125_A_notx_7_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_7_15_port);
mult_125_AN1_7_14 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_7_14_port);
mult_125_AN1_7_13 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_7_13_port);
mult_125_AN1_7_12 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_7_12_port);
mult_125_AN1_7_11 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_7_11_port);
mult_125_AN1_7_10 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_7_10_port);
mult_125_AN1_7_9 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_7_9_port)
;
mult_125_AN1_7_8 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_7_8_port)
;
mult_125_AN1_7_7 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_7_7_port)
;
mult_125_AN1_7_6 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_7_6_port)
;
mult_125_AN1_7_5 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_7_5_port)
;
mult_125_AN1_7_4 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_7_4_port)
;
mult_125_AN1_7_3 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_7_3_port)
;
mult_125_AN1_7_2 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_7_2_port)
;
mult_125_AN1_7_1 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_7_1_port)
;
mult_125_AN1_7_0_0 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_7_0_port)
;
mult_125_AN2_6_15 : nor2 port map( a => mult_125_A_notx_6_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_6_15_port);
mult_125_AN1_6_14 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_6_14_port);
mult_125_AN1_6_13 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_6_13_port);
mult_125_AN1_6_12 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_6_12_port);
mult_125_AN1_6_11 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_6_11_port);
mult_125_AN1_6_10 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_6_10_port);
mult_125_AN1_6_9 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_6_9_port)
;
mult_125_AN1_6_8 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_6_8_port)
;
mult_125_AN1_6_7 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_6_7_port)
;
mult_125_AN1_6_6 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_6_6_port)
;
mult_125_AN1_6_5 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_6_5_port)
;
mult_125_AN1_6_4 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_6_4_port)
;
mult_125_AN1_6_3 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_6_3_port)
;
mult_125_AN1_6_2 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_6_2_port)
;
mult_125_AN1_6_1 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_6_1_port)
;
mult_125_AN1_6_0_0 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_6_0_port)
;
mult_125_AN2_5_15 : nor2 port map( a => mult_125_A_notx_5_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_5_15_port);
mult_125_AN1_5_14 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_5_14_port);
mult_125_AN1_5_13 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_5_13_port);
mult_125_AN1_5_12 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_5_12_port);
mult_125_AN1_5_11 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_5_11_port);
mult_125_AN1_5_10 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_5_10_port);
mult_125_AN1_5_9 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_5_9_port)
;
mult_125_AN1_5_8 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_5_8_port)
;
mult_125_AN1_5_7 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_5_7_port)
;
mult_125_AN1_5_6 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_5_6_port)
;
mult_125_AN1_5_5 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_5_5_port)
;
mult_125_AN1_5_4 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_5_4_port)
;
mult_125_AN1_5_3 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_5_3_port)
;
mult_125_AN1_5_2 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_5_2_port)
;
mult_125_AN1_5_1 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_5_1_port)
;
mult_125_AN1_5_0_0 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_5_0_port)
;
mult_125_AN2_4_15 : nor2 port map( a => mult_125_A_notx_4_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_4_15_port);
mult_125_AN1_4_14 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_4_14_port);
mult_125_AN1_4_13 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_4_13_port);
mult_125_AN1_4_12 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_4_12_port);
mult_125_AN1_4_11 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_4_11_port);
mult_125_AN1_4_10 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_4_10_port);
mult_125_AN1_4_9 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_4_9_port)
;
mult_125_AN1_4_8 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_4_8_port)
;
mult_125_AN1_4_7 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_4_7_port)
;
mult_125_AN1_4_6 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_4_6_port)
;
mult_125_AN1_4_5 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_4_5_port)
;
mult_125_AN1_4_4 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_4_4_port)
;
mult_125_AN1_4_3 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_4_3_port)
;
mult_125_AN1_4_2 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_4_2_port)
;
mult_125_AN1_4_1 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_4_1_port)
;
mult_125_AN1_4_0_0 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_4_0_port)
;
mult_125_AN2_3_15 : nor2 port map( a => mult_125_A_notx_3_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_3_15_port);
mult_125_AN1_3_14 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_3_14_port);
mult_125_AN1_3_13 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_3_13_port);
mult_125_AN1_3_12 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_3_12_port);
mult_125_AN1_3_11 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_3_11_port);
mult_125_AN1_3_10 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_3_10_port);
mult_125_AN1_3_9 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_3_9_port)
;
mult_125_AN1_3_8 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_3_8_port)
;
mult_125_AN1_3_7 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_3_7_port)
;
mult_125_AN1_3_6 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_3_6_port)
;
mult_125_AN1_3_5 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_3_5_port)
;
mult_125_AN1_3_4 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_3_4_port)
;
mult_125_AN1_3_3 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_3_3_port)
;
mult_125_AN1_3_2 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_3_2_port)
;
mult_125_AN1_3_1 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_3_1_port)
;
mult_125_AN1_3_0_0 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_3_0_port)
;
mult_125_AN2_2_15 : nor2 port map( a => mult_125_A_notx_2_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_2_15_port);
mult_125_AN1_2_14 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_2_14_port);
mult_125_AN1_2_13 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_2_13_port);
mult_125_AN1_2_12 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_2_12_port);
mult_125_AN1_2_11 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_2_11_port);
mult_125_AN1_2_10 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_2_10_port);
mult_125_AN1_2_9 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_2_9_port)
;
mult_125_AN1_2_8 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_2_8_port)
;
mult_125_AN1_2_7 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_2_7_port)
;
mult_125_AN1_2_6 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_2_6_port)
;
mult_125_AN1_2_5 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_2_5_port)
;
mult_125_AN1_2_4 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_2_4_port)
;
mult_125_AN1_2_3 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_2_3_port)
;
mult_125_AN1_2_2 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_2_2_port)
;
mult_125_AN1_2_1 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_2_1_port)
;
mult_125_AN1_2_0_0 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_2_0_port)
;
mult_125_AN2_1_15 : nor2 port map( a => mult_125_A_notx_1_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_1_15_port);
mult_125_AN1_1_14 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_1_14_port);
mult_125_AN1_1_13 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_1_13_port);
mult_125_AN1_1_12 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_1_12_port);
mult_125_AN1_1_11 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_1_11_port);
mult_125_AN1_1_10 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_1_10_port);
mult_125_AN1_1_9 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_1_9_port)
;
mult_125_AN1_1_8 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_1_8_port)
;
mult_125_AN1_1_7 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_1_7_port)
;
mult_125_AN1_1_6 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_1_6_port)
;
mult_125_AN1_1_5 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_1_5_port)
;
mult_125_AN1_1_4 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_1_4_port)
;
mult_125_AN1_1_3 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_1_3_port)
;
mult_125_AN1_1_2 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_1_2_port)
;
mult_125_AN1_1_1 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_1_1_port)
;
mult_125_AN1_1_0_0 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_1_0_port)
;
mult_125_AN2_0_15 : nor2 port map( a => mult_125_A_notx_0_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_0_15_port);
mult_125_AN1_0_14 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_0_14_port);
mult_125_AN1_0_13 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_0_13_port);
mult_125_AN1_0_12 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_0_12_port);
mult_125_AN1_0_11 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_0_11_port);
mult_125_AN1_0_10 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_0_10_port);
mult_125_AN1_0_9 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_0_9_port)
;
mult_125_AN1_0_8 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_0_8_port)
;
mult_125_AN1_0_7 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_0_7_port)
;
mult_125_AN1_0_6 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_0_6_port)
;
mult_125_AN1_0_5 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_0_5_port)
;
mult_125_AN1_0_4 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_0_4_port)
;
mult_125_AN1_0_3 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_0_3_port)
;
mult_125_AN1_0_2 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_0_2_port)
;
mult_125_AN1_0_1 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_0_1_port)
;
mult_125_AN1_0_0_0 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_0_port, outb =>
multiplier_sigs_0_0_port);
mult_125_G4_FS_1_U6_1_1_3 : oai12 port map( b => n5657, c => n5658, a =>
n5659, outb => mult_125_G4_FS_1_C_1_7_0_port);
mult_125_G4_FS_1_U6_1_1_2 : oai12 port map( b => n5654, c => n5655, a =>
n5656, outb => mult_125_G4_FS_1_C_1_6_0_port);
mult_125_G4_FS_1_U6_1_1_1 : oai12 port map( b => n5651, c => n5652, a =>
n5653, outb => mult_125_G4_FS_1_C_1_5_0_port);
mult_125_G4_FS_1_U6_0_7_1 : oai12 port map( b => n5648, c => n5649, a =>
mult_125_G4_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_G4_FS_1_C_1_7_1_port);
mult_125_G4_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_7_1_port, b =>
mult_125_G4_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_3_31_port);
mult_125_G4_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_7_1_port, b =>
mult_125_G4_FS_1_P_0_7_1_port, outb => n5647);
mult_125_G4_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_G4_A1_29_port, b
=> mult_125_G4_A2_29_port, outb =>
mult_125_G4_FS_1_G_n_int_0_7_1_port);
mult_125_G4_FS_1_U1_0_7_1 : nand2 port map( a => n5645, b => n5646, outb =>
mult_125_G4_FS_1_P_0_7_1_port);
mult_125_G4_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_7_0_port, b =>
mult_125_G4_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_3_30_port);
mult_125_G4_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_7_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_7_0_port, outb => n5644);
mult_125_G4_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_G4_A1_28_port, b
=> mult_125_G4_A2_28_port, outb =>
mult_125_G4_FS_1_G_n_int_0_7_0_port);
mult_125_G4_FS_1_U1_0_7_0 : nand2 port map( a => n5642, b => n5643, outb =>
mult_125_G4_FS_1_TEMP_P_0_7_0_port);
mult_125_G4_FS_1_U6_0_6_3 : oai12 port map( b => n5640, c => n5641, a =>
mult_125_G4_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G4_FS_1_C_1_6_3_port);
mult_125_G4_FS_1_U5_0_6_3 : oai12 port map( b => n5638, c => n5639, a =>
mult_125_G4_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_G4_FS_1_G_1_1_2_port);
mult_125_G4_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_G4_FS_1_P_0_6_3_port, outb => n5658);
mult_125_G4_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_3_port, b =>
mult_125_G4_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_3_29_port);
mult_125_G4_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_3_port, b =>
mult_125_G4_FS_1_P_0_6_3_port, outb => n5637);
mult_125_G4_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_G4_A1_27_port, b
=> mult_125_G4_A2_27_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_3_port);
mult_125_G4_FS_1_U1_0_6_3 : nand2 port map( a => n5635, b => n5636, outb =>
mult_125_G4_FS_1_P_0_6_3_port);
mult_125_G4_FS_1_U6_0_6_2 : oai12 port map( b => n5633, c => n5634, a =>
mult_125_G4_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G4_FS_1_C_1_6_2_port);
mult_125_G4_FS_1_U5_0_6_2 : oai12 port map( b => n5632, c => n5641, a =>
mult_125_G4_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_6_2_port);
mult_125_G4_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_G4_FS_1_P_0_6_2_port, outb => n5631);
mult_125_G4_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_2_port, b =>
mult_125_G4_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_3_28_port);
mult_125_G4_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_2_port, b =>
mult_125_G4_FS_1_P_0_6_2_port, outb => n5630);
mult_125_G4_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_G4_A1_26_port, b
=> mult_125_G4_A2_26_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_2_port);
mult_125_G4_FS_1_U1_0_6_2 : nand2 port map( a => n5628, b => n5629, outb =>
mult_125_G4_FS_1_P_0_6_2_port);
mult_125_G4_FS_1_U6_0_6_1 : oai12 port map( b => n5657, c => n5627, a =>
mult_125_G4_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_G4_FS_1_C_1_6_1_port);
mult_125_G4_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_G4_FS_1_G_n_int_0_6_0_port, c => n5634, a
=> mult_125_G4_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_6_1_port);
mult_125_G4_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_G4_FS_1_P_0_6_1_port, outb => n5626);
mult_125_G4_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_1_port, b =>
mult_125_G4_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_3_27_port);
mult_125_G4_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_1_port, b =>
mult_125_G4_FS_1_P_0_6_1_port, outb => n5625);
mult_125_G4_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_G4_A1_25_port, b
=> mult_125_G4_A2_25_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_1_port);
mult_125_G4_FS_1_U1_0_6_1 : nand2 port map( a => n5623, b => n5624, outb =>
mult_125_G4_FS_1_P_0_6_1_port);
mult_125_G4_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_0_port, b =>
mult_125_G4_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_3_26_port);
mult_125_G4_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_6_0_port, outb => n5622);
mult_125_G4_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_G4_A1_24_port, b
=> mult_125_G4_A2_24_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_0_port);
mult_125_G4_FS_1_U1_0_6_0 : nand2 port map( a => n5620, b => n5621, outb =>
mult_125_G4_FS_1_TEMP_P_0_6_0_port);
mult_125_G4_FS_1_U6_0_5_3 : oai12 port map( b => n5618, c => n5619, a =>
mult_125_G4_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G4_FS_1_C_1_5_3_port);
mult_125_G4_FS_1_U5_0_5_3 : oai12 port map( b => n5616, c => n5617, a =>
mult_125_G4_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_G4_FS_1_G_1_1_1_port);
mult_125_G4_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_G4_FS_1_P_0_5_3_port, outb => n5655);
mult_125_G4_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_3_port, b =>
mult_125_G4_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_3_25_port);
mult_125_G4_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_3_port, b =>
mult_125_G4_FS_1_P_0_5_3_port, outb => n5615);
mult_125_G4_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_G4_A1_23_port, b
=> mult_125_G4_A2_23_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_3_port);
mult_125_G4_FS_1_U1_0_5_3 : nand2 port map( a => n5613, b => n5614, outb =>
mult_125_G4_FS_1_P_0_5_3_port);
mult_125_G4_FS_1_U6_0_5_2 : oai12 port map( b => n5611, c => n5612, a =>
mult_125_G4_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G4_FS_1_C_1_5_2_port);
mult_125_G4_FS_1_U5_0_5_2 : oai12 port map( b => n5610, c => n5619, a =>
mult_125_G4_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_5_2_port);
mult_125_G4_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_G4_FS_1_P_0_5_2_port, outb => n5609);
mult_125_G4_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_2_port, b =>
mult_125_G4_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_3_24_port);
mult_125_G4_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_2_port, b =>
mult_125_G4_FS_1_P_0_5_2_port, outb => n5608);
mult_125_G4_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_G4_A1_22_port, b
=> mult_125_G4_A2_22_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_2_port);
mult_125_G4_FS_1_U1_0_5_2 : nand2 port map( a => n5606, b => n5607, outb =>
mult_125_G4_FS_1_P_0_5_2_port);
mult_125_G4_FS_1_U6_0_5_1 : oai12 port map( b => n5654, c => n5605, a =>
mult_125_G4_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_G4_FS_1_C_1_5_1_port);
mult_125_G4_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_G4_FS_1_G_n_int_0_5_0_port, c => n5612, a
=> mult_125_G4_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_5_1_port);
mult_125_G4_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_G4_FS_1_P_0_5_1_port, outb => n5604);
mult_125_G4_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_1_port, b =>
mult_125_G4_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_3_23_port);
mult_125_G4_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_1_port, b =>
mult_125_G4_FS_1_P_0_5_1_port, outb => n5603);
mult_125_G4_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_G4_A1_21_port, b
=> mult_125_G4_A2_21_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_1_port);
mult_125_G4_FS_1_U1_0_5_1 : nand2 port map( a => n5601, b => n5602, outb =>
mult_125_G4_FS_1_P_0_5_1_port);
mult_125_G4_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_0_port, b =>
mult_125_G4_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_3_22_port);
mult_125_G4_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_5_0_port, outb => n5600);
mult_125_G4_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_G4_A1_20_port, b
=> mult_125_G4_A2_20_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_0_port);
mult_125_G4_FS_1_U1_0_5_0 : nand2 port map( a => n5598, b => n5599, outb =>
mult_125_G4_FS_1_TEMP_P_0_5_0_port);
mult_125_G4_FS_1_U6_0_4_3 : oai12 port map( b => n5596, c => n5597, a =>
mult_125_G4_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G4_FS_1_C_1_4_3_port);
mult_125_G4_FS_1_U5_0_4_3 : oai12 port map( b => n5594, c => n5595, a =>
mult_125_G4_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_G4_FS_1_G_1_1_0_port);
mult_125_G4_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_G4_FS_1_P_0_4_3_port, outb => n5652);
mult_125_G4_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_3_port, b =>
mult_125_G4_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_3_21_port);
mult_125_G4_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_3_port, b =>
mult_125_G4_FS_1_P_0_4_3_port, outb => n5593);
mult_125_G4_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_G4_A1_19_port, b
=> mult_125_G4_A2_19_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_3_port);
mult_125_G4_FS_1_U1_0_4_3 : nand2 port map( a => n5591, b => n5592, outb =>
mult_125_G4_FS_1_P_0_4_3_port);
mult_125_G4_FS_1_U6_0_4_2 : oai12 port map( b => n5589, c => n5590, a =>
mult_125_G4_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G4_FS_1_C_1_4_2_port);
mult_125_G4_FS_1_U5_0_4_2 : oai12 port map( b => n5588, c => n5597, a =>
mult_125_G4_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_4_2_port);
mult_125_G4_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_G4_FS_1_P_0_4_2_port, outb => n5587);
mult_125_G4_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_2_port, b =>
mult_125_G4_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_3_20_port);
mult_125_G4_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_2_port, b =>
mult_125_G4_FS_1_P_0_4_2_port, outb => n5586);
mult_125_G4_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_G4_A1_18_port, b
=> mult_125_G4_A2_18_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_2_port);
mult_125_G4_FS_1_U1_0_4_2 : nand2 port map( a => n5584, b => n5585, outb =>
mult_125_G4_FS_1_P_0_4_2_port);
mult_125_G4_FS_1_U6_0_4_1 : oai12 port map( b => n5651, c => n5583, a =>
mult_125_G4_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_G4_FS_1_C_1_4_1_port);
mult_125_G4_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_G4_FS_1_G_n_int_0_4_0_port, c => n5590, a
=> mult_125_G4_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_4_1_port);
mult_125_G4_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_G4_FS_1_P_0_4_1_port, outb => n5582);
mult_125_G4_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_1_port, b =>
mult_125_G4_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_3_19_port);
mult_125_G4_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_1_port, b =>
mult_125_G4_FS_1_P_0_4_1_port, outb => n5581);
mult_125_G4_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_G4_A1_17_port, b
=> mult_125_G4_A2_17_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_1_port);
mult_125_G4_FS_1_U1_0_4_1 : nand2 port map( a => n5579, b => n5580, outb =>
mult_125_G4_FS_1_P_0_4_1_port);
mult_125_G4_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_0_port, b =>
mult_125_G4_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_3_18_port);
mult_125_G4_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_4_0_port, outb => n5578);
mult_125_G4_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_G4_A1_16_port, b
=> mult_125_G4_A2_16_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_0_port);
mult_125_G4_FS_1_U1_0_4_0 : nand2 port map( a => n5576, b => n5577, outb =>
mult_125_G4_FS_1_TEMP_P_0_4_0_port);
mult_125_G4_FS_1_U5_0_3_3 : oai12 port map( b => n5574, c => n5575, a =>
mult_125_G4_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_G4_FS_1_G_1_0_3_port);
mult_125_G4_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_3_3_port, b =>
mult_125_G4_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_3_17_port);
mult_125_G4_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_3_3_port, b =>
mult_125_G4_FS_1_P_0_3_3_port, outb => n5573);
mult_125_G4_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_G4_A1_15_port, b
=> mult_125_G4_A2_15_port, outb =>
mult_125_G4_FS_1_G_n_int_0_3_3_port);
mult_125_G4_FS_1_U1_0_3_3 : nand2 port map( a => n5571, b => n5572, outb =>
mult_125_G4_FS_1_P_0_3_3_port);
mult_125_G4_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_3_2_port, b =>
mult_125_G4_FS_1_P_0_3_2_port, outb => n5570);
mult_125_G4_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_G4_A1_14_port, b
=> mult_125_G4_A2_14_port, outb =>
mult_125_G4_FS_1_G_n_int_0_3_2_port);
mult_125_G4_FS_1_U1_0_3_2 : nand2 port map( a => n5568, b => n5569, outb =>
mult_125_G4_FS_1_P_0_3_2_port);
mult_125_G4_AN1_15 : inv port map( inb => coefficient_mem_array_3_15_port,
outb => mult_125_G4_A_not_15_port);
mult_125_G4_AN1_14 : inv port map( inb => coefficient_mem_array_3_14_port,
outb => mult_125_G4_A_not_14_port);
mult_125_G4_AN1_13 : inv port map( inb => coefficient_mem_array_3_13_port,
outb => mult_125_G4_A_not_13_port);
mult_125_G4_AN1_12 : inv port map( inb => coefficient_mem_array_3_12_port,
outb => mult_125_G4_A_not_12_port);
mult_125_G4_AN1_11 : inv port map( inb => coefficient_mem_array_3_11_port,
outb => mult_125_G4_A_not_11_port);
mult_125_G4_AN1_10 : inv port map( inb => coefficient_mem_array_3_10_port,
outb => mult_125_G4_A_not_10_port);
mult_125_G4_AN1_9 : inv port map( inb => coefficient_mem_array_3_9_port,
outb => mult_125_G4_A_not_9_port);
mult_125_G4_AN1_8 : inv port map( inb => coefficient_mem_array_3_8_port,
outb => mult_125_G4_A_not_8_port);
mult_125_G4_AN1_7 : inv port map( inb => coefficient_mem_array_3_7_port,
outb => mult_125_G4_A_not_7_port);
mult_125_G4_AN1_6 : inv port map( inb => coefficient_mem_array_3_6_port,
outb => mult_125_G4_A_not_6_port);
mult_125_G4_AN1_5 : inv port map( inb => coefficient_mem_array_3_5_port,
outb => mult_125_G4_A_not_5_port);
mult_125_G4_AN1_4 : inv port map( inb => coefficient_mem_array_3_4_port,
outb => mult_125_G4_A_not_4_port);
mult_125_G4_AN1_3 : inv port map( inb => coefficient_mem_array_3_3_port,
outb => mult_125_G4_A_not_3_port);
mult_125_G4_AN1_2 : inv port map( inb => coefficient_mem_array_3_2_port,
outb => mult_125_G4_A_not_2_port);
mult_125_G4_AN1_1 : inv port map( inb => coefficient_mem_array_3_1_port,
outb => mult_125_G4_A_not_1_port);
mult_125_G4_AN1_0 : inv port map( inb => coefficient_mem_array_3_0_port,
outb => mult_125_G4_A_not_0_port);
mult_125_G4_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb
=> mult_125_G4_B_not_15_port);
mult_125_G4_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb
=> mult_125_G4_B_not_14_port);
mult_125_G4_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb
=> mult_125_G4_B_not_13_port);
mult_125_G4_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb
=> mult_125_G4_B_not_12_port);
mult_125_G4_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb
=> mult_125_G4_B_not_11_port);
mult_125_G4_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb
=> mult_125_G4_B_not_10_port);
mult_125_G4_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_G4_B_not_9_port);
mult_125_G4_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_G4_B_not_8_port);
mult_125_G4_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_G4_B_not_7_port);
mult_125_G4_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_G4_B_not_6_port);
mult_125_G4_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_G4_B_not_5_port);
mult_125_G4_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_G4_B_not_4_port);
mult_125_G4_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_G4_B_not_3_port);
mult_125_G4_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_G4_B_not_2_port);
mult_125_G4_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_G4_B_not_1_port);
mult_125_G4_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_G4_B_not_0_port);
mult_125_G4_AN1_15_15 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_15_15_port);
mult_125_G4_AN3_15_14 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_14_port, outb =>
mult_125_G4_ab_15_14_port);
mult_125_G4_AN3_15_13 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_13_port, outb =>
mult_125_G4_ab_15_13_port);
mult_125_G4_AN3_15_12 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_12_port, outb =>
mult_125_G4_ab_15_12_port);
mult_125_G4_AN3_15_11 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_11_port, outb =>
mult_125_G4_ab_15_11_port);
mult_125_G4_AN3_15_10 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_10_port, outb =>
mult_125_G4_ab_15_10_port);
mult_125_G4_AN3_15_9 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_9_port, outb =>
mult_125_G4_ab_15_9_port);
mult_125_G4_AN3_15_8 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_8_port, outb =>
mult_125_G4_ab_15_8_port);
mult_125_G4_AN3_15_7 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_7_port, outb =>
mult_125_G4_ab_15_7_port);
mult_125_G4_AN3_15_6 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_6_port, outb =>
mult_125_G4_ab_15_6_port);
mult_125_G4_AN3_15_5 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_5_port, outb =>
mult_125_G4_ab_15_5_port);
mult_125_G4_AN3_15_4 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_4_port, outb =>
mult_125_G4_ab_15_4_port);
mult_125_G4_AN3_15_3 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_3_port, outb =>
mult_125_G4_ab_15_3_port);
mult_125_G4_AN3_15_2 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_2_port, outb =>
mult_125_G4_ab_15_2_port);
mult_125_G4_AN3_15_1 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_1_port, outb =>
mult_125_G4_ab_15_1_port);
mult_125_G4_AN3_15_0 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_0_port, outb =>
mult_125_G4_ab_15_0_port);
mult_125_G4_AN2_14_15 : nor2 port map( a => mult_125_G4_A_notx_14_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_14_15_port);
mult_125_G4_AN1_14_14 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_14_14_port);
mult_125_G4_AN1_14_13 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_14_13_port);
mult_125_G4_AN1_14_12 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_14_12_port);
mult_125_G4_AN1_14_11 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_14_11_port);
mult_125_G4_AN1_14_10 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_14_10_port);
mult_125_G4_AN1_14_9 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_14_9_port);
mult_125_G4_AN1_14_8 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_14_8_port);
mult_125_G4_AN1_14_7 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_14_7_port);
mult_125_G4_AN1_14_6 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_14_6_port);
mult_125_G4_AN1_14_5 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_14_5_port);
mult_125_G4_AN1_14_4 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_14_4_port);
mult_125_G4_AN1_14_3 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_14_3_port);
mult_125_G4_AN1_14_2 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_14_2_port);
mult_125_G4_AN1_14_1 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_14_1_port);
mult_125_G4_AN1_14_0_0 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_14_0_port);
mult_125_G4_AN2_13_15 : nor2 port map( a => mult_125_G4_A_notx_13_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_13_15_port);
mult_125_G4_AN1_13_14 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_13_14_port);
mult_125_G4_AN1_13_13 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_13_13_port);
mult_125_G4_AN1_13_12 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_13_12_port);
mult_125_G4_AN1_13_11 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_13_11_port);
mult_125_G4_AN1_13_10 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_13_10_port);
mult_125_G4_AN1_13_9 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_13_9_port);
mult_125_G4_AN1_13_8 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_13_8_port);
mult_125_G4_AN1_13_7 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_13_7_port);
mult_125_G4_AN1_13_6 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_13_6_port);
mult_125_G4_AN1_13_5 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_13_5_port);
mult_125_G4_AN1_13_4 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_13_4_port);
mult_125_G4_AN1_13_3 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_13_3_port);
mult_125_G4_AN1_13_2 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_13_2_port);
mult_125_G4_AN1_13_1 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_13_1_port);
mult_125_G4_AN1_13_0_0 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_13_0_port);
mult_125_G4_AN2_12_15 : nor2 port map( a => mult_125_G4_A_notx_12_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_12_15_port);
mult_125_G4_AN1_12_14 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_12_14_port);
mult_125_G4_AN1_12_13 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_12_13_port);
mult_125_G4_AN1_12_12 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_12_12_port);
mult_125_G4_AN1_12_11 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_12_11_port);
mult_125_G4_AN1_12_10 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_12_10_port);
mult_125_G4_AN1_12_9 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_12_9_port);
mult_125_G4_AN1_12_8 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_12_8_port);
mult_125_G4_AN1_12_7 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_12_7_port);
mult_125_G4_AN1_12_6 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_12_6_port);
mult_125_G4_AN1_12_5 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_12_5_port);
mult_125_G4_AN1_12_4 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_12_4_port);
mult_125_G4_AN1_12_3 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_12_3_port);
mult_125_G4_AN1_12_2 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_12_2_port);
mult_125_G4_AN1_12_1 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_12_1_port);
mult_125_G4_AN1_12_0_0 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_12_0_port);
mult_125_G4_AN2_11_15 : nor2 port map( a => mult_125_G4_A_notx_11_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_11_15_port);
mult_125_G4_AN1_11_14 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_11_14_port);
mult_125_G4_AN1_11_13 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_11_13_port);
mult_125_G4_AN1_11_12 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_11_12_port);
mult_125_G4_AN1_11_11 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_11_11_port);
mult_125_G4_AN1_11_10 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_11_10_port);
mult_125_G4_AN1_11_9 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_11_9_port);
mult_125_G4_AN1_11_8 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_11_8_port);
mult_125_G4_AN1_11_7 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_11_7_port);
mult_125_G4_AN1_11_6 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_11_6_port);
mult_125_G4_AN1_11_5 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_11_5_port);
mult_125_G4_AN1_11_4 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_11_4_port);
mult_125_G4_AN1_11_3 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_11_3_port);
mult_125_G4_AN1_11_2 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_11_2_port);
mult_125_G4_AN1_11_1 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_11_1_port);
mult_125_G4_AN1_11_0_0 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_11_0_port);
mult_125_G4_AN2_10_15 : nor2 port map( a => mult_125_G4_A_notx_10_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_10_15_port);
mult_125_G4_AN1_10_14 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_10_14_port);
mult_125_G4_AN1_10_13 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_10_13_port);
mult_125_G4_AN1_10_12 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_10_12_port);
mult_125_G4_AN1_10_11 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_10_11_port);
mult_125_G4_AN1_10_10 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_10_10_port);
mult_125_G4_AN1_10_9 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_10_9_port);
mult_125_G4_AN1_10_8 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_10_8_port);
mult_125_G4_AN1_10_7 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_10_7_port);
mult_125_G4_AN1_10_6 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_10_6_port);
mult_125_G4_AN1_10_5 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_10_5_port);
mult_125_G4_AN1_10_4 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_10_4_port);
mult_125_G4_AN1_10_3 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_10_3_port);
mult_125_G4_AN1_10_2 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_10_2_port);
mult_125_G4_AN1_10_1 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_10_1_port);
mult_125_G4_AN1_10_0_0 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_10_0_port);
mult_125_G4_AN2_9_15 : nor2 port map( a => mult_125_G4_A_notx_9_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_9_15_port);
mult_125_G4_AN1_9_14 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_9_14_port);
mult_125_G4_AN1_9_13 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_9_13_port);
mult_125_G4_AN1_9_12 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_9_12_port);
mult_125_G4_AN1_9_11 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_9_11_port);
mult_125_G4_AN1_9_10 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_9_10_port);
mult_125_G4_AN1_9_9 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_9_9_port);
mult_125_G4_AN1_9_8 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_9_8_port);
mult_125_G4_AN1_9_7 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_9_7_port);
mult_125_G4_AN1_9_6 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_9_6_port);
mult_125_G4_AN1_9_5 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_9_5_port);
mult_125_G4_AN1_9_4 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_9_4_port);
mult_125_G4_AN1_9_3 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_9_3_port);
mult_125_G4_AN1_9_2 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_9_2_port);
mult_125_G4_AN1_9_1 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_9_1_port);
mult_125_G4_AN1_9_0_0 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_9_0_port);
mult_125_G4_AN2_8_15 : nor2 port map( a => mult_125_G4_A_notx_8_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_8_15_port);
mult_125_G4_AN1_8_14 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_8_14_port);
mult_125_G4_AN1_8_13 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_8_13_port);
mult_125_G4_AN1_8_12 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_8_12_port);
mult_125_G4_AN1_8_11 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_8_11_port);
mult_125_G4_AN1_8_10 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_8_10_port);
mult_125_G4_AN1_8_9 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_8_9_port);
mult_125_G4_AN1_8_8 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_8_8_port);
mult_125_G4_AN1_8_7 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_8_7_port);
mult_125_G4_AN1_8_6 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_8_6_port);
mult_125_G4_AN1_8_5 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_8_5_port);
mult_125_G4_AN1_8_4 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_8_4_port);
mult_125_G4_AN1_8_3 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_8_3_port);
mult_125_G4_AN1_8_2 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_8_2_port);
mult_125_G4_AN1_8_1 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_8_1_port);
mult_125_G4_AN1_8_0_0 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_8_0_port);
mult_125_G4_AN2_7_15 : nor2 port map( a => mult_125_G4_A_notx_7_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_7_15_port);
mult_125_G4_AN1_7_14 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_7_14_port);
mult_125_G4_AN1_7_13 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_7_13_port);
mult_125_G4_AN1_7_12 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_7_12_port);
mult_125_G4_AN1_7_11 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_7_11_port);
mult_125_G4_AN1_7_10 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_7_10_port);
mult_125_G4_AN1_7_9 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_7_9_port);
mult_125_G4_AN1_7_8 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_7_8_port);
mult_125_G4_AN1_7_7 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_7_7_port);
mult_125_G4_AN1_7_6 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_7_6_port);
mult_125_G4_AN1_7_5 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_7_5_port);
mult_125_G4_AN1_7_4 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_7_4_port);
mult_125_G4_AN1_7_3 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_7_3_port);
mult_125_G4_AN1_7_2 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_7_2_port);
mult_125_G4_AN1_7_1 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_7_1_port);
mult_125_G4_AN1_7_0_0 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_7_0_port);
mult_125_G4_AN2_6_15 : nor2 port map( a => mult_125_G4_A_notx_6_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_6_15_port);
mult_125_G4_AN1_6_14 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_6_14_port);
mult_125_G4_AN1_6_13 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_6_13_port);
mult_125_G4_AN1_6_12 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_6_12_port);
mult_125_G4_AN1_6_11 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_6_11_port);
mult_125_G4_AN1_6_10 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_6_10_port);
mult_125_G4_AN1_6_9 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_6_9_port);
mult_125_G4_AN1_6_8 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_6_8_port);
mult_125_G4_AN1_6_7 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_6_7_port);
mult_125_G4_AN1_6_6 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_6_6_port);
mult_125_G4_AN1_6_5 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_6_5_port);
mult_125_G4_AN1_6_4 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_6_4_port);
mult_125_G4_AN1_6_3 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_6_3_port);
mult_125_G4_AN1_6_2 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_6_2_port);
mult_125_G4_AN1_6_1 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_6_1_port);
mult_125_G4_AN1_6_0_0 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_6_0_port);
mult_125_G4_AN2_5_15 : nor2 port map( a => mult_125_G4_A_notx_5_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_5_15_port);
mult_125_G4_AN1_5_14 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_5_14_port);
mult_125_G4_AN1_5_13 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_5_13_port);
mult_125_G4_AN1_5_12 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_5_12_port);
mult_125_G4_AN1_5_11 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_5_11_port);
mult_125_G4_AN1_5_10 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_5_10_port);
mult_125_G4_AN1_5_9 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_5_9_port);
mult_125_G4_AN1_5_8 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_5_8_port);
mult_125_G4_AN1_5_7 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_5_7_port);
mult_125_G4_AN1_5_6 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_5_6_port);
mult_125_G4_AN1_5_5 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_5_5_port);
mult_125_G4_AN1_5_4 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_5_4_port);
mult_125_G4_AN1_5_3 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_5_3_port);
mult_125_G4_AN1_5_2 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_5_2_port);
mult_125_G4_AN1_5_1 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_5_1_port);
mult_125_G4_AN1_5_0_0 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_5_0_port);
mult_125_G4_AN2_4_15 : nor2 port map( a => mult_125_G4_A_notx_4_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_4_15_port);
mult_125_G4_AN1_4_14 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_4_14_port);
mult_125_G4_AN1_4_13 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_4_13_port);
mult_125_G4_AN1_4_12 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_4_12_port);
mult_125_G4_AN1_4_11 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_4_11_port);
mult_125_G4_AN1_4_10 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_4_10_port);
mult_125_G4_AN1_4_9 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_4_9_port);
mult_125_G4_AN1_4_8 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_4_8_port);
mult_125_G4_AN1_4_7 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_4_7_port);
mult_125_G4_AN1_4_6 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_4_6_port);
mult_125_G4_AN1_4_5 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_4_5_port);
mult_125_G4_AN1_4_4 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_4_4_port);
mult_125_G4_AN1_4_3 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_4_3_port);
mult_125_G4_AN1_4_2 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_4_2_port);
mult_125_G4_AN1_4_1 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_4_1_port);
mult_125_G4_AN1_4_0_0 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_4_0_port);
mult_125_G4_AN2_3_15 : nor2 port map( a => mult_125_G4_A_notx_3_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_3_15_port);
mult_125_G4_AN1_3_14 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_3_14_port);
mult_125_G4_AN1_3_13 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_3_13_port);
mult_125_G4_AN1_3_12 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_3_12_port);
mult_125_G4_AN1_3_11 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_3_11_port);
mult_125_G4_AN1_3_10 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_3_10_port);
mult_125_G4_AN1_3_9 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_3_9_port);
mult_125_G4_AN1_3_8 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_3_8_port);
mult_125_G4_AN1_3_7 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_3_7_port);
mult_125_G4_AN1_3_6 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_3_6_port);
mult_125_G4_AN1_3_5 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_3_5_port);
mult_125_G4_AN1_3_4 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_3_4_port);
mult_125_G4_AN1_3_3 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_3_3_port);
mult_125_G4_AN1_3_2 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_3_2_port);
mult_125_G4_AN1_3_1 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_3_1_port);
mult_125_G4_AN1_3_0_0 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_3_0_port);
mult_125_G4_AN2_2_15 : nor2 port map( a => mult_125_G4_A_notx_2_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_2_15_port);
mult_125_G4_AN1_2_14 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_2_14_port);
mult_125_G4_AN1_2_13 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_2_13_port);
mult_125_G4_AN1_2_12 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_2_12_port);
mult_125_G4_AN1_2_11 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_2_11_port);
mult_125_G4_AN1_2_10 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_2_10_port);
mult_125_G4_AN1_2_9 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_2_9_port);
mult_125_G4_AN1_2_8 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_2_8_port);
mult_125_G4_AN1_2_7 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_2_7_port);
mult_125_G4_AN1_2_6 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_2_6_port);
mult_125_G4_AN1_2_5 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_2_5_port);
mult_125_G4_AN1_2_4 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_2_4_port);
mult_125_G4_AN1_2_3 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_2_3_port);
mult_125_G4_AN1_2_2 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_2_2_port);
mult_125_G4_AN1_2_1 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_2_1_port);
mult_125_G4_AN1_2_0_0 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_2_0_port);
mult_125_G4_AN2_1_15 : nor2 port map( a => mult_125_G4_A_notx_1_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_1_15_port);
mult_125_G4_AN1_1_14 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_1_14_port);
mult_125_G4_AN1_1_13 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_1_13_port);
mult_125_G4_AN1_1_12 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_1_12_port);
mult_125_G4_AN1_1_11 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_1_11_port);
mult_125_G4_AN1_1_10 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_1_10_port);
mult_125_G4_AN1_1_9 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_1_9_port);
mult_125_G4_AN1_1_8 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_1_8_port);
mult_125_G4_AN1_1_7 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_1_7_port);
mult_125_G4_AN1_1_6 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_1_6_port);
mult_125_G4_AN1_1_5 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_1_5_port);
mult_125_G4_AN1_1_4 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_1_4_port);
mult_125_G4_AN1_1_3 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_1_3_port);
mult_125_G4_AN1_1_2 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_1_2_port);
mult_125_G4_AN1_1_1 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_1_1_port);
mult_125_G4_AN1_1_0_0 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_1_0_port);
mult_125_G4_AN2_0_15 : nor2 port map( a => mult_125_G4_A_notx_0_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_0_15_port);
mult_125_G4_AN1_0_14 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_0_14_port);
mult_125_G4_AN1_0_13 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_0_13_port);
mult_125_G4_AN1_0_12 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_0_12_port);
mult_125_G4_AN1_0_11 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_0_11_port);
mult_125_G4_AN1_0_10 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_0_10_port);
mult_125_G4_AN1_0_9 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_0_9_port);
mult_125_G4_AN1_0_8 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_0_8_port);
mult_125_G4_AN1_0_7 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_0_7_port);
mult_125_G4_AN1_0_6 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_0_6_port);
mult_125_G4_AN1_0_5 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_0_5_port);
mult_125_G4_AN1_0_4 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_0_4_port);
mult_125_G4_AN1_0_3 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_0_3_port);
mult_125_G4_AN1_0_2 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_0_2_port);
mult_125_G4_AN1_0_1 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_0_1_port);
mult_125_G4_AN1_0_0_0 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_0_port, outb =>
multiplier_sigs_3_0_port);
U267 : inv port map( inb => input_sample_mem_15_port, outb => n5911);
U268 : inv port map( inb => coefficient_mem_array_2_15_port, outb => n5912);
U269 : inv port map( inb => mult_125_G3_B_not_15_port, outb => n5913);
U270 : inv port map( inb => mult_125_G3_A_not_15_port, outb => n5914);
U271 : inv port map( inb => mult_125_G3_A_not_0_port, outb =>
mult_125_G3_A_notx_0_port);
U272 : inv port map( inb => mult_125_G3_A_not_1_port, outb =>
mult_125_G3_A_notx_1_port);
U273 : inv port map( inb => mult_125_G3_A_not_2_port, outb =>
mult_125_G3_A_notx_2_port);
U274 : inv port map( inb => mult_125_G3_A_not_3_port, outb =>
mult_125_G3_A_notx_3_port);
U275 : inv port map( inb => mult_125_G3_A_not_4_port, outb =>
mult_125_G3_A_notx_4_port);
U276 : inv port map( inb => mult_125_G3_A_not_5_port, outb =>
mult_125_G3_A_notx_5_port);
U277 : inv port map( inb => mult_125_G3_A_not_6_port, outb =>
mult_125_G3_A_notx_6_port);
U278 : inv port map( inb => mult_125_G3_A_not_7_port, outb =>
mult_125_G3_A_notx_7_port);
U279 : inv port map( inb => mult_125_G3_A_not_8_port, outb =>
mult_125_G3_A_notx_8_port);
U280 : inv port map( inb => mult_125_G3_A_not_9_port, outb =>
mult_125_G3_A_notx_9_port);
U281 : inv port map( inb => mult_125_G3_A_not_10_port, outb =>
mult_125_G3_A_notx_10_port);
U282 : inv port map( inb => mult_125_G3_A_not_11_port, outb =>
mult_125_G3_A_notx_11_port);
U283 : inv port map( inb => mult_125_G3_A_not_12_port, outb =>
mult_125_G3_A_notx_12_port);
U284 : inv port map( inb => mult_125_G3_A_not_13_port, outb =>
mult_125_G3_A_notx_13_port);
U285 : inv port map( inb => mult_125_G3_A_not_14_port, outb =>
mult_125_G3_A_notx_14_port);
U286 : inv port map( inb => mult_125_G3_B_not_0_port, outb =>
mult_125_G3_B_notx_0_port);
U287 : inv port map( inb => mult_125_G3_B_not_1_port, outb =>
mult_125_G3_B_notx_1_port);
U288 : inv port map( inb => mult_125_G3_B_not_2_port, outb =>
mult_125_G3_B_notx_2_port);
U289 : inv port map( inb => mult_125_G3_B_not_3_port, outb =>
mult_125_G3_B_notx_3_port);
U290 : inv port map( inb => mult_125_G3_B_not_4_port, outb =>
mult_125_G3_B_notx_4_port);
U291 : inv port map( inb => mult_125_G3_B_not_5_port, outb =>
mult_125_G3_B_notx_5_port);
U292 : inv port map( inb => mult_125_G3_B_not_6_port, outb =>
mult_125_G3_B_notx_6_port);
U293 : inv port map( inb => mult_125_G3_B_not_7_port, outb =>
mult_125_G3_B_notx_7_port);
U294 : inv port map( inb => mult_125_G3_B_not_8_port, outb =>
mult_125_G3_B_notx_8_port);
U295 : inv port map( inb => mult_125_G3_B_not_9_port, outb =>
mult_125_G3_B_notx_9_port);
U296 : inv port map( inb => mult_125_G3_B_not_10_port, outb =>
mult_125_G3_B_notx_10_port);
U297 : inv port map( inb => mult_125_G3_B_not_11_port, outb =>
mult_125_G3_B_notx_11_port);
U298 : inv port map( inb => mult_125_G3_B_not_12_port, outb =>
mult_125_G3_B_notx_12_port);
U299 : inv port map( inb => mult_125_G3_B_not_13_port, outb =>
mult_125_G3_B_notx_13_port);
U300 : inv port map( inb => mult_125_G3_B_not_14_port, outb =>
mult_125_G3_B_notx_14_port);
U301 : inv port map( inb => input_sample_mem_15_port, outb => n5786);
U302 : inv port map( inb => coefficient_mem_array_1_15_port, outb => n5787);
U303 : inv port map( inb => mult_125_G2_B_not_15_port, outb => n5788);
U304 : inv port map( inb => mult_125_G2_A_not_15_port, outb => n5789);
U305 : inv port map( inb => mult_125_G2_A_not_0_port, outb =>
mult_125_G2_A_notx_0_port);
U306 : inv port map( inb => mult_125_G2_A_not_1_port, outb =>
mult_125_G2_A_notx_1_port);
U307 : inv port map( inb => mult_125_G2_A_not_2_port, outb =>
mult_125_G2_A_notx_2_port);
U308 : inv port map( inb => mult_125_G2_A_not_3_port, outb =>
mult_125_G2_A_notx_3_port);
U309 : inv port map( inb => mult_125_G2_A_not_4_port, outb =>
mult_125_G2_A_notx_4_port);
U310 : inv port map( inb => mult_125_G2_A_not_5_port, outb =>
mult_125_G2_A_notx_5_port);
U311 : inv port map( inb => mult_125_G2_A_not_6_port, outb =>
mult_125_G2_A_notx_6_port);
U312 : inv port map( inb => mult_125_G2_A_not_7_port, outb =>
mult_125_G2_A_notx_7_port);
U313 : inv port map( inb => mult_125_G2_A_not_8_port, outb =>
mult_125_G2_A_notx_8_port);
U314 : inv port map( inb => mult_125_G2_A_not_9_port, outb =>
mult_125_G2_A_notx_9_port);
U315 : inv port map( inb => mult_125_G2_A_not_10_port, outb =>
mult_125_G2_A_notx_10_port);
U316 : inv port map( inb => mult_125_G2_A_not_11_port, outb =>
mult_125_G2_A_notx_11_port);
U317 : inv port map( inb => mult_125_G2_A_not_12_port, outb =>
mult_125_G2_A_notx_12_port);
U318 : inv port map( inb => mult_125_G2_A_not_13_port, outb =>
mult_125_G2_A_notx_13_port);
U319 : inv port map( inb => mult_125_G2_A_not_14_port, outb =>
mult_125_G2_A_notx_14_port);
U320 : inv port map( inb => mult_125_G2_B_not_0_port, outb =>
mult_125_G2_B_notx_0_port);
U321 : inv port map( inb => mult_125_G2_B_not_1_port, outb =>
mult_125_G2_B_notx_1_port);
U322 : inv port map( inb => mult_125_G2_B_not_2_port, outb =>
mult_125_G2_B_notx_2_port);
U323 : inv port map( inb => mult_125_G2_B_not_3_port, outb =>
mult_125_G2_B_notx_3_port);
U324 : inv port map( inb => mult_125_G2_B_not_4_port, outb =>
mult_125_G2_B_notx_4_port);
U325 : inv port map( inb => mult_125_G2_B_not_5_port, outb =>
mult_125_G2_B_notx_5_port);
U326 : inv port map( inb => mult_125_G2_B_not_6_port, outb =>
mult_125_G2_B_notx_6_port);
U327 : inv port map( inb => mult_125_G2_B_not_7_port, outb =>
mult_125_G2_B_notx_7_port);
U328 : inv port map( inb => mult_125_G2_B_not_8_port, outb =>
mult_125_G2_B_notx_8_port);
U329 : inv port map( inb => mult_125_G2_B_not_9_port, outb =>
mult_125_G2_B_notx_9_port);
U330 : inv port map( inb => mult_125_G2_B_not_10_port, outb =>
mult_125_G2_B_notx_10_port);
U331 : inv port map( inb => mult_125_G2_B_not_11_port, outb =>
mult_125_G2_B_notx_11_port);
U332 : inv port map( inb => mult_125_G2_B_not_12_port, outb =>
mult_125_G2_B_notx_12_port);
U333 : inv port map( inb => mult_125_G2_B_not_13_port, outb =>
mult_125_G2_B_notx_13_port);
U334 : inv port map( inb => mult_125_G2_B_not_14_port, outb =>
mult_125_G2_B_notx_14_port);
U335 : inv port map( inb => input_sample_mem_15_port, outb => n5661);
U336 : inv port map( inb => coefficient_mem_array_0_15_port, outb => n5662);
U337 : inv port map( inb => mult_125_B_not_15_port, outb => n5663);
U338 : inv port map( inb => mult_125_A_not_15_port, outb => n5664);
U339 : inv port map( inb => mult_125_A_not_0_port, outb =>
mult_125_A_notx_0_port);
U340 : inv port map( inb => mult_125_A_not_1_port, outb =>
mult_125_A_notx_1_port);
U341 : inv port map( inb => mult_125_A_not_2_port, outb =>
mult_125_A_notx_2_port);
U342 : inv port map( inb => mult_125_A_not_3_port, outb =>
mult_125_A_notx_3_port);
U343 : inv port map( inb => mult_125_A_not_4_port, outb =>
mult_125_A_notx_4_port);
U344 : inv port map( inb => mult_125_A_not_5_port, outb =>
mult_125_A_notx_5_port);
U345 : inv port map( inb => mult_125_A_not_6_port, outb =>
mult_125_A_notx_6_port);
U346 : inv port map( inb => mult_125_A_not_7_port, outb =>
mult_125_A_notx_7_port);
U347 : inv port map( inb => mult_125_A_not_8_port, outb =>
mult_125_A_notx_8_port);
U348 : inv port map( inb => mult_125_A_not_9_port, outb =>
mult_125_A_notx_9_port);
U349 : inv port map( inb => mult_125_A_not_10_port, outb =>
mult_125_A_notx_10_port);
U350 : inv port map( inb => mult_125_A_not_11_port, outb =>
mult_125_A_notx_11_port);
U351 : inv port map( inb => mult_125_A_not_12_port, outb =>
mult_125_A_notx_12_port);
U352 : inv port map( inb => mult_125_A_not_13_port, outb =>
mult_125_A_notx_13_port);
U353 : inv port map( inb => mult_125_A_not_14_port, outb =>
mult_125_A_notx_14_port);
U354 : inv port map( inb => mult_125_B_not_0_port, outb =>
mult_125_B_notx_0_port);
U355 : inv port map( inb => mult_125_B_not_1_port, outb =>
mult_125_B_notx_1_port);
U356 : inv port map( inb => mult_125_B_not_2_port, outb =>
mult_125_B_notx_2_port);
U357 : inv port map( inb => mult_125_B_not_3_port, outb =>
mult_125_B_notx_3_port);
U358 : inv port map( inb => mult_125_B_not_4_port, outb =>
mult_125_B_notx_4_port);
U359 : inv port map( inb => mult_125_B_not_5_port, outb =>
mult_125_B_notx_5_port);
U360 : inv port map( inb => mult_125_B_not_6_port, outb =>
mult_125_B_notx_6_port);
U361 : inv port map( inb => mult_125_B_not_7_port, outb =>
mult_125_B_notx_7_port);
U362 : inv port map( inb => mult_125_B_not_8_port, outb =>
mult_125_B_notx_8_port);
U363 : inv port map( inb => mult_125_B_not_9_port, outb =>
mult_125_B_notx_9_port);
U364 : inv port map( inb => mult_125_B_not_10_port, outb =>
mult_125_B_notx_10_port);
U365 : inv port map( inb => mult_125_B_not_11_port, outb =>
mult_125_B_notx_11_port);
U366 : inv port map( inb => mult_125_B_not_12_port, outb =>
mult_125_B_notx_12_port);
U367 : inv port map( inb => mult_125_B_not_13_port, outb =>
mult_125_B_notx_13_port);
U368 : inv port map( inb => mult_125_B_not_14_port, outb =>
mult_125_B_notx_14_port);
U369 : inv port map( inb => input_sample_mem_15_port, outb => n5536);
U370 : inv port map( inb => coefficient_mem_array_3_15_port, outb => n5537);
U371 : inv port map( inb => mult_125_G4_B_not_15_port, outb => n5538);
U372 : inv port map( inb => mult_125_G4_A_not_15_port, outb => n5539);
U373 : inv port map( inb => mult_125_G4_A_not_0_port, outb =>
mult_125_G4_A_notx_0_port);
U374 : inv port map( inb => mult_125_G4_A_not_1_port, outb =>
mult_125_G4_A_notx_1_port);
U375 : inv port map( inb => mult_125_G4_A_not_2_port, outb =>
mult_125_G4_A_notx_2_port);
U376 : inv port map( inb => mult_125_G4_A_not_3_port, outb =>
mult_125_G4_A_notx_3_port);
U377 : inv port map( inb => mult_125_G4_A_not_4_port, outb =>
mult_125_G4_A_notx_4_port);
U378 : inv port map( inb => mult_125_G4_A_not_5_port, outb =>
mult_125_G4_A_notx_5_port);
U379 : inv port map( inb => mult_125_G4_A_not_6_port, outb =>
mult_125_G4_A_notx_6_port);
U380 : inv port map( inb => mult_125_G4_A_not_7_port, outb =>
mult_125_G4_A_notx_7_port);
U381 : inv port map( inb => mult_125_G4_A_not_8_port, outb =>
mult_125_G4_A_notx_8_port);
U382 : inv port map( inb => mult_125_G4_A_not_9_port, outb =>
mult_125_G4_A_notx_9_port);
U383 : inv port map( inb => mult_125_G4_A_not_10_port, outb =>
mult_125_G4_A_notx_10_port);
U384 : inv port map( inb => mult_125_G4_A_not_11_port, outb =>
mult_125_G4_A_notx_11_port);
U385 : inv port map( inb => mult_125_G4_A_not_12_port, outb =>
mult_125_G4_A_notx_12_port);
U386 : inv port map( inb => mult_125_G4_A_not_13_port, outb =>
mult_125_G4_A_notx_13_port);
U387 : inv port map( inb => mult_125_G4_A_not_14_port, outb =>
mult_125_G4_A_notx_14_port);
U388 : inv port map( inb => mult_125_G4_B_not_0_port, outb =>
mult_125_G4_B_notx_0_port);
U389 : inv port map( inb => mult_125_G4_B_not_1_port, outb =>
mult_125_G4_B_notx_1_port);
U390 : inv port map( inb => mult_125_G4_B_not_2_port, outb =>
mult_125_G4_B_notx_2_port);
U391 : inv port map( inb => mult_125_G4_B_not_3_port, outb =>
mult_125_G4_B_notx_3_port);
U392 : inv port map( inb => mult_125_G4_B_not_4_port, outb =>
mult_125_G4_B_notx_4_port);
U393 : inv port map( inb => mult_125_G4_B_not_5_port, outb =>
mult_125_G4_B_notx_5_port);
U394 : inv port map( inb => mult_125_G4_B_not_6_port, outb =>
mult_125_G4_B_notx_6_port);
U395 : inv port map( inb => mult_125_G4_B_not_7_port, outb =>
mult_125_G4_B_notx_7_port);
U396 : inv port map( inb => mult_125_G4_B_not_8_port, outb =>
mult_125_G4_B_notx_8_port);
U397 : inv port map( inb => mult_125_G4_B_not_9_port, outb =>
mult_125_G4_B_notx_9_port);
U398 : inv port map( inb => mult_125_G4_B_not_10_port, outb =>
mult_125_G4_B_notx_10_port);
U399 : inv port map( inb => mult_125_G4_B_not_11_port, outb =>
mult_125_G4_B_notx_11_port);
U400 : inv port map( inb => mult_125_G4_B_not_12_port, outb =>
mult_125_G4_B_notx_12_port);
U401 : inv port map( inb => mult_125_G4_B_not_13_port, outb =>
mult_125_G4_B_notx_13_port);
U402 : inv port map( inb => mult_125_G4_B_not_14_port, outb =>
mult_125_G4_B_notx_14_port);
U403 : inv port map( inb => n5540, outb =>
mult_125_G4_FS_1_TEMP_P_0_0_0_port);
U404 : inv port map( inb => n5660, outb => mult_125_G4_FS_1_C_1_4_0_port);
U405 : inv port map( inb => n5665, outb => mult_125_FS_1_TEMP_P_0_0_0_port);
U406 : inv port map( inb => n5785, outb => mult_125_FS_1_C_1_4_0_port);
U407 : inv port map( inb => n5790, outb =>
mult_125_G2_FS_1_TEMP_P_0_0_0_port);
U408 : inv port map( inb => n5910, outb => mult_125_G2_FS_1_C_1_4_0_port);
U409 : inv port map( inb => n5915, outb =>
mult_125_G3_FS_1_TEMP_P_0_0_0_port);
U410 : inv port map( inb => n6035, outb => mult_125_G3_FS_1_C_1_4_0_port);
U411 : inv port map( inb => mult_125_FS_1_TEMP_P_0_0_0_port, outb => n5666);
U412 : inv port map( inb => n5667, outb => mult_125_FS_1_P_0_0_1_port);
U413 : inv port map( inb => mult_125_FS_1_P_0_0_1_port, outb => n5668);
U414 : inv port map( inb => n5669, outb => mult_125_FS_1_P_0_0_2_port);
U415 : inv port map( inb => mult_125_FS_1_P_0_0_2_port, outb => n5670);
U416 : inv port map( inb => n5671, outb => mult_125_FS_1_P_0_0_3_port);
U417 : inv port map( inb => mult_125_FS_1_P_0_0_3_port, outb => n5672);
U418 : inv port map( inb => n5673, outb => mult_125_FS_1_TEMP_P_0_1_0_port);
U419 : inv port map( inb => mult_125_FS_1_TEMP_P_0_1_0_port, outb => n5674);
U420 : inv port map( inb => n5675, outb => mult_125_FS_1_P_0_1_1_port);
U421 : inv port map( inb => mult_125_FS_1_P_0_1_1_port, outb => n5676);
U422 : inv port map( inb => n5677, outb => mult_125_FS_1_P_0_1_2_port);
U423 : inv port map( inb => mult_125_FS_1_P_0_1_2_port, outb => n5678);
U424 : inv port map( inb => n5679, outb => mult_125_FS_1_P_0_1_3_port);
U425 : inv port map( inb => mult_125_FS_1_P_0_1_3_port, outb => n5680);
U426 : inv port map( inb => n5681, outb => mult_125_FS_1_TEMP_P_0_2_0_port);
U427 : inv port map( inb => mult_125_FS_1_TEMP_P_0_2_0_port, outb => n5682);
U428 : inv port map( inb => n5683, outb => mult_125_FS_1_P_0_2_1_port);
U429 : inv port map( inb => mult_125_FS_1_P_0_2_1_port, outb => n5684);
U430 : inv port map( inb => n5685, outb => mult_125_FS_1_P_0_2_2_port);
U431 : inv port map( inb => mult_125_FS_1_P_0_2_2_port, outb => n5686);
U432 : inv port map( inb => n5687, outb => mult_125_FS_1_P_0_2_3_port);
U433 : inv port map( inb => mult_125_FS_1_P_0_2_3_port, outb => n5688);
U434 : inv port map( inb => n5775, outb => mult_125_FS_1_G_2_0_0_port);
U435 : inv port map( inb => n5689, outb => mult_125_FS_1_TEMP_P_0_3_0_port);
U436 : inv port map( inb => mult_125_FS_1_TEMP_P_0_3_0_port, outb => n5690);
U437 : inv port map( inb => n5691, outb => mult_125_FS_1_P_0_3_1_port);
U438 : inv port map( inb => mult_125_FS_1_P_0_3_1_port, outb => n5692);
U439 : inv port map( inb => mult_125_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_FS_1_C_1_3_3_port);
U440 : inv port map( inb => mult_125_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_FS_1_TEMP_G_0_3_2_port);
U441 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_0_0_port, outb =>
n5791);
U442 : inv port map( inb => n5792, outb => mult_125_G2_FS_1_P_0_0_1_port);
U443 : inv port map( inb => mult_125_G2_FS_1_P_0_0_1_port, outb => n5793);
U444 : inv port map( inb => n5794, outb => mult_125_G2_FS_1_P_0_0_2_port);
U445 : inv port map( inb => mult_125_G2_FS_1_P_0_0_2_port, outb => n5795);
U446 : inv port map( inb => n5796, outb => mult_125_G2_FS_1_P_0_0_3_port);
U447 : inv port map( inb => mult_125_G2_FS_1_P_0_0_3_port, outb => n5797);
U448 : inv port map( inb => n5798, outb =>
mult_125_G2_FS_1_TEMP_P_0_1_0_port);
U449 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_1_0_port, outb =>
n5799);
U450 : inv port map( inb => n5800, outb => mult_125_G2_FS_1_P_0_1_1_port);
U451 : inv port map( inb => mult_125_G2_FS_1_P_0_1_1_port, outb => n5801);
U452 : inv port map( inb => n5802, outb => mult_125_G2_FS_1_P_0_1_2_port);
U453 : inv port map( inb => mult_125_G2_FS_1_P_0_1_2_port, outb => n5803);
U454 : inv port map( inb => n5804, outb => mult_125_G2_FS_1_P_0_1_3_port);
U455 : inv port map( inb => mult_125_G2_FS_1_P_0_1_3_port, outb => n5805);
U456 : inv port map( inb => n5806, outb =>
mult_125_G2_FS_1_TEMP_P_0_2_0_port);
U457 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_2_0_port, outb =>
n5807);
U458 : inv port map( inb => n5808, outb => mult_125_G2_FS_1_P_0_2_1_port);
U459 : inv port map( inb => mult_125_G2_FS_1_P_0_2_1_port, outb => n5809);
U460 : inv port map( inb => n5810, outb => mult_125_G2_FS_1_P_0_2_2_port);
U461 : inv port map( inb => mult_125_G2_FS_1_P_0_2_2_port, outb => n5811);
U462 : inv port map( inb => n5812, outb => mult_125_G2_FS_1_P_0_2_3_port);
U463 : inv port map( inb => mult_125_G2_FS_1_P_0_2_3_port, outb => n5813);
U464 : inv port map( inb => n5900, outb => mult_125_G2_FS_1_G_2_0_0_port);
U465 : inv port map( inb => n5814, outb =>
mult_125_G2_FS_1_TEMP_P_0_3_0_port);
U466 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_3_0_port, outb =>
n5815);
U467 : inv port map( inb => n5816, outb => mult_125_G2_FS_1_P_0_3_1_port);
U468 : inv port map( inb => mult_125_G2_FS_1_P_0_3_1_port, outb => n5817);
U469 : inv port map( inb => mult_125_G2_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G2_FS_1_C_1_3_3_port);
U470 : inv port map( inb => mult_125_G2_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_3_2_port);
U471 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_0_0_port, outb =>
n5916);
U472 : inv port map( inb => n5917, outb => mult_125_G3_FS_1_P_0_0_1_port);
U473 : inv port map( inb => mult_125_G3_FS_1_P_0_0_1_port, outb => n5918);
U474 : inv port map( inb => n5919, outb => mult_125_G3_FS_1_P_0_0_2_port);
U475 : inv port map( inb => mult_125_G3_FS_1_P_0_0_2_port, outb => n5920);
U476 : inv port map( inb => n5921, outb => mult_125_G3_FS_1_P_0_0_3_port);
U477 : inv port map( inb => mult_125_G3_FS_1_P_0_0_3_port, outb => n5922);
U478 : inv port map( inb => n5923, outb =>
mult_125_G3_FS_1_TEMP_P_0_1_0_port);
U479 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_1_0_port, outb =>
n5924);
U480 : inv port map( inb => n5925, outb => mult_125_G3_FS_1_P_0_1_1_port);
U481 : inv port map( inb => mult_125_G3_FS_1_P_0_1_1_port, outb => n5926);
U482 : inv port map( inb => n5927, outb => mult_125_G3_FS_1_P_0_1_2_port);
U483 : inv port map( inb => mult_125_G3_FS_1_P_0_1_2_port, outb => n5928);
U484 : inv port map( inb => n5929, outb => mult_125_G3_FS_1_P_0_1_3_port);
U485 : inv port map( inb => mult_125_G3_FS_1_P_0_1_3_port, outb => n5930);
U486 : inv port map( inb => n5931, outb =>
mult_125_G3_FS_1_TEMP_P_0_2_0_port);
U487 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_2_0_port, outb =>
n5932);
U488 : inv port map( inb => n5933, outb => mult_125_G3_FS_1_P_0_2_1_port);
U489 : inv port map( inb => mult_125_G3_FS_1_P_0_2_1_port, outb => n5934);
U490 : inv port map( inb => n5935, outb => mult_125_G3_FS_1_P_0_2_2_port);
U491 : inv port map( inb => mult_125_G3_FS_1_P_0_2_2_port, outb => n5936);
U492 : inv port map( inb => n5937, outb => mult_125_G3_FS_1_P_0_2_3_port);
U493 : inv port map( inb => mult_125_G3_FS_1_P_0_2_3_port, outb => n5938);
U494 : inv port map( inb => n6025, outb => mult_125_G3_FS_1_G_2_0_0_port);
U495 : inv port map( inb => n5939, outb =>
mult_125_G3_FS_1_TEMP_P_0_3_0_port);
U496 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_3_0_port, outb =>
n5940);
U497 : inv port map( inb => n5941, outb => mult_125_G3_FS_1_P_0_3_1_port);
U498 : inv port map( inb => mult_125_G3_FS_1_P_0_3_1_port, outb => n5942);
U499 : inv port map( inb => mult_125_G3_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G3_FS_1_C_1_3_3_port);
U500 : inv port map( inb => mult_125_G3_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_3_2_port);
U501 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_0_0_port, outb =>
n5541);
U502 : inv port map( inb => n5542, outb => mult_125_G4_FS_1_P_0_0_1_port);
U503 : inv port map( inb => mult_125_G4_FS_1_P_0_0_1_port, outb => n5543);
U504 : inv port map( inb => n5544, outb => mult_125_G4_FS_1_P_0_0_2_port);
U505 : inv port map( inb => mult_125_G4_FS_1_P_0_0_2_port, outb => n5545);
U506 : inv port map( inb => n5546, outb => mult_125_G4_FS_1_P_0_0_3_port);
U507 : inv port map( inb => mult_125_G4_FS_1_P_0_0_3_port, outb => n5547);
U508 : inv port map( inb => n5548, outb =>
mult_125_G4_FS_1_TEMP_P_0_1_0_port);
U509 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_1_0_port, outb =>
n5549);
U510 : inv port map( inb => n5550, outb => mult_125_G4_FS_1_P_0_1_1_port);
U511 : inv port map( inb => mult_125_G4_FS_1_P_0_1_1_port, outb => n5551);
U512 : inv port map( inb => n5552, outb => mult_125_G4_FS_1_P_0_1_2_port);
U513 : inv port map( inb => mult_125_G4_FS_1_P_0_1_2_port, outb => n5553);
U514 : inv port map( inb => n5554, outb => mult_125_G4_FS_1_P_0_1_3_port);
U515 : inv port map( inb => mult_125_G4_FS_1_P_0_1_3_port, outb => n5555);
U516 : inv port map( inb => n5556, outb =>
mult_125_G4_FS_1_TEMP_P_0_2_0_port);
U517 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_2_0_port, outb =>
n5557);
U518 : inv port map( inb => n5558, outb => mult_125_G4_FS_1_P_0_2_1_port);
U519 : inv port map( inb => mult_125_G4_FS_1_P_0_2_1_port, outb => n5559);
U520 : inv port map( inb => n5560, outb => mult_125_G4_FS_1_P_0_2_2_port);
U521 : inv port map( inb => mult_125_G4_FS_1_P_0_2_2_port, outb => n5561);
U522 : inv port map( inb => n5562, outb => mult_125_G4_FS_1_P_0_2_3_port);
U523 : inv port map( inb => mult_125_G4_FS_1_P_0_2_3_port, outb => n5563);
U524 : inv port map( inb => n5650, outb => mult_125_G4_FS_1_G_2_0_0_port);
U525 : inv port map( inb => n5564, outb =>
mult_125_G4_FS_1_TEMP_P_0_3_0_port);
U526 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_3_0_port, outb =>
n5565);
U527 : inv port map( inb => n5566, outb => mult_125_G4_FS_1_P_0_3_1_port);
U528 : inv port map( inb => mult_125_G4_FS_1_P_0_3_1_port, outb => n5567);
U529 : inv port map( inb => mult_125_G4_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G4_FS_1_C_1_3_3_port);
U530 : inv port map( inb => mult_125_G4_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_3_2_port);
U531 : oai22 port map( a => mult_125_G4_QB, b => mult_125_G4_ab_15_15_port,
c => mult_125_G4_QA, d => n240, outb =>
mult_125_G4_A1_29_port);
U532 : nor2 port map( a => n241, b => n242, outb => mult_125_G4_A2_29_port);
U533 : nor2 port map( a => n243, b => n244, outb => mult_125_G4_A2_28_port);
U534 : nor2 port map( a => n245, b => n246, outb => mult_125_G4_A2_27_port);
U535 : nor2 port map( a => n247, b => n248, outb => mult_125_G4_A2_26_port);
U536 : nor2 port map( a => n249, b => n250, outb => mult_125_G4_A2_25_port);
U537 : nor2 port map( a => n251, b => n252, outb => mult_125_G4_A2_24_port);
U538 : nor2 port map( a => n253, b => n254, outb => mult_125_G4_A2_23_port);
U539 : nor2 port map( a => n255, b => n256, outb => mult_125_G4_A2_22_port);
U540 : nor2 port map( a => n257, b => n258, outb => mult_125_G4_A2_21_port);
U541 : nor2 port map( a => n259, b => n260, outb => mult_125_G4_A2_20_port);
U542 : nor2 port map( a => n261, b => n262, outb => mult_125_G4_A2_19_port);
U543 : nor2 port map( a => n263, b => n264, outb => mult_125_G4_A2_18_port);
U544 : nand2 port map( a => n266, b => n267, outb => n265);
U545 : nor2 port map( a => n268, b => n269, outb => mult_125_G4_A2_16_port);
U546 : nor2 port map( a => n270, b => n271, outb => mult_125_G4_A2_15_port);
U547 : oai22 port map( a => n272, b => n273, c => n274, d => n275, outb =>
mult_125_G4_A2_14_port);
U548 : oai22 port map( a => mult_125_QB, b => mult_125_ab_15_15_port, c =>
mult_125_QA, d => n276, outb => mult_125_A1_29_port)
;
U549 : nor2 port map( a => n277, b => n278, outb => mult_125_A2_29_port);
U550 : nor2 port map( a => n279, b => n280, outb => mult_125_A2_28_port);
U551 : nor2 port map( a => n281, b => n282, outb => mult_125_A2_27_port);
U552 : nor2 port map( a => n283, b => n284, outb => mult_125_A2_26_port);
U553 : nor2 port map( a => n285, b => n286, outb => mult_125_A2_25_port);
U554 : nor2 port map( a => n287, b => n288, outb => mult_125_A2_24_port);
U555 : nor2 port map( a => n289, b => n290, outb => mult_125_A2_23_port);
U556 : nor2 port map( a => n291, b => n292, outb => mult_125_A2_22_port);
U557 : nor2 port map( a => n293, b => n294, outb => mult_125_A2_21_port);
U558 : nor2 port map( a => n295, b => n296, outb => mult_125_A2_20_port);
U559 : nor2 port map( a => n297, b => n298, outb => mult_125_A2_19_port);
U560 : nor2 port map( a => n299, b => n300, outb => mult_125_A2_18_port);
U561 : nand2 port map( a => n302, b => n303, outb => n301);
U562 : nor2 port map( a => n304, b => n305, outb => mult_125_A2_16_port);
U563 : nor2 port map( a => n306, b => n307, outb => mult_125_A2_15_port);
U564 : oai22 port map( a => n308, b => n309, c => n310, d => n311, outb =>
mult_125_A2_14_port);
U565 : oai22 port map( a => mult_125_G2_QB, b => mult_125_G2_ab_15_15_port,
c => mult_125_G2_QA, d => n312, outb =>
mult_125_G2_A1_29_port);
U566 : nor2 port map( a => n313, b => n314, outb => mult_125_G2_A2_29_port);
U567 : nor2 port map( a => n315, b => n316, outb => mult_125_G2_A2_28_port);
U568 : nor2 port map( a => n317, b => n318, outb => mult_125_G2_A2_27_port);
U569 : nor2 port map( a => n319, b => n320, outb => mult_125_G2_A2_26_port);
U570 : nor2 port map( a => n321, b => n322, outb => mult_125_G2_A2_25_port);
U571 : nor2 port map( a => n323, b => n324, outb => mult_125_G2_A2_24_port);
U572 : nor2 port map( a => n325, b => n326, outb => mult_125_G2_A2_23_port);
U573 : nor2 port map( a => n327, b => n328, outb => mult_125_G2_A2_22_port);
U574 : nor2 port map( a => n329, b => n330, outb => mult_125_G2_A2_21_port);
U575 : nor2 port map( a => n331, b => n332, outb => mult_125_G2_A2_20_port);
U576 : nor2 port map( a => n333, b => n334, outb => mult_125_G2_A2_19_port);
U577 : nor2 port map( a => n335, b => n336, outb => mult_125_G2_A2_18_port);
U578 : nand2 port map( a => n338, b => n339, outb => n337);
U579 : nor2 port map( a => n340, b => n341, outb => mult_125_G2_A2_16_port);
U580 : nor2 port map( a => n342, b => n343, outb => mult_125_G2_A2_15_port);
U581 : oai22 port map( a => n344, b => n345, c => n346, d => n347, outb =>
mult_125_G2_A2_14_port);
U582 : oai22 port map( a => mult_125_G3_QB, b => mult_125_G3_ab_15_15_port,
c => mult_125_G3_QA, d => n348, outb =>
mult_125_G3_A1_29_port);
U583 : nor2 port map( a => n349, b => n350, outb => mult_125_G3_A2_29_port);
U584 : nor2 port map( a => n351, b => n352, outb => mult_125_G3_A2_28_port);
U585 : nor2 port map( a => n353, b => n354, outb => mult_125_G3_A2_27_port);
U586 : nor2 port map( a => n355, b => n356, outb => mult_125_G3_A2_26_port);
U587 : nor2 port map( a => n357, b => n358, outb => mult_125_G3_A2_25_port);
U588 : nor2 port map( a => n359, b => n360, outb => mult_125_G3_A2_24_port);
U589 : nor2 port map( a => n361, b => n362, outb => mult_125_G3_A2_23_port);
U590 : nor2 port map( a => n363, b => n364, outb => mult_125_G3_A2_22_port);
U591 : nor2 port map( a => n365, b => n366, outb => mult_125_G3_A2_21_port);
U592 : nor2 port map( a => n367, b => n368, outb => mult_125_G3_A2_20_port);
U593 : nor2 port map( a => n369, b => n370, outb => mult_125_G3_A2_19_port);
U594 : nor2 port map( a => n371, b => n372, outb => mult_125_G3_A2_18_port);
U595 : nand2 port map( a => n374, b => n375, outb => n373);
U596 : nor2 port map( a => n376, b => n377, outb => mult_125_G3_A2_16_port);
U597 : nor2 port map( a => n378, b => n379, outb => mult_125_G3_A2_15_port);
U598 : oai22 port map( a => n380, b => n381, c => n382, d => n383, outb =>
mult_125_G3_A2_14_port);
U599 : nor2 port map( a => mult_125_G4_ab_1_15_port, b =>
mult_125_G4_ab_2_14_port, outb => n384);
U600 : nor2 port map( a => mult_125_G4_ab_2_15_port, b =>
mult_125_G4_ab_3_14_port, outb => n385);
U601 : nor2 port map( a => mult_125_G4_ab_3_15_port, b =>
mult_125_G4_ab_4_14_port, outb => n386);
U602 : nor2 port map( a => mult_125_G4_ab_4_15_port, b =>
mult_125_G4_ab_5_14_port, outb => n387);
U603 : nor2 port map( a => mult_125_G4_ab_5_15_port, b =>
mult_125_G4_ab_6_14_port, outb => n388);
U604 : nor2 port map( a => mult_125_G4_ab_6_15_port, b =>
mult_125_G4_ab_7_14_port, outb => n389);
U605 : nor2 port map( a => mult_125_G4_ab_7_15_port, b =>
mult_125_G4_ab_8_14_port, outb => n390);
U606 : nor2 port map( a => mult_125_G4_ab_8_15_port, b =>
mult_125_G4_ab_9_14_port, outb => n391);
U607 : nor2 port map( a => mult_125_G4_ab_9_15_port, b =>
mult_125_G4_ab_10_14_port, outb => n392);
U608 : nor2 port map( a => mult_125_G4_ab_10_15_port, b =>
mult_125_G4_ab_11_14_port, outb => n393);
U609 : nor2 port map( a => mult_125_G4_ab_11_15_port, b =>
mult_125_G4_ab_12_14_port, outb => n394);
U610 : nor2 port map( a => mult_125_G4_ab_12_15_port, b =>
mult_125_G4_ab_13_14_port, outb => n395);
U611 : nor2 port map( a => mult_125_G4_ab_13_15_port, b =>
mult_125_G4_ab_14_14_port, outb => n396);
U612 : nor2 port map( a => mult_125_G4_ab_14_15_port, b =>
mult_125_G4_ab_15_14_port, outb => n397);
U613 : nand2 port map( a => n399, b => n400, outb => n398);
U614 : nand2 port map( a => n402, b => n403, outb => n401);
U615 : nor2 port map( a => mult_125_G4_ab_4_13_port, b => n405, outb => n404
);
U616 : nor2 port map( a => mult_125_G4_ab_5_13_port, b => n407, outb => n406
);
U617 : nor2 port map( a => mult_125_G4_ab_6_13_port, b => n409, outb => n408
);
U618 : nor2 port map( a => mult_125_G4_ab_7_13_port, b => n411, outb => n410
);
U619 : nor2 port map( a => mult_125_G4_ab_8_13_port, b => n413, outb => n412
);
U620 : nor2 port map( a => mult_125_G4_ab_9_13_port, b => n415, outb => n414
);
U621 : nor2 port map( a => mult_125_G4_ab_10_13_port, b => n417, outb =>
n416);
U622 : nor2 port map( a => mult_125_G4_ab_11_13_port, b => n419, outb =>
n418);
U623 : nor2 port map( a => mult_125_G4_ab_12_13_port, b => n421, outb =>
n420);
U624 : nor2 port map( a => mult_125_G4_ab_13_13_port, b => n423, outb =>
n422);
U625 : nor2 port map( a => mult_125_G4_ab_14_13_port, b => n425, outb =>
n424);
U626 : nor2 port map( a => mult_125_G4_ab_15_13_port, b => n427, outb =>
n426);
U627 : nand2 port map( a => n429, b => n430, outb => n428);
U628 : nor2 port map( a => mult_125_G4_ab_3_12_port, b => n432, outb => n431
);
U629 : nor2 port map( a => mult_125_G4_ab_4_12_port, b => n434, outb => n433
);
U630 : nor2 port map( a => mult_125_G4_ab_5_12_port, b => n436, outb => n435
);
U631 : nor2 port map( a => mult_125_G4_ab_6_12_port, b => n438, outb => n437
);
U632 : nor2 port map( a => mult_125_G4_ab_7_12_port, b => n440, outb => n439
);
U633 : nor2 port map( a => mult_125_G4_ab_8_12_port, b => n442, outb => n441
);
U634 : nor2 port map( a => mult_125_G4_ab_9_12_port, b => n444, outb => n443
);
U635 : nor2 port map( a => mult_125_G4_ab_10_12_port, b => n446, outb =>
n445);
U636 : nor2 port map( a => mult_125_G4_ab_11_12_port, b => n448, outb =>
n447);
U637 : nor2 port map( a => mult_125_G4_ab_12_12_port, b => n450, outb =>
n449);
U638 : nor2 port map( a => mult_125_G4_ab_13_12_port, b => n452, outb =>
n451);
U639 : nor2 port map( a => mult_125_G4_ab_14_12_port, b => n454, outb =>
n453);
U640 : nor2 port map( a => mult_125_G4_ab_15_12_port, b => n456, outb =>
n455);
U641 : nand2 port map( a => n458, b => n459, outb => n457);
U642 : nand2 port map( a => n461, b => n462, outb => n460);
U643 : nor2 port map( a => mult_125_G4_ab_4_11_port, b => n464, outb => n463
);
U644 : nor2 port map( a => mult_125_G4_ab_5_11_port, b => n466, outb => n465
);
U645 : nor2 port map( a => mult_125_G4_ab_6_11_port, b => n468, outb => n467
);
U646 : nor2 port map( a => mult_125_G4_ab_7_11_port, b => n470, outb => n469
);
U647 : nor2 port map( a => mult_125_G4_ab_8_11_port, b => n472, outb => n471
);
U648 : nor2 port map( a => mult_125_G4_ab_9_11_port, b => n474, outb => n473
);
U649 : nor2 port map( a => mult_125_G4_ab_10_11_port, b => n476, outb =>
n475);
U650 : nor2 port map( a => mult_125_G4_ab_11_11_port, b => n478, outb =>
n477);
U651 : nor2 port map( a => mult_125_G4_ab_12_11_port, b => n480, outb =>
n479);
U652 : nor2 port map( a => mult_125_G4_ab_13_11_port, b => n482, outb =>
n481);
U653 : nor2 port map( a => mult_125_G4_ab_14_11_port, b => n484, outb =>
n483);
U654 : nand2 port map( a => n486, b => n487, outb => n485);
U655 : nand2 port map( a => n489, b => n490, outb => n488);
U656 : nor2 port map( a => mult_125_G4_ab_3_10_port, b => n492, outb => n491
);
U657 : nor2 port map( a => mult_125_G4_ab_4_10_port, b => n494, outb => n493
);
U658 : nand2 port map( a => n496, b => n497, outb => n495);
U659 : nor2 port map( a => mult_125_G4_ab_6_10_port, b => n499, outb => n498
);
U660 : nor2 port map( a => mult_125_G4_ab_7_10_port, b => n501, outb => n500
);
U661 : nor2 port map( a => mult_125_G4_ab_8_10_port, b => n503, outb => n502
);
U662 : nor2 port map( a => mult_125_G4_ab_9_10_port, b => n505, outb => n504
);
U663 : nor2 port map( a => mult_125_G4_ab_10_10_port, b => n507, outb =>
n506);
U664 : nor2 port map( a => mult_125_G4_ab_11_10_port, b => n509, outb =>
n508);
U665 : nor2 port map( a => mult_125_G4_ab_12_10_port, b => n511, outb =>
n510);
U666 : nor2 port map( a => mult_125_G4_ab_13_10_port, b => n513, outb =>
n512);
U667 : nor2 port map( a => mult_125_G4_ab_14_10_port, b => n515, outb =>
n514);
U668 : nor2 port map( a => mult_125_G4_ab_15_10_port, b => n517, outb =>
n516);
U669 : nand2 port map( a => n519, b => n520, outb => n518);
U670 : nor2 port map( a => mult_125_G4_ab_3_9_port, b => n522, outb => n521)
;
U671 : nor2 port map( a => mult_125_G4_ab_4_9_port, b => n524, outb => n523)
;
U672 : nor2 port map( a => mult_125_G4_ab_5_9_port, b => n526, outb => n525)
;
U673 : nor2 port map( a => mult_125_G4_ab_6_9_port, b => n528, outb => n527)
;
U674 : nor2 port map( a => mult_125_G4_ab_7_9_port, b => n530, outb => n529)
;
U675 : nor2 port map( a => mult_125_G4_ab_8_9_port, b => n532, outb => n531)
;
U676 : nor2 port map( a => mult_125_G4_ab_9_9_port, b => n534, outb => n533)
;
U677 : nor2 port map( a => mult_125_G4_ab_10_9_port, b => n536, outb => n535
);
U678 : nor2 port map( a => mult_125_G4_ab_11_9_port, b => n538, outb => n537
);
U679 : nor2 port map( a => mult_125_G4_ab_12_9_port, b => n540, outb => n539
);
U680 : nor2 port map( a => mult_125_G4_ab_13_9_port, b => n542, outb => n541
);
U681 : nor2 port map( a => mult_125_G4_ab_14_9_port, b => n544, outb => n543
);
U682 : nand2 port map( a => n546, b => n547, outb => n545);
U683 : nand2 port map( a => n549, b => n550, outb => n548);
U684 : nor2 port map( a => mult_125_G4_ab_3_8_port, b => n552, outb => n551)
;
U685 : nor2 port map( a => mult_125_G4_ab_4_8_port, b => n554, outb => n553)
;
U686 : nor2 port map( a => mult_125_G4_ab_5_8_port, b => n556, outb => n555)
;
U687 : nor2 port map( a => mult_125_G4_ab_6_8_port, b => n558, outb => n557)
;
U688 : nor2 port map( a => mult_125_G4_ab_7_8_port, b => n560, outb => n559)
;
U689 : nor2 port map( a => mult_125_G4_ab_8_8_port, b => n562, outb => n561)
;
U690 : nor2 port map( a => mult_125_G4_ab_9_8_port, b => n564, outb => n563)
;
U691 : nor2 port map( a => mult_125_G4_ab_10_8_port, b => n566, outb => n565
);
U692 : nor2 port map( a => mult_125_G4_ab_11_8_port, b => n568, outb => n567
);
U693 : nor2 port map( a => mult_125_G4_ab_12_8_port, b => n570, outb => n569
);
U694 : nor2 port map( a => mult_125_G4_ab_13_8_port, b => n572, outb => n571
);
U695 : nor2 port map( a => mult_125_G4_ab_14_8_port, b => n574, outb => n573
);
U696 : nor2 port map( a => mult_125_G4_ab_15_8_port, b => n576, outb => n575
);
U697 : nand2 port map( a => n578, b => n579, outb => n577);
U698 : nand2 port map( a => n581, b => n582, outb => n580);
U699 : nor2 port map( a => mult_125_G4_ab_4_7_port, b => n584, outb => n583)
;
U700 : nor2 port map( a => mult_125_G4_ab_5_7_port, b => n586, outb => n585)
;
U701 : nor2 port map( a => mult_125_G4_ab_6_7_port, b => n588, outb => n587)
;
U702 : nor2 port map( a => mult_125_G4_ab_7_7_port, b => n590, outb => n589)
;
U703 : nor2 port map( a => mult_125_G4_ab_8_7_port, b => n592, outb => n591)
;
U704 : nor2 port map( a => mult_125_G4_ab_9_7_port, b => n594, outb => n593)
;
U705 : nor2 port map( a => mult_125_G4_ab_10_7_port, b => n596, outb => n595
);
U706 : nor2 port map( a => mult_125_G4_ab_11_7_port, b => n598, outb => n597
);
U707 : nor2 port map( a => mult_125_G4_ab_12_7_port, b => n600, outb => n599
);
U708 : nor2 port map( a => mult_125_G4_ab_13_7_port, b => n602, outb => n601
);
U709 : nor2 port map( a => mult_125_G4_ab_14_7_port, b => n604, outb => n603
);
U710 : nand2 port map( a => n606, b => n607, outb => n605);
U711 : nand2 port map( a => n609, b => n610, outb => n608);
U712 : nor2 port map( a => mult_125_G4_ab_3_6_port, b => n612, outb => n611)
;
U713 : nor2 port map( a => mult_125_G4_ab_4_6_port, b => n614, outb => n613)
;
U714 : nand2 port map( a => n616, b => n617, outb => n615);
U715 : nor2 port map( a => mult_125_G4_ab_6_6_port, b => n619, outb => n618)
;
U716 : nor2 port map( a => mult_125_G4_ab_7_6_port, b => n621, outb => n620)
;
U717 : nor2 port map( a => mult_125_G4_ab_8_6_port, b => n623, outb => n622)
;
U718 : nand2 port map( a => n625, b => n626, outb => n624);
U719 : nor2 port map( a => mult_125_G4_ab_10_6_port, b => n628, outb => n627
);
U720 : nor2 port map( a => mult_125_G4_ab_11_6_port, b => n630, outb => n629
);
U721 : nor2 port map( a => mult_125_G4_ab_12_6_port, b => n632, outb => n631
);
U722 : nor2 port map( a => mult_125_G4_ab_13_6_port, b => n634, outb => n633
);
U723 : nor2 port map( a => mult_125_G4_ab_14_6_port, b => n636, outb => n635
);
U724 : nor2 port map( a => mult_125_G4_ab_15_6_port, b => n638, outb => n637
);
U725 : nand2 port map( a => n640, b => n641, outb => n639);
U726 : nand2 port map( a => n643, b => n644, outb => n642);
U727 : nor2 port map( a => mult_125_G4_ab_4_5_port, b => n646, outb => n645)
;
U728 : nor2 port map( a => mult_125_G4_ab_5_5_port, b => n648, outb => n647)
;
U729 : nand2 port map( a => n650, b => n651, outb => n649);
U730 : nor2 port map( a => mult_125_G4_ab_7_5_port, b => n653, outb => n652)
;
U731 : nor2 port map( a => mult_125_G4_ab_8_5_port, b => n655, outb => n654)
;
U732 : nor2 port map( a => mult_125_G4_ab_9_5_port, b => n657, outb => n656)
;
U733 : nor2 port map( a => mult_125_G4_ab_10_5_port, b => n659, outb => n658
);
U734 : nor2 port map( a => mult_125_G4_ab_11_5_port, b => n661, outb => n660
);
U735 : nor2 port map( a => mult_125_G4_ab_12_5_port, b => n663, outb => n662
);
U736 : nor2 port map( a => mult_125_G4_ab_13_5_port, b => n665, outb => n664
);
U737 : nor2 port map( a => mult_125_G4_ab_14_5_port, b => n667, outb => n666
);
U738 : nand2 port map( a => n669, b => n670, outb => n668);
U739 : nand2 port map( a => n672, b => n673, outb => n671);
U740 : nor2 port map( a => mult_125_G4_ab_3_4_port, b => n675, outb => n674)
;
U741 : nor2 port map( a => mult_125_G4_ab_4_4_port, b => n677, outb => n676)
;
U742 : nand2 port map( a => n679, b => n680, outb => n678);
U743 : nor2 port map( a => mult_125_G4_ab_6_4_port, b => n682, outb => n681)
;
U744 : nand2 port map( a => n684, b => n685, outb => n683);
U745 : nor2 port map( a => mult_125_G4_ab_8_4_port, b => n687, outb => n686)
;
U746 : nor2 port map( a => mult_125_G4_ab_9_4_port, b => n689, outb => n688)
;
U747 : nor2 port map( a => mult_125_G4_ab_10_4_port, b => n691, outb => n690
);
U748 : nand2 port map( a => n693, b => n694, outb => n692);
U749 : nor2 port map( a => mult_125_G4_ab_12_4_port, b => n696, outb => n695
);
U750 : nor2 port map( a => mult_125_G4_ab_13_4_port, b => n698, outb => n697
);
U751 : nor2 port map( a => mult_125_G4_ab_14_4_port, b => n700, outb => n699
);
U752 : nand2 port map( a => n702, b => n703, outb => n701);
U753 : nand2 port map( a => n705, b => n706, outb => n704);
U754 : nand2 port map( a => n708, b => n709, outb => n707);
U755 : nor2 port map( a => mult_125_G4_ab_4_3_port, b => n711, outb => n710)
;
U756 : nor2 port map( a => mult_125_G4_ab_5_3_port, b => n713, outb => n712)
;
U757 : nor2 port map( a => mult_125_G4_ab_6_3_port, b => n715, outb => n714)
;
U758 : nor2 port map( a => mult_125_G4_ab_7_3_port, b => n717, outb => n716)
;
U759 : nor2 port map( a => mult_125_G4_ab_8_3_port, b => n719, outb => n718)
;
U760 : nor2 port map( a => mult_125_G4_ab_9_3_port, b => n721, outb => n720)
;
U761 : nor2 port map( a => mult_125_G4_ab_10_3_port, b => n723, outb => n722
);
U762 : nor2 port map( a => mult_125_G4_ab_11_3_port, b => n725, outb => n724
);
U763 : nor2 port map( a => mult_125_G4_ab_12_3_port, b => n727, outb => n726
);
U764 : nor2 port map( a => mult_125_G4_ab_13_3_port, b => n729, outb => n728
);
U765 : nor2 port map( a => mult_125_G4_ab_14_3_port, b => n731, outb => n730
);
U766 : nor2 port map( a => mult_125_G4_ab_15_3_port, b => n733, outb => n732
);
U767 : nand2 port map( a => n735, b => n736, outb => n734);
U768 : nor2 port map( a => mult_125_G4_ab_3_2_port, b => n738, outb => n737)
;
U769 : nor2 port map( a => mult_125_G4_ab_4_2_port, b => n740, outb => n739)
;
U770 : nor2 port map( a => mult_125_G4_ab_5_2_port, b => n742, outb => n741)
;
U771 : nor2 port map( a => mult_125_G4_ab_6_2_port, b => n744, outb => n743)
;
U772 : nand2 port map( a => n746, b => n747, outb => n745);
U773 : nor2 port map( a => mult_125_G4_ab_8_2_port, b => n749, outb => n748)
;
U774 : nor2 port map( a => mult_125_G4_ab_9_2_port, b => n751, outb => n750)
;
U775 : nor2 port map( a => mult_125_G4_ab_10_2_port, b => n753, outb => n752
);
U776 : nor2 port map( a => mult_125_G4_ab_11_2_port, b => n755, outb => n754
);
U777 : nor2 port map( a => mult_125_G4_ab_12_2_port, b => n757, outb => n756
);
U778 : nor2 port map( a => mult_125_G4_ab_13_2_port, b => n759, outb => n758
);
U779 : nor2 port map( a => mult_125_G4_ab_14_2_port, b => n761, outb => n760
);
U780 : nor2 port map( a => mult_125_G4_ab_15_2_port, b => n763, outb => n762
);
U781 : nand2 port map( a => n765, b => n766, outb => n764);
U782 : nor2 port map( a => mult_125_G4_ab_3_1_port, b => n768, outb => n767)
;
U783 : nor2 port map( a => mult_125_G4_ab_4_1_port, b => n770, outb => n769)
;
U784 : nor2 port map( a => mult_125_G4_ab_5_1_port, b => n772, outb => n771)
;
U785 : nor2 port map( a => mult_125_G4_ab_6_1_port, b => n774, outb => n773)
;
U786 : nor2 port map( a => mult_125_G4_ab_7_1_port, b => n776, outb => n775)
;
U787 : nor2 port map( a => mult_125_G4_ab_8_1_port, b => n778, outb => n777)
;
U788 : nor2 port map( a => mult_125_G4_ab_9_1_port, b => n780, outb => n779)
;
U789 : nor2 port map( a => mult_125_G4_ab_10_1_port, b => n782, outb => n781
);
U790 : nor2 port map( a => mult_125_G4_ab_11_1_port, b => n784, outb => n783
);
U791 : nor2 port map( a => mult_125_G4_ab_12_1_port, b => n786, outb => n785
);
U792 : nor2 port map( a => mult_125_G4_ab_13_1_port, b => n788, outb => n787
);
U793 : nor2 port map( a => mult_125_G4_ab_14_1_port, b => n790, outb => n789
);
U794 : nor2 port map( a => mult_125_G4_ab_15_1_port, b => n792, outb => n791
);
U795 : nor2 port map( a => mult_125_G4_ab_2_0_port, b => n794, outb => n793)
;
U796 : nor2 port map( a => mult_125_G4_ab_3_0_port, b => n796, outb => n795)
;
U797 : nor2 port map( a => mult_125_G4_ab_4_0_port, b => n798, outb => n797)
;
U798 : nor2 port map( a => mult_125_G4_ab_5_0_port, b => n800, outb => n799)
;
U799 : nor2 port map( a => mult_125_G4_ab_6_0_port, b => n802, outb => n801)
;
U800 : nor2 port map( a => mult_125_G4_ab_7_0_port, b => n804, outb => n803)
;
U801 : nor2 port map( a => mult_125_G4_ab_8_0_port, b => n806, outb => n805)
;
U802 : nor2 port map( a => mult_125_G4_ab_9_0_port, b => n808, outb => n807)
;
U803 : nor2 port map( a => mult_125_G4_ab_10_0_port, b => n810, outb => n809
);
U804 : nor2 port map( a => mult_125_G4_ab_11_0_port, b => n812, outb => n811
);
U805 : nor2 port map( a => mult_125_G4_ab_12_0_port, b => n814, outb => n813
);
U806 : nor2 port map( a => mult_125_G4_ab_13_0_port, b => n816, outb => n815
);
U807 : nor2 port map( a => mult_125_G4_ab_14_0_port, b => n818, outb => n817
);
U808 : nor2 port map( a => mult_125_G4_ab_15_0_port, b => n820, outb => n819
);
U809 : nor2 port map( a => mult_125_G4_ZB, b => mult_125_G4_ZA, outb => n274
);
U810 : nand2 port map( a => mult_125_G4_QB, b => mult_125_G4_ab_15_15_port,
outb => n821);
U811 : nor2 port map( a => mult_125_G3_ab_1_15_port, b =>
mult_125_G3_ab_2_14_port, outb => n822);
U812 : nor2 port map( a => mult_125_G3_ab_2_15_port, b =>
mult_125_G3_ab_3_14_port, outb => n823);
U813 : nor2 port map( a => mult_125_G3_ab_3_15_port, b =>
mult_125_G3_ab_4_14_port, outb => n824);
U814 : nor2 port map( a => mult_125_G3_ab_4_15_port, b =>
mult_125_G3_ab_5_14_port, outb => n825);
U815 : nor2 port map( a => mult_125_G3_ab_5_15_port, b =>
mult_125_G3_ab_6_14_port, outb => n826);
U816 : nor2 port map( a => mult_125_G3_ab_6_15_port, b =>
mult_125_G3_ab_7_14_port, outb => n827);
U817 : nor2 port map( a => mult_125_G3_ab_7_15_port, b =>
mult_125_G3_ab_8_14_port, outb => n828);
U818 : nor2 port map( a => mult_125_G3_ab_8_15_port, b =>
mult_125_G3_ab_9_14_port, outb => n829);
U819 : nor2 port map( a => mult_125_G3_ab_9_15_port, b =>
mult_125_G3_ab_10_14_port, outb => n830);
U820 : nor2 port map( a => mult_125_G3_ab_10_15_port, b =>
mult_125_G3_ab_11_14_port, outb => n831);
U821 : nor2 port map( a => mult_125_G3_ab_11_15_port, b =>
mult_125_G3_ab_12_14_port, outb => n832);
U822 : nor2 port map( a => mult_125_G3_ab_12_15_port, b =>
mult_125_G3_ab_13_14_port, outb => n833);
U823 : nor2 port map( a => mult_125_G3_ab_13_15_port, b =>
mult_125_G3_ab_14_14_port, outb => n834);
U824 : nor2 port map( a => mult_125_G3_ab_14_15_port, b =>
mult_125_G3_ab_15_14_port, outb => n835);
U825 : nand2 port map( a => n837, b => n838, outb => n836);
U826 : nand2 port map( a => n840, b => n841, outb => n839);
U827 : nor2 port map( a => mult_125_G3_ab_4_13_port, b => n843, outb => n842
);
U828 : nor2 port map( a => mult_125_G3_ab_5_13_port, b => n845, outb => n844
);
U829 : nor2 port map( a => mult_125_G3_ab_6_13_port, b => n847, outb => n846
);
U830 : nor2 port map( a => mult_125_G3_ab_7_13_port, b => n849, outb => n848
);
U831 : nor2 port map( a => mult_125_G3_ab_8_13_port, b => n851, outb => n850
);
U832 : nor2 port map( a => mult_125_G3_ab_9_13_port, b => n853, outb => n852
);
U833 : nor2 port map( a => mult_125_G3_ab_10_13_port, b => n855, outb =>
n854);
U834 : nor2 port map( a => mult_125_G3_ab_11_13_port, b => n857, outb =>
n856);
U835 : nor2 port map( a => mult_125_G3_ab_12_13_port, b => n859, outb =>
n858);
U836 : nor2 port map( a => mult_125_G3_ab_13_13_port, b => n861, outb =>
n860);
U837 : nor2 port map( a => mult_125_G3_ab_14_13_port, b => n863, outb =>
n862);
U838 : nor2 port map( a => mult_125_G3_ab_15_13_port, b => n865, outb =>
n864);
U839 : nand2 port map( a => n867, b => n868, outb => n866);
U840 : nor2 port map( a => mult_125_G3_ab_3_12_port, b => n870, outb => n869
);
U841 : nor2 port map( a => mult_125_G3_ab_4_12_port, b => n872, outb => n871
);
U842 : nor2 port map( a => mult_125_G3_ab_5_12_port, b => n874, outb => n873
);
U843 : nor2 port map( a => mult_125_G3_ab_6_12_port, b => n876, outb => n875
);
U844 : nor2 port map( a => mult_125_G3_ab_7_12_port, b => n878, outb => n877
);
U845 : nor2 port map( a => mult_125_G3_ab_8_12_port, b => n880, outb => n879
);
U846 : nor2 port map( a => mult_125_G3_ab_9_12_port, b => n882, outb => n881
);
U847 : nor2 port map( a => mult_125_G3_ab_10_12_port, b => n884, outb =>
n883);
U848 : nor2 port map( a => mult_125_G3_ab_11_12_port, b => n886, outb =>
n885);
U849 : nor2 port map( a => mult_125_G3_ab_12_12_port, b => n888, outb =>
n887);
U850 : nor2 port map( a => mult_125_G3_ab_13_12_port, b => n890, outb =>
n889);
U851 : nor2 port map( a => mult_125_G3_ab_14_12_port, b => n892, outb =>
n891);
U852 : nor2 port map( a => mult_125_G3_ab_15_12_port, b => n894, outb =>
n893);
U853 : nand2 port map( a => n896, b => n897, outb => n895);
U854 : nand2 port map( a => n899, b => n900, outb => n898);
U855 : nor2 port map( a => mult_125_G3_ab_4_11_port, b => n902, outb => n901
);
U856 : nor2 port map( a => mult_125_G3_ab_5_11_port, b => n904, outb => n903
);
U857 : nor2 port map( a => mult_125_G3_ab_6_11_port, b => n906, outb => n905
);
U858 : nor2 port map( a => mult_125_G3_ab_7_11_port, b => n908, outb => n907
);
U859 : nor2 port map( a => mult_125_G3_ab_8_11_port, b => n910, outb => n909
);
U860 : nor2 port map( a => mult_125_G3_ab_9_11_port, b => n912, outb => n911
);
U861 : nor2 port map( a => mult_125_G3_ab_10_11_port, b => n914, outb =>
n913);
U862 : nor2 port map( a => mult_125_G3_ab_11_11_port, b => n916, outb =>
n915);
U863 : nor2 port map( a => mult_125_G3_ab_12_11_port, b => n918, outb =>
n917);
U864 : nor2 port map( a => mult_125_G3_ab_13_11_port, b => n920, outb =>
n919);
U865 : nor2 port map( a => mult_125_G3_ab_14_11_port, b => n922, outb =>
n921);
U866 : nand2 port map( a => n924, b => n925, outb => n923);
U867 : nand2 port map( a => n927, b => n928, outb => n926);
U868 : nor2 port map( a => mult_125_G3_ab_3_10_port, b => n930, outb => n929
);
U869 : nor2 port map( a => mult_125_G3_ab_4_10_port, b => n932, outb => n931
);
U870 : nand2 port map( a => n934, b => n935, outb => n933);
U871 : nor2 port map( a => mult_125_G3_ab_6_10_port, b => n937, outb => n936
);
U872 : nor2 port map( a => mult_125_G3_ab_7_10_port, b => n939, outb => n938
);
U873 : nor2 port map( a => mult_125_G3_ab_8_10_port, b => n941, outb => n940
);
U874 : nor2 port map( a => mult_125_G3_ab_9_10_port, b => n943, outb => n942
);
U875 : nor2 port map( a => mult_125_G3_ab_10_10_port, b => n945, outb =>
n944);
U876 : nor2 port map( a => mult_125_G3_ab_11_10_port, b => n947, outb =>
n946);
U877 : nor2 port map( a => mult_125_G3_ab_12_10_port, b => n949, outb =>
n948);
U878 : nor2 port map( a => mult_125_G3_ab_13_10_port, b => n951, outb =>
n950);
U879 : nor2 port map( a => mult_125_G3_ab_14_10_port, b => n953, outb =>
n952);
U880 : nor2 port map( a => mult_125_G3_ab_15_10_port, b => n955, outb =>
n954);
U881 : nand2 port map( a => n957, b => n958, outb => n956);
U882 : nor2 port map( a => mult_125_G3_ab_3_9_port, b => n960, outb => n959)
;
U883 : nor2 port map( a => mult_125_G3_ab_4_9_port, b => n962, outb => n961)
;
U884 : nor2 port map( a => mult_125_G3_ab_5_9_port, b => n964, outb => n963)
;
U885 : nor2 port map( a => mult_125_G3_ab_6_9_port, b => n966, outb => n965)
;
U886 : nor2 port map( a => mult_125_G3_ab_7_9_port, b => n968, outb => n967)
;
U887 : nor2 port map( a => mult_125_G3_ab_8_9_port, b => n970, outb => n969)
;
U888 : nor2 port map( a => mult_125_G3_ab_9_9_port, b => n972, outb => n971)
;
U889 : nor2 port map( a => mult_125_G3_ab_10_9_port, b => n974, outb => n973
);
U890 : nor2 port map( a => mult_125_G3_ab_11_9_port, b => n976, outb => n975
);
U891 : nor2 port map( a => mult_125_G3_ab_12_9_port, b => n978, outb => n977
);
U892 : nor2 port map( a => mult_125_G3_ab_13_9_port, b => n980, outb => n979
);
U893 : nor2 port map( a => mult_125_G3_ab_14_9_port, b => n982, outb => n981
);
U894 : nand2 port map( a => n984, b => n985, outb => n983);
U895 : nand2 port map( a => n987, b => n988, outb => n986);
U896 : nor2 port map( a => mult_125_G3_ab_3_8_port, b => n990, outb => n989)
;
U897 : nor2 port map( a => mult_125_G3_ab_4_8_port, b => n992, outb => n991)
;
U898 : nor2 port map( a => mult_125_G3_ab_5_8_port, b => n994, outb => n993)
;
U899 : nor2 port map( a => mult_125_G3_ab_6_8_port, b => n996, outb => n995)
;
U900 : nor2 port map( a => mult_125_G3_ab_7_8_port, b => n998, outb => n997)
;
U901 : nor2 port map( a => mult_125_G3_ab_8_8_port, b => n1000, outb => n999
);
U902 : nor2 port map( a => mult_125_G3_ab_9_8_port, b => n1002, outb =>
n1001);
U903 : nor2 port map( a => mult_125_G3_ab_10_8_port, b => n1004, outb =>
n1003);
U904 : nor2 port map( a => mult_125_G3_ab_11_8_port, b => n1006, outb =>
n1005);
U905 : nor2 port map( a => mult_125_G3_ab_12_8_port, b => n1008, outb =>
n1007);
U906 : nor2 port map( a => mult_125_G3_ab_13_8_port, b => n1010, outb =>
n1009);
U907 : nor2 port map( a => mult_125_G3_ab_14_8_port, b => n1012, outb =>
n1011);
U908 : nor2 port map( a => mult_125_G3_ab_15_8_port, b => n1014, outb =>
n1013);
U909 : nand2 port map( a => n1016, b => n1017, outb => n1015);
U910 : nand2 port map( a => n1019, b => n1020, outb => n1018);
U911 : nor2 port map( a => mult_125_G3_ab_4_7_port, b => n1022, outb =>
n1021);
U912 : nor2 port map( a => mult_125_G3_ab_5_7_port, b => n1024, outb =>
n1023);
U913 : nor2 port map( a => mult_125_G3_ab_6_7_port, b => n1026, outb =>
n1025);
U914 : nor2 port map( a => mult_125_G3_ab_7_7_port, b => n1028, outb =>
n1027);
U915 : nor2 port map( a => mult_125_G3_ab_8_7_port, b => n1030, outb =>
n1029);
U916 : nor2 port map( a => mult_125_G3_ab_9_7_port, b => n1032, outb =>
n1031);
U917 : nor2 port map( a => mult_125_G3_ab_10_7_port, b => n1034, outb =>
n1033);
U918 : nor2 port map( a => mult_125_G3_ab_11_7_port, b => n1036, outb =>
n1035);
U919 : nor2 port map( a => mult_125_G3_ab_12_7_port, b => n1038, outb =>
n1037);
U920 : nor2 port map( a => mult_125_G3_ab_13_7_port, b => n1040, outb =>
n1039);
U921 : nor2 port map( a => mult_125_G3_ab_14_7_port, b => n1042, outb =>
n1041);
U922 : nand2 port map( a => n1044, b => n1045, outb => n1043);
U923 : nand2 port map( a => n1047, b => n1048, outb => n1046);
U924 : nor2 port map( a => mult_125_G3_ab_3_6_port, b => n1050, outb =>
n1049);
U925 : nor2 port map( a => mult_125_G3_ab_4_6_port, b => n1052, outb =>
n1051);
U926 : nand2 port map( a => n1054, b => n1055, outb => n1053);
U927 : nor2 port map( a => mult_125_G3_ab_6_6_port, b => n1057, outb =>
n1056);
U928 : nor2 port map( a => mult_125_G3_ab_7_6_port, b => n1059, outb =>
n1058);
U929 : nor2 port map( a => mult_125_G3_ab_8_6_port, b => n1061, outb =>
n1060);
U930 : nand2 port map( a => n1063, b => n1064, outb => n1062);
U931 : nor2 port map( a => mult_125_G3_ab_10_6_port, b => n1066, outb =>
n1065);
U932 : nor2 port map( a => mult_125_G3_ab_11_6_port, b => n1068, outb =>
n1067);
U933 : nor2 port map( a => mult_125_G3_ab_12_6_port, b => n1070, outb =>
n1069);
U934 : nor2 port map( a => mult_125_G3_ab_13_6_port, b => n1072, outb =>
n1071);
U935 : nor2 port map( a => mult_125_G3_ab_14_6_port, b => n1074, outb =>
n1073);
U936 : nor2 port map( a => mult_125_G3_ab_15_6_port, b => n1076, outb =>
n1075);
U937 : nand2 port map( a => n1078, b => n1079, outb => n1077);
U938 : nand2 port map( a => n1081, b => n1082, outb => n1080);
U939 : nor2 port map( a => mult_125_G3_ab_4_5_port, b => n1084, outb =>
n1083);
U940 : nor2 port map( a => mult_125_G3_ab_5_5_port, b => n1086, outb =>
n1085);
U941 : nand2 port map( a => n1088, b => n1089, outb => n1087);
U942 : nor2 port map( a => mult_125_G3_ab_7_5_port, b => n1091, outb =>
n1090);
U943 : nor2 port map( a => mult_125_G3_ab_8_5_port, b => n1093, outb =>
n1092);
U944 : nor2 port map( a => mult_125_G3_ab_9_5_port, b => n1095, outb =>
n1094);
U945 : nor2 port map( a => mult_125_G3_ab_10_5_port, b => n1097, outb =>
n1096);
U946 : nor2 port map( a => mult_125_G3_ab_11_5_port, b => n1099, outb =>
n1098);
U947 : nor2 port map( a => mult_125_G3_ab_12_5_port, b => n1101, outb =>
n1100);
U948 : nor2 port map( a => mult_125_G3_ab_13_5_port, b => n1103, outb =>
n1102);
U949 : nor2 port map( a => mult_125_G3_ab_14_5_port, b => n1105, outb =>
n1104);
U950 : nand2 port map( a => n1107, b => n1108, outb => n1106);
U951 : nand2 port map( a => n1110, b => n1111, outb => n1109);
U952 : nor2 port map( a => mult_125_G3_ab_3_4_port, b => n1113, outb =>
n1112);
U953 : nor2 port map( a => mult_125_G3_ab_4_4_port, b => n1115, outb =>
n1114);
U954 : nand2 port map( a => n1117, b => n1118, outb => n1116);
U955 : nor2 port map( a => mult_125_G3_ab_6_4_port, b => n1120, outb =>
n1119);
U956 : nand2 port map( a => n1122, b => n1123, outb => n1121);
U957 : nor2 port map( a => mult_125_G3_ab_8_4_port, b => n1125, outb =>
n1124);
U958 : nor2 port map( a => mult_125_G3_ab_9_4_port, b => n1127, outb =>
n1126);
U959 : nor2 port map( a => mult_125_G3_ab_10_4_port, b => n1129, outb =>
n1128);
U960 : nand2 port map( a => n1131, b => n1132, outb => n1130);
U961 : nor2 port map( a => mult_125_G3_ab_12_4_port, b => n1134, outb =>
n1133);
U962 : nor2 port map( a => mult_125_G3_ab_13_4_port, b => n1136, outb =>
n1135);
U963 : nor2 port map( a => mult_125_G3_ab_14_4_port, b => n1138, outb =>
n1137);
U964 : nand2 port map( a => n1140, b => n1141, outb => n1139);
U965 : nand2 port map( a => n1143, b => n1144, outb => n1142);
U966 : nand2 port map( a => n1146, b => n1147, outb => n1145);
U967 : nor2 port map( a => mult_125_G3_ab_4_3_port, b => n1149, outb =>
n1148);
U968 : nor2 port map( a => mult_125_G3_ab_5_3_port, b => n1151, outb =>
n1150);
U969 : nor2 port map( a => mult_125_G3_ab_6_3_port, b => n1153, outb =>
n1152);
U970 : nor2 port map( a => mult_125_G3_ab_7_3_port, b => n1155, outb =>
n1154);
U971 : nor2 port map( a => mult_125_G3_ab_8_3_port, b => n1157, outb =>
n1156);
U972 : nor2 port map( a => mult_125_G3_ab_9_3_port, b => n1159, outb =>
n1158);
U973 : nor2 port map( a => mult_125_G3_ab_10_3_port, b => n1161, outb =>
n1160);
U974 : nor2 port map( a => mult_125_G3_ab_11_3_port, b => n1163, outb =>
n1162);
U975 : nor2 port map( a => mult_125_G3_ab_12_3_port, b => n1165, outb =>
n1164);
U976 : nor2 port map( a => mult_125_G3_ab_13_3_port, b => n1167, outb =>
n1166);
U977 : nor2 port map( a => mult_125_G3_ab_14_3_port, b => n1169, outb =>
n1168);
U978 : nor2 port map( a => mult_125_G3_ab_15_3_port, b => n1171, outb =>
n1170);
U979 : nand2 port map( a => n1173, b => n1174, outb => n1172);
U980 : nor2 port map( a => mult_125_G3_ab_3_2_port, b => n1176, outb =>
n1175);
U981 : nor2 port map( a => mult_125_G3_ab_4_2_port, b => n1178, outb =>
n1177);
U982 : nor2 port map( a => mult_125_G3_ab_5_2_port, b => n1180, outb =>
n1179);
U983 : nor2 port map( a => mult_125_G3_ab_6_2_port, b => n1182, outb =>
n1181);
U984 : nand2 port map( a => n1184, b => n1185, outb => n1183);
U985 : nor2 port map( a => mult_125_G3_ab_8_2_port, b => n1187, outb =>
n1186);
U986 : nor2 port map( a => mult_125_G3_ab_9_2_port, b => n1189, outb =>
n1188);
U987 : nor2 port map( a => mult_125_G3_ab_10_2_port, b => n1191, outb =>
n1190);
U988 : nor2 port map( a => mult_125_G3_ab_11_2_port, b => n1193, outb =>
n1192);
U989 : nor2 port map( a => mult_125_G3_ab_12_2_port, b => n1195, outb =>
n1194);
U990 : nor2 port map( a => mult_125_G3_ab_13_2_port, b => n1197, outb =>
n1196);
U991 : nor2 port map( a => mult_125_G3_ab_14_2_port, b => n1199, outb =>
n1198);
U992 : nor2 port map( a => mult_125_G3_ab_15_2_port, b => n1201, outb =>
n1200);
U993 : nand2 port map( a => n1203, b => n1204, outb => n1202);
U994 : nor2 port map( a => mult_125_G3_ab_3_1_port, b => n1206, outb =>
n1205);
U995 : nor2 port map( a => mult_125_G3_ab_4_1_port, b => n1208, outb =>
n1207);
U996 : nor2 port map( a => mult_125_G3_ab_5_1_port, b => n1210, outb =>
n1209);
U997 : nor2 port map( a => mult_125_G3_ab_6_1_port, b => n1212, outb =>
n1211);
U998 : nor2 port map( a => mult_125_G3_ab_7_1_port, b => n1214, outb =>
n1213);
U999 : nor2 port map( a => mult_125_G3_ab_8_1_port, b => n1216, outb =>
n1215);
U1000 : nor2 port map( a => mult_125_G3_ab_9_1_port, b => n1218, outb =>
n1217);
U1001 : nor2 port map( a => mult_125_G3_ab_10_1_port, b => n1220, outb =>
n1219);
U1002 : nor2 port map( a => mult_125_G3_ab_11_1_port, b => n1222, outb =>
n1221);
U1003 : nor2 port map( a => mult_125_G3_ab_12_1_port, b => n1224, outb =>
n1223);
U1004 : nor2 port map( a => mult_125_G3_ab_13_1_port, b => n1226, outb =>
n1225);
U1005 : nor2 port map( a => mult_125_G3_ab_14_1_port, b => n1228, outb =>
n1227);
U1006 : nor2 port map( a => mult_125_G3_ab_15_1_port, b => n1230, outb =>
n1229);
U1007 : nor2 port map( a => mult_125_G3_ab_2_0_port, b => n1232, outb =>
n1231);
U1008 : nor2 port map( a => mult_125_G3_ab_3_0_port, b => n1234, outb =>
n1233);
U1009 : nor2 port map( a => mult_125_G3_ab_4_0_port, b => n1236, outb =>
n1235);
U1010 : nor2 port map( a => mult_125_G3_ab_5_0_port, b => n1238, outb =>
n1237);
U1011 : nor2 port map( a => mult_125_G3_ab_6_0_port, b => n1240, outb =>
n1239);
U1012 : nor2 port map( a => mult_125_G3_ab_7_0_port, b => n1242, outb =>
n1241);
U1013 : nor2 port map( a => mult_125_G3_ab_8_0_port, b => n1244, outb =>
n1243);
U1014 : nor2 port map( a => mult_125_G3_ab_9_0_port, b => n1246, outb =>
n1245);
U1015 : nor2 port map( a => mult_125_G3_ab_10_0_port, b => n1248, outb =>
n1247);
U1016 : nor2 port map( a => mult_125_G3_ab_11_0_port, b => n1250, outb =>
n1249);
U1017 : nor2 port map( a => mult_125_G3_ab_12_0_port, b => n1252, outb =>
n1251);
U1018 : nor2 port map( a => mult_125_G3_ab_13_0_port, b => n1254, outb =>
n1253);
U1019 : nor2 port map( a => mult_125_G3_ab_14_0_port, b => n1256, outb =>
n1255);
U1020 : nor2 port map( a => mult_125_G3_ab_15_0_port, b => n1258, outb =>
n1257);
U1021 : nor2 port map( a => mult_125_G3_ZB, b => mult_125_G3_ZA, outb =>
n382);
U1022 : nand2 port map( a => mult_125_G3_QB, b => mult_125_G3_ab_15_15_port,
outb => n1259);
U1023 : nor2 port map( a => mult_125_G2_ab_1_15_port, b =>
mult_125_G2_ab_2_14_port, outb => n1260);
U1024 : nor2 port map( a => mult_125_G2_ab_2_15_port, b =>
mult_125_G2_ab_3_14_port, outb => n1261);
U1025 : nor2 port map( a => mult_125_G2_ab_3_15_port, b =>
mult_125_G2_ab_4_14_port, outb => n1262);
U1026 : nor2 port map( a => mult_125_G2_ab_4_15_port, b =>
mult_125_G2_ab_5_14_port, outb => n1263);
U1027 : nor2 port map( a => mult_125_G2_ab_5_15_port, b =>
mult_125_G2_ab_6_14_port, outb => n1264);
U1028 : nor2 port map( a => mult_125_G2_ab_6_15_port, b =>
mult_125_G2_ab_7_14_port, outb => n1265);
U1029 : nor2 port map( a => mult_125_G2_ab_7_15_port, b =>
mult_125_G2_ab_8_14_port, outb => n1266);
U1030 : nor2 port map( a => mult_125_G2_ab_8_15_port, b =>
mult_125_G2_ab_9_14_port, outb => n1267);
U1031 : nor2 port map( a => mult_125_G2_ab_9_15_port, b =>
mult_125_G2_ab_10_14_port, outb => n1268);
U1032 : nor2 port map( a => mult_125_G2_ab_10_15_port, b =>
mult_125_G2_ab_11_14_port, outb => n1269);
U1033 : nor2 port map( a => mult_125_G2_ab_11_15_port, b =>
mult_125_G2_ab_12_14_port, outb => n1270);
U1034 : nor2 port map( a => mult_125_G2_ab_12_15_port, b =>
mult_125_G2_ab_13_14_port, outb => n1271);
U1035 : nor2 port map( a => mult_125_G2_ab_13_15_port, b =>
mult_125_G2_ab_14_14_port, outb => n1272);
U1036 : nor2 port map( a => mult_125_G2_ab_14_15_port, b =>
mult_125_G2_ab_15_14_port, outb => n1273);
U1037 : nand2 port map( a => n1275, b => n1276, outb => n1274);
U1038 : nand2 port map( a => n1278, b => n1279, outb => n1277);
U1039 : nor2 port map( a => mult_125_G2_ab_4_13_port, b => n1281, outb =>
n1280);
U1040 : nor2 port map( a => mult_125_G2_ab_5_13_port, b => n1283, outb =>
n1282);
U1041 : nor2 port map( a => mult_125_G2_ab_6_13_port, b => n1285, outb =>
n1284);
U1042 : nor2 port map( a => mult_125_G2_ab_7_13_port, b => n1287, outb =>
n1286);
U1043 : nor2 port map( a => mult_125_G2_ab_8_13_port, b => n1289, outb =>
n1288);
U1044 : nor2 port map( a => mult_125_G2_ab_9_13_port, b => n1291, outb =>
n1290);
U1045 : nor2 port map( a => mult_125_G2_ab_10_13_port, b => n1293, outb =>
n1292);
U1046 : nor2 port map( a => mult_125_G2_ab_11_13_port, b => n1295, outb =>
n1294);
U1047 : nor2 port map( a => mult_125_G2_ab_12_13_port, b => n1297, outb =>
n1296);
U1048 : nor2 port map( a => mult_125_G2_ab_13_13_port, b => n1299, outb =>
n1298);
U1049 : nor2 port map( a => mult_125_G2_ab_14_13_port, b => n1301, outb =>
n1300);
U1050 : nor2 port map( a => mult_125_G2_ab_15_13_port, b => n1303, outb =>
n1302);
U1051 : nand2 port map( a => n1305, b => n1306, outb => n1304);
U1052 : nor2 port map( a => mult_125_G2_ab_3_12_port, b => n1308, outb =>
n1307);
U1053 : nor2 port map( a => mult_125_G2_ab_4_12_port, b => n1310, outb =>
n1309);
U1054 : nor2 port map( a => mult_125_G2_ab_5_12_port, b => n1312, outb =>
n1311);
U1055 : nor2 port map( a => mult_125_G2_ab_6_12_port, b => n1314, outb =>
n1313);
U1056 : nor2 port map( a => mult_125_G2_ab_7_12_port, b => n1316, outb =>
n1315);
U1057 : nor2 port map( a => mult_125_G2_ab_8_12_port, b => n1318, outb =>
n1317);
U1058 : nor2 port map( a => mult_125_G2_ab_9_12_port, b => n1320, outb =>
n1319);
U1059 : nor2 port map( a => mult_125_G2_ab_10_12_port, b => n1322, outb =>
n1321);
U1060 : nor2 port map( a => mult_125_G2_ab_11_12_port, b => n1324, outb =>
n1323);
U1061 : nor2 port map( a => mult_125_G2_ab_12_12_port, b => n1326, outb =>
n1325);
U1062 : nor2 port map( a => mult_125_G2_ab_13_12_port, b => n1328, outb =>
n1327);
U1063 : nor2 port map( a => mult_125_G2_ab_14_12_port, b => n1330, outb =>
n1329);
U1064 : nor2 port map( a => mult_125_G2_ab_15_12_port, b => n1332, outb =>
n1331);
U1065 : nand2 port map( a => n1334, b => n1335, outb => n1333);
U1066 : nand2 port map( a => n1337, b => n1338, outb => n1336);
U1067 : nor2 port map( a => mult_125_G2_ab_4_11_port, b => n1340, outb =>
n1339);
U1068 : nor2 port map( a => mult_125_G2_ab_5_11_port, b => n1342, outb =>
n1341);
U1069 : nor2 port map( a => mult_125_G2_ab_6_11_port, b => n1344, outb =>
n1343);
U1070 : nor2 port map( a => mult_125_G2_ab_7_11_port, b => n1346, outb =>
n1345);
U1071 : nor2 port map( a => mult_125_G2_ab_8_11_port, b => n1348, outb =>
n1347);
U1072 : nor2 port map( a => mult_125_G2_ab_9_11_port, b => n1350, outb =>
n1349);
U1073 : nor2 port map( a => mult_125_G2_ab_10_11_port, b => n1352, outb =>
n1351);
U1074 : nor2 port map( a => mult_125_G2_ab_11_11_port, b => n1354, outb =>
n1353);
U1075 : nor2 port map( a => mult_125_G2_ab_12_11_port, b => n1356, outb =>
n1355);
U1076 : nor2 port map( a => mult_125_G2_ab_13_11_port, b => n1358, outb =>
n1357);
U1077 : nor2 port map( a => mult_125_G2_ab_14_11_port, b => n1360, outb =>
n1359);
U1078 : nand2 port map( a => n1362, b => n1363, outb => n1361);
U1079 : nand2 port map( a => n1365, b => n1366, outb => n1364);
U1080 : nor2 port map( a => mult_125_G2_ab_3_10_port, b => n1368, outb =>
n1367);
U1081 : nor2 port map( a => mult_125_G2_ab_4_10_port, b => n1370, outb =>
n1369);
U1082 : nand2 port map( a => n1372, b => n1373, outb => n1371);
U1083 : nor2 port map( a => mult_125_G2_ab_6_10_port, b => n1375, outb =>
n1374);
U1084 : nor2 port map( a => mult_125_G2_ab_7_10_port, b => n1377, outb =>
n1376);
U1085 : nor2 port map( a => mult_125_G2_ab_8_10_port, b => n1379, outb =>
n1378);
U1086 : nor2 port map( a => mult_125_G2_ab_9_10_port, b => n1381, outb =>
n1380);
U1087 : nor2 port map( a => mult_125_G2_ab_10_10_port, b => n1383, outb =>
n1382);
U1088 : nor2 port map( a => mult_125_G2_ab_11_10_port, b => n1385, outb =>
n1384);
U1089 : nor2 port map( a => mult_125_G2_ab_12_10_port, b => n1387, outb =>
n1386);
U1090 : nor2 port map( a => mult_125_G2_ab_13_10_port, b => n1389, outb =>
n1388);
U1091 : nor2 port map( a => mult_125_G2_ab_14_10_port, b => n1391, outb =>
n1390);
U1092 : nor2 port map( a => mult_125_G2_ab_15_10_port, b => n1393, outb =>
n1392);
U1093 : nand2 port map( a => n1395, b => n1396, outb => n1394);
U1094 : nor2 port map( a => mult_125_G2_ab_3_9_port, b => n1398, outb =>
n1397);
U1095 : nor2 port map( a => mult_125_G2_ab_4_9_port, b => n1400, outb =>
n1399);
U1096 : nor2 port map( a => mult_125_G2_ab_5_9_port, b => n1402, outb =>
n1401);
U1097 : nor2 port map( a => mult_125_G2_ab_6_9_port, b => n1404, outb =>
n1403);
U1098 : nor2 port map( a => mult_125_G2_ab_7_9_port, b => n1406, outb =>
n1405);
U1099 : nor2 port map( a => mult_125_G2_ab_8_9_port, b => n1408, outb =>
n1407);
U1100 : nor2 port map( a => mult_125_G2_ab_9_9_port, b => n1410, outb =>
n1409);
U1101 : nor2 port map( a => mult_125_G2_ab_10_9_port, b => n1412, outb =>
n1411);
U1102 : nor2 port map( a => mult_125_G2_ab_11_9_port, b => n1414, outb =>
n1413);
U1103 : nor2 port map( a => mult_125_G2_ab_12_9_port, b => n1416, outb =>
n1415);
U1104 : nor2 port map( a => mult_125_G2_ab_13_9_port, b => n1418, outb =>
n1417);
U1105 : nor2 port map( a => mult_125_G2_ab_14_9_port, b => n1420, outb =>
n1419);
U1106 : nand2 port map( a => n1422, b => n1423, outb => n1421);
U1107 : nand2 port map( a => n1425, b => n1426, outb => n1424);
U1108 : nor2 port map( a => mult_125_G2_ab_3_8_port, b => n1428, outb =>
n1427);
U1109 : nor2 port map( a => mult_125_G2_ab_4_8_port, b => n1430, outb =>
n1429);
U1110 : nor2 port map( a => mult_125_G2_ab_5_8_port, b => n1432, outb =>
n1431);
U1111 : nor2 port map( a => mult_125_G2_ab_6_8_port, b => n1434, outb =>
n1433);
U1112 : nor2 port map( a => mult_125_G2_ab_7_8_port, b => n1436, outb =>
n1435);
U1113 : nor2 port map( a => mult_125_G2_ab_8_8_port, b => n1438, outb =>
n1437);
U1114 : nor2 port map( a => mult_125_G2_ab_9_8_port, b => n1440, outb =>
n1439);
U1115 : nor2 port map( a => mult_125_G2_ab_10_8_port, b => n1442, outb =>
n1441);
U1116 : nor2 port map( a => mult_125_G2_ab_11_8_port, b => n1444, outb =>
n1443);
U1117 : nor2 port map( a => mult_125_G2_ab_12_8_port, b => n1446, outb =>
n1445);
U1118 : nor2 port map( a => mult_125_G2_ab_13_8_port, b => n1448, outb =>
n1447);
U1119 : nor2 port map( a => mult_125_G2_ab_14_8_port, b => n1450, outb =>
n1449);
U1120 : nor2 port map( a => mult_125_G2_ab_15_8_port, b => n1452, outb =>
n1451);
U1121 : nand2 port map( a => n1454, b => n1455, outb => n1453);
U1122 : nand2 port map( a => n1457, b => n1458, outb => n1456);
U1123 : nor2 port map( a => mult_125_G2_ab_4_7_port, b => n1460, outb =>
n1459);
U1124 : nor2 port map( a => mult_125_G2_ab_5_7_port, b => n1462, outb =>
n1461);
U1125 : nor2 port map( a => mult_125_G2_ab_6_7_port, b => n1464, outb =>
n1463);
U1126 : nor2 port map( a => mult_125_G2_ab_7_7_port, b => n1466, outb =>
n1465);
U1127 : nor2 port map( a => mult_125_G2_ab_8_7_port, b => n1468, outb =>
n1467);
U1128 : nor2 port map( a => mult_125_G2_ab_9_7_port, b => n1470, outb =>
n1469);
U1129 : nor2 port map( a => mult_125_G2_ab_10_7_port, b => n1472, outb =>
n1471);
U1130 : nor2 port map( a => mult_125_G2_ab_11_7_port, b => n1474, outb =>
n1473);
U1131 : nor2 port map( a => mult_125_G2_ab_12_7_port, b => n1476, outb =>
n1475);
U1132 : nor2 port map( a => mult_125_G2_ab_13_7_port, b => n1478, outb =>
n1477);
U1133 : nor2 port map( a => mult_125_G2_ab_14_7_port, b => n1480, outb =>
n1479);
U1134 : nand2 port map( a => n1482, b => n1483, outb => n1481);
U1135 : nand2 port map( a => n1485, b => n1486, outb => n1484);
U1136 : nor2 port map( a => mult_125_G2_ab_3_6_port, b => n1488, outb =>
n1487);
U1137 : nor2 port map( a => mult_125_G2_ab_4_6_port, b => n1490, outb =>
n1489);
U1138 : nand2 port map( a => n1492, b => n1493, outb => n1491);
U1139 : nor2 port map( a => mult_125_G2_ab_6_6_port, b => n1495, outb =>
n1494);
U1140 : nor2 port map( a => mult_125_G2_ab_7_6_port, b => n1497, outb =>
n1496);
U1141 : nor2 port map( a => mult_125_G2_ab_8_6_port, b => n1499, outb =>
n1498);
U1142 : nand2 port map( a => n1501, b => n1502, outb => n1500);
U1143 : nor2 port map( a => mult_125_G2_ab_10_6_port, b => n1504, outb =>
n1503);
U1144 : nor2 port map( a => mult_125_G2_ab_11_6_port, b => n1506, outb =>
n1505);
U1145 : nor2 port map( a => mult_125_G2_ab_12_6_port, b => n1508, outb =>
n1507);
U1146 : nor2 port map( a => mult_125_G2_ab_13_6_port, b => n1510, outb =>
n1509);
U1147 : nor2 port map( a => mult_125_G2_ab_14_6_port, b => n1512, outb =>
n1511);
U1148 : nor2 port map( a => mult_125_G2_ab_15_6_port, b => n1514, outb =>
n1513);
U1149 : nand2 port map( a => n1516, b => n1517, outb => n1515);
U1150 : nand2 port map( a => n1519, b => n1520, outb => n1518);
U1151 : nor2 port map( a => mult_125_G2_ab_4_5_port, b => n1522, outb =>
n1521);
U1152 : nor2 port map( a => mult_125_G2_ab_5_5_port, b => n1524, outb =>
n1523);
U1153 : nand2 port map( a => n1526, b => n1527, outb => n1525);
U1154 : nor2 port map( a => mult_125_G2_ab_7_5_port, b => n1529, outb =>
n1528);
U1155 : nor2 port map( a => mult_125_G2_ab_8_5_port, b => n1531, outb =>
n1530);
U1156 : nor2 port map( a => mult_125_G2_ab_9_5_port, b => n1533, outb =>
n1532);
U1157 : nor2 port map( a => mult_125_G2_ab_10_5_port, b => n1535, outb =>
n1534);
U1158 : nor2 port map( a => mult_125_G2_ab_11_5_port, b => n1537, outb =>
n1536);
U1159 : nor2 port map( a => mult_125_G2_ab_12_5_port, b => n1539, outb =>
n1538);
U1160 : nor2 port map( a => mult_125_G2_ab_13_5_port, b => n1541, outb =>
n1540);
U1161 : nor2 port map( a => mult_125_G2_ab_14_5_port, b => n1543, outb =>
n1542);
U1162 : nand2 port map( a => n1545, b => n1546, outb => n1544);
U1163 : nand2 port map( a => n1548, b => n1549, outb => n1547);
U1164 : nor2 port map( a => mult_125_G2_ab_3_4_port, b => n1551, outb =>
n1550);
U1165 : nor2 port map( a => mult_125_G2_ab_4_4_port, b => n1553, outb =>
n1552);
U1166 : nand2 port map( a => n1555, b => n1556, outb => n1554);
U1167 : nor2 port map( a => mult_125_G2_ab_6_4_port, b => n1558, outb =>
n1557);
U1168 : nand2 port map( a => n1560, b => n1561, outb => n1559);
U1169 : nor2 port map( a => mult_125_G2_ab_8_4_port, b => n1563, outb =>
n1562);
U1170 : nor2 port map( a => mult_125_G2_ab_9_4_port, b => n1565, outb =>
n1564);
U1171 : nor2 port map( a => mult_125_G2_ab_10_4_port, b => n1567, outb =>
n1566);
U1172 : nand2 port map( a => n1569, b => n1570, outb => n1568);
U1173 : nor2 port map( a => mult_125_G2_ab_12_4_port, b => n1572, outb =>
n1571);
U1174 : nor2 port map( a => mult_125_G2_ab_13_4_port, b => n1574, outb =>
n1573);
U1175 : nor2 port map( a => mult_125_G2_ab_14_4_port, b => n1576, outb =>
n1575);
U1176 : nand2 port map( a => n1578, b => n1579, outb => n1577);
U1177 : nand2 port map( a => n1581, b => n1582, outb => n1580);
U1178 : nand2 port map( a => n1584, b => n1585, outb => n1583);
U1179 : nor2 port map( a => mult_125_G2_ab_4_3_port, b => n1587, outb =>
n1586);
U1180 : nor2 port map( a => mult_125_G2_ab_5_3_port, b => n1589, outb =>
n1588);
U1181 : nor2 port map( a => mult_125_G2_ab_6_3_port, b => n1591, outb =>
n1590);
U1182 : nor2 port map( a => mult_125_G2_ab_7_3_port, b => n1593, outb =>
n1592);
U1183 : nor2 port map( a => mult_125_G2_ab_8_3_port, b => n1595, outb =>
n1594);
U1184 : nor2 port map( a => mult_125_G2_ab_9_3_port, b => n1597, outb =>
n1596);
U1185 : nor2 port map( a => mult_125_G2_ab_10_3_port, b => n1599, outb =>
n1598);
U1186 : nor2 port map( a => mult_125_G2_ab_11_3_port, b => n1601, outb =>
n1600);
U1187 : nor2 port map( a => mult_125_G2_ab_12_3_port, b => n1603, outb =>
n1602);
U1188 : nor2 port map( a => mult_125_G2_ab_13_3_port, b => n1605, outb =>
n1604);
U1189 : nor2 port map( a => mult_125_G2_ab_14_3_port, b => n1607, outb =>
n1606);
U1190 : nor2 port map( a => mult_125_G2_ab_15_3_port, b => n1609, outb =>
n1608);
U1191 : nand2 port map( a => n1611, b => n1612, outb => n1610);
U1192 : nor2 port map( a => mult_125_G2_ab_3_2_port, b => n1614, outb =>
n1613);
U1193 : nor2 port map( a => mult_125_G2_ab_4_2_port, b => n1616, outb =>
n1615);
U1194 : nor2 port map( a => mult_125_G2_ab_5_2_port, b => n1618, outb =>
n1617);
U1195 : nor2 port map( a => mult_125_G2_ab_6_2_port, b => n1620, outb =>
n1619);
U1196 : nand2 port map( a => n1622, b => n1623, outb => n1621);
U1197 : nor2 port map( a => mult_125_G2_ab_8_2_port, b => n1625, outb =>
n1624);
U1198 : nor2 port map( a => mult_125_G2_ab_9_2_port, b => n1627, outb =>
n1626);
U1199 : nor2 port map( a => mult_125_G2_ab_10_2_port, b => n1629, outb =>
n1628);
U1200 : nor2 port map( a => mult_125_G2_ab_11_2_port, b => n1631, outb =>
n1630);
U1201 : nor2 port map( a => mult_125_G2_ab_12_2_port, b => n1633, outb =>
n1632);
U1202 : nor2 port map( a => mult_125_G2_ab_13_2_port, b => n1635, outb =>
n1634);
U1203 : nor2 port map( a => mult_125_G2_ab_14_2_port, b => n1637, outb =>
n1636);
U1204 : nor2 port map( a => mult_125_G2_ab_15_2_port, b => n1639, outb =>
n1638);
U1205 : nand2 port map( a => n1641, b => n1642, outb => n1640);
U1206 : nor2 port map( a => mult_125_G2_ab_3_1_port, b => n1644, outb =>
n1643);
U1207 : nor2 port map( a => mult_125_G2_ab_4_1_port, b => n1646, outb =>
n1645);
U1208 : nor2 port map( a => mult_125_G2_ab_5_1_port, b => n1648, outb =>
n1647);
U1209 : nor2 port map( a => mult_125_G2_ab_6_1_port, b => n1650, outb =>
n1649);
U1210 : nor2 port map( a => mult_125_G2_ab_7_1_port, b => n1652, outb =>
n1651);
U1211 : nor2 port map( a => mult_125_G2_ab_8_1_port, b => n1654, outb =>
n1653);
U1212 : nor2 port map( a => mult_125_G2_ab_9_1_port, b => n1656, outb =>
n1655);
U1213 : nor2 port map( a => mult_125_G2_ab_10_1_port, b => n1658, outb =>
n1657);
U1214 : nor2 port map( a => mult_125_G2_ab_11_1_port, b => n1660, outb =>
n1659);
U1215 : nor2 port map( a => mult_125_G2_ab_12_1_port, b => n1662, outb =>
n1661);
U1216 : nor2 port map( a => mult_125_G2_ab_13_1_port, b => n1664, outb =>
n1663);
U1217 : nor2 port map( a => mult_125_G2_ab_14_1_port, b => n1666, outb =>
n1665);
U1218 : nor2 port map( a => mult_125_G2_ab_15_1_port, b => n1668, outb =>
n1667);
U1219 : nor2 port map( a => mult_125_G2_ab_2_0_port, b => n1670, outb =>
n1669);
U1220 : nor2 port map( a => mult_125_G2_ab_3_0_port, b => n1672, outb =>
n1671);
U1221 : nor2 port map( a => mult_125_G2_ab_4_0_port, b => n1674, outb =>
n1673);
U1222 : nor2 port map( a => mult_125_G2_ab_5_0_port, b => n1676, outb =>
n1675);
U1223 : nor2 port map( a => mult_125_G2_ab_6_0_port, b => n1678, outb =>
n1677);
U1224 : nor2 port map( a => mult_125_G2_ab_7_0_port, b => n1680, outb =>
n1679);
U1225 : nor2 port map( a => mult_125_G2_ab_8_0_port, b => n1682, outb =>
n1681);
U1226 : nor2 port map( a => mult_125_G2_ab_9_0_port, b => n1684, outb =>
n1683);
U1227 : nor2 port map( a => mult_125_G2_ab_10_0_port, b => n1686, outb =>
n1685);
U1228 : nor2 port map( a => mult_125_G2_ab_11_0_port, b => n1688, outb =>
n1687);
U1229 : nor2 port map( a => mult_125_G2_ab_12_0_port, b => n1690, outb =>
n1689);
U1230 : nor2 port map( a => mult_125_G2_ab_13_0_port, b => n1692, outb =>
n1691);
U1231 : nor2 port map( a => mult_125_G2_ab_14_0_port, b => n1694, outb =>
n1693);
U1232 : nor2 port map( a => mult_125_G2_ab_15_0_port, b => n1696, outb =>
n1695);
U1233 : nor2 port map( a => mult_125_G2_ZB, b => mult_125_G2_ZA, outb =>
n346);
U1234 : nand2 port map( a => mult_125_G2_QB, b => mult_125_G2_ab_15_15_port,
outb => n1697);
U1235 : nor2 port map( a => mult_125_ab_1_15_port, b =>
mult_125_ab_2_14_port, outb => n1698);
U1236 : nor2 port map( a => mult_125_ab_2_15_port, b =>
mult_125_ab_3_14_port, outb => n1699);
U1237 : nor2 port map( a => mult_125_ab_3_15_port, b =>
mult_125_ab_4_14_port, outb => n1700);
U1238 : nor2 port map( a => mult_125_ab_4_15_port, b =>
mult_125_ab_5_14_port, outb => n1701);
U1239 : nor2 port map( a => mult_125_ab_5_15_port, b =>
mult_125_ab_6_14_port, outb => n1702);
U1240 : nor2 port map( a => mult_125_ab_6_15_port, b =>
mult_125_ab_7_14_port, outb => n1703);
U1241 : nor2 port map( a => mult_125_ab_7_15_port, b =>
mult_125_ab_8_14_port, outb => n1704);
U1242 : nor2 port map( a => mult_125_ab_8_15_port, b =>
mult_125_ab_9_14_port, outb => n1705);
U1243 : nor2 port map( a => mult_125_ab_9_15_port, b =>
mult_125_ab_10_14_port, outb => n1706);
U1244 : nor2 port map( a => mult_125_ab_10_15_port, b =>
mult_125_ab_11_14_port, outb => n1707);
U1245 : nor2 port map( a => mult_125_ab_11_15_port, b =>
mult_125_ab_12_14_port, outb => n1708);
U1246 : nor2 port map( a => mult_125_ab_12_15_port, b =>
mult_125_ab_13_14_port, outb => n1709);
U1247 : nor2 port map( a => mult_125_ab_13_15_port, b =>
mult_125_ab_14_14_port, outb => n1710);
U1248 : nor2 port map( a => mult_125_ab_14_15_port, b =>
mult_125_ab_15_14_port, outb => n1711);
U1249 : nand2 port map( a => n1713, b => n1714, outb => n1712);
U1250 : nand2 port map( a => n1716, b => n1717, outb => n1715);
U1251 : nor2 port map( a => mult_125_ab_4_13_port, b => n1719, outb => n1718
);
U1252 : nor2 port map( a => mult_125_ab_5_13_port, b => n1721, outb => n1720
);
U1253 : nor2 port map( a => mult_125_ab_6_13_port, b => n1723, outb => n1722
);
U1254 : nor2 port map( a => mult_125_ab_7_13_port, b => n1725, outb => n1724
);
U1255 : nor2 port map( a => mult_125_ab_8_13_port, b => n1727, outb => n1726
);
U1256 : nor2 port map( a => mult_125_ab_9_13_port, b => n1729, outb => n1728
);
U1257 : nor2 port map( a => mult_125_ab_10_13_port, b => n1731, outb =>
n1730);
U1258 : nor2 port map( a => mult_125_ab_11_13_port, b => n1733, outb =>
n1732);
U1259 : nor2 port map( a => mult_125_ab_12_13_port, b => n1735, outb =>
n1734);
U1260 : nor2 port map( a => mult_125_ab_13_13_port, b => n1737, outb =>
n1736);
U1261 : nor2 port map( a => mult_125_ab_14_13_port, b => n1739, outb =>
n1738);
U1262 : nor2 port map( a => mult_125_ab_15_13_port, b => n1741, outb =>
n1740);
U1263 : nand2 port map( a => n1743, b => n1744, outb => n1742);
U1264 : nor2 port map( a => mult_125_ab_3_12_port, b => n1746, outb => n1745
);
U1265 : nor2 port map( a => mult_125_ab_4_12_port, b => n1748, outb => n1747
);
U1266 : nor2 port map( a => mult_125_ab_5_12_port, b => n1750, outb => n1749
);
U1267 : nor2 port map( a => mult_125_ab_6_12_port, b => n1752, outb => n1751
);
U1268 : nor2 port map( a => mult_125_ab_7_12_port, b => n1754, outb => n1753
);
U1269 : nor2 port map( a => mult_125_ab_8_12_port, b => n1756, outb => n1755
);
U1270 : nor2 port map( a => mult_125_ab_9_12_port, b => n1758, outb => n1757
);
U1271 : nor2 port map( a => mult_125_ab_10_12_port, b => n1760, outb =>
n1759);
U1272 : nor2 port map( a => mult_125_ab_11_12_port, b => n1762, outb =>
n1761);
U1273 : nor2 port map( a => mult_125_ab_12_12_port, b => n1764, outb =>
n1763);
U1274 : nor2 port map( a => mult_125_ab_13_12_port, b => n1766, outb =>
n1765);
U1275 : nor2 port map( a => mult_125_ab_14_12_port, b => n1768, outb =>
n1767);
U1276 : nor2 port map( a => mult_125_ab_15_12_port, b => n1770, outb =>
n1769);
U1277 : nand2 port map( a => n1772, b => n1773, outb => n1771);
U1278 : nand2 port map( a => n1775, b => n1776, outb => n1774);
U1279 : nor2 port map( a => mult_125_ab_4_11_port, b => n1778, outb => n1777
);
U1280 : nor2 port map( a => mult_125_ab_5_11_port, b => n1780, outb => n1779
);
U1281 : nor2 port map( a => mult_125_ab_6_11_port, b => n1782, outb => n1781
);
U1282 : nor2 port map( a => mult_125_ab_7_11_port, b => n1784, outb => n1783
);
U1283 : nor2 port map( a => mult_125_ab_8_11_port, b => n1786, outb => n1785
);
U1284 : nor2 port map( a => mult_125_ab_9_11_port, b => n1788, outb => n1787
);
U1285 : nor2 port map( a => mult_125_ab_10_11_port, b => n1790, outb =>
n1789);
U1286 : nor2 port map( a => mult_125_ab_11_11_port, b => n1792, outb =>
n1791);
U1287 : nor2 port map( a => mult_125_ab_12_11_port, b => n1794, outb =>
n1793);
U1288 : nor2 port map( a => mult_125_ab_13_11_port, b => n1796, outb =>
n1795);
U1289 : nor2 port map( a => mult_125_ab_14_11_port, b => n1798, outb =>
n1797);
U1290 : nand2 port map( a => n1800, b => n1801, outb => n1799);
U1291 : nand2 port map( a => n1803, b => n1804, outb => n1802);
U1292 : nor2 port map( a => mult_125_ab_3_10_port, b => n1806, outb => n1805
);
U1293 : nor2 port map( a => mult_125_ab_4_10_port, b => n1808, outb => n1807
);
U1294 : nand2 port map( a => n1810, b => n1811, outb => n1809);
U1295 : nor2 port map( a => mult_125_ab_6_10_port, b => n1813, outb => n1812
);
U1296 : nor2 port map( a => mult_125_ab_7_10_port, b => n1815, outb => n1814
);
U1297 : nor2 port map( a => mult_125_ab_8_10_port, b => n1817, outb => n1816
);
U1298 : nor2 port map( a => mult_125_ab_9_10_port, b => n1819, outb => n1818
);
U1299 : nor2 port map( a => mult_125_ab_10_10_port, b => n1821, outb =>
n1820);
U1300 : nor2 port map( a => mult_125_ab_11_10_port, b => n1823, outb =>
n1822);
U1301 : nor2 port map( a => mult_125_ab_12_10_port, b => n1825, outb =>
n1824);
U1302 : nor2 port map( a => mult_125_ab_13_10_port, b => n1827, outb =>
n1826);
U1303 : nor2 port map( a => mult_125_ab_14_10_port, b => n1829, outb =>
n1828);
U1304 : nor2 port map( a => mult_125_ab_15_10_port, b => n1831, outb =>
n1830);
U1305 : nand2 port map( a => n1833, b => n1834, outb => n1832);
U1306 : nor2 port map( a => mult_125_ab_3_9_port, b => n1836, outb => n1835)
;
U1307 : nor2 port map( a => mult_125_ab_4_9_port, b => n1838, outb => n1837)
;
U1308 : nor2 port map( a => mult_125_ab_5_9_port, b => n1840, outb => n1839)
;
U1309 : nor2 port map( a => mult_125_ab_6_9_port, b => n1842, outb => n1841)
;
U1310 : nor2 port map( a => mult_125_ab_7_9_port, b => n1844, outb => n1843)
;
U1311 : nor2 port map( a => mult_125_ab_8_9_port, b => n1846, outb => n1845)
;
U1312 : nor2 port map( a => mult_125_ab_9_9_port, b => n1848, outb => n1847)
;
U1313 : nor2 port map( a => mult_125_ab_10_9_port, b => n1850, outb => n1849
);
U1314 : nor2 port map( a => mult_125_ab_11_9_port, b => n1852, outb => n1851
);
U1315 : nor2 port map( a => mult_125_ab_12_9_port, b => n1854, outb => n1853
);
U1316 : nor2 port map( a => mult_125_ab_13_9_port, b => n1856, outb => n1855
);
U1317 : nor2 port map( a => mult_125_ab_14_9_port, b => n1858, outb => n1857
);
U1318 : nand2 port map( a => n1860, b => n1861, outb => n1859);
U1319 : nand2 port map( a => n1863, b => n1864, outb => n1862);
U1320 : nor2 port map( a => mult_125_ab_3_8_port, b => n1866, outb => n1865)
;
U1321 : nor2 port map( a => mult_125_ab_4_8_port, b => n1868, outb => n1867)
;
U1322 : nor2 port map( a => mult_125_ab_5_8_port, b => n1870, outb => n1869)
;
U1323 : nor2 port map( a => mult_125_ab_6_8_port, b => n1872, outb => n1871)
;
U1324 : nor2 port map( a => mult_125_ab_7_8_port, b => n1874, outb => n1873)
;
U1325 : nor2 port map( a => mult_125_ab_8_8_port, b => n1876, outb => n1875)
;
U1326 : nor2 port map( a => mult_125_ab_9_8_port, b => n1878, outb => n1877)
;
U1327 : nor2 port map( a => mult_125_ab_10_8_port, b => n1880, outb => n1879
);
U1328 : nor2 port map( a => mult_125_ab_11_8_port, b => n1882, outb => n1881
);
U1329 : nor2 port map( a => mult_125_ab_12_8_port, b => n1884, outb => n1883
);
U1330 : nor2 port map( a => mult_125_ab_13_8_port, b => n1886, outb => n1885
);
U1331 : nor2 port map( a => mult_125_ab_14_8_port, b => n1888, outb => n1887
);
U1332 : nor2 port map( a => mult_125_ab_15_8_port, b => n1890, outb => n1889
);
U1333 : nand2 port map( a => n1892, b => n1893, outb => n1891);
U1334 : nand2 port map( a => n1895, b => n1896, outb => n1894);
U1335 : nor2 port map( a => mult_125_ab_4_7_port, b => n1898, outb => n1897)
;
U1336 : nor2 port map( a => mult_125_ab_5_7_port, b => n1900, outb => n1899)
;
U1337 : nor2 port map( a => mult_125_ab_6_7_port, b => n1902, outb => n1901)
;
U1338 : nor2 port map( a => mult_125_ab_7_7_port, b => n1904, outb => n1903)
;
U1339 : nor2 port map( a => mult_125_ab_8_7_port, b => n1906, outb => n1905)
;
U1340 : nor2 port map( a => mult_125_ab_9_7_port, b => n1908, outb => n1907)
;
U1341 : nor2 port map( a => mult_125_ab_10_7_port, b => n1910, outb => n1909
);
U1342 : nor2 port map( a => mult_125_ab_11_7_port, b => n1912, outb => n1911
);
U1343 : nor2 port map( a => mult_125_ab_12_7_port, b => n1914, outb => n1913
);
U1344 : nor2 port map( a => mult_125_ab_13_7_port, b => n1916, outb => n1915
);
U1345 : nor2 port map( a => mult_125_ab_14_7_port, b => n1918, outb => n1917
);
U1346 : nand2 port map( a => n1920, b => n1921, outb => n1919);
U1347 : nand2 port map( a => n1923, b => n1924, outb => n1922);
U1348 : nor2 port map( a => mult_125_ab_3_6_port, b => n1926, outb => n1925)
;
U1349 : nor2 port map( a => mult_125_ab_4_6_port, b => n1928, outb => n1927)
;
U1350 : nand2 port map( a => n1930, b => n1931, outb => n1929);
U1351 : nor2 port map( a => mult_125_ab_6_6_port, b => n1933, outb => n1932)
;
U1352 : nor2 port map( a => mult_125_ab_7_6_port, b => n1935, outb => n1934)
;
U1353 : nor2 port map( a => mult_125_ab_8_6_port, b => n1937, outb => n1936)
;
U1354 : nand2 port map( a => n1939, b => n1940, outb => n1938);
U1355 : nor2 port map( a => mult_125_ab_10_6_port, b => n1942, outb => n1941
);
U1356 : nor2 port map( a => mult_125_ab_11_6_port, b => n1944, outb => n1943
);
U1357 : nor2 port map( a => mult_125_ab_12_6_port, b => n1946, outb => n1945
);
U1358 : nor2 port map( a => mult_125_ab_13_6_port, b => n1948, outb => n1947
);
U1359 : nor2 port map( a => mult_125_ab_14_6_port, b => n1950, outb => n1949
);
U1360 : nor2 port map( a => mult_125_ab_15_6_port, b => n1952, outb => n1951
);
U1361 : nand2 port map( a => n1954, b => n1955, outb => n1953);
U1362 : nand2 port map( a => n1957, b => n1958, outb => n1956);
U1363 : nor2 port map( a => mult_125_ab_4_5_port, b => n1960, outb => n1959)
;
U1364 : nor2 port map( a => mult_125_ab_5_5_port, b => n1962, outb => n1961)
;
U1365 : nand2 port map( a => n1964, b => n1965, outb => n1963);
U1366 : nor2 port map( a => mult_125_ab_7_5_port, b => n1967, outb => n1966)
;
U1367 : nor2 port map( a => mult_125_ab_8_5_port, b => n1969, outb => n1968)
;
U1368 : nor2 port map( a => mult_125_ab_9_5_port, b => n1971, outb => n1970)
;
U1369 : nor2 port map( a => mult_125_ab_10_5_port, b => n1973, outb => n1972
);
U1370 : nor2 port map( a => mult_125_ab_11_5_port, b => n1975, outb => n1974
);
U1371 : nor2 port map( a => mult_125_ab_12_5_port, b => n1977, outb => n1976
);
U1372 : nor2 port map( a => mult_125_ab_13_5_port, b => n1979, outb => n1978
);
U1373 : nor2 port map( a => mult_125_ab_14_5_port, b => n1981, outb => n1980
);
U1374 : nand2 port map( a => n1983, b => n1984, outb => n1982);
U1375 : nand2 port map( a => n1986, b => n1987, outb => n1985);
U1376 : nor2 port map( a => mult_125_ab_3_4_port, b => n1989, outb => n1988)
;
U1377 : nor2 port map( a => mult_125_ab_4_4_port, b => n1991, outb => n1990)
;
U1378 : nand2 port map( a => n1993, b => n1994, outb => n1992);
U1379 : nor2 port map( a => mult_125_ab_6_4_port, b => n1996, outb => n1995)
;
U1380 : nand2 port map( a => n1998, b => n1999, outb => n1997);
U1381 : nor2 port map( a => mult_125_ab_8_4_port, b => n2001, outb => n2000)
;
U1382 : nor2 port map( a => mult_125_ab_9_4_port, b => n2003, outb => n2002)
;
U1383 : nor2 port map( a => mult_125_ab_10_4_port, b => n2005, outb => n2004
);
U1384 : nand2 port map( a => n2007, b => n2008, outb => n2006);
U1385 : nor2 port map( a => mult_125_ab_12_4_port, b => n2010, outb => n2009
);
U1386 : nor2 port map( a => mult_125_ab_13_4_port, b => n2012, outb => n2011
);
U1387 : nor2 port map( a => mult_125_ab_14_4_port, b => n2014, outb => n2013
);
U1388 : nand2 port map( a => n2016, b => n2017, outb => n2015);
U1389 : nand2 port map( a => n2019, b => n2020, outb => n2018);
U1390 : nand2 port map( a => n2022, b => n2023, outb => n2021);
U1391 : nor2 port map( a => mult_125_ab_4_3_port, b => n2025, outb => n2024)
;
U1392 : nor2 port map( a => mult_125_ab_5_3_port, b => n2027, outb => n2026)
;
U1393 : nor2 port map( a => mult_125_ab_6_3_port, b => n2029, outb => n2028)
;
U1394 : nor2 port map( a => mult_125_ab_7_3_port, b => n2031, outb => n2030)
;
U1395 : nor2 port map( a => mult_125_ab_8_3_port, b => n2033, outb => n2032)
;
U1396 : nor2 port map( a => mult_125_ab_9_3_port, b => n2035, outb => n2034)
;
U1397 : nor2 port map( a => mult_125_ab_10_3_port, b => n2037, outb => n2036
);
U1398 : nor2 port map( a => mult_125_ab_11_3_port, b => n2039, outb => n2038
);
U1399 : nor2 port map( a => mult_125_ab_12_3_port, b => n2041, outb => n2040
);
U1400 : nor2 port map( a => mult_125_ab_13_3_port, b => n2043, outb => n2042
);
U1401 : nor2 port map( a => mult_125_ab_14_3_port, b => n2045, outb => n2044
);
U1402 : nor2 port map( a => mult_125_ab_15_3_port, b => n2047, outb => n2046
);
U1403 : nand2 port map( a => n2049, b => n2050, outb => n2048);
U1404 : nor2 port map( a => mult_125_ab_3_2_port, b => n2052, outb => n2051)
;
U1405 : nor2 port map( a => mult_125_ab_4_2_port, b => n2054, outb => n2053)
;
U1406 : nor2 port map( a => mult_125_ab_5_2_port, b => n2056, outb => n2055)
;
U1407 : nor2 port map( a => mult_125_ab_6_2_port, b => n2058, outb => n2057)
;
U1408 : nand2 port map( a => n2060, b => n2061, outb => n2059);
U1409 : nor2 port map( a => mult_125_ab_8_2_port, b => n2063, outb => n2062)
;
U1410 : nor2 port map( a => mult_125_ab_9_2_port, b => n2065, outb => n2064)
;
U1411 : nor2 port map( a => mult_125_ab_10_2_port, b => n2067, outb => n2066
);
U1412 : nor2 port map( a => mult_125_ab_11_2_port, b => n2069, outb => n2068
);
U1413 : nor2 port map( a => mult_125_ab_12_2_port, b => n2071, outb => n2070
);
U1414 : nor2 port map( a => mult_125_ab_13_2_port, b => n2073, outb => n2072
);
U1415 : nor2 port map( a => mult_125_ab_14_2_port, b => n2075, outb => n2074
);
U1416 : nor2 port map( a => mult_125_ab_15_2_port, b => n2077, outb => n2076
);
U1417 : nand2 port map( a => n2079, b => n2080, outb => n2078);
U1418 : nor2 port map( a => mult_125_ab_3_1_port, b => n2082, outb => n2081)
;
U1419 : nor2 port map( a => mult_125_ab_4_1_port, b => n2084, outb => n2083)
;
U1420 : nor2 port map( a => mult_125_ab_5_1_port, b => n2086, outb => n2085)
;
U1421 : nor2 port map( a => mult_125_ab_6_1_port, b => n2088, outb => n2087)
;
U1422 : nor2 port map( a => mult_125_ab_7_1_port, b => n2090, outb => n2089)
;
U1423 : nor2 port map( a => mult_125_ab_8_1_port, b => n2092, outb => n2091)
;
U1424 : nor2 port map( a => mult_125_ab_9_1_port, b => n2094, outb => n2093)
;
U1425 : nor2 port map( a => mult_125_ab_10_1_port, b => n2096, outb => n2095
);
U1426 : nor2 port map( a => mult_125_ab_11_1_port, b => n2098, outb => n2097
);
U1427 : nor2 port map( a => mult_125_ab_12_1_port, b => n2100, outb => n2099
);
U1428 : nor2 port map( a => mult_125_ab_13_1_port, b => n2102, outb => n2101
);
U1429 : nor2 port map( a => mult_125_ab_14_1_port, b => n2104, outb => n2103
);
U1430 : nor2 port map( a => mult_125_ab_15_1_port, b => n2106, outb => n2105
);
U1431 : nor2 port map( a => mult_125_ab_2_0_port, b => n2108, outb => n2107)
;
U1432 : nor2 port map( a => mult_125_ab_3_0_port, b => n2110, outb => n2109)
;
U1433 : nor2 port map( a => mult_125_ab_4_0_port, b => n2112, outb => n2111)
;
U1434 : nor2 port map( a => mult_125_ab_5_0_port, b => n2114, outb => n2113)
;
U1435 : nor2 port map( a => mult_125_ab_6_0_port, b => n2116, outb => n2115)
;
U1436 : nor2 port map( a => mult_125_ab_7_0_port, b => n2118, outb => n2117)
;
U1437 : nor2 port map( a => mult_125_ab_8_0_port, b => n2120, outb => n2119)
;
U1438 : nor2 port map( a => mult_125_ab_9_0_port, b => n2122, outb => n2121)
;
U1439 : nor2 port map( a => mult_125_ab_10_0_port, b => n2124, outb => n2123
);
U1440 : nor2 port map( a => mult_125_ab_11_0_port, b => n2126, outb => n2125
);
U1441 : nor2 port map( a => mult_125_ab_12_0_port, b => n2128, outb => n2127
);
U1442 : nor2 port map( a => mult_125_ab_13_0_port, b => n2130, outb => n2129
);
U1443 : nor2 port map( a => mult_125_ab_14_0_port, b => n2132, outb => n2131
);
U1444 : nor2 port map( a => mult_125_ab_15_0_port, b => n2134, outb => n2133
);
U1445 : nor2 port map( a => mult_125_ZB, b => mult_125_ZA, outb => n310);
U1446 : nand2 port map( a => mult_125_QB, b => mult_125_ab_15_15_port, outb
=> n2135);
U1447 : nor2 port map( a => adder_mem_array_3_1_port, b => n2137, outb =>
n2136);
U1448 : nor2 port map( a => multiplier_sigs_2_2_port, b =>
adder_mem_array_3_2_port, outb => n2138);
U1449 : nor2 port map( a => multiplier_sigs_2_3_port, b =>
adder_mem_array_3_3_port, outb => n2139);
U1450 : nor2 port map( a => multiplier_sigs_2_4_port, b =>
adder_mem_array_3_4_port, outb => n2140);
U1451 : nor2 port map( a => multiplier_sigs_2_5_port, b =>
adder_mem_array_3_5_port, outb => n2141);
U1452 : nor2 port map( a => multiplier_sigs_2_6_port, b =>
adder_mem_array_3_6_port, outb => n2142);
U1453 : nor2 port map( a => multiplier_sigs_2_7_port, b =>
adder_mem_array_3_7_port, outb => n2143);
U1454 : nor2 port map( a => multiplier_sigs_2_8_port, b =>
adder_mem_array_3_8_port, outb => n2144);
U1455 : nor2 port map( a => multiplier_sigs_2_9_port, b =>
adder_mem_array_3_9_port, outb => n2145);
U1456 : nor2 port map( a => multiplier_sigs_2_10_port, b =>
adder_mem_array_3_10_port, outb => n2146);
U1457 : nor2 port map( a => multiplier_sigs_2_11_port, b =>
adder_mem_array_3_11_port, outb => n2147);
U1458 : nor2 port map( a => multiplier_sigs_2_12_port, b =>
adder_mem_array_3_12_port, outb => n2148);
U1459 : nor2 port map( a => multiplier_sigs_2_13_port, b =>
adder_mem_array_3_13_port, outb => n2149);
U1460 : nor2 port map( a => multiplier_sigs_2_14_port, b =>
adder_mem_array_3_14_port, outb => n2150);
U1461 : nor2 port map( a => multiplier_sigs_2_15_port, b =>
adder_mem_array_3_15_port, outb => n2151);
U1462 : nor2 port map( a => multiplier_sigs_2_16_port, b =>
adder_mem_array_3_16_port, outb => n2152);
U1463 : nor2 port map( a => multiplier_sigs_2_17_port, b =>
adder_mem_array_3_17_port, outb => n2153);
U1464 : nor2 port map( a => multiplier_sigs_2_18_port, b =>
adder_mem_array_3_18_port, outb => n2154);
U1465 : nor2 port map( a => multiplier_sigs_2_19_port, b =>
adder_mem_array_3_19_port, outb => n2155);
U1466 : nor2 port map( a => multiplier_sigs_2_20_port, b =>
adder_mem_array_3_20_port, outb => n2156);
U1467 : nor2 port map( a => multiplier_sigs_2_21_port, b =>
adder_mem_array_3_21_port, outb => n2157);
U1468 : nor2 port map( a => multiplier_sigs_2_22_port, b =>
adder_mem_array_3_22_port, outb => n2158);
U1469 : nor2 port map( a => multiplier_sigs_2_23_port, b =>
adder_mem_array_3_23_port, outb => n2159);
U1470 : nor2 port map( a => multiplier_sigs_2_24_port, b =>
adder_mem_array_3_24_port, outb => n2160);
U1471 : nor2 port map( a => multiplier_sigs_2_25_port, b =>
adder_mem_array_3_25_port, outb => n2161);
U1472 : nor2 port map( a => multiplier_sigs_2_26_port, b =>
adder_mem_array_3_26_port, outb => n2162);
U1473 : nor2 port map( a => adder_mem_array_1_1_port, b => n2164, outb =>
n2163);
U1474 : nor2 port map( a => multiplier_sigs_0_2_port, b =>
adder_mem_array_1_2_port, outb => n2165);
U1475 : nor2 port map( a => adder_mem_array_2_1_port, b => n2167, outb =>
n2166);
U1476 : nor2 port map( a => multiplier_sigs_1_2_port, b =>
adder_mem_array_2_2_port, outb => n2168);
U1477 : nor2 port map( a => multiplier_sigs_1_3_port, b =>
adder_mem_array_2_3_port, outb => n2169);
U1478 : nor2 port map( a => multiplier_sigs_1_4_port, b =>
adder_mem_array_2_4_port, outb => n2170);
U1479 : nor2 port map( a => multiplier_sigs_1_5_port, b =>
adder_mem_array_2_5_port, outb => n2171);
U1480 : nor2 port map( a => multiplier_sigs_1_6_port, b =>
adder_mem_array_2_6_port, outb => n2172);
U1481 : nor2 port map( a => multiplier_sigs_1_7_port, b =>
adder_mem_array_2_7_port, outb => n2173);
U1482 : nor2 port map( a => multiplier_sigs_1_8_port, b =>
adder_mem_array_2_8_port, outb => n2174);
U1483 : nor2 port map( a => multiplier_sigs_1_9_port, b =>
adder_mem_array_2_9_port, outb => n2175);
U1484 : nor2 port map( a => multiplier_sigs_1_10_port, b =>
adder_mem_array_2_10_port, outb => n2176);
U1485 : nor2 port map( a => multiplier_sigs_1_11_port, b =>
adder_mem_array_2_11_port, outb => n2177);
U1486 : nor2 port map( a => multiplier_sigs_1_12_port, b =>
adder_mem_array_2_12_port, outb => n2178);
U1487 : nor2 port map( a => multiplier_sigs_1_13_port, b =>
adder_mem_array_2_13_port, outb => n2179);
U1488 : nor2 port map( a => multiplier_sigs_1_14_port, b =>
adder_mem_array_2_14_port, outb => n2180);
U1489 : nor2 port map( a => multiplier_sigs_1_15_port, b =>
adder_mem_array_2_15_port, outb => n2181);
U1490 : nor2 port map( a => multiplier_sigs_1_16_port, b =>
adder_mem_array_2_16_port, outb => n2182);
U1491 : nor2 port map( a => multiplier_sigs_1_17_port, b =>
adder_mem_array_2_17_port, outb => n2183);
U1492 : nor2 port map( a => multiplier_sigs_1_18_port, b =>
adder_mem_array_2_18_port, outb => n2184);
U1493 : nor2 port map( a => multiplier_sigs_1_19_port, b =>
adder_mem_array_2_19_port, outb => n2185);
U1494 : nor2 port map( a => multiplier_sigs_1_20_port, b =>
adder_mem_array_2_20_port, outb => n2186);
U1495 : nor2 port map( a => multiplier_sigs_1_21_port, b =>
adder_mem_array_2_21_port, outb => n2187);
U1496 : nor2 port map( a => multiplier_sigs_1_22_port, b =>
adder_mem_array_2_22_port, outb => n2188);
U1497 : nor2 port map( a => multiplier_sigs_1_23_port, b =>
adder_mem_array_2_23_port, outb => n2189);
U1498 : nor2 port map( a => multiplier_sigs_1_24_port, b =>
adder_mem_array_2_24_port, outb => n2190);
U1499 : nor2 port map( a => multiplier_sigs_1_25_port, b =>
adder_mem_array_2_25_port, outb => n2191);
U1500 : nor2 port map( a => multiplier_sigs_1_26_port, b =>
adder_mem_array_2_26_port, outb => n2192);
U1501 : nor2 port map( a => multiplier_sigs_1_27_port, b =>
adder_mem_array_2_27_port, outb => n2193);
U1502 : nor2 port map( a => multiplier_sigs_1_28_port, b =>
adder_mem_array_2_28_port, outb => n2194);
U1503 : nor2 port map( a => multiplier_sigs_1_29_port, b =>
adder_mem_array_2_29_port, outb => n2195);
U1504 : nor2 port map( a => multiplier_sigs_1_30_port, b =>
adder_mem_array_2_30_port, outb => n2196);
U1505 : aoi22 port map( a => n2198, b => n2199, c =>
adder_mem_array_2_31_port, d =>
multiplier_sigs_1_31_port, outb => n2197);
U1506 : nor2 port map( a => multiplier_sigs_0_3_port, b =>
adder_mem_array_1_3_port, outb => n2200);
U1507 : nor2 port map( a => multiplier_sigs_0_4_port, b =>
adder_mem_array_1_4_port, outb => n2201);
U1508 : nor2 port map( a => multiplier_sigs_0_5_port, b =>
adder_mem_array_1_5_port, outb => n2202);
U1509 : nor2 port map( a => multiplier_sigs_0_6_port, b =>
adder_mem_array_1_6_port, outb => n2203);
U1510 : nor2 port map( a => multiplier_sigs_0_7_port, b =>
adder_mem_array_1_7_port, outb => n2204);
U1511 : nor2 port map( a => multiplier_sigs_0_8_port, b =>
adder_mem_array_1_8_port, outb => n2205);
U1512 : nor2 port map( a => multiplier_sigs_0_9_port, b =>
adder_mem_array_1_9_port, outb => n2206);
U1513 : nor2 port map( a => multiplier_sigs_0_10_port, b =>
adder_mem_array_1_10_port, outb => n2207);
U1514 : nor2 port map( a => multiplier_sigs_0_11_port, b =>
adder_mem_array_1_11_port, outb => n2208);
U1515 : nor2 port map( a => multiplier_sigs_0_12_port, b =>
adder_mem_array_1_12_port, outb => n2209);
U1516 : nor2 port map( a => multiplier_sigs_0_13_port, b =>
adder_mem_array_1_13_port, outb => n2210);
U1517 : nor2 port map( a => multiplier_sigs_0_14_port, b =>
adder_mem_array_1_14_port, outb => n2211);
U1518 : nor2 port map( a => multiplier_sigs_0_15_port, b =>
adder_mem_array_1_15_port, outb => n2212);
U1519 : nor2 port map( a => multiplier_sigs_0_16_port, b =>
adder_mem_array_1_16_port, outb => n2213);
U1520 : nor2 port map( a => multiplier_sigs_0_17_port, b =>
adder_mem_array_1_17_port, outb => n2214);
U1521 : nor2 port map( a => multiplier_sigs_0_18_port, b =>
adder_mem_array_1_18_port, outb => n2215);
U1522 : nor2 port map( a => multiplier_sigs_0_19_port, b =>
adder_mem_array_1_19_port, outb => n2216);
U1523 : nor2 port map( a => multiplier_sigs_0_20_port, b =>
adder_mem_array_1_20_port, outb => n2217);
U1524 : nor2 port map( a => multiplier_sigs_0_21_port, b =>
adder_mem_array_1_21_port, outb => n2218);
U1525 : nor2 port map( a => multiplier_sigs_0_22_port, b =>
adder_mem_array_1_22_port, outb => n2219);
U1526 : nor2 port map( a => multiplier_sigs_0_23_port, b =>
adder_mem_array_1_23_port, outb => n2220);
U1527 : nor2 port map( a => multiplier_sigs_0_24_port, b =>
adder_mem_array_1_24_port, outb => n2221);
U1528 : nor2 port map( a => multiplier_sigs_0_25_port, b =>
adder_mem_array_1_25_port, outb => n2222);
U1529 : nor2 port map( a => multiplier_sigs_0_26_port, b =>
adder_mem_array_1_26_port, outb => n2223);
U1530 : nor2 port map( a => multiplier_sigs_0_27_port, b =>
adder_mem_array_1_27_port, outb => n2224);
U1531 : nor2 port map( a => multiplier_sigs_0_28_port, b =>
adder_mem_array_1_28_port, outb => n2225);
U1532 : nor2 port map( a => multiplier_sigs_0_29_port, b =>
adder_mem_array_1_29_port, outb => n2226);
U1533 : nor2 port map( a => multiplier_sigs_0_30_port, b =>
adder_mem_array_1_30_port, outb => n2227);
U1534 : aoi22 port map( a => n2229, b => n2230, c =>
adder_mem_array_1_31_port, d =>
multiplier_sigs_0_31_port, outb => n2228);
U1535 : nor2 port map( a => multiplier_sigs_2_27_port, b =>
adder_mem_array_3_27_port, outb => n2231);
U1536 : nor2 port map( a => multiplier_sigs_2_28_port, b =>
adder_mem_array_3_28_port, outb => n2232);
U1537 : nor2 port map( a => multiplier_sigs_2_29_port, b =>
adder_mem_array_3_29_port, outb => n2233);
U1538 : nor2 port map( a => multiplier_sigs_2_30_port, b =>
adder_mem_array_3_30_port, outb => n2234);
U1539 : aoi22 port map( a => n2236, b => n2237, c =>
adder_mem_array_3_31_port, d =>
multiplier_sigs_2_31_port, outb => n2235);
U1540 : xor2 port map( a => mult_125_G4_ab_15_15_port, b => n2239, outb =>
n2238);
U1541 : xor2 port map( a => mult_125_G4_ab_1_14_port, b =>
mult_125_G4_ab_0_15_port, outb => n2240);
U1542 : xor2 port map( a => n2242, b => mult_125_G4_ab_1_15_port, outb =>
n2241);
U1543 : xor2 port map( a => mult_125_G4_ab_1_13_port, b =>
mult_125_G4_ab_0_14_port, outb => n2243);
U1544 : xor2 port map( a => n2245, b => n2240, outb => n2244);
U1545 : xor2 port map( a => n2247, b => n2248, outb => n2246);
U1546 : xor2 port map( a => n2250, b => n2251, outb => n2249);
U1547 : xor2 port map( a => n2253, b => n2254, outb => n2252);
U1548 : xor2 port map( a => n2256, b => n2257, outb => n2255);
U1549 : xor2 port map( a => n2259, b => n2260, outb => n2258);
U1550 : xor2 port map( a => n2262, b => n2263, outb => n2261);
U1551 : xor2 port map( a => n2265, b => n2266, outb => n2264);
U1552 : xor2 port map( a => n2268, b => n2269, outb => n2267);
U1553 : xor2 port map( a => n2271, b => n2272, outb => n2270);
U1554 : xor2 port map( a => n2274, b => n2275, outb => n2273);
U1555 : xor2 port map( a => n2277, b => n2278, outb => n2276);
U1556 : xor2 port map( a => n2279, b => n2280, outb => n246);
U1557 : xor2 port map( a => mult_125_G4_ab_1_12_port, b =>
mult_125_G4_ab_0_13_port, outb => n2281);
U1558 : xor2 port map( a => n2283, b => n2243, outb => n2282);
U1559 : xor2 port map( a => n2285, b => n2286, outb => n2284);
U1560 : xor2 port map( a => mult_125_G4_ab_1_11_port, b =>
mult_125_G4_ab_0_12_port, outb => n2287);
U1561 : xor2 port map( a => n2289, b => n2281, outb => n2288);
U1562 : xor2 port map( a => n2291, b => n2292, outb => n2290);
U1563 : xor2 port map( a => n2294, b => n2295, outb => n2293);
U1564 : xor2 port map( a => n2297, b => n2298, outb => n2296);
U1565 : xor2 port map( a => n2300, b => n2301, outb => n2299);
U1566 : xor2 port map( a => n2303, b => n2304, outb => n2302);
U1567 : xor2 port map( a => n2306, b => n2307, outb => n2305);
U1568 : xor2 port map( a => n2309, b => n2310, outb => n2308);
U1569 : xor2 port map( a => n2312, b => n2313, outb => n2311);
U1570 : xor2 port map( a => n2315, b => n2316, outb => n2314);
U1571 : xor2 port map( a => n2318, b => n2319, outb => n2317);
U1572 : xor2 port map( a => n2320, b => n2321, outb => n250);
U1573 : xor2 port map( a => mult_125_G4_ab_1_10_port, b =>
mult_125_G4_ab_0_11_port, outb => n2322);
U1574 : xor2 port map( a => n2324, b => n2287, outb => n2323);
U1575 : xor2 port map( a => n2326, b => n2327, outb => n2325);
U1576 : xor2 port map( a => n2329, b => n2330, outb => n2328);
U1577 : xor2 port map( a => mult_125_G4_ab_1_9_port, b =>
mult_125_G4_ab_0_10_port, outb => n2331);
U1578 : xor2 port map( a => n2333, b => n2322, outb => n2332);
U1579 : xor2 port map( a => n2335, b => n2336, outb => n2334);
U1580 : xor2 port map( a => n2338, b => n2339, outb => n2337);
U1581 : xor2 port map( a => n2341, b => n2342, outb => n2340);
U1582 : xor2 port map( a => n2344, b => n2345, outb => n2343);
U1583 : xor2 port map( a => n2347, b => n2348, outb => n2346);
U1584 : xor2 port map( a => n2350, b => n2351, outb => n2349);
U1585 : xor2 port map( a => n2353, b => n2354, outb => n2352);
U1586 : xor2 port map( a => n2356, b => n2357, outb => n2355);
U1587 : xor2 port map( a => n2359, b => n2360, outb => n2358);
U1588 : xor2 port map( a => n2361, b => n2362, outb => n254);
U1589 : xor2 port map( a => mult_125_G4_ab_1_8_port, b =>
mult_125_G4_ab_0_9_port, outb => n2363);
U1590 : xor2 port map( a => n2365, b => n2331, outb => n2364);
U1591 : xor2 port map( a => n2367, b => n2368, outb => n2366);
U1592 : xor2 port map( a => n2370, b => n2371, outb => n2369);
U1593 : xor2 port map( a => n2373, b => n2374, outb => n2372);
U1594 : xor2 port map( a => mult_125_G4_ab_1_7_port, b =>
mult_125_G4_ab_0_8_port, outb => n2375);
U1595 : xor2 port map( a => n2377, b => n2363, outb => n2376);
U1596 : xor2 port map( a => n2379, b => n2380, outb => n2378);
U1597 : xor2 port map( a => n2382, b => n2383, outb => n2381);
U1598 : xor2 port map( a => n2385, b => n2386, outb => n2384);
U1599 : xor2 port map( a => n2388, b => n2389, outb => n2387);
U1600 : xor2 port map( a => n2391, b => n2392, outb => n2390);
U1601 : xor2 port map( a => n2394, b => n2395, outb => n2393);
U1602 : xor2 port map( a => n2397, b => n2398, outb => n2396);
U1603 : xor2 port map( a => n2400, b => n2401, outb => n2399);
U1604 : xor2 port map( a => n2402, b => n2403, outb => n258);
U1605 : xor2 port map( a => mult_125_G4_ab_1_6_port, b =>
mult_125_G4_ab_0_7_port, outb => n2404);
U1606 : xor2 port map( a => n2406, b => n2375, outb => n2405);
U1607 : xor2 port map( a => n2408, b => n2409, outb => n2407);
U1608 : xor2 port map( a => n2411, b => n2412, outb => n2410);
U1609 : xor2 port map( a => n2414, b => n2415, outb => n2413);
U1610 : xor2 port map( a => n2417, b => n2418, outb => n2416);
U1611 : xor2 port map( a => mult_125_G4_ab_1_5_port, b =>
mult_125_G4_ab_0_6_port, outb => n2419);
U1612 : xor2 port map( a => n2421, b => n2404, outb => n2420);
U1613 : xor2 port map( a => n2423, b => n2424, outb => n2422);
U1614 : xor2 port map( a => n2426, b => n2427, outb => n2425);
U1615 : xor2 port map( a => n2429, b => n2430, outb => n2428);
U1616 : xor2 port map( a => n2432, b => n2433, outb => n2431);
U1617 : xor2 port map( a => n2435, b => n2436, outb => n2434);
U1618 : xor2 port map( a => n2438, b => n2439, outb => n2437);
U1619 : xor2 port map( a => n2441, b => n2442, outb => n2440);
U1620 : xor2 port map( a => n2443, b => n2444, outb => n262);
U1621 : xor2 port map( a => mult_125_G4_ab_1_4_port, b =>
mult_125_G4_ab_0_5_port, outb => n2445);
U1622 : xor2 port map( a => n2447, b => n2419, outb => n2446);
U1623 : xor2 port map( a => n2449, b => n2450, outb => n2448);
U1624 : xor2 port map( a => n2452, b => n2453, outb => n2451);
U1625 : xor2 port map( a => n2455, b => n2456, outb => n2454);
U1626 : xor2 port map( a => n2458, b => n2459, outb => n2457);
U1627 : xor2 port map( a => n2461, b => n2462, outb => n2460);
U1628 : xor2 port map( a => mult_125_G4_ab_1_3_port, b =>
mult_125_G4_ab_0_4_port, outb => n2463);
U1629 : xor2 port map( a => n2465, b => n2445, outb => n2464);
U1630 : xor2 port map( a => n2467, b => n2468, outb => n2466);
U1631 : xor2 port map( a => n2470, b => n2471, outb => n2469);
U1632 : xor2 port map( a => n2473, b => n2474, outb => n2472);
U1633 : xor2 port map( a => n2476, b => n2477, outb => n2475);
U1634 : xor2 port map( a => n2479, b => n2480, outb => n2478);
U1635 : xor2 port map( a => n2482, b => n2483, outb => n2481);
U1636 : xor2 port map( a => n2484, b => n2485, outb => n267);
U1637 : xor2 port map( a => mult_125_G4_ab_1_2_port, b =>
mult_125_G4_ab_0_3_port, outb => n2486);
U1638 : xor2 port map( a => n2488, b => n2463, outb => n2487);
U1639 : xor2 port map( a => n2490, b => n2491, outb => n2489);
U1640 : xor2 port map( a => n2493, b => n2494, outb => n2492);
U1641 : xor2 port map( a => n2496, b => n2497, outb => n2495);
U1642 : xor2 port map( a => n2499, b => n2500, outb => n2498);
U1643 : xor2 port map( a => n2502, b => n2503, outb => n2501);
U1644 : xor2 port map( a => n2505, b => n2506, outb => n2504);
U1645 : xor2 port map( a => mult_125_G4_ab_1_1_port, b =>
mult_125_G4_ab_0_2_port, outb => n2507);
U1646 : xor2 port map( a => n2509, b => n2486, outb => n2508);
U1647 : xor2 port map( a => n2511, b => n2512, outb => n2510);
U1648 : xor2 port map( a => n2514, b => n2515, outb => n2513);
U1649 : xor2 port map( a => n2517, b => n2518, outb => n2516);
U1650 : xor2 port map( a => n2520, b => n2521, outb => n2519);
U1651 : xor2 port map( a => n2523, b => n2524, outb => n2522);
U1652 : xor2 port map( a => n2526, b => n2527, outb => n2525);
U1653 : xor2 port map( a => n2528, b => n2519, outb => mult_125_G4_A1_9_port
);
U1654 : xor2 port map( a => n2529, b => n2516, outb => mult_125_G4_A1_7_port
);
U1655 : xor2 port map( a => n2530, b => n2513, outb => mult_125_G4_A1_5_port
);
U1656 : xor2 port map( a => n2531, b => n2510, outb => mult_125_G4_A1_3_port
);
U1657 : xor2 port map( a => n242, b => n241, outb => mult_125_G4_A1_28_port)
;
U1658 : xor2 port map( a => n246, b => n245, outb => mult_125_G4_A1_26_port)
;
U1659 : xor2 port map( a => n250, b => n249, outb => mult_125_G4_A1_24_port)
;
U1660 : xor2 port map( a => n254, b => n253, outb => mult_125_G4_A1_22_port)
;
U1661 : xor2 port map( a => n258, b => n257, outb => mult_125_G4_A1_20_port)
;
U1662 : xor2 port map( a => n2532, b => n2508, outb => mult_125_G4_A1_1_port
);
U1663 : xor2 port map( a => n262, b => n261, outb => mult_125_G4_A1_18_port)
;
U1664 : xor2 port map( a => n267, b => n266, outb => mult_125_G4_A1_16_port)
;
U1665 : xor2 port map( a => n2533, b => n275, outb => mult_125_G4_A1_13_port
);
U1666 : xor2 port map( a => n2534, b => n2522, outb =>
mult_125_G4_A1_11_port);
U1667 : xor2 port map( a => mult_125_G3_ab_15_15_port, b => n2536, outb =>
n2535);
U1668 : xor2 port map( a => mult_125_G3_ab_1_14_port, b =>
mult_125_G3_ab_0_15_port, outb => n2537);
U1669 : xor2 port map( a => n2539, b => mult_125_G3_ab_1_15_port, outb =>
n2538);
U1670 : xor2 port map( a => mult_125_G3_ab_1_13_port, b =>
mult_125_G3_ab_0_14_port, outb => n2540);
U1671 : xor2 port map( a => n2542, b => n2537, outb => n2541);
U1672 : xor2 port map( a => n2544, b => n2545, outb => n2543);
U1673 : xor2 port map( a => n2547, b => n2548, outb => n2546);
U1674 : xor2 port map( a => n2550, b => n2551, outb => n2549);
U1675 : xor2 port map( a => n2553, b => n2554, outb => n2552);
U1676 : xor2 port map( a => n2556, b => n2557, outb => n2555);
U1677 : xor2 port map( a => n2559, b => n2560, outb => n2558);
U1678 : xor2 port map( a => n2562, b => n2563, outb => n2561);
U1679 : xor2 port map( a => n2565, b => n2566, outb => n2564);
U1680 : xor2 port map( a => n2568, b => n2569, outb => n2567);
U1681 : xor2 port map( a => n2571, b => n2572, outb => n2570);
U1682 : xor2 port map( a => n2574, b => n2575, outb => n2573);
U1683 : xor2 port map( a => n2576, b => n2577, outb => n354);
U1684 : xor2 port map( a => mult_125_G3_ab_1_12_port, b =>
mult_125_G3_ab_0_13_port, outb => n2578);
U1685 : xor2 port map( a => n2580, b => n2540, outb => n2579);
U1686 : xor2 port map( a => n2582, b => n2583, outb => n2581);
U1687 : xor2 port map( a => mult_125_G3_ab_1_11_port, b =>
mult_125_G3_ab_0_12_port, outb => n2584);
U1688 : xor2 port map( a => n2586, b => n2578, outb => n2585);
U1689 : xor2 port map( a => n2588, b => n2589, outb => n2587);
U1690 : xor2 port map( a => n2591, b => n2592, outb => n2590);
U1691 : xor2 port map( a => n2594, b => n2595, outb => n2593);
U1692 : xor2 port map( a => n2597, b => n2598, outb => n2596);
U1693 : xor2 port map( a => n2600, b => n2601, outb => n2599);
U1694 : xor2 port map( a => n2603, b => n2604, outb => n2602);
U1695 : xor2 port map( a => n2606, b => n2607, outb => n2605);
U1696 : xor2 port map( a => n2609, b => n2610, outb => n2608);
U1697 : xor2 port map( a => n2612, b => n2613, outb => n2611);
U1698 : xor2 port map( a => n2615, b => n2616, outb => n2614);
U1699 : xor2 port map( a => n2617, b => n2618, outb => n358);
U1700 : xor2 port map( a => mult_125_G3_ab_1_10_port, b =>
mult_125_G3_ab_0_11_port, outb => n2619);
U1701 : xor2 port map( a => n2621, b => n2584, outb => n2620);
U1702 : xor2 port map( a => n2623, b => n2624, outb => n2622);
U1703 : xor2 port map( a => n2626, b => n2627, outb => n2625);
U1704 : xor2 port map( a => mult_125_G3_ab_1_9_port, b =>
mult_125_G3_ab_0_10_port, outb => n2628);
U1705 : xor2 port map( a => n2630, b => n2619, outb => n2629);
U1706 : xor2 port map( a => n2632, b => n2633, outb => n2631);
U1707 : xor2 port map( a => n2635, b => n2636, outb => n2634);
U1708 : xor2 port map( a => n2638, b => n2639, outb => n2637);
U1709 : xor2 port map( a => n2641, b => n2642, outb => n2640);
U1710 : xor2 port map( a => n2644, b => n2645, outb => n2643);
U1711 : xor2 port map( a => n2647, b => n2648, outb => n2646);
U1712 : xor2 port map( a => n2650, b => n2651, outb => n2649);
U1713 : xor2 port map( a => n2653, b => n2654, outb => n2652);
U1714 : xor2 port map( a => n2656, b => n2657, outb => n2655);
U1715 : xor2 port map( a => n2658, b => n2659, outb => n362);
U1716 : xor2 port map( a => mult_125_G3_ab_1_8_port, b =>
mult_125_G3_ab_0_9_port, outb => n2660);
U1717 : xor2 port map( a => n2662, b => n2628, outb => n2661);
U1718 : xor2 port map( a => n2664, b => n2665, outb => n2663);
U1719 : xor2 port map( a => n2667, b => n2668, outb => n2666);
U1720 : xor2 port map( a => n2670, b => n2671, outb => n2669);
U1721 : xor2 port map( a => mult_125_G3_ab_1_7_port, b =>
mult_125_G3_ab_0_8_port, outb => n2672);
U1722 : xor2 port map( a => n2674, b => n2660, outb => n2673);
U1723 : xor2 port map( a => n2676, b => n2677, outb => n2675);
U1724 : xor2 port map( a => n2679, b => n2680, outb => n2678);
U1725 : xor2 port map( a => n2682, b => n2683, outb => n2681);
U1726 : xor2 port map( a => n2685, b => n2686, outb => n2684);
U1727 : xor2 port map( a => n2688, b => n2689, outb => n2687);
U1728 : xor2 port map( a => n2691, b => n2692, outb => n2690);
U1729 : xor2 port map( a => n2694, b => n2695, outb => n2693);
U1730 : xor2 port map( a => n2697, b => n2698, outb => n2696);
U1731 : xor2 port map( a => n2699, b => n2700, outb => n366);
U1732 : xor2 port map( a => mult_125_G3_ab_1_6_port, b =>
mult_125_G3_ab_0_7_port, outb => n2701);
U1733 : xor2 port map( a => n2703, b => n2672, outb => n2702);
U1734 : xor2 port map( a => n2705, b => n2706, outb => n2704);
U1735 : xor2 port map( a => n2708, b => n2709, outb => n2707);
U1736 : xor2 port map( a => n2711, b => n2712, outb => n2710);
U1737 : xor2 port map( a => n2714, b => n2715, outb => n2713);
U1738 : xor2 port map( a => mult_125_G3_ab_1_5_port, b =>
mult_125_G3_ab_0_6_port, outb => n2716);
U1739 : xor2 port map( a => n2718, b => n2701, outb => n2717);
U1740 : xor2 port map( a => n2720, b => n2721, outb => n2719);
U1741 : xor2 port map( a => n2723, b => n2724, outb => n2722);
U1742 : xor2 port map( a => n2726, b => n2727, outb => n2725);
U1743 : xor2 port map( a => n2729, b => n2730, outb => n2728);
U1744 : xor2 port map( a => n2732, b => n2733, outb => n2731);
U1745 : xor2 port map( a => n2735, b => n2736, outb => n2734);
U1746 : xor2 port map( a => n2738, b => n2739, outb => n2737);
U1747 : xor2 port map( a => n2740, b => n2741, outb => n370);
U1748 : xor2 port map( a => mult_125_G3_ab_1_4_port, b =>
mult_125_G3_ab_0_5_port, outb => n2742);
U1749 : xor2 port map( a => n2744, b => n2716, outb => n2743);
U1750 : xor2 port map( a => n2746, b => n2747, outb => n2745);
U1751 : xor2 port map( a => n2749, b => n2750, outb => n2748);
U1752 : xor2 port map( a => n2752, b => n2753, outb => n2751);
U1753 : xor2 port map( a => n2755, b => n2756, outb => n2754);
U1754 : xor2 port map( a => n2758, b => n2759, outb => n2757);
U1755 : xor2 port map( a => mult_125_G3_ab_1_3_port, b =>
mult_125_G3_ab_0_4_port, outb => n2760);
U1756 : xor2 port map( a => n2762, b => n2742, outb => n2761);
U1757 : xor2 port map( a => n2764, b => n2765, outb => n2763);
U1758 : xor2 port map( a => n2767, b => n2768, outb => n2766);
U1759 : xor2 port map( a => n2770, b => n2771, outb => n2769);
U1760 : xor2 port map( a => n2773, b => n2774, outb => n2772);
U1761 : xor2 port map( a => n2776, b => n2777, outb => n2775);
U1762 : xor2 port map( a => n2779, b => n2780, outb => n2778);
U1763 : xor2 port map( a => n2781, b => n2782, outb => n375);
U1764 : xor2 port map( a => mult_125_G3_ab_1_2_port, b =>
mult_125_G3_ab_0_3_port, outb => n2783);
U1765 : xor2 port map( a => n2785, b => n2760, outb => n2784);
U1766 : xor2 port map( a => n2787, b => n2788, outb => n2786);
U1767 : xor2 port map( a => n2790, b => n2791, outb => n2789);
U1768 : xor2 port map( a => n2793, b => n2794, outb => n2792);
U1769 : xor2 port map( a => n2796, b => n2797, outb => n2795);
U1770 : xor2 port map( a => n2799, b => n2800, outb => n2798);
U1771 : xor2 port map( a => n2802, b => n2803, outb => n2801);
U1772 : xor2 port map( a => mult_125_G3_ab_1_1_port, b =>
mult_125_G3_ab_0_2_port, outb => n2804);
U1773 : xor2 port map( a => n2806, b => n2783, outb => n2805);
U1774 : xor2 port map( a => n2808, b => n2809, outb => n2807);
U1775 : xor2 port map( a => n2811, b => n2812, outb => n2810);
U1776 : xor2 port map( a => n2814, b => n2815, outb => n2813);
U1777 : xor2 port map( a => n2817, b => n2818, outb => n2816);
U1778 : xor2 port map( a => n2820, b => n2821, outb => n2819);
U1779 : xor2 port map( a => n2823, b => n2824, outb => n2822);
U1780 : xor2 port map( a => n2825, b => n2816, outb => mult_125_G3_A1_9_port
);
U1781 : xor2 port map( a => n2826, b => n2813, outb => mult_125_G3_A1_7_port
);
U1782 : xor2 port map( a => n2827, b => n2810, outb => mult_125_G3_A1_5_port
);
U1783 : xor2 port map( a => n2828, b => n2807, outb => mult_125_G3_A1_3_port
);
U1784 : xor2 port map( a => n350, b => n349, outb => mult_125_G3_A1_28_port)
;
U1785 : xor2 port map( a => n354, b => n353, outb => mult_125_G3_A1_26_port)
;
U1786 : xor2 port map( a => n358, b => n357, outb => mult_125_G3_A1_24_port)
;
U1787 : xor2 port map( a => n362, b => n361, outb => mult_125_G3_A1_22_port)
;
U1788 : xor2 port map( a => n366, b => n365, outb => mult_125_G3_A1_20_port)
;
U1789 : xor2 port map( a => n2829, b => n2805, outb => mult_125_G3_A1_1_port
);
U1790 : xor2 port map( a => n370, b => n369, outb => mult_125_G3_A1_18_port)
;
U1791 : xor2 port map( a => n375, b => n374, outb => mult_125_G3_A1_16_port)
;
U1792 : xor2 port map( a => n2830, b => n383, outb => mult_125_G3_A1_13_port
);
U1793 : xor2 port map( a => n2831, b => n2819, outb =>
mult_125_G3_A1_11_port);
U1794 : xor2 port map( a => mult_125_G2_ab_15_15_port, b => n2833, outb =>
n2832);
U1795 : xor2 port map( a => mult_125_G2_ab_1_14_port, b =>
mult_125_G2_ab_0_15_port, outb => n2834);
U1796 : xor2 port map( a => n2836, b => mult_125_G2_ab_1_15_port, outb =>
n2835);
U1797 : xor2 port map( a => mult_125_G2_ab_1_13_port, b =>
mult_125_G2_ab_0_14_port, outb => n2837);
U1798 : xor2 port map( a => n2839, b => n2834, outb => n2838);
U1799 : xor2 port map( a => n2841, b => n2842, outb => n2840);
U1800 : xor2 port map( a => n2844, b => n2845, outb => n2843);
U1801 : xor2 port map( a => n2847, b => n2848, outb => n2846);
U1802 : xor2 port map( a => n2850, b => n2851, outb => n2849);
U1803 : xor2 port map( a => n2853, b => n2854, outb => n2852);
U1804 : xor2 port map( a => n2856, b => n2857, outb => n2855);
U1805 : xor2 port map( a => n2859, b => n2860, outb => n2858);
U1806 : xor2 port map( a => n2862, b => n2863, outb => n2861);
U1807 : xor2 port map( a => n2865, b => n2866, outb => n2864);
U1808 : xor2 port map( a => n2868, b => n2869, outb => n2867);
U1809 : xor2 port map( a => n2871, b => n2872, outb => n2870);
U1810 : xor2 port map( a => n2873, b => n2874, outb => n318);
U1811 : xor2 port map( a => mult_125_G2_ab_1_12_port, b =>
mult_125_G2_ab_0_13_port, outb => n2875);
U1812 : xor2 port map( a => n2877, b => n2837, outb => n2876);
U1813 : xor2 port map( a => n2879, b => n2880, outb => n2878);
U1814 : xor2 port map( a => mult_125_G2_ab_1_11_port, b =>
mult_125_G2_ab_0_12_port, outb => n2881);
U1815 : xor2 port map( a => n2883, b => n2875, outb => n2882);
U1816 : xor2 port map( a => n2885, b => n2886, outb => n2884);
U1817 : xor2 port map( a => n2888, b => n2889, outb => n2887);
U1818 : xor2 port map( a => n2891, b => n2892, outb => n2890);
U1819 : xor2 port map( a => n2894, b => n2895, outb => n2893);
U1820 : xor2 port map( a => n2897, b => n2898, outb => n2896);
U1821 : xor2 port map( a => n2900, b => n2901, outb => n2899);
U1822 : xor2 port map( a => n2903, b => n2904, outb => n2902);
U1823 : xor2 port map( a => n2906, b => n2907, outb => n2905);
U1824 : xor2 port map( a => n2909, b => n2910, outb => n2908);
U1825 : xor2 port map( a => n2912, b => n2913, outb => n2911);
U1826 : xor2 port map( a => n2914, b => n2915, outb => n322);
U1827 : xor2 port map( a => mult_125_G2_ab_1_10_port, b =>
mult_125_G2_ab_0_11_port, outb => n2916);
U1828 : xor2 port map( a => n2918, b => n2881, outb => n2917);
U1829 : xor2 port map( a => n2920, b => n2921, outb => n2919);
U1830 : xor2 port map( a => n2923, b => n2924, outb => n2922);
U1831 : xor2 port map( a => mult_125_G2_ab_1_9_port, b =>
mult_125_G2_ab_0_10_port, outb => n2925);
U1832 : xor2 port map( a => n2927, b => n2916, outb => n2926);
U1833 : xor2 port map( a => n2929, b => n2930, outb => n2928);
U1834 : xor2 port map( a => n2932, b => n2933, outb => n2931);
U1835 : xor2 port map( a => n2935, b => n2936, outb => n2934);
U1836 : xor2 port map( a => n2938, b => n2939, outb => n2937);
U1837 : xor2 port map( a => n2941, b => n2942, outb => n2940);
U1838 : xor2 port map( a => n2944, b => n2945, outb => n2943);
U1839 : xor2 port map( a => n2947, b => n2948, outb => n2946);
U1840 : xor2 port map( a => n2950, b => n2951, outb => n2949);
U1841 : xor2 port map( a => n2953, b => n2954, outb => n2952);
U1842 : xor2 port map( a => n2955, b => n2956, outb => n326);
U1843 : xor2 port map( a => mult_125_G2_ab_1_8_port, b =>
mult_125_G2_ab_0_9_port, outb => n2957);
U1844 : xor2 port map( a => n2959, b => n2925, outb => n2958);
U1845 : xor2 port map( a => n2961, b => n2962, outb => n2960);
U1846 : xor2 port map( a => n2964, b => n2965, outb => n2963);
U1847 : xor2 port map( a => n2967, b => n2968, outb => n2966);
U1848 : xor2 port map( a => mult_125_G2_ab_1_7_port, b =>
mult_125_G2_ab_0_8_port, outb => n2969);
U1849 : xor2 port map( a => n2971, b => n2957, outb => n2970);
U1850 : xor2 port map( a => n2973, b => n2974, outb => n2972);
U1851 : xor2 port map( a => n2976, b => n2977, outb => n2975);
U1852 : xor2 port map( a => n2979, b => n2980, outb => n2978);
U1853 : xor2 port map( a => n2982, b => n2983, outb => n2981);
U1854 : xor2 port map( a => n2985, b => n2986, outb => n2984);
U1855 : xor2 port map( a => n2988, b => n2989, outb => n2987);
U1856 : xor2 port map( a => n2991, b => n2992, outb => n2990);
U1857 : xor2 port map( a => n2994, b => n2995, outb => n2993);
U1858 : xor2 port map( a => n2996, b => n2997, outb => n330);
U1859 : xor2 port map( a => mult_125_G2_ab_1_6_port, b =>
mult_125_G2_ab_0_7_port, outb => n2998);
U1860 : xor2 port map( a => n3000, b => n2969, outb => n2999);
U1861 : xor2 port map( a => n3002, b => n3003, outb => n3001);
U1862 : xor2 port map( a => n3005, b => n3006, outb => n3004);
U1863 : xor2 port map( a => n3008, b => n3009, outb => n3007);
U1864 : xor2 port map( a => n3011, b => n3012, outb => n3010);
U1865 : xor2 port map( a => mult_125_G2_ab_1_5_port, b =>
mult_125_G2_ab_0_6_port, outb => n3013);
U1866 : xor2 port map( a => n3015, b => n2998, outb => n3014);
U1867 : xor2 port map( a => n3017, b => n3018, outb => n3016);
U1868 : xor2 port map( a => n3020, b => n3021, outb => n3019);
U1869 : xor2 port map( a => n3023, b => n3024, outb => n3022);
U1870 : xor2 port map( a => n3026, b => n3027, outb => n3025);
U1871 : xor2 port map( a => n3029, b => n3030, outb => n3028);
U1872 : xor2 port map( a => n3032, b => n3033, outb => n3031);
U1873 : xor2 port map( a => n3035, b => n3036, outb => n3034);
U1874 : xor2 port map( a => n3037, b => n3038, outb => n334);
U1875 : xor2 port map( a => mult_125_G2_ab_1_4_port, b =>
mult_125_G2_ab_0_5_port, outb => n3039);
U1876 : xor2 port map( a => n3041, b => n3013, outb => n3040);
U1877 : xor2 port map( a => n3043, b => n3044, outb => n3042);
U1878 : xor2 port map( a => n3046, b => n3047, outb => n3045);
U1879 : xor2 port map( a => n3049, b => n3050, outb => n3048);
U1880 : xor2 port map( a => n3052, b => n3053, outb => n3051);
U1881 : xor2 port map( a => n3055, b => n3056, outb => n3054);
U1882 : xor2 port map( a => mult_125_G2_ab_1_3_port, b =>
mult_125_G2_ab_0_4_port, outb => n3057);
U1883 : xor2 port map( a => n3059, b => n3039, outb => n3058);
U1884 : xor2 port map( a => n3061, b => n3062, outb => n3060);
U1885 : xor2 port map( a => n3064, b => n3065, outb => n3063);
U1886 : xor2 port map( a => n3067, b => n3068, outb => n3066);
U1887 : xor2 port map( a => n3070, b => n3071, outb => n3069);
U1888 : xor2 port map( a => n3073, b => n3074, outb => n3072);
U1889 : xor2 port map( a => n3076, b => n3077, outb => n3075);
U1890 : xor2 port map( a => n3078, b => n3079, outb => n339);
U1891 : xor2 port map( a => mult_125_G2_ab_1_2_port, b =>
mult_125_G2_ab_0_3_port, outb => n3080);
U1892 : xor2 port map( a => n3082, b => n3057, outb => n3081);
U1893 : xor2 port map( a => n3084, b => n3085, outb => n3083);
U1894 : xor2 port map( a => n3087, b => n3088, outb => n3086);
U1895 : xor2 port map( a => n3090, b => n3091, outb => n3089);
U1896 : xor2 port map( a => n3093, b => n3094, outb => n3092);
U1897 : xor2 port map( a => n3096, b => n3097, outb => n3095);
U1898 : xor2 port map( a => n3099, b => n3100, outb => n3098);
U1899 : xor2 port map( a => mult_125_G2_ab_1_1_port, b =>
mult_125_G2_ab_0_2_port, outb => n3101);
U1900 : xor2 port map( a => n3103, b => n3080, outb => n3102);
U1901 : xor2 port map( a => n3105, b => n3106, outb => n3104);
U1902 : xor2 port map( a => n3108, b => n3109, outb => n3107);
U1903 : xor2 port map( a => n3111, b => n3112, outb => n3110);
U1904 : xor2 port map( a => n3114, b => n3115, outb => n3113);
U1905 : xor2 port map( a => n3117, b => n3118, outb => n3116);
U1906 : xor2 port map( a => n3120, b => n3121, outb => n3119);
U1907 : xor2 port map( a => n3122, b => n3113, outb => mult_125_G2_A1_9_port
);
U1908 : xor2 port map( a => n3123, b => n3110, outb => mult_125_G2_A1_7_port
);
U1909 : xor2 port map( a => n3124, b => n3107, outb => mult_125_G2_A1_5_port
);
U1910 : xor2 port map( a => n3125, b => n3104, outb => mult_125_G2_A1_3_port
);
U1911 : xor2 port map( a => n314, b => n313, outb => mult_125_G2_A1_28_port)
;
U1912 : xor2 port map( a => n318, b => n317, outb => mult_125_G2_A1_26_port)
;
U1913 : xor2 port map( a => n322, b => n321, outb => mult_125_G2_A1_24_port)
;
U1914 : xor2 port map( a => n326, b => n325, outb => mult_125_G2_A1_22_port)
;
U1915 : xor2 port map( a => n330, b => n329, outb => mult_125_G2_A1_20_port)
;
U1916 : xor2 port map( a => n3126, b => n3102, outb => mult_125_G2_A1_1_port
);
U1917 : xor2 port map( a => n334, b => n333, outb => mult_125_G2_A1_18_port)
;
U1918 : xor2 port map( a => n339, b => n338, outb => mult_125_G2_A1_16_port)
;
U1919 : xor2 port map( a => n3127, b => n347, outb => mult_125_G2_A1_13_port
);
U1920 : xor2 port map( a => n3128, b => n3116, outb =>
mult_125_G2_A1_11_port);
U1921 : xor2 port map( a => mult_125_ab_15_15_port, b => n3130, outb =>
n3129);
U1922 : xor2 port map( a => mult_125_ab_1_14_port, b =>
mult_125_ab_0_15_port, outb => n3131);
U1923 : xor2 port map( a => n3133, b => mult_125_ab_1_15_port, outb => n3132
);
U1924 : xor2 port map( a => mult_125_ab_1_13_port, b =>
mult_125_ab_0_14_port, outb => n3134);
U1925 : xor2 port map( a => n3136, b => n3131, outb => n3135);
U1926 : xor2 port map( a => n3138, b => n3139, outb => n3137);
U1927 : xor2 port map( a => n3141, b => n3142, outb => n3140);
U1928 : xor2 port map( a => n3144, b => n3145, outb => n3143);
U1929 : xor2 port map( a => n3147, b => n3148, outb => n3146);
U1930 : xor2 port map( a => n3150, b => n3151, outb => n3149);
U1931 : xor2 port map( a => n3153, b => n3154, outb => n3152);
U1932 : xor2 port map( a => n3156, b => n3157, outb => n3155);
U1933 : xor2 port map( a => n3159, b => n3160, outb => n3158);
U1934 : xor2 port map( a => n3162, b => n3163, outb => n3161);
U1935 : xor2 port map( a => n3165, b => n3166, outb => n3164);
U1936 : xor2 port map( a => n3168, b => n3169, outb => n3167);
U1937 : xor2 port map( a => n3170, b => n3171, outb => n282);
U1938 : xor2 port map( a => mult_125_ab_1_12_port, b =>
mult_125_ab_0_13_port, outb => n3172);
U1939 : xor2 port map( a => n3174, b => n3134, outb => n3173);
U1940 : xor2 port map( a => n3176, b => n3177, outb => n3175);
U1941 : xor2 port map( a => mult_125_ab_1_11_port, b =>
mult_125_ab_0_12_port, outb => n3178);
U1942 : xor2 port map( a => n3180, b => n3172, outb => n3179);
U1943 : xor2 port map( a => n3182, b => n3183, outb => n3181);
U1944 : xor2 port map( a => n3185, b => n3186, outb => n3184);
U1945 : xor2 port map( a => n3188, b => n3189, outb => n3187);
U1946 : xor2 port map( a => n3191, b => n3192, outb => n3190);
U1947 : xor2 port map( a => n3194, b => n3195, outb => n3193);
U1948 : xor2 port map( a => n3197, b => n3198, outb => n3196);
U1949 : xor2 port map( a => n3200, b => n3201, outb => n3199);
U1950 : xor2 port map( a => n3203, b => n3204, outb => n3202);
U1951 : xor2 port map( a => n3206, b => n3207, outb => n3205);
U1952 : xor2 port map( a => n3209, b => n3210, outb => n3208);
U1953 : xor2 port map( a => n3211, b => n3212, outb => n286);
U1954 : xor2 port map( a => mult_125_ab_1_10_port, b =>
mult_125_ab_0_11_port, outb => n3213);
U1955 : xor2 port map( a => n3215, b => n3178, outb => n3214);
U1956 : xor2 port map( a => n3217, b => n3218, outb => n3216);
U1957 : xor2 port map( a => n3220, b => n3221, outb => n3219);
U1958 : xor2 port map( a => mult_125_ab_1_9_port, b => mult_125_ab_0_10_port
, outb => n3222);
U1959 : xor2 port map( a => n3224, b => n3213, outb => n3223);
U1960 : xor2 port map( a => n3226, b => n3227, outb => n3225);
U1961 : xor2 port map( a => n3229, b => n3230, outb => n3228);
U1962 : xor2 port map( a => n3232, b => n3233, outb => n3231);
U1963 : xor2 port map( a => n3235, b => n3236, outb => n3234);
U1964 : xor2 port map( a => n3238, b => n3239, outb => n3237);
U1965 : xor2 port map( a => n3241, b => n3242, outb => n3240);
U1966 : xor2 port map( a => n3244, b => n3245, outb => n3243);
U1967 : xor2 port map( a => n3247, b => n3248, outb => n3246);
U1968 : xor2 port map( a => n3250, b => n3251, outb => n3249);
U1969 : xor2 port map( a => n3252, b => n3253, outb => n290);
U1970 : xor2 port map( a => mult_125_ab_1_8_port, b => mult_125_ab_0_9_port,
outb => n3254);
U1971 : xor2 port map( a => n3256, b => n3222, outb => n3255);
U1972 : xor2 port map( a => n3258, b => n3259, outb => n3257);
U1973 : xor2 port map( a => n3261, b => n3262, outb => n3260);
U1974 : xor2 port map( a => n3264, b => n3265, outb => n3263);
U1975 : xor2 port map( a => mult_125_ab_1_7_port, b => mult_125_ab_0_8_port,
outb => n3266);
U1976 : xor2 port map( a => n3268, b => n3254, outb => n3267);
U1977 : xor2 port map( a => n3270, b => n3271, outb => n3269);
U1978 : xor2 port map( a => n3273, b => n3274, outb => n3272);
U1979 : xor2 port map( a => n3276, b => n3277, outb => n3275);
U1980 : xor2 port map( a => n3279, b => n3280, outb => n3278);
U1981 : xor2 port map( a => n3282, b => n3283, outb => n3281);
U1982 : xor2 port map( a => n3285, b => n3286, outb => n3284);
U1983 : xor2 port map( a => n3288, b => n3289, outb => n3287);
U1984 : xor2 port map( a => n3291, b => n3292, outb => n3290);
U1985 : xor2 port map( a => n3293, b => n3294, outb => n294);
U1986 : xor2 port map( a => mult_125_ab_1_6_port, b => mult_125_ab_0_7_port,
outb => n3295);
U1987 : xor2 port map( a => n3297, b => n3266, outb => n3296);
U1988 : xor2 port map( a => n3299, b => n3300, outb => n3298);
U1989 : xor2 port map( a => n3302, b => n3303, outb => n3301);
U1990 : xor2 port map( a => n3305, b => n3306, outb => n3304);
U1991 : xor2 port map( a => n3308, b => n3309, outb => n3307);
U1992 : xor2 port map( a => mult_125_ab_1_5_port, b => mult_125_ab_0_6_port,
outb => n3310);
U1993 : xor2 port map( a => n3312, b => n3295, outb => n3311);
U1994 : xor2 port map( a => n3314, b => n3315, outb => n3313);
U1995 : xor2 port map( a => n3317, b => n3318, outb => n3316);
U1996 : xor2 port map( a => n3320, b => n3321, outb => n3319);
U1997 : xor2 port map( a => n3323, b => n3324, outb => n3322);
U1998 : xor2 port map( a => n3326, b => n3327, outb => n3325);
U1999 : xor2 port map( a => n3329, b => n3330, outb => n3328);
U2000 : xor2 port map( a => n3332, b => n3333, outb => n3331);
U2001 : xor2 port map( a => n3334, b => n3335, outb => n298);
U2002 : xor2 port map( a => mult_125_ab_1_4_port, b => mult_125_ab_0_5_port,
outb => n3336);
U2003 : xor2 port map( a => n3338, b => n3310, outb => n3337);
U2004 : xor2 port map( a => n3340, b => n3341, outb => n3339);
U2005 : xor2 port map( a => n3343, b => n3344, outb => n3342);
U2006 : xor2 port map( a => n3346, b => n3347, outb => n3345);
U2007 : xor2 port map( a => n3349, b => n3350, outb => n3348);
U2008 : xor2 port map( a => n3352, b => n3353, outb => n3351);
U2009 : xor2 port map( a => mult_125_ab_1_3_port, b => mult_125_ab_0_4_port,
outb => n3354);
U2010 : xor2 port map( a => n3356, b => n3336, outb => n3355);
U2011 : xor2 port map( a => n3358, b => n3359, outb => n3357);
U2012 : xor2 port map( a => n3361, b => n3362, outb => n3360);
U2013 : xor2 port map( a => n3364, b => n3365, outb => n3363);
U2014 : xor2 port map( a => n3367, b => n3368, outb => n3366);
U2015 : xor2 port map( a => n3370, b => n3371, outb => n3369);
U2016 : xor2 port map( a => n3373, b => n3374, outb => n3372);
U2017 : xor2 port map( a => n3375, b => n3376, outb => n303);
U2018 : xor2 port map( a => mult_125_ab_1_2_port, b => mult_125_ab_0_3_port,
outb => n3377);
U2019 : xor2 port map( a => n3379, b => n3354, outb => n3378);
U2020 : xor2 port map( a => n3381, b => n3382, outb => n3380);
U2021 : xor2 port map( a => n3384, b => n3385, outb => n3383);
U2022 : xor2 port map( a => n3387, b => n3388, outb => n3386);
U2023 : xor2 port map( a => n3390, b => n3391, outb => n3389);
U2024 : xor2 port map( a => n3393, b => n3394, outb => n3392);
U2025 : xor2 port map( a => n3396, b => n3397, outb => n3395);
U2026 : xor2 port map( a => mult_125_ab_1_1_port, b => mult_125_ab_0_2_port,
outb => n3398);
U2027 : xor2 port map( a => n3400, b => n3377, outb => n3399);
U2028 : xor2 port map( a => n3402, b => n3403, outb => n3401);
U2029 : xor2 port map( a => n3405, b => n3406, outb => n3404);
U2030 : xor2 port map( a => n3408, b => n3409, outb => n3407);
U2031 : xor2 port map( a => n3411, b => n3412, outb => n3410);
U2032 : xor2 port map( a => n3414, b => n3415, outb => n3413);
U2033 : xor2 port map( a => n3417, b => n3418, outb => n3416);
U2034 : xor2 port map( a => n3419, b => n3410, outb => mult_125_A1_9_port);
U2035 : xor2 port map( a => n3420, b => n3407, outb => mult_125_A1_7_port);
U2036 : xor2 port map( a => n3421, b => n3404, outb => mult_125_A1_5_port);
U2037 : xor2 port map( a => n3422, b => n3401, outb => mult_125_A1_3_port);
U2038 : xor2 port map( a => n278, b => n277, outb => mult_125_A1_28_port);
U2039 : xor2 port map( a => n282, b => n281, outb => mult_125_A1_26_port);
U2040 : xor2 port map( a => n286, b => n285, outb => mult_125_A1_24_port);
U2041 : xor2 port map( a => n290, b => n289, outb => mult_125_A1_22_port);
U2042 : xor2 port map( a => n294, b => n293, outb => mult_125_A1_20_port);
U2043 : xor2 port map( a => n3423, b => n3399, outb => mult_125_A1_1_port);
U2044 : xor2 port map( a => n298, b => n297, outb => mult_125_A1_18_port);
U2045 : xor2 port map( a => n303, b => n302, outb => mult_125_A1_16_port);
U2046 : xor2 port map( a => n3424, b => n311, outb => mult_125_A1_13_port);
U2047 : xor2 port map( a => n3425, b => n3413, outb => mult_125_A1_11_port);
U2048 : xor2 port map( a => mult_125_G3_ab_1_0_port, b =>
mult_125_G3_ab_0_1_port, outb => n3426);
U2049 : xor2 port map( a => n3427, b => n3428, outb => N99);
U2050 : xor2 port map( a => n3429, b => n3430, outb => N98);
U2051 : xor2 port map( a => n3431, b => n3432, outb => N97);
U2052 : xor2 port map( a => n3433, b => n3434, outb => N96);
U2053 : xor2 port map( a => n3435, b => n3436, outb => N95);
U2054 : xor2 port map( a => n3437, b => n3438, outb => N94);
U2055 : xor2 port map( a => n3439, b => n3440, outb => N93);
U2056 : xor2 port map( a => n3441, b => n3442, outb => N92);
U2057 : xor2 port map( a => n3443, b => n3444, outb => N91);
U2058 : xor2 port map( a => n3445, b => n3446, outb => N90);
U2059 : xor2 port map( a => mult_125_ab_1_0_port, b => mult_125_ab_0_1_port,
outb => n3447);
U2060 : xor2 port map( a => n3448, b => n3449, outb => N9);
U2061 : xor2 port map( a => n3450, b => n3451, outb => N89);
U2062 : xor2 port map( a => n3452, b => n3453, outb => N88);
U2063 : xor2 port map( a => n3454, b => n3455, outb => N87);
U2064 : xor2 port map( a => n3456, b => n3457, outb => N86);
U2065 : xor2 port map( a => n3458, b => n3459, outb => N85);
U2066 : xor2 port map( a => n3460, b => n3461, outb => N84);
U2067 : xor2 port map( a => n3462, b => n3463, outb => N83);
U2068 : xor2 port map( a => n3464, b => n3465, outb => N82);
U2069 : xor2 port map( a => n3466, b => n3467, outb => N81);
U2070 : xor2 port map( a => n3468, b => n3469, outb => N80);
U2071 : xor2 port map( a => n3470, b => n3471, outb => N8);
U2072 : xor2 port map( a => n3472, b => n3473, outb => N79);
U2073 : xor2 port map( a => n3474, b => n3475, outb => N78);
U2074 : xor2 port map( a => n3476, b => n3477, outb => N77);
U2075 : xor2 port map( a => n3478, b => n3479, outb => N76);
U2076 : xor2 port map( a => n3480, b => n3481, outb => N75);
U2077 : xor2 port map( a => n3482, b => n3483, outb => N74);
U2078 : xor2 port map( a => mult_125_G2_ab_1_0_port, b =>
mult_125_G2_ab_0_1_port, outb => n3484);
U2079 : xor2 port map( a => n3485, b => n2197, outb => N71);
U2080 : xor2 port map( a => n2199, b => n3486, outb => N70);
U2081 : xor2 port map( a => n3487, b => n3488, outb => N69);
U2082 : xor2 port map( a => n3489, b => n3490, outb => N68);
U2083 : xor2 port map( a => n3491, b => n3492, outb => N67);
U2084 : xor2 port map( a => n3493, b => n3494, outb => N66);
U2085 : xor2 port map( a => n3495, b => n3496, outb => N65);
U2086 : xor2 port map( a => n3497, b => n3498, outb => N64);
U2087 : xor2 port map( a => n3499, b => n3500, outb => N63);
U2088 : xor2 port map( a => n3501, b => n3502, outb => N62);
U2089 : xor2 port map( a => n3503, b => n3504, outb => N61);
U2090 : xor2 port map( a => n3505, b => n3506, outb => N60);
U2091 : xor2 port map( a => n3507, b => n3508, outb => N59);
U2092 : xor2 port map( a => n3509, b => n3510, outb => N58);
U2093 : xor2 port map( a => n3511, b => n3512, outb => N57);
U2094 : xor2 port map( a => n3513, b => n3514, outb => N56);
U2095 : xor2 port map( a => n3515, b => n3516, outb => N55);
U2096 : xor2 port map( a => n3517, b => n3518, outb => N54);
U2097 : xor2 port map( a => n3519, b => n3520, outb => N53);
U2098 : xor2 port map( a => n3521, b => n3522, outb => N52);
U2099 : xor2 port map( a => n3523, b => n3524, outb => N51);
U2100 : xor2 port map( a => n3525, b => n3526, outb => N50);
U2101 : xor2 port map( a => n3527, b => n3528, outb => N49);
U2102 : xor2 port map( a => n3529, b => n3530, outb => N48);
U2103 : xor2 port map( a => n3531, b => n3532, outb => N47);
U2104 : xor2 port map( a => n3533, b => n3534, outb => N46);
U2105 : xor2 port map( a => n3535, b => n3536, outb => N45);
U2106 : xor2 port map( a => n3537, b => n3538, outb => N44);
U2107 : xor2 port map( a => n3539, b => n3540, outb => N43);
U2108 : xor2 port map( a => n3541, b => n3542, outb => N42);
U2109 : xor2 port map( a => n3543, b => n3544, outb => N41);
U2110 : xor2 port map( a => n3545, b => n2228, outb => N38);
U2111 : xor2 port map( a => n2230, b => n3546, outb => N37);
U2112 : xor2 port map( a => n3547, b => n3548, outb => N36);
U2113 : xor2 port map( a => n3549, b => n3550, outb => N35);
U2114 : xor2 port map( a => n3551, b => n3552, outb => N34);
U2115 : xor2 port map( a => n3553, b => n3554, outb => N33);
U2116 : xor2 port map( a => n3555, b => n3556, outb => N32);
U2117 : xor2 port map( a => n3557, b => n3558, outb => N31);
U2118 : xor2 port map( a => n3559, b => n3560, outb => N30);
U2119 : xor2 port map( a => n3561, b => n3562, outb => N29);
U2120 : xor2 port map( a => n3563, b => n3564, outb => N28);
U2121 : xor2 port map( a => n3565, b => n3566, outb => N27);
U2122 : xor2 port map( a => n3567, b => n3568, outb => N26);
U2123 : xor2 port map( a => n3569, b => n3570, outb => N25);
U2124 : xor2 port map( a => n3571, b => n3572, outb => N24);
U2125 : xor2 port map( a => n3573, b => n3574, outb => N23);
U2126 : xor2 port map( a => n3575, b => n3576, outb => N22);
U2127 : xor2 port map( a => n3577, b => n3578, outb => N21);
U2128 : xor2 port map( a => n3579, b => n3580, outb => N20);
U2129 : xor2 port map( a => n3581, b => n3582, outb => N19);
U2130 : xor2 port map( a => n3583, b => n3584, outb => N18);
U2131 : xor2 port map( a => n3585, b => n3586, outb => N17);
U2132 : xor2 port map( a => n3587, b => n3588, outb => N16);
U2133 : xor2 port map( a => n3589, b => n3590, outb => N15);
U2134 : xor2 port map( a => n3591, b => n3592, outb => N14);
U2135 : xor2 port map( a => n3593, b => n3594, outb => N13);
U2136 : xor2 port map( a => n3595, b => n3596, outb => N12);
U2137 : xor2 port map( a => n3597, b => n3598, outb => N11);
U2138 : xor2 port map( a => n3599, b => n2235, outb => N104);
U2139 : xor2 port map( a => n2237, b => n3600, outb => N103);
U2140 : xor2 port map( a => n3601, b => n3602, outb => N102);
U2141 : xor2 port map( a => n3603, b => n3604, outb => N101);
U2142 : xor2 port map( a => n3605, b => n3606, outb => N100);
U2143 : xor2 port map( a => n3607, b => n3608, outb => N10);
U2144 : nand2 port map( a => mult_125_G4_ab_0_15_port, b =>
mult_125_G4_ab_1_14_port, outb => n3609);
U2145 : inv port map( inb => mult_125_G4_ab_3_15_port, outb => n3610);
U2146 : inv port map( inb => mult_125_G4_ab_4_14_port, outb => n3611);
U2147 : inv port map( inb => mult_125_G4_ab_5_15_port, outb => n3612);
U2148 : inv port map( inb => mult_125_G4_ab_6_14_port, outb => n3613);
U2149 : inv port map( inb => mult_125_G4_ab_7_15_port, outb => n3614);
U2150 : inv port map( inb => mult_125_G4_ab_8_14_port, outb => n3615);
U2151 : inv port map( inb => mult_125_G4_ab_9_15_port, outb => n3616);
U2152 : inv port map( inb => mult_125_G4_ab_10_14_port, outb => n3617);
U2153 : inv port map( inb => mult_125_G4_ab_11_15_port, outb => n3618);
U2154 : inv port map( inb => mult_125_G4_ab_12_14_port, outb => n3619);
U2155 : nand2 port map( a => mult_125_G4_ab_0_14_port, b =>
mult_125_G4_ab_1_13_port, outb => n400);
U2156 : aoi22 port map( a => mult_125_G4_ab_2_13_port, b => n3620, c => n398
, d => n2240, outb => n403);
U2157 : oai22 port map( a => n403, b => n402, c => n3621, d => n2241, outb
=> n405);
U2158 : aoi22 port map( a => n405, b => mult_125_G4_ab_4_13_port, c => n3623
, d => n2248, outb => n3622);
U2159 : oai22 port map( a => n3622, b => n3624, c => n406, d => n2251, outb
=> n409);
U2160 : aoi22 port map( a => n409, b => mult_125_G4_ab_6_13_port, c => n3626
, d => n2254, outb => n3625);
U2161 : inv port map( inb => mult_125_G4_ab_7_13_port, outb => n3627);
U2162 : oai22 port map( a => n3625, b => n3627, c => n410, d => n2257, outb
=> n413);
U2163 : aoi22 port map( a => n413, b => mult_125_G4_ab_8_13_port, c => n3629
, d => n2260, outb => n3628);
U2164 : inv port map( inb => mult_125_G4_ab_9_13_port, outb => n3630);
U2165 : oai22 port map( a => n3628, b => n3630, c => n414, d => n2263, outb
=> n417);
U2166 : aoi22 port map( a => n417, b => mult_125_G4_ab_10_13_port, c =>
n3632, d => n2266, outb => n3631);
U2167 : inv port map( inb => mult_125_G4_ab_11_13_port, outb => n3633);
U2168 : oai22 port map( a => n3631, b => n3633, c => n418, d => n2269, outb
=> n421);
U2169 : aoi22 port map( a => n421, b => mult_125_G4_ab_12_13_port, c =>
n3635, d => n2272, outb => n3634);
U2170 : inv port map( inb => mult_125_G4_ab_13_13_port, outb => n3636);
U2171 : oai22 port map( a => n3634, b => n3636, c => n422, d => n2275, outb
=> n425);
U2172 : aoi22 port map( a => n425, b => mult_125_G4_ab_14_13_port, c =>
n3638, d => n2278, outb => n3637);
U2173 : nand2 port map( a => mult_125_G4_ab_0_13_port, b =>
mult_125_G4_ab_1_12_port, outb => n430);
U2174 : aoi22 port map( a => mult_125_G4_ab_2_12_port, b => n3640, c => n428
, d => n2243, outb => n3639);
U2175 : oai22 port map( a => n3639, b => n3641, c => n431, d => n2244, outb
=> n434);
U2176 : aoi22 port map( a => n434, b => mult_125_G4_ab_4_12_port, c => n3643
, d => n2286, outb => n3642);
U2177 : aoi22 port map( a => n436, b => mult_125_G4_ab_5_12_port, c => n3645
, d => n2246, outb => n3644);
U2178 : inv port map( inb => mult_125_G4_ab_6_12_port, outb => n3646);
U2179 : oai22 port map( a => n3644, b => n3646, c => n437, d => n2249, outb
=> n440);
U2180 : aoi22 port map( a => n440, b => mult_125_G4_ab_7_12_port, c => n3648
, d => n2252, outb => n3647);
U2181 : inv port map( inb => mult_125_G4_ab_8_12_port, outb => n3649);
U2182 : oai22 port map( a => n3647, b => n3649, c => n441, d => n2255, outb
=> n444);
U2183 : aoi22 port map( a => n444, b => mult_125_G4_ab_9_12_port, c => n3651
, d => n2258, outb => n3650);
U2184 : inv port map( inb => mult_125_G4_ab_10_12_port, outb => n3652);
U2185 : oai22 port map( a => n3650, b => n3652, c => n445, d => n2261, outb
=> n448);
U2186 : aoi22 port map( a => n448, b => mult_125_G4_ab_11_12_port, c =>
n3654, d => n2264, outb => n3653);
U2187 : inv port map( inb => mult_125_G4_ab_12_12_port, outb => n3655);
U2188 : oai22 port map( a => n3653, b => n3655, c => n449, d => n2267, outb
=> n452);
U2189 : aoi22 port map( a => n452, b => mult_125_G4_ab_13_12_port, c =>
n3657, d => n2270, outb => n3656);
U2190 : inv port map( inb => mult_125_G4_ab_14_12_port, outb => n3658);
U2191 : oai22 port map( a => n3656, b => n3658, c => n453, d => n2273, outb
=> n456);
U2192 : nand2 port map( a => mult_125_G4_ab_0_12_port, b =>
mult_125_G4_ab_1_11_port, outb => n459);
U2193 : aoi22 port map( a => mult_125_G4_ab_2_11_port, b => n3659, c => n457
, d => n2281, outb => n462);
U2194 : oai22 port map( a => n462, b => n461, c => n3660, d => n2282, outb
=> n464);
U2195 : oai22 port map( a => n3661, b => n3662, c => n463, d => n2292, outb
=> n466);
U2196 : aoi22 port map( a => n466, b => mult_125_G4_ab_5_11_port, c => n3664
, d => n2284, outb => n3663);
U2197 : oai22 port map( a => n3663, b => n3665, c => n467, d => n2295, outb
=> n470);
U2198 : oai22 port map( a => n3666, b => n3667, c => n469, d => n2298, outb
=> n472);
U2199 : aoi22 port map( a => n472, b => mult_125_G4_ab_8_11_port, c => n3669
, d => n2301, outb => n3668);
U2200 : inv port map( inb => mult_125_G4_ab_9_11_port, outb => n3670);
U2201 : oai22 port map( a => n3668, b => n3670, c => n473, d => n2304, outb
=> n476);
U2202 : aoi22 port map( a => n476, b => mult_125_G4_ab_10_11_port, c =>
n3672, d => n2307, outb => n3671);
U2203 : inv port map( inb => mult_125_G4_ab_11_11_port, outb => n3673);
U2204 : oai22 port map( a => n3671, b => n3673, c => n477, d => n2310, outb
=> n480);
U2205 : aoi22 port map( a => n480, b => mult_125_G4_ab_12_11_port, c =>
n3675, d => n2313, outb => n3674);
U2206 : inv port map( inb => mult_125_G4_ab_13_11_port, outb => n3676);
U2207 : oai22 port map( a => n3674, b => n3676, c => n481, d => n2316, outb
=> n484);
U2208 : aoi22 port map( a => n484, b => mult_125_G4_ab_14_11_port, c =>
n3677, d => n2319, outb => n487);
U2209 : nand2 port map( a => mult_125_G4_ab_0_11_port, b =>
mult_125_G4_ab_1_10_port, outb => n490);
U2210 : aoi22 port map( a => mult_125_G4_ab_2_10_port, b => n3679, c => n488
, d => n2287, outb => n3678);
U2211 : oai22 port map( a => n3678, b => n3680, c => n491, d => n2288, outb
=> n494);
U2212 : aoi22 port map( a => n494, b => mult_125_G4_ab_4_10_port, c => n3681
, d => n2327, outb => n497);
U2213 : oai22 port map( a => n497, b => n496, c => n3682, d => n2290, outb
=> n499);
U2214 : aoi22 port map( a => n499, b => mult_125_G4_ab_6_10_port, c => n3684
, d => n2330, outb => n3683);
U2215 : oai22 port map( a => n3683, b => n3685, c => n500, d => n2293, outb
=> n503);
U2216 : inv port map( inb => mult_125_G4_ab_8_10_port, outb => n3686);
U2217 : oai22 port map( a => n3687, b => n3686, c => n502, d => n2296, outb
=> n505);
U2218 : aoi22 port map( a => n505, b => mult_125_G4_ab_9_10_port, c => n3689
, d => n2299, outb => n3688);
U2219 : inv port map( inb => mult_125_G4_ab_10_10_port, outb => n3690);
U2220 : oai22 port map( a => n3688, b => n3690, c => n506, d => n2302, outb
=> n509);
U2221 : aoi22 port map( a => n509, b => mult_125_G4_ab_11_10_port, c =>
n3692, d => n2305, outb => n3691);
U2222 : inv port map( inb => mult_125_G4_ab_12_10_port, outb => n3693);
U2223 : oai22 port map( a => n3691, b => n3693, c => n510, d => n2308, outb
=> n513);
U2224 : aoi22 port map( a => n513, b => mult_125_G4_ab_13_10_port, c =>
n3695, d => n2311, outb => n3694);
U2225 : inv port map( inb => mult_125_G4_ab_14_10_port, outb => n3696);
U2226 : oai22 port map( a => n3694, b => n3696, c => n514, d => n2314, outb
=> n517);
U2227 : nand2 port map( a => mult_125_G4_ab_0_10_port, b =>
mult_125_G4_ab_1_9_port, outb => n520);
U2228 : aoi22 port map( a => mult_125_G4_ab_2_9_port, b => n3698, c => n518,
d => n2322, outb => n3697);
U2229 : oai22 port map( a => n3697, b => n3699, c => n521, d => n2323, outb
=> n524);
U2230 : oai22 port map( a => n3700, b => n3701, c => n523, d => n2336, outb
=> n526);
U2231 : aoi22 port map( a => n526, b => mult_125_G4_ab_5_9_port, c => n3703,
d => n2325, outb => n3702);
U2232 : oai22 port map( a => n3702, b => n3704, c => n527, d => n2339, outb
=> n530);
U2233 : aoi22 port map( a => n530, b => mult_125_G4_ab_7_9_port, c => n3706,
d => n2328, outb => n3705);
U2234 : oai22 port map( a => n3705, b => n3707, c => n531, d => n2342, outb
=> n534);
U2235 : oai22 port map( a => n3708, b => n3709, c => n533, d => n2345, outb
=> n536);
U2236 : aoi22 port map( a => n536, b => mult_125_G4_ab_10_9_port, c => n3711
, d => n2348, outb => n3710);
U2237 : inv port map( inb => mult_125_G4_ab_11_9_port, outb => n3712);
U2238 : oai22 port map( a => n3710, b => n3712, c => n537, d => n2351, outb
=> n540);
U2239 : aoi22 port map( a => n540, b => mult_125_G4_ab_12_9_port, c => n3714
, d => n2354, outb => n3713);
U2240 : inv port map( inb => mult_125_G4_ab_13_9_port, outb => n3715);
U2241 : oai22 port map( a => n3713, b => n3715, c => n541, d => n2357, outb
=> n544);
U2242 : aoi22 port map( a => n544, b => mult_125_G4_ab_14_9_port, c => n3716
, d => n2360, outb => n547);
U2243 : nand2 port map( a => mult_125_G4_ab_0_9_port, b =>
mult_125_G4_ab_1_8_port, outb => n550);
U2244 : aoi22 port map( a => mult_125_G4_ab_2_8_port, b => n3718, c => n548,
d => n2331, outb => n3717);
U2245 : oai22 port map( a => n3717, b => n3719, c => n551, d => n2332, outb
=> n554);
U2246 : oai22 port map( a => n3720, b => n3721, c => n553, d => n2368, outb
=> n556);
U2247 : oai22 port map( a => n3722, b => n3723, c => n555, d => n2334, outb
=> n558);
U2248 : aoi22 port map( a => n558, b => mult_125_G4_ab_6_8_port, c => n3725,
d => n2371, outb => n3724);
U2249 : oai22 port map( a => n3724, b => n3726, c => n559, d => n2337, outb
=> n562);
U2250 : aoi22 port map( a => n562, b => mult_125_G4_ab_8_8_port, c => n3728,
d => n2374, outb => n3727);
U2251 : oai22 port map( a => n3727, b => n3729, c => n563, d => n2340, outb
=> n566);
U2252 : inv port map( inb => mult_125_G4_ab_10_8_port, outb => n3730);
U2253 : oai22 port map( a => n3731, b => n3730, c => n565, d => n2343, outb
=> n568);
U2254 : aoi22 port map( a => n568, b => mult_125_G4_ab_11_8_port, c => n3733
, d => n2346, outb => n3732);
U2255 : inv port map( inb => mult_125_G4_ab_12_8_port, outb => n3734);
U2256 : oai22 port map( a => n3732, b => n3734, c => n569, d => n2349, outb
=> n572);
U2257 : aoi22 port map( a => n572, b => mult_125_G4_ab_13_8_port, c => n3736
, d => n2352, outb => n3735);
U2258 : inv port map( inb => mult_125_G4_ab_14_8_port, outb => n3737);
U2259 : oai22 port map( a => n3735, b => n3737, c => n573, d => n2355, outb
=> n576);
U2260 : nand2 port map( a => mult_125_G4_ab_0_8_port, b =>
mult_125_G4_ab_1_7_port, outb => n579);
U2261 : aoi22 port map( a => mult_125_G4_ab_2_7_port, b => n3738, c => n577,
d => n2363, outb => n582);
U2262 : oai22 port map( a => n582, b => n581, c => n3739, d => n2364, outb
=> n584);
U2263 : oai22 port map( a => n3740, b => n3741, c => n583, d => n2380, outb
=> n586);
U2264 : aoi22 port map( a => n586, b => mult_125_G4_ab_5_7_port, c => n3743,
d => n2366, outb => n3742);
U2265 : oai22 port map( a => n3742, b => n3744, c => n587, d => n2383, outb
=> n590);
U2266 : aoi22 port map( a => n590, b => mult_125_G4_ab_7_7_port, c => n3746,
d => n2369, outb => n3745);
U2267 : oai22 port map( a => n3745, b => n3747, c => n591, d => n2386, outb
=> n594);
U2268 : aoi22 port map( a => n594, b => mult_125_G4_ab_9_7_port, c => n3749,
d => n2372, outb => n3748);
U2269 : oai22 port map( a => n3748, b => n3750, c => n595, d => n2389, outb
=> n598);
U2270 : oai22 port map( a => n3751, b => n3752, c => n597, d => n2392, outb
=> n600);
U2271 : aoi22 port map( a => n600, b => mult_125_G4_ab_12_7_port, c => n3754
, d => n2395, outb => n3753);
U2272 : inv port map( inb => mult_125_G4_ab_13_7_port, outb => n3755);
U2273 : oai22 port map( a => n3753, b => n3755, c => n601, d => n2398, outb
=> n604);
U2274 : aoi22 port map( a => n604, b => mult_125_G4_ab_14_7_port, c => n3756
, d => n2401, outb => n607);
U2275 : nand2 port map( a => mult_125_G4_ab_0_7_port, b =>
mult_125_G4_ab_1_6_port, outb => n610);
U2276 : aoi22 port map( a => mult_125_G4_ab_2_6_port, b => n3758, c => n608,
d => n2375, outb => n3757);
U2277 : oai22 port map( a => n3757, b => n3759, c => n611, d => n2376, outb
=> n614);
U2278 : aoi22 port map( a => n614, b => mult_125_G4_ab_4_6_port, c => n3760,
d => n2409, outb => n617);
U2279 : oai22 port map( a => n617, b => n616, c => n3761, d => n2378, outb
=> n619);
U2280 : aoi22 port map( a => n619, b => mult_125_G4_ab_6_6_port, c => n3763,
d => n2412, outb => n3762);
U2281 : oai22 port map( a => n3762, b => n3764, c => n620, d => n2381, outb
=> n623);
U2282 : aoi22 port map( a => n623, b => mult_125_G4_ab_8_6_port, c => n3765,
d => n2415, outb => n626);
U2283 : oai22 port map( a => n626, b => n625, c => n3766, d => n2384, outb
=> n628);
U2284 : aoi22 port map( a => n628, b => mult_125_G4_ab_10_6_port, c => n3768
, d => n2418, outb => n3767);
U2285 : oai22 port map( a => n3767, b => n3769, c => n629, d => n2387, outb
=> n632);
U2286 : inv port map( inb => mult_125_G4_ab_12_6_port, outb => n3770);
U2287 : oai22 port map( a => n3771, b => n3770, c => n631, d => n2390, outb
=> n634);
U2288 : aoi22 port map( a => n634, b => mult_125_G4_ab_13_6_port, c => n3773
, d => n2393, outb => n3772);
U2289 : inv port map( inb => mult_125_G4_ab_14_6_port, outb => n3774);
U2290 : oai22 port map( a => n3772, b => n3774, c => n635, d => n2396, outb
=> n638);
U2291 : nand2 port map( a => mult_125_G4_ab_0_6_port, b =>
mult_125_G4_ab_1_5_port, outb => n641);
U2292 : aoi22 port map( a => mult_125_G4_ab_2_5_port, b => n3775, c => n639,
d => n2404, outb => n644);
U2293 : oai22 port map( a => n644, b => n643, c => n3776, d => n2405, outb
=> n646);
U2294 : oai22 port map( a => n3777, b => n3778, c => n645, d => n2424, outb
=> n648);
U2295 : aoi22 port map( a => n648, b => mult_125_G4_ab_5_5_port, c => n3779,
d => n2407, outb => n651);
U2296 : oai22 port map( a => n651, b => n650, c => n3780, d => n2427, outb
=> n653);
U2297 : aoi22 port map( a => n653, b => mult_125_G4_ab_7_5_port, c => n3782,
d => n2410, outb => n3781);
U2298 : oai22 port map( a => n3781, b => n3783, c => n654, d => n2430, outb
=> n657);
U2299 : aoi22 port map( a => n657, b => mult_125_G4_ab_9_5_port, c => n3785,
d => n2413, outb => n3784);
U2300 : oai22 port map( a => n3784, b => n3786, c => n658, d => n2433, outb
=> n661);
U2301 : aoi22 port map( a => n661, b => mult_125_G4_ab_11_5_port, c => n3788
, d => n2416, outb => n3787);
U2302 : oai22 port map( a => n3787, b => n3789, c => n662, d => n2436, outb
=> n665);
U2303 : oai22 port map( a => n3790, b => n3791, c => n664, d => n2439, outb
=> n667);
U2304 : aoi22 port map( a => n667, b => mult_125_G4_ab_14_5_port, c => n3792
, d => n2442, outb => n670);
U2305 : nand2 port map( a => mult_125_G4_ab_0_5_port, b =>
mult_125_G4_ab_1_4_port, outb => n673);
U2306 : aoi22 port map( a => mult_125_G4_ab_2_4_port, b => n3794, c => n671,
d => n2419, outb => n3793);
U2307 : oai22 port map( a => n3793, b => n3795, c => n674, d => n2420, outb
=> n677);
U2308 : aoi22 port map( a => n677, b => mult_125_G4_ab_4_4_port, c => n3796,
d => n2450, outb => n680);
U2309 : oai22 port map( a => n680, b => n679, c => n3797, d => n2422, outb
=> n682);
U2310 : aoi22 port map( a => n682, b => mult_125_G4_ab_6_4_port, c => n3798,
d => n2453, outb => n685);
U2311 : oai22 port map( a => n685, b => n684, c => n3799, d => n2425, outb
=> n687);
U2312 : aoi22 port map( a => n687, b => mult_125_G4_ab_8_4_port, c => n3801,
d => n2456, outb => n3800);
U2313 : oai22 port map( a => n3800, b => n3802, c => n688, d => n2428, outb
=> n691);
U2314 : aoi22 port map( a => n691, b => mult_125_G4_ab_10_4_port, c => n3803
, d => n2459, outb => n694);
U2315 : oai22 port map( a => n694, b => n693, c => n3804, d => n2431, outb
=> n696);
U2316 : aoi22 port map( a => n696, b => mult_125_G4_ab_12_4_port, c => n3806
, d => n2462, outb => n3805);
U2317 : oai22 port map( a => n3805, b => n3807, c => n697, d => n2434, outb
=> n700);
U2318 : aoi22 port map( a => n700, b => mult_125_G4_ab_14_4_port, c => n3808
, d => n2437, outb => n703);
U2319 : nand2 port map( a => mult_125_G4_ab_0_4_port, b =>
mult_125_G4_ab_1_3_port, outb => n706);
U2320 : aoi22 port map( a => mult_125_G4_ab_2_3_port, b => n3809, c => n704,
d => n2445, outb => n709);
U2321 : oai22 port map( a => n709, b => n708, c => n3810, d => n2446, outb
=> n711);
U2322 : oai22 port map( a => n3811, b => n3812, c => n710, d => n2468, outb
=> n713);
U2323 : aoi22 port map( a => n713, b => mult_125_G4_ab_5_3_port, c => n3814,
d => n2448, outb => n3813);
U2324 : oai22 port map( a => n3813, b => n3815, c => n714, d => n2471, outb
=> n717);
U2325 : aoi22 port map( a => n717, b => mult_125_G4_ab_7_3_port, c => n3817,
d => n2451, outb => n3816);
U2326 : oai22 port map( a => n3816, b => n3818, c => n718, d => n2474, outb
=> n721);
U2327 : aoi22 port map( a => n721, b => mult_125_G4_ab_9_3_port, c => n3820,
d => n2454, outb => n3819);
U2328 : oai22 port map( a => n3819, b => n3821, c => n722, d => n2477, outb
=> n725);
U2329 : aoi22 port map( a => n725, b => mult_125_G4_ab_11_3_port, c => n3823
, d => n2457, outb => n3822);
U2330 : oai22 port map( a => n3822, b => n3824, c => n726, d => n2480, outb
=> n729);
U2331 : aoi22 port map( a => n729, b => mult_125_G4_ab_13_3_port, c => n3826
, d => n2460, outb => n3825);
U2332 : inv port map( inb => mult_125_G4_ab_14_3_port, outb => n3827);
U2333 : oai22 port map( a => n3825, b => n3827, c => n730, d => n2483, outb
=> n733);
U2334 : nand2 port map( a => mult_125_G4_ab_0_3_port, b =>
mult_125_G4_ab_1_2_port, outb => n736);
U2335 : aoi22 port map( a => mult_125_G4_ab_2_2_port, b => n3829, c => n734,
d => n2463, outb => n3828);
U2336 : oai22 port map( a => n3828, b => n3830, c => n737, d => n2464, outb
=> n740);
U2337 : aoi22 port map( a => n740, b => mult_125_G4_ab_4_2_port, c => n3832,
d => n2491, outb => n3831);
U2338 : oai22 port map( a => n3831, b => n3833, c => n741, d => n2466, outb
=> n744);
U2339 : aoi22 port map( a => n744, b => mult_125_G4_ab_6_2_port, c => n3834,
d => n2494, outb => n747);
U2340 : oai22 port map( a => n747, b => n746, c => n3835, d => n2469, outb
=> n749);
U2341 : aoi22 port map( a => n749, b => mult_125_G4_ab_8_2_port, c => n3837,
d => n2497, outb => n3836);
U2342 : oai22 port map( a => n3836, b => n3838, c => n750, d => n2472, outb
=> n753);
U2343 : aoi22 port map( a => n753, b => mult_125_G4_ab_10_2_port, c => n3840
, d => n2500, outb => n3839);
U2344 : oai22 port map( a => n3839, b => n3841, c => n754, d => n2475, outb
=> n757);
U2345 : aoi22 port map( a => n757, b => mult_125_G4_ab_12_2_port, c => n3843
, d => n2503, outb => n3842);
U2346 : oai22 port map( a => n3842, b => n3844, c => n758, d => n2478, outb
=> n761);
U2347 : aoi22 port map( a => n761, b => mult_125_G4_ab_14_2_port, c => n3846
, d => n2506, outb => n3845);
U2348 : nand2 port map( a => mult_125_G4_ab_0_2_port, b =>
mult_125_G4_ab_1_1_port, outb => n766);
U2349 : aoi22 port map( a => mult_125_G4_ab_2_1_port, b => n3848, c => n764,
d => n2486, outb => n3847);
U2350 : oai22 port map( a => n3847, b => n3849, c => n767, d => n2487, outb
=> n770);
U2351 : inv port map( inb => mult_125_G4_ab_4_1_port, outb => n3850);
U2352 : oai22 port map( a => n3851, b => n3850, c => n769, d => n2512, outb
=> n772);
U2353 : aoi22 port map( a => n772, b => mult_125_G4_ab_5_1_port, c => n3853,
d => n2489, outb => n3852);
U2354 : oai22 port map( a => n3852, b => n3854, c => n773, d => n2515, outb
=> n776);
U2355 : aoi22 port map( a => n776, b => mult_125_G4_ab_7_1_port, c => n3856,
d => n2492, outb => n3855);
U2356 : oai22 port map( a => n3855, b => n3857, c => n777, d => n2518, outb
=> n780);
U2357 : aoi22 port map( a => n780, b => mult_125_G4_ab_9_1_port, c => n3859,
d => n2495, outb => n3858);
U2358 : oai22 port map( a => n3858, b => n3860, c => n781, d => n2521, outb
=> n784);
U2359 : aoi22 port map( a => n784, b => mult_125_G4_ab_11_1_port, c => n3862
, d => n2498, outb => n3861);
U2360 : oai22 port map( a => n3861, b => n3863, c => n785, d => n2524, outb
=> n788);
U2361 : aoi22 port map( a => n788, b => mult_125_G4_ab_13_1_port, c => n3865
, d => n2501, outb => n3864);
U2362 : inv port map( inb => mult_125_G4_ab_14_1_port, outb => n3866);
U2363 : oai22 port map( a => n3864, b => n3866, c => n789, d => n2527, outb
=> n792);
U2364 : nand2 port map( a => mult_125_G4_ab_1_0_port, b =>
mult_125_G4_ab_0_1_port, outb => n3867);
U2365 : aoi22 port map( a => mult_125_G4_ab_2_0_port, b => n794, c => n3869,
d => n2507, outb => n3868);
U2366 : aoi22 port map( a => n796, b => mult_125_G4_ab_3_0_port, c => n3871,
d => n2508, outb => n3870);
U2367 : inv port map( inb => mult_125_G4_ab_4_0_port, outb => n3872);
U2368 : oai22 port map( a => n3870, b => n3872, c => n797, d => n3873, outb
=> n800);
U2369 : aoi22 port map( a => n800, b => mult_125_G4_ab_5_0_port, c => n3875,
d => n2510, outb => n3874);
U2370 : inv port map( inb => mult_125_G4_ab_6_0_port, outb => n3876);
U2371 : oai22 port map( a => n3874, b => n3876, c => n801, d => n3877, outb
=> n804);
U2372 : aoi22 port map( a => n804, b => mult_125_G4_ab_7_0_port, c => n3879,
d => n2513, outb => n3878);
U2373 : inv port map( inb => mult_125_G4_ab_8_0_port, outb => n3880);
U2374 : oai22 port map( a => n3878, b => n3880, c => n805, d => n3881, outb
=> n808);
U2375 : aoi22 port map( a => n808, b => mult_125_G4_ab_9_0_port, c => n3883,
d => n2516, outb => n3882);
U2376 : inv port map( inb => mult_125_G4_ab_10_0_port, outb => n3884);
U2377 : oai22 port map( a => n3882, b => n3884, c => n809, d => n3885, outb
=> n812);
U2378 : aoi22 port map( a => n812, b => mult_125_G4_ab_11_0_port, c => n3887
, d => n2519, outb => n3886);
U2379 : inv port map( inb => mult_125_G4_ab_12_0_port, outb => n3888);
U2380 : oai22 port map( a => n3886, b => n3888, c => n813, d => n3889, outb
=> n816);
U2381 : aoi22 port map( a => n816, b => mult_125_G4_ab_13_0_port, c => n3891
, d => n2522, outb => n3890);
U2382 : inv port map( inb => mult_125_G4_ab_14_0_port, outb => n3892);
U2383 : oai22 port map( a => n3890, b => n3892, c => n817, d => n3893, outb
=> n820);
U2384 : inv port map( inb => mult_125_G4_ZB, outb => n272);
U2385 : inv port map( inb => mult_125_G4_ZA, outb => n273);
U2386 : nand2 port map( a => mult_125_G3_ab_0_15_port, b =>
mult_125_G3_ab_1_14_port, outb => n3894);
U2387 : inv port map( inb => mult_125_G3_ab_3_15_port, outb => n3895);
U2388 : inv port map( inb => mult_125_G3_ab_4_14_port, outb => n3896);
U2389 : inv port map( inb => mult_125_G3_ab_5_15_port, outb => n3897);
U2390 : inv port map( inb => mult_125_G3_ab_6_14_port, outb => n3898);
U2391 : inv port map( inb => mult_125_G3_ab_7_15_port, outb => n3899);
U2392 : inv port map( inb => mult_125_G3_ab_8_14_port, outb => n3900);
U2393 : inv port map( inb => mult_125_G3_ab_9_15_port, outb => n3901);
U2394 : inv port map( inb => mult_125_G3_ab_10_14_port, outb => n3902);
U2395 : inv port map( inb => mult_125_G3_ab_11_15_port, outb => n3903);
U2396 : inv port map( inb => mult_125_G3_ab_12_14_port, outb => n3904);
U2397 : nand2 port map( a => mult_125_G3_ab_0_14_port, b =>
mult_125_G3_ab_1_13_port, outb => n838);
U2398 : aoi22 port map( a => mult_125_G3_ab_2_13_port, b => n3905, c => n836
, d => n2537, outb => n841);
U2399 : oai22 port map( a => n841, b => n840, c => n3906, d => n2538, outb
=> n843);
U2400 : aoi22 port map( a => n843, b => mult_125_G3_ab_4_13_port, c => n3908
, d => n2545, outb => n3907);
U2401 : oai22 port map( a => n3907, b => n3909, c => n844, d => n2548, outb
=> n847);
U2402 : aoi22 port map( a => n847, b => mult_125_G3_ab_6_13_port, c => n3911
, d => n2551, outb => n3910);
U2403 : inv port map( inb => mult_125_G3_ab_7_13_port, outb => n3912);
U2404 : oai22 port map( a => n3910, b => n3912, c => n848, d => n2554, outb
=> n851);
U2405 : aoi22 port map( a => n851, b => mult_125_G3_ab_8_13_port, c => n3914
, d => n2557, outb => n3913);
U2406 : inv port map( inb => mult_125_G3_ab_9_13_port, outb => n3915);
U2407 : oai22 port map( a => n3913, b => n3915, c => n852, d => n2560, outb
=> n855);
U2408 : aoi22 port map( a => n855, b => mult_125_G3_ab_10_13_port, c =>
n3917, d => n2563, outb => n3916);
U2409 : inv port map( inb => mult_125_G3_ab_11_13_port, outb => n3918);
U2410 : oai22 port map( a => n3916, b => n3918, c => n856, d => n2566, outb
=> n859);
U2411 : aoi22 port map( a => n859, b => mult_125_G3_ab_12_13_port, c =>
n3920, d => n2569, outb => n3919);
U2412 : inv port map( inb => mult_125_G3_ab_13_13_port, outb => n3921);
U2413 : oai22 port map( a => n3919, b => n3921, c => n860, d => n2572, outb
=> n863);
U2414 : aoi22 port map( a => n863, b => mult_125_G3_ab_14_13_port, c =>
n3923, d => n2575, outb => n3922);
U2415 : nand2 port map( a => mult_125_G3_ab_0_13_port, b =>
mult_125_G3_ab_1_12_port, outb => n868);
U2416 : aoi22 port map( a => mult_125_G3_ab_2_12_port, b => n3925, c => n866
, d => n2540, outb => n3924);
U2417 : oai22 port map( a => n3924, b => n3926, c => n869, d => n2541, outb
=> n872);
U2418 : aoi22 port map( a => n872, b => mult_125_G3_ab_4_12_port, c => n3928
, d => n2583, outb => n3927);
U2419 : aoi22 port map( a => n874, b => mult_125_G3_ab_5_12_port, c => n3930
, d => n2543, outb => n3929);
U2420 : inv port map( inb => mult_125_G3_ab_6_12_port, outb => n3931);
U2421 : oai22 port map( a => n3929, b => n3931, c => n875, d => n2546, outb
=> n878);
U2422 : aoi22 port map( a => n878, b => mult_125_G3_ab_7_12_port, c => n3933
, d => n2549, outb => n3932);
U2423 : inv port map( inb => mult_125_G3_ab_8_12_port, outb => n3934);
U2424 : oai22 port map( a => n3932, b => n3934, c => n879, d => n2552, outb
=> n882);
U2425 : aoi22 port map( a => n882, b => mult_125_G3_ab_9_12_port, c => n3936
, d => n2555, outb => n3935);
U2426 : inv port map( inb => mult_125_G3_ab_10_12_port, outb => n3937);
U2427 : oai22 port map( a => n3935, b => n3937, c => n883, d => n2558, outb
=> n886);
U2428 : aoi22 port map( a => n886, b => mult_125_G3_ab_11_12_port, c =>
n3939, d => n2561, outb => n3938);
U2429 : inv port map( inb => mult_125_G3_ab_12_12_port, outb => n3940);
U2430 : oai22 port map( a => n3938, b => n3940, c => n887, d => n2564, outb
=> n890);
U2431 : aoi22 port map( a => n890, b => mult_125_G3_ab_13_12_port, c =>
n3942, d => n2567, outb => n3941);
U2432 : inv port map( inb => mult_125_G3_ab_14_12_port, outb => n3943);
U2433 : oai22 port map( a => n3941, b => n3943, c => n891, d => n2570, outb
=> n894);
U2434 : nand2 port map( a => mult_125_G3_ab_0_12_port, b =>
mult_125_G3_ab_1_11_port, outb => n897);
U2435 : aoi22 port map( a => mult_125_G3_ab_2_11_port, b => n3944, c => n895
, d => n2578, outb => n900);
U2436 : oai22 port map( a => n900, b => n899, c => n3945, d => n2579, outb
=> n902);
U2437 : oai22 port map( a => n3946, b => n3947, c => n901, d => n2589, outb
=> n904);
U2438 : aoi22 port map( a => n904, b => mult_125_G3_ab_5_11_port, c => n3949
, d => n2581, outb => n3948);
U2439 : oai22 port map( a => n3948, b => n3950, c => n905, d => n2592, outb
=> n908);
U2440 : oai22 port map( a => n3951, b => n3952, c => n907, d => n2595, outb
=> n910);
U2441 : aoi22 port map( a => n910, b => mult_125_G3_ab_8_11_port, c => n3954
, d => n2598, outb => n3953);
U2442 : inv port map( inb => mult_125_G3_ab_9_11_port, outb => n3955);
U2443 : oai22 port map( a => n3953, b => n3955, c => n911, d => n2601, outb
=> n914);
U2444 : aoi22 port map( a => n914, b => mult_125_G3_ab_10_11_port, c =>
n3957, d => n2604, outb => n3956);
U2445 : inv port map( inb => mult_125_G3_ab_11_11_port, outb => n3958);
U2446 : oai22 port map( a => n3956, b => n3958, c => n915, d => n2607, outb
=> n918);
U2447 : aoi22 port map( a => n918, b => mult_125_G3_ab_12_11_port, c =>
n3960, d => n2610, outb => n3959);
U2448 : inv port map( inb => mult_125_G3_ab_13_11_port, outb => n3961);
U2449 : oai22 port map( a => n3959, b => n3961, c => n919, d => n2613, outb
=> n922);
U2450 : aoi22 port map( a => n922, b => mult_125_G3_ab_14_11_port, c =>
n3962, d => n2616, outb => n925);
U2451 : nand2 port map( a => mult_125_G3_ab_0_11_port, b =>
mult_125_G3_ab_1_10_port, outb => n928);
U2452 : aoi22 port map( a => mult_125_G3_ab_2_10_port, b => n3964, c => n926
, d => n2584, outb => n3963);
U2453 : oai22 port map( a => n3963, b => n3965, c => n929, d => n2585, outb
=> n932);
U2454 : aoi22 port map( a => n932, b => mult_125_G3_ab_4_10_port, c => n3966
, d => n2624, outb => n935);
U2455 : oai22 port map( a => n935, b => n934, c => n3967, d => n2587, outb
=> n937);
U2456 : aoi22 port map( a => n937, b => mult_125_G3_ab_6_10_port, c => n3969
, d => n2627, outb => n3968);
U2457 : oai22 port map( a => n3968, b => n3970, c => n938, d => n2590, outb
=> n941);
U2458 : inv port map( inb => mult_125_G3_ab_8_10_port, outb => n3971);
U2459 : oai22 port map( a => n3972, b => n3971, c => n940, d => n2593, outb
=> n943);
U2460 : aoi22 port map( a => n943, b => mult_125_G3_ab_9_10_port, c => n3974
, d => n2596, outb => n3973);
U2461 : inv port map( inb => mult_125_G3_ab_10_10_port, outb => n3975);
U2462 : oai22 port map( a => n3973, b => n3975, c => n944, d => n2599, outb
=> n947);
U2463 : aoi22 port map( a => n947, b => mult_125_G3_ab_11_10_port, c =>
n3977, d => n2602, outb => n3976);
U2464 : inv port map( inb => mult_125_G3_ab_12_10_port, outb => n3978);
U2465 : oai22 port map( a => n3976, b => n3978, c => n948, d => n2605, outb
=> n951);
U2466 : aoi22 port map( a => n951, b => mult_125_G3_ab_13_10_port, c =>
n3980, d => n2608, outb => n3979);
U2467 : inv port map( inb => mult_125_G3_ab_14_10_port, outb => n3981);
U2468 : oai22 port map( a => n3979, b => n3981, c => n952, d => n2611, outb
=> n955);
U2469 : nand2 port map( a => mult_125_G3_ab_0_10_port, b =>
mult_125_G3_ab_1_9_port, outb => n958);
U2470 : aoi22 port map( a => mult_125_G3_ab_2_9_port, b => n3983, c => n956,
d => n2619, outb => n3982);
U2471 : oai22 port map( a => n3982, b => n3984, c => n959, d => n2620, outb
=> n962);
U2472 : oai22 port map( a => n3985, b => n3986, c => n961, d => n2633, outb
=> n964);
U2473 : aoi22 port map( a => n964, b => mult_125_G3_ab_5_9_port, c => n3988,
d => n2622, outb => n3987);
U2474 : oai22 port map( a => n3987, b => n3989, c => n965, d => n2636, outb
=> n968);
U2475 : aoi22 port map( a => n968, b => mult_125_G3_ab_7_9_port, c => n3991,
d => n2625, outb => n3990);
U2476 : oai22 port map( a => n3990, b => n3992, c => n969, d => n2639, outb
=> n972);
U2477 : oai22 port map( a => n3993, b => n3994, c => n971, d => n2642, outb
=> n974);
U2478 : aoi22 port map( a => n974, b => mult_125_G3_ab_10_9_port, c => n3996
, d => n2645, outb => n3995);
U2479 : inv port map( inb => mult_125_G3_ab_11_9_port, outb => n3997);
U2480 : oai22 port map( a => n3995, b => n3997, c => n975, d => n2648, outb
=> n978);
U2481 : aoi22 port map( a => n978, b => mult_125_G3_ab_12_9_port, c => n3999
, d => n2651, outb => n3998);
U2482 : inv port map( inb => mult_125_G3_ab_13_9_port, outb => n4000);
U2483 : oai22 port map( a => n3998, b => n4000, c => n979, d => n2654, outb
=> n982);
U2484 : aoi22 port map( a => n982, b => mult_125_G3_ab_14_9_port, c => n4001
, d => n2657, outb => n985);
U2485 : nand2 port map( a => mult_125_G3_ab_0_9_port, b =>
mult_125_G3_ab_1_8_port, outb => n988);
U2486 : aoi22 port map( a => mult_125_G3_ab_2_8_port, b => n4003, c => n986,
d => n2628, outb => n4002);
U2487 : oai22 port map( a => n4002, b => n4004, c => n989, d => n2629, outb
=> n992);
U2488 : oai22 port map( a => n4005, b => n4006, c => n991, d => n2665, outb
=> n994);
U2489 : oai22 port map( a => n4007, b => n4008, c => n993, d => n2631, outb
=> n996);
U2490 : aoi22 port map( a => n996, b => mult_125_G3_ab_6_8_port, c => n4010,
d => n2668, outb => n4009);
U2491 : oai22 port map( a => n4009, b => n4011, c => n997, d => n2634, outb
=> n1000);
U2492 : aoi22 port map( a => n1000, b => mult_125_G3_ab_8_8_port, c => n4013
, d => n2671, outb => n4012);
U2493 : oai22 port map( a => n4012, b => n4014, c => n1001, d => n2637, outb
=> n1004);
U2494 : inv port map( inb => mult_125_G3_ab_10_8_port, outb => n4015);
U2495 : oai22 port map( a => n4016, b => n4015, c => n1003, d => n2640, outb
=> n1006);
U2496 : aoi22 port map( a => n1006, b => mult_125_G3_ab_11_8_port, c =>
n4018, d => n2643, outb => n4017);
U2497 : inv port map( inb => mult_125_G3_ab_12_8_port, outb => n4019);
U2498 : oai22 port map( a => n4017, b => n4019, c => n1007, d => n2646, outb
=> n1010);
U2499 : aoi22 port map( a => n1010, b => mult_125_G3_ab_13_8_port, c =>
n4021, d => n2649, outb => n4020);
U2500 : inv port map( inb => mult_125_G3_ab_14_8_port, outb => n4022);
U2501 : oai22 port map( a => n4020, b => n4022, c => n1011, d => n2652, outb
=> n1014);
U2502 : nand2 port map( a => mult_125_G3_ab_0_8_port, b =>
mult_125_G3_ab_1_7_port, outb => n1017);
U2503 : aoi22 port map( a => mult_125_G3_ab_2_7_port, b => n4023, c => n1015
, d => n2660, outb => n1020);
U2504 : oai22 port map( a => n1020, b => n1019, c => n4024, d => n2661, outb
=> n1022);
U2505 : oai22 port map( a => n4025, b => n4026, c => n1021, d => n2677, outb
=> n1024);
U2506 : aoi22 port map( a => n1024, b => mult_125_G3_ab_5_7_port, c => n4028
, d => n2663, outb => n4027);
U2507 : oai22 port map( a => n4027, b => n4029, c => n1025, d => n2680, outb
=> n1028);
U2508 : aoi22 port map( a => n1028, b => mult_125_G3_ab_7_7_port, c => n4031
, d => n2666, outb => n4030);
U2509 : oai22 port map( a => n4030, b => n4032, c => n1029, d => n2683, outb
=> n1032);
U2510 : aoi22 port map( a => n1032, b => mult_125_G3_ab_9_7_port, c => n4034
, d => n2669, outb => n4033);
U2511 : oai22 port map( a => n4033, b => n4035, c => n1033, d => n2686, outb
=> n1036);
U2512 : oai22 port map( a => n4036, b => n4037, c => n1035, d => n2689, outb
=> n1038);
U2513 : aoi22 port map( a => n1038, b => mult_125_G3_ab_12_7_port, c =>
n4039, d => n2692, outb => n4038);
U2514 : inv port map( inb => mult_125_G3_ab_13_7_port, outb => n4040);
U2515 : oai22 port map( a => n4038, b => n4040, c => n1039, d => n2695, outb
=> n1042);
U2516 : aoi22 port map( a => n1042, b => mult_125_G3_ab_14_7_port, c =>
n4041, d => n2698, outb => n1045);
U2517 : nand2 port map( a => mult_125_G3_ab_0_7_port, b =>
mult_125_G3_ab_1_6_port, outb => n1048);
U2518 : aoi22 port map( a => mult_125_G3_ab_2_6_port, b => n4043, c => n1046
, d => n2672, outb => n4042);
U2519 : oai22 port map( a => n4042, b => n4044, c => n1049, d => n2673, outb
=> n1052);
U2520 : aoi22 port map( a => n1052, b => mult_125_G3_ab_4_6_port, c => n4045
, d => n2706, outb => n1055);
U2521 : oai22 port map( a => n1055, b => n1054, c => n4046, d => n2675, outb
=> n1057);
U2522 : aoi22 port map( a => n1057, b => mult_125_G3_ab_6_6_port, c => n4048
, d => n2709, outb => n4047);
U2523 : oai22 port map( a => n4047, b => n4049, c => n1058, d => n2678, outb
=> n1061);
U2524 : aoi22 port map( a => n1061, b => mult_125_G3_ab_8_6_port, c => n4050
, d => n2712, outb => n1064);
U2525 : oai22 port map( a => n1064, b => n1063, c => n4051, d => n2681, outb
=> n1066);
U2526 : aoi22 port map( a => n1066, b => mult_125_G3_ab_10_6_port, c =>
n4053, d => n2715, outb => n4052);
U2527 : oai22 port map( a => n4052, b => n4054, c => n1067, d => n2684, outb
=> n1070);
U2528 : inv port map( inb => mult_125_G3_ab_12_6_port, outb => n4055);
U2529 : oai22 port map( a => n4056, b => n4055, c => n1069, d => n2687, outb
=> n1072);
U2530 : aoi22 port map( a => n1072, b => mult_125_G3_ab_13_6_port, c =>
n4058, d => n2690, outb => n4057);
U2531 : inv port map( inb => mult_125_G3_ab_14_6_port, outb => n4059);
U2532 : oai22 port map( a => n4057, b => n4059, c => n1073, d => n2693, outb
=> n1076);
U2533 : nand2 port map( a => mult_125_G3_ab_0_6_port, b =>
mult_125_G3_ab_1_5_port, outb => n1079);
U2534 : aoi22 port map( a => mult_125_G3_ab_2_5_port, b => n4060, c => n1077
, d => n2701, outb => n1082);
U2535 : oai22 port map( a => n1082, b => n1081, c => n4061, d => n2702, outb
=> n1084);
U2536 : oai22 port map( a => n4062, b => n4063, c => n1083, d => n2721, outb
=> n1086);
U2537 : aoi22 port map( a => n1086, b => mult_125_G3_ab_5_5_port, c => n4064
, d => n2704, outb => n1089);
U2538 : oai22 port map( a => n1089, b => n1088, c => n4065, d => n2724, outb
=> n1091);
U2539 : aoi22 port map( a => n1091, b => mult_125_G3_ab_7_5_port, c => n4067
, d => n2707, outb => n4066);
U2540 : oai22 port map( a => n4066, b => n4068, c => n1092, d => n2727, outb
=> n1095);
U2541 : aoi22 port map( a => n1095, b => mult_125_G3_ab_9_5_port, c => n4070
, d => n2710, outb => n4069);
U2542 : oai22 port map( a => n4069, b => n4071, c => n1096, d => n2730, outb
=> n1099);
U2543 : aoi22 port map( a => n1099, b => mult_125_G3_ab_11_5_port, c =>
n4073, d => n2713, outb => n4072);
U2544 : oai22 port map( a => n4072, b => n4074, c => n1100, d => n2733, outb
=> n1103);
U2545 : oai22 port map( a => n4075, b => n4076, c => n1102, d => n2736, outb
=> n1105);
U2546 : aoi22 port map( a => n1105, b => mult_125_G3_ab_14_5_port, c =>
n4077, d => n2739, outb => n1108);
U2547 : nand2 port map( a => mult_125_G3_ab_0_5_port, b =>
mult_125_G3_ab_1_4_port, outb => n1111);
U2548 : aoi22 port map( a => mult_125_G3_ab_2_4_port, b => n4079, c => n1109
, d => n2716, outb => n4078);
U2549 : oai22 port map( a => n4078, b => n4080, c => n1112, d => n2717, outb
=> n1115);
U2550 : aoi22 port map( a => n1115, b => mult_125_G3_ab_4_4_port, c => n4081
, d => n2747, outb => n1118);
U2551 : oai22 port map( a => n1118, b => n1117, c => n4082, d => n2719, outb
=> n1120);
U2552 : aoi22 port map( a => n1120, b => mult_125_G3_ab_6_4_port, c => n4083
, d => n2750, outb => n1123);
U2553 : oai22 port map( a => n1123, b => n1122, c => n4084, d => n2722, outb
=> n1125);
U2554 : aoi22 port map( a => n1125, b => mult_125_G3_ab_8_4_port, c => n4086
, d => n2753, outb => n4085);
U2555 : oai22 port map( a => n4085, b => n4087, c => n1126, d => n2725, outb
=> n1129);
U2556 : aoi22 port map( a => n1129, b => mult_125_G3_ab_10_4_port, c =>
n4088, d => n2756, outb => n1132);
U2557 : oai22 port map( a => n1132, b => n1131, c => n4089, d => n2728, outb
=> n1134);
U2558 : aoi22 port map( a => n1134, b => mult_125_G3_ab_12_4_port, c =>
n4091, d => n2759, outb => n4090);
U2559 : oai22 port map( a => n4090, b => n4092, c => n1135, d => n2731, outb
=> n1138);
U2560 : aoi22 port map( a => n1138, b => mult_125_G3_ab_14_4_port, c =>
n4093, d => n2734, outb => n1141);
U2561 : nand2 port map( a => mult_125_G3_ab_0_4_port, b =>
mult_125_G3_ab_1_3_port, outb => n1144);
U2562 : aoi22 port map( a => mult_125_G3_ab_2_3_port, b => n4094, c => n1142
, d => n2742, outb => n1147);
U2563 : oai22 port map( a => n1147, b => n1146, c => n4095, d => n2743, outb
=> n1149);
U2564 : oai22 port map( a => n4096, b => n4097, c => n1148, d => n2765, outb
=> n1151);
U2565 : aoi22 port map( a => n1151, b => mult_125_G3_ab_5_3_port, c => n4099
, d => n2745, outb => n4098);
U2566 : oai22 port map( a => n4098, b => n4100, c => n1152, d => n2768, outb
=> n1155);
U2567 : aoi22 port map( a => n1155, b => mult_125_G3_ab_7_3_port, c => n4102
, d => n2748, outb => n4101);
U2568 : oai22 port map( a => n4101, b => n4103, c => n1156, d => n2771, outb
=> n1159);
U2569 : aoi22 port map( a => n1159, b => mult_125_G3_ab_9_3_port, c => n4105
, d => n2751, outb => n4104);
U2570 : oai22 port map( a => n4104, b => n4106, c => n1160, d => n2774, outb
=> n1163);
U2571 : aoi22 port map( a => n1163, b => mult_125_G3_ab_11_3_port, c =>
n4108, d => n2754, outb => n4107);
U2572 : oai22 port map( a => n4107, b => n4109, c => n1164, d => n2777, outb
=> n1167);
U2573 : aoi22 port map( a => n1167, b => mult_125_G3_ab_13_3_port, c =>
n4111, d => n2757, outb => n4110);
U2574 : inv port map( inb => mult_125_G3_ab_14_3_port, outb => n4112);
U2575 : oai22 port map( a => n4110, b => n4112, c => n1168, d => n2780, outb
=> n1171);
U2576 : nand2 port map( a => mult_125_G3_ab_0_3_port, b =>
mult_125_G3_ab_1_2_port, outb => n1174);
U2577 : aoi22 port map( a => mult_125_G3_ab_2_2_port, b => n4114, c => n1172
, d => n2760, outb => n4113);
U2578 : oai22 port map( a => n4113, b => n4115, c => n1175, d => n2761, outb
=> n1178);
U2579 : aoi22 port map( a => n1178, b => mult_125_G3_ab_4_2_port, c => n4117
, d => n2788, outb => n4116);
U2580 : oai22 port map( a => n4116, b => n4118, c => n1179, d => n2763, outb
=> n1182);
U2581 : aoi22 port map( a => n1182, b => mult_125_G3_ab_6_2_port, c => n4119
, d => n2791, outb => n1185);
U2582 : oai22 port map( a => n1185, b => n1184, c => n4120, d => n2766, outb
=> n1187);
U2583 : aoi22 port map( a => n1187, b => mult_125_G3_ab_8_2_port, c => n4122
, d => n2794, outb => n4121);
U2584 : oai22 port map( a => n4121, b => n4123, c => n1188, d => n2769, outb
=> n1191);
U2585 : aoi22 port map( a => n1191, b => mult_125_G3_ab_10_2_port, c =>
n4125, d => n2797, outb => n4124);
U2586 : oai22 port map( a => n4124, b => n4126, c => n1192, d => n2772, outb
=> n1195);
U2587 : aoi22 port map( a => n1195, b => mult_125_G3_ab_12_2_port, c =>
n4128, d => n2800, outb => n4127);
U2588 : oai22 port map( a => n4127, b => n4129, c => n1196, d => n2775, outb
=> n1199);
U2589 : aoi22 port map( a => n1199, b => mult_125_G3_ab_14_2_port, c =>
n4131, d => n2803, outb => n4130);
U2590 : nand2 port map( a => mult_125_G3_ab_0_2_port, b =>
mult_125_G3_ab_1_1_port, outb => n1204);
U2591 : aoi22 port map( a => mult_125_G3_ab_2_1_port, b => n4133, c => n1202
, d => n2783, outb => n4132);
U2592 : oai22 port map( a => n4132, b => n4134, c => n1205, d => n2784, outb
=> n1208);
U2593 : inv port map( inb => mult_125_G3_ab_4_1_port, outb => n4135);
U2594 : oai22 port map( a => n4136, b => n4135, c => n1207, d => n2809, outb
=> n1210);
U2595 : aoi22 port map( a => n1210, b => mult_125_G3_ab_5_1_port, c => n4138
, d => n2786, outb => n4137);
U2596 : oai22 port map( a => n4137, b => n4139, c => n1211, d => n2812, outb
=> n1214);
U2597 : aoi22 port map( a => n1214, b => mult_125_G3_ab_7_1_port, c => n4141
, d => n2789, outb => n4140);
U2598 : oai22 port map( a => n4140, b => n4142, c => n1215, d => n2815, outb
=> n1218);
U2599 : aoi22 port map( a => n1218, b => mult_125_G3_ab_9_1_port, c => n4144
, d => n2792, outb => n4143);
U2600 : oai22 port map( a => n4143, b => n4145, c => n1219, d => n2818, outb
=> n1222);
U2601 : aoi22 port map( a => n1222, b => mult_125_G3_ab_11_1_port, c =>
n4147, d => n2795, outb => n4146);
U2602 : oai22 port map( a => n4146, b => n4148, c => n1223, d => n2821, outb
=> n1226);
U2603 : aoi22 port map( a => n1226, b => mult_125_G3_ab_13_1_port, c =>
n4150, d => n2798, outb => n4149);
U2604 : inv port map( inb => mult_125_G3_ab_14_1_port, outb => n4151);
U2605 : oai22 port map( a => n4149, b => n4151, c => n1227, d => n2824, outb
=> n1230);
U2606 : nand2 port map( a => mult_125_G3_ab_0_1_port, b =>
mult_125_G3_ab_1_0_port, outb => n4152);
U2607 : aoi22 port map( a => mult_125_G3_ab_2_0_port, b => n1232, c => n4154
, d => n2804, outb => n4153);
U2608 : aoi22 port map( a => n1234, b => mult_125_G3_ab_3_0_port, c => n4156
, d => n2805, outb => n4155);
U2609 : inv port map( inb => mult_125_G3_ab_4_0_port, outb => n4157);
U2610 : oai22 port map( a => n4155, b => n4157, c => n1235, d => n4158, outb
=> n1238);
U2611 : aoi22 port map( a => n1238, b => mult_125_G3_ab_5_0_port, c => n4160
, d => n2807, outb => n4159);
U2612 : inv port map( inb => mult_125_G3_ab_6_0_port, outb => n4161);
U2613 : oai22 port map( a => n4159, b => n4161, c => n1239, d => n4162, outb
=> n1242);
U2614 : aoi22 port map( a => n1242, b => mult_125_G3_ab_7_0_port, c => n4164
, d => n2810, outb => n4163);
U2615 : inv port map( inb => mult_125_G3_ab_8_0_port, outb => n4165);
U2616 : oai22 port map( a => n4163, b => n4165, c => n1243, d => n4166, outb
=> n1246);
U2617 : aoi22 port map( a => n1246, b => mult_125_G3_ab_9_0_port, c => n4168
, d => n2813, outb => n4167);
U2618 : inv port map( inb => mult_125_G3_ab_10_0_port, outb => n4169);
U2619 : oai22 port map( a => n4167, b => n4169, c => n1247, d => n4170, outb
=> n1250);
U2620 : aoi22 port map( a => n1250, b => mult_125_G3_ab_11_0_port, c =>
n4172, d => n2816, outb => n4171);
U2621 : inv port map( inb => mult_125_G3_ab_12_0_port, outb => n4173);
U2622 : oai22 port map( a => n4171, b => n4173, c => n1251, d => n4174, outb
=> n1254);
U2623 : aoi22 port map( a => n1254, b => mult_125_G3_ab_13_0_port, c =>
n4176, d => n2819, outb => n4175);
U2624 : inv port map( inb => mult_125_G3_ab_14_0_port, outb => n4177);
U2625 : oai22 port map( a => n4175, b => n4177, c => n1255, d => n4178, outb
=> n1258);
U2626 : inv port map( inb => mult_125_G3_ZB, outb => n380);
U2627 : inv port map( inb => mult_125_G3_ZA, outb => n381);
U2628 : nand2 port map( a => mult_125_G2_ab_0_15_port, b =>
mult_125_G2_ab_1_14_port, outb => n4179);
U2629 : inv port map( inb => mult_125_G2_ab_3_15_port, outb => n4180);
U2630 : inv port map( inb => mult_125_G2_ab_4_14_port, outb => n4181);
U2631 : inv port map( inb => mult_125_G2_ab_5_15_port, outb => n4182);
U2632 : inv port map( inb => mult_125_G2_ab_6_14_port, outb => n4183);
U2633 : inv port map( inb => mult_125_G2_ab_7_15_port, outb => n4184);
U2634 : inv port map( inb => mult_125_G2_ab_8_14_port, outb => n4185);
U2635 : inv port map( inb => mult_125_G2_ab_9_15_port, outb => n4186);
U2636 : inv port map( inb => mult_125_G2_ab_10_14_port, outb => n4187);
U2637 : inv port map( inb => mult_125_G2_ab_11_15_port, outb => n4188);
U2638 : inv port map( inb => mult_125_G2_ab_12_14_port, outb => n4189);
U2639 : nand2 port map( a => mult_125_G2_ab_0_14_port, b =>
mult_125_G2_ab_1_13_port, outb => n1276);
U2640 : aoi22 port map( a => mult_125_G2_ab_2_13_port, b => n4190, c =>
n1274, d => n2834, outb => n1279);
U2641 : oai22 port map( a => n1279, b => n1278, c => n4191, d => n2835, outb
=> n1281);
U2642 : aoi22 port map( a => n1281, b => mult_125_G2_ab_4_13_port, c =>
n4193, d => n2842, outb => n4192);
U2643 : oai22 port map( a => n4192, b => n4194, c => n1282, d => n2845, outb
=> n1285);
U2644 : aoi22 port map( a => n1285, b => mult_125_G2_ab_6_13_port, c =>
n4196, d => n2848, outb => n4195);
U2645 : inv port map( inb => mult_125_G2_ab_7_13_port, outb => n4197);
U2646 : oai22 port map( a => n4195, b => n4197, c => n1286, d => n2851, outb
=> n1289);
U2647 : aoi22 port map( a => n1289, b => mult_125_G2_ab_8_13_port, c =>
n4199, d => n2854, outb => n4198);
U2648 : inv port map( inb => mult_125_G2_ab_9_13_port, outb => n4200);
U2649 : oai22 port map( a => n4198, b => n4200, c => n1290, d => n2857, outb
=> n1293);
U2650 : aoi22 port map( a => n1293, b => mult_125_G2_ab_10_13_port, c =>
n4202, d => n2860, outb => n4201);
U2651 : inv port map( inb => mult_125_G2_ab_11_13_port, outb => n4203);
U2652 : oai22 port map( a => n4201, b => n4203, c => n1294, d => n2863, outb
=> n1297);
U2653 : aoi22 port map( a => n1297, b => mult_125_G2_ab_12_13_port, c =>
n4205, d => n2866, outb => n4204);
U2654 : inv port map( inb => mult_125_G2_ab_13_13_port, outb => n4206);
U2655 : oai22 port map( a => n4204, b => n4206, c => n1298, d => n2869, outb
=> n1301);
U2656 : aoi22 port map( a => n1301, b => mult_125_G2_ab_14_13_port, c =>
n4208, d => n2872, outb => n4207);
U2657 : nand2 port map( a => mult_125_G2_ab_0_13_port, b =>
mult_125_G2_ab_1_12_port, outb => n1306);
U2658 : aoi22 port map( a => mult_125_G2_ab_2_12_port, b => n4210, c =>
n1304, d => n2837, outb => n4209);
U2659 : oai22 port map( a => n4209, b => n4211, c => n1307, d => n2838, outb
=> n1310);
U2660 : aoi22 port map( a => n1310, b => mult_125_G2_ab_4_12_port, c =>
n4213, d => n2880, outb => n4212);
U2661 : aoi22 port map( a => n1312, b => mult_125_G2_ab_5_12_port, c =>
n4215, d => n2840, outb => n4214);
U2662 : inv port map( inb => mult_125_G2_ab_6_12_port, outb => n4216);
U2663 : oai22 port map( a => n4214, b => n4216, c => n1313, d => n2843, outb
=> n1316);
U2664 : aoi22 port map( a => n1316, b => mult_125_G2_ab_7_12_port, c =>
n4218, d => n2846, outb => n4217);
U2665 : inv port map( inb => mult_125_G2_ab_8_12_port, outb => n4219);
U2666 : oai22 port map( a => n4217, b => n4219, c => n1317, d => n2849, outb
=> n1320);
U2667 : aoi22 port map( a => n1320, b => mult_125_G2_ab_9_12_port, c =>
n4221, d => n2852, outb => n4220);
U2668 : inv port map( inb => mult_125_G2_ab_10_12_port, outb => n4222);
U2669 : oai22 port map( a => n4220, b => n4222, c => n1321, d => n2855, outb
=> n1324);
U2670 : aoi22 port map( a => n1324, b => mult_125_G2_ab_11_12_port, c =>
n4224, d => n2858, outb => n4223);
U2671 : inv port map( inb => mult_125_G2_ab_12_12_port, outb => n4225);
U2672 : oai22 port map( a => n4223, b => n4225, c => n1325, d => n2861, outb
=> n1328);
U2673 : aoi22 port map( a => n1328, b => mult_125_G2_ab_13_12_port, c =>
n4227, d => n2864, outb => n4226);
U2674 : inv port map( inb => mult_125_G2_ab_14_12_port, outb => n4228);
U2675 : oai22 port map( a => n4226, b => n4228, c => n1329, d => n2867, outb
=> n1332);
U2676 : nand2 port map( a => mult_125_G2_ab_0_12_port, b =>
mult_125_G2_ab_1_11_port, outb => n1335);
U2677 : aoi22 port map( a => mult_125_G2_ab_2_11_port, b => n4229, c =>
n1333, d => n2875, outb => n1338);
U2678 : oai22 port map( a => n1338, b => n1337, c => n4230, d => n2876, outb
=> n1340);
U2679 : oai22 port map( a => n4231, b => n4232, c => n1339, d => n2886, outb
=> n1342);
U2680 : aoi22 port map( a => n1342, b => mult_125_G2_ab_5_11_port, c =>
n4234, d => n2878, outb => n4233);
U2681 : oai22 port map( a => n4233, b => n4235, c => n1343, d => n2889, outb
=> n1346);
U2682 : oai22 port map( a => n4236, b => n4237, c => n1345, d => n2892, outb
=> n1348);
U2683 : aoi22 port map( a => n1348, b => mult_125_G2_ab_8_11_port, c =>
n4239, d => n2895, outb => n4238);
U2684 : inv port map( inb => mult_125_G2_ab_9_11_port, outb => n4240);
U2685 : oai22 port map( a => n4238, b => n4240, c => n1349, d => n2898, outb
=> n1352);
U2686 : aoi22 port map( a => n1352, b => mult_125_G2_ab_10_11_port, c =>
n4242, d => n2901, outb => n4241);
U2687 : inv port map( inb => mult_125_G2_ab_11_11_port, outb => n4243);
U2688 : oai22 port map( a => n4241, b => n4243, c => n1353, d => n2904, outb
=> n1356);
U2689 : aoi22 port map( a => n1356, b => mult_125_G2_ab_12_11_port, c =>
n4245, d => n2907, outb => n4244);
U2690 : inv port map( inb => mult_125_G2_ab_13_11_port, outb => n4246);
U2691 : oai22 port map( a => n4244, b => n4246, c => n1357, d => n2910, outb
=> n1360);
U2692 : aoi22 port map( a => n1360, b => mult_125_G2_ab_14_11_port, c =>
n4247, d => n2913, outb => n1363);
U2693 : nand2 port map( a => mult_125_G2_ab_0_11_port, b =>
mult_125_G2_ab_1_10_port, outb => n1366);
U2694 : aoi22 port map( a => mult_125_G2_ab_2_10_port, b => n4249, c =>
n1364, d => n2881, outb => n4248);
U2695 : oai22 port map( a => n4248, b => n4250, c => n1367, d => n2882, outb
=> n1370);
U2696 : aoi22 port map( a => n1370, b => mult_125_G2_ab_4_10_port, c =>
n4251, d => n2921, outb => n1373);
U2697 : oai22 port map( a => n1373, b => n1372, c => n4252, d => n2884, outb
=> n1375);
U2698 : aoi22 port map( a => n1375, b => mult_125_G2_ab_6_10_port, c =>
n4254, d => n2924, outb => n4253);
U2699 : oai22 port map( a => n4253, b => n4255, c => n1376, d => n2887, outb
=> n1379);
U2700 : inv port map( inb => mult_125_G2_ab_8_10_port, outb => n4256);
U2701 : oai22 port map( a => n4257, b => n4256, c => n1378, d => n2890, outb
=> n1381);
U2702 : aoi22 port map( a => n1381, b => mult_125_G2_ab_9_10_port, c =>
n4259, d => n2893, outb => n4258);
U2703 : inv port map( inb => mult_125_G2_ab_10_10_port, outb => n4260);
U2704 : oai22 port map( a => n4258, b => n4260, c => n1382, d => n2896, outb
=> n1385);
U2705 : aoi22 port map( a => n1385, b => mult_125_G2_ab_11_10_port, c =>
n4262, d => n2899, outb => n4261);
U2706 : inv port map( inb => mult_125_G2_ab_12_10_port, outb => n4263);
U2707 : oai22 port map( a => n4261, b => n4263, c => n1386, d => n2902, outb
=> n1389);
U2708 : aoi22 port map( a => n1389, b => mult_125_G2_ab_13_10_port, c =>
n4265, d => n2905, outb => n4264);
U2709 : inv port map( inb => mult_125_G2_ab_14_10_port, outb => n4266);
U2710 : oai22 port map( a => n4264, b => n4266, c => n1390, d => n2908, outb
=> n1393);
U2711 : nand2 port map( a => mult_125_G2_ab_0_10_port, b =>
mult_125_G2_ab_1_9_port, outb => n1396);
U2712 : aoi22 port map( a => mult_125_G2_ab_2_9_port, b => n4268, c => n1394
, d => n2916, outb => n4267);
U2713 : oai22 port map( a => n4267, b => n4269, c => n1397, d => n2917, outb
=> n1400);
U2714 : oai22 port map( a => n4270, b => n4271, c => n1399, d => n2930, outb
=> n1402);
U2715 : aoi22 port map( a => n1402, b => mult_125_G2_ab_5_9_port, c => n4273
, d => n2919, outb => n4272);
U2716 : oai22 port map( a => n4272, b => n4274, c => n1403, d => n2933, outb
=> n1406);
U2717 : aoi22 port map( a => n1406, b => mult_125_G2_ab_7_9_port, c => n4276
, d => n2922, outb => n4275);
U2718 : oai22 port map( a => n4275, b => n4277, c => n1407, d => n2936, outb
=> n1410);
U2719 : oai22 port map( a => n4278, b => n4279, c => n1409, d => n2939, outb
=> n1412);
U2720 : aoi22 port map( a => n1412, b => mult_125_G2_ab_10_9_port, c =>
n4281, d => n2942, outb => n4280);
U2721 : inv port map( inb => mult_125_G2_ab_11_9_port, outb => n4282);
U2722 : oai22 port map( a => n4280, b => n4282, c => n1413, d => n2945, outb
=> n1416);
U2723 : aoi22 port map( a => n1416, b => mult_125_G2_ab_12_9_port, c =>
n4284, d => n2948, outb => n4283);
U2724 : inv port map( inb => mult_125_G2_ab_13_9_port, outb => n4285);
U2725 : oai22 port map( a => n4283, b => n4285, c => n1417, d => n2951, outb
=> n1420);
U2726 : aoi22 port map( a => n1420, b => mult_125_G2_ab_14_9_port, c =>
n4286, d => n2954, outb => n1423);
U2727 : nand2 port map( a => mult_125_G2_ab_0_9_port, b =>
mult_125_G2_ab_1_8_port, outb => n1426);
U2728 : aoi22 port map( a => mult_125_G2_ab_2_8_port, b => n4288, c => n1424
, d => n2925, outb => n4287);
U2729 : oai22 port map( a => n4287, b => n4289, c => n1427, d => n2926, outb
=> n1430);
U2730 : oai22 port map( a => n4290, b => n4291, c => n1429, d => n2962, outb
=> n1432);
U2731 : oai22 port map( a => n4292, b => n4293, c => n1431, d => n2928, outb
=> n1434);
U2732 : aoi22 port map( a => n1434, b => mult_125_G2_ab_6_8_port, c => n4295
, d => n2965, outb => n4294);
U2733 : oai22 port map( a => n4294, b => n4296, c => n1435, d => n2931, outb
=> n1438);
U2734 : aoi22 port map( a => n1438, b => mult_125_G2_ab_8_8_port, c => n4298
, d => n2968, outb => n4297);
U2735 : oai22 port map( a => n4297, b => n4299, c => n1439, d => n2934, outb
=> n1442);
U2736 : inv port map( inb => mult_125_G2_ab_10_8_port, outb => n4300);
U2737 : oai22 port map( a => n4301, b => n4300, c => n1441, d => n2937, outb
=> n1444);
U2738 : aoi22 port map( a => n1444, b => mult_125_G2_ab_11_8_port, c =>
n4303, d => n2940, outb => n4302);
U2739 : inv port map( inb => mult_125_G2_ab_12_8_port, outb => n4304);
U2740 : oai22 port map( a => n4302, b => n4304, c => n1445, d => n2943, outb
=> n1448);
U2741 : aoi22 port map( a => n1448, b => mult_125_G2_ab_13_8_port, c =>
n4306, d => n2946, outb => n4305);
U2742 : inv port map( inb => mult_125_G2_ab_14_8_port, outb => n4307);
U2743 : oai22 port map( a => n4305, b => n4307, c => n1449, d => n2949, outb
=> n1452);
U2744 : nand2 port map( a => mult_125_G2_ab_0_8_port, b =>
mult_125_G2_ab_1_7_port, outb => n1455);
U2745 : aoi22 port map( a => mult_125_G2_ab_2_7_port, b => n4308, c => n1453
, d => n2957, outb => n1458);
U2746 : oai22 port map( a => n1458, b => n1457, c => n4309, d => n2958, outb
=> n1460);
U2747 : oai22 port map( a => n4310, b => n4311, c => n1459, d => n2974, outb
=> n1462);
U2748 : aoi22 port map( a => n1462, b => mult_125_G2_ab_5_7_port, c => n4313
, d => n2960, outb => n4312);
U2749 : oai22 port map( a => n4312, b => n4314, c => n1463, d => n2977, outb
=> n1466);
U2750 : aoi22 port map( a => n1466, b => mult_125_G2_ab_7_7_port, c => n4316
, d => n2963, outb => n4315);
U2751 : oai22 port map( a => n4315, b => n4317, c => n1467, d => n2980, outb
=> n1470);
U2752 : aoi22 port map( a => n1470, b => mult_125_G2_ab_9_7_port, c => n4319
, d => n2966, outb => n4318);
U2753 : oai22 port map( a => n4318, b => n4320, c => n1471, d => n2983, outb
=> n1474);
U2754 : oai22 port map( a => n4321, b => n4322, c => n1473, d => n2986, outb
=> n1476);
U2755 : aoi22 port map( a => n1476, b => mult_125_G2_ab_12_7_port, c =>
n4324, d => n2989, outb => n4323);
U2756 : inv port map( inb => mult_125_G2_ab_13_7_port, outb => n4325);
U2757 : oai22 port map( a => n4323, b => n4325, c => n1477, d => n2992, outb
=> n1480);
U2758 : aoi22 port map( a => n1480, b => mult_125_G2_ab_14_7_port, c =>
n4326, d => n2995, outb => n1483);
U2759 : nand2 port map( a => mult_125_G2_ab_0_7_port, b =>
mult_125_G2_ab_1_6_port, outb => n1486);
U2760 : aoi22 port map( a => mult_125_G2_ab_2_6_port, b => n4328, c => n1484
, d => n2969, outb => n4327);
U2761 : oai22 port map( a => n4327, b => n4329, c => n1487, d => n2970, outb
=> n1490);
U2762 : aoi22 port map( a => n1490, b => mult_125_G2_ab_4_6_port, c => n4330
, d => n3003, outb => n1493);
U2763 : oai22 port map( a => n1493, b => n1492, c => n4331, d => n2972, outb
=> n1495);
U2764 : aoi22 port map( a => n1495, b => mult_125_G2_ab_6_6_port, c => n4333
, d => n3006, outb => n4332);
U2765 : oai22 port map( a => n4332, b => n4334, c => n1496, d => n2975, outb
=> n1499);
U2766 : aoi22 port map( a => n1499, b => mult_125_G2_ab_8_6_port, c => n4335
, d => n3009, outb => n1502);
U2767 : oai22 port map( a => n1502, b => n1501, c => n4336, d => n2978, outb
=> n1504);
U2768 : aoi22 port map( a => n1504, b => mult_125_G2_ab_10_6_port, c =>
n4338, d => n3012, outb => n4337);
U2769 : oai22 port map( a => n4337, b => n4339, c => n1505, d => n2981, outb
=> n1508);
U2770 : inv port map( inb => mult_125_G2_ab_12_6_port, outb => n4340);
U2771 : oai22 port map( a => n4341, b => n4340, c => n1507, d => n2984, outb
=> n1510);
U2772 : aoi22 port map( a => n1510, b => mult_125_G2_ab_13_6_port, c =>
n4343, d => n2987, outb => n4342);
U2773 : inv port map( inb => mult_125_G2_ab_14_6_port, outb => n4344);
U2774 : oai22 port map( a => n4342, b => n4344, c => n1511, d => n2990, outb
=> n1514);
U2775 : nand2 port map( a => mult_125_G2_ab_0_6_port, b =>
mult_125_G2_ab_1_5_port, outb => n1517);
U2776 : aoi22 port map( a => mult_125_G2_ab_2_5_port, b => n4345, c => n1515
, d => n2998, outb => n1520);
U2777 : oai22 port map( a => n1520, b => n1519, c => n4346, d => n2999, outb
=> n1522);
U2778 : oai22 port map( a => n4347, b => n4348, c => n1521, d => n3018, outb
=> n1524);
U2779 : aoi22 port map( a => n1524, b => mult_125_G2_ab_5_5_port, c => n4349
, d => n3001, outb => n1527);
U2780 : oai22 port map( a => n1527, b => n1526, c => n4350, d => n3021, outb
=> n1529);
U2781 : aoi22 port map( a => n1529, b => mult_125_G2_ab_7_5_port, c => n4352
, d => n3004, outb => n4351);
U2782 : oai22 port map( a => n4351, b => n4353, c => n1530, d => n3024, outb
=> n1533);
U2783 : aoi22 port map( a => n1533, b => mult_125_G2_ab_9_5_port, c => n4355
, d => n3007, outb => n4354);
U2784 : oai22 port map( a => n4354, b => n4356, c => n1534, d => n3027, outb
=> n1537);
U2785 : aoi22 port map( a => n1537, b => mult_125_G2_ab_11_5_port, c =>
n4358, d => n3010, outb => n4357);
U2786 : oai22 port map( a => n4357, b => n4359, c => n1538, d => n3030, outb
=> n1541);
U2787 : oai22 port map( a => n4360, b => n4361, c => n1540, d => n3033, outb
=> n1543);
U2788 : aoi22 port map( a => n1543, b => mult_125_G2_ab_14_5_port, c =>
n4362, d => n3036, outb => n1546);
U2789 : nand2 port map( a => mult_125_G2_ab_0_5_port, b =>
mult_125_G2_ab_1_4_port, outb => n1549);
U2790 : aoi22 port map( a => mult_125_G2_ab_2_4_port, b => n4364, c => n1547
, d => n3013, outb => n4363);
U2791 : oai22 port map( a => n4363, b => n4365, c => n1550, d => n3014, outb
=> n1553);
U2792 : aoi22 port map( a => n1553, b => mult_125_G2_ab_4_4_port, c => n4366
, d => n3044, outb => n1556);
U2793 : oai22 port map( a => n1556, b => n1555, c => n4367, d => n3016, outb
=> n1558);
U2794 : aoi22 port map( a => n1558, b => mult_125_G2_ab_6_4_port, c => n4368
, d => n3047, outb => n1561);
U2795 : oai22 port map( a => n1561, b => n1560, c => n4369, d => n3019, outb
=> n1563);
U2796 : aoi22 port map( a => n1563, b => mult_125_G2_ab_8_4_port, c => n4371
, d => n3050, outb => n4370);
U2797 : oai22 port map( a => n4370, b => n4372, c => n1564, d => n3022, outb
=> n1567);
U2798 : aoi22 port map( a => n1567, b => mult_125_G2_ab_10_4_port, c =>
n4373, d => n3053, outb => n1570);
U2799 : oai22 port map( a => n1570, b => n1569, c => n4374, d => n3025, outb
=> n1572);
U2800 : aoi22 port map( a => n1572, b => mult_125_G2_ab_12_4_port, c =>
n4376, d => n3056, outb => n4375);
U2801 : oai22 port map( a => n4375, b => n4377, c => n1573, d => n3028, outb
=> n1576);
U2802 : aoi22 port map( a => n1576, b => mult_125_G2_ab_14_4_port, c =>
n4378, d => n3031, outb => n1579);
U2803 : nand2 port map( a => mult_125_G2_ab_0_4_port, b =>
mult_125_G2_ab_1_3_port, outb => n1582);
U2804 : aoi22 port map( a => mult_125_G2_ab_2_3_port, b => n4379, c => n1580
, d => n3039, outb => n1585);
U2805 : oai22 port map( a => n1585, b => n1584, c => n4380, d => n3040, outb
=> n1587);
U2806 : oai22 port map( a => n4381, b => n4382, c => n1586, d => n3062, outb
=> n1589);
U2807 : aoi22 port map( a => n1589, b => mult_125_G2_ab_5_3_port, c => n4384
, d => n3042, outb => n4383);
U2808 : oai22 port map( a => n4383, b => n4385, c => n1590, d => n3065, outb
=> n1593);
U2809 : aoi22 port map( a => n1593, b => mult_125_G2_ab_7_3_port, c => n4387
, d => n3045, outb => n4386);
U2810 : oai22 port map( a => n4386, b => n4388, c => n1594, d => n3068, outb
=> n1597);
U2811 : aoi22 port map( a => n1597, b => mult_125_G2_ab_9_3_port, c => n4390
, d => n3048, outb => n4389);
U2812 : oai22 port map( a => n4389, b => n4391, c => n1598, d => n3071, outb
=> n1601);
U2813 : aoi22 port map( a => n1601, b => mult_125_G2_ab_11_3_port, c =>
n4393, d => n3051, outb => n4392);
U2814 : oai22 port map( a => n4392, b => n4394, c => n1602, d => n3074, outb
=> n1605);
U2815 : aoi22 port map( a => n1605, b => mult_125_G2_ab_13_3_port, c =>
n4396, d => n3054, outb => n4395);
U2816 : inv port map( inb => mult_125_G2_ab_14_3_port, outb => n4397);
U2817 : oai22 port map( a => n4395, b => n4397, c => n1606, d => n3077, outb
=> n1609);
U2818 : nand2 port map( a => mult_125_G2_ab_0_3_port, b =>
mult_125_G2_ab_1_2_port, outb => n1612);
U2819 : aoi22 port map( a => mult_125_G2_ab_2_2_port, b => n4399, c => n1610
, d => n3057, outb => n4398);
U2820 : oai22 port map( a => n4398, b => n4400, c => n1613, d => n3058, outb
=> n1616);
U2821 : aoi22 port map( a => n1616, b => mult_125_G2_ab_4_2_port, c => n4402
, d => n3085, outb => n4401);
U2822 : oai22 port map( a => n4401, b => n4403, c => n1617, d => n3060, outb
=> n1620);
U2823 : aoi22 port map( a => n1620, b => mult_125_G2_ab_6_2_port, c => n4404
, d => n3088, outb => n1623);
U2824 : oai22 port map( a => n1623, b => n1622, c => n4405, d => n3063, outb
=> n1625);
U2825 : aoi22 port map( a => n1625, b => mult_125_G2_ab_8_2_port, c => n4407
, d => n3091, outb => n4406);
U2826 : oai22 port map( a => n4406, b => n4408, c => n1626, d => n3066, outb
=> n1629);
U2827 : aoi22 port map( a => n1629, b => mult_125_G2_ab_10_2_port, c =>
n4410, d => n3094, outb => n4409);
U2828 : oai22 port map( a => n4409, b => n4411, c => n1630, d => n3069, outb
=> n1633);
U2829 : aoi22 port map( a => n1633, b => mult_125_G2_ab_12_2_port, c =>
n4413, d => n3097, outb => n4412);
U2830 : oai22 port map( a => n4412, b => n4414, c => n1634, d => n3072, outb
=> n1637);
U2831 : aoi22 port map( a => n1637, b => mult_125_G2_ab_14_2_port, c =>
n4416, d => n3100, outb => n4415);
U2832 : nand2 port map( a => mult_125_G2_ab_0_2_port, b =>
mult_125_G2_ab_1_1_port, outb => n1642);
U2833 : aoi22 port map( a => mult_125_G2_ab_2_1_port, b => n4418, c => n1640
, d => n3080, outb => n4417);
U2834 : oai22 port map( a => n4417, b => n4419, c => n1643, d => n3081, outb
=> n1646);
U2835 : inv port map( inb => mult_125_G2_ab_4_1_port, outb => n4420);
U2836 : oai22 port map( a => n4421, b => n4420, c => n1645, d => n3106, outb
=> n1648);
U2837 : aoi22 port map( a => n1648, b => mult_125_G2_ab_5_1_port, c => n4423
, d => n3083, outb => n4422);
U2838 : oai22 port map( a => n4422, b => n4424, c => n1649, d => n3109, outb
=> n1652);
U2839 : aoi22 port map( a => n1652, b => mult_125_G2_ab_7_1_port, c => n4426
, d => n3086, outb => n4425);
U2840 : oai22 port map( a => n4425, b => n4427, c => n1653, d => n3112, outb
=> n1656);
U2841 : aoi22 port map( a => n1656, b => mult_125_G2_ab_9_1_port, c => n4429
, d => n3089, outb => n4428);
U2842 : oai22 port map( a => n4428, b => n4430, c => n1657, d => n3115, outb
=> n1660);
U2843 : aoi22 port map( a => n1660, b => mult_125_G2_ab_11_1_port, c =>
n4432, d => n3092, outb => n4431);
U2844 : oai22 port map( a => n4431, b => n4433, c => n1661, d => n3118, outb
=> n1664);
U2845 : aoi22 port map( a => n1664, b => mult_125_G2_ab_13_1_port, c =>
n4435, d => n3095, outb => n4434);
U2846 : inv port map( inb => mult_125_G2_ab_14_1_port, outb => n4436);
U2847 : oai22 port map( a => n4434, b => n4436, c => n1665, d => n3121, outb
=> n1668);
U2848 : nand2 port map( a => mult_125_G2_ab_0_1_port, b =>
mult_125_G2_ab_1_0_port, outb => n4437);
U2849 : aoi22 port map( a => mult_125_G2_ab_2_0_port, b => n1670, c => n4439
, d => n3101, outb => n4438);
U2850 : aoi22 port map( a => n1672, b => mult_125_G2_ab_3_0_port, c => n4441
, d => n3102, outb => n4440);
U2851 : inv port map( inb => mult_125_G2_ab_4_0_port, outb => n4442);
U2852 : oai22 port map( a => n4440, b => n4442, c => n1673, d => n4443, outb
=> n1676);
U2853 : aoi22 port map( a => n1676, b => mult_125_G2_ab_5_0_port, c => n4445
, d => n3104, outb => n4444);
U2854 : inv port map( inb => mult_125_G2_ab_6_0_port, outb => n4446);
U2855 : oai22 port map( a => n4444, b => n4446, c => n1677, d => n4447, outb
=> n1680);
U2856 : aoi22 port map( a => n1680, b => mult_125_G2_ab_7_0_port, c => n4449
, d => n3107, outb => n4448);
U2857 : inv port map( inb => mult_125_G2_ab_8_0_port, outb => n4450);
U2858 : oai22 port map( a => n4448, b => n4450, c => n1681, d => n4451, outb
=> n1684);
U2859 : aoi22 port map( a => n1684, b => mult_125_G2_ab_9_0_port, c => n4453
, d => n3110, outb => n4452);
U2860 : inv port map( inb => mult_125_G2_ab_10_0_port, outb => n4454);
U2861 : oai22 port map( a => n4452, b => n4454, c => n1685, d => n4455, outb
=> n1688);
U2862 : aoi22 port map( a => n1688, b => mult_125_G2_ab_11_0_port, c =>
n4457, d => n3113, outb => n4456);
U2863 : inv port map( inb => mult_125_G2_ab_12_0_port, outb => n4458);
U2864 : oai22 port map( a => n4456, b => n4458, c => n1689, d => n4459, outb
=> n1692);
U2865 : aoi22 port map( a => n1692, b => mult_125_G2_ab_13_0_port, c =>
n4461, d => n3116, outb => n4460);
U2866 : inv port map( inb => mult_125_G2_ab_14_0_port, outb => n4462);
U2867 : oai22 port map( a => n4460, b => n4462, c => n1693, d => n4463, outb
=> n1696);
U2868 : inv port map( inb => mult_125_G2_ZB, outb => n344);
U2869 : inv port map( inb => mult_125_G2_ZA, outb => n345);
U2870 : nand2 port map( a => mult_125_ab_0_15_port, b =>
mult_125_ab_1_14_port, outb => n4464);
U2871 : inv port map( inb => mult_125_ab_3_15_port, outb => n4465);
U2872 : inv port map( inb => mult_125_ab_4_14_port, outb => n4466);
U2873 : inv port map( inb => mult_125_ab_5_15_port, outb => n4467);
U2874 : inv port map( inb => mult_125_ab_6_14_port, outb => n4468);
U2875 : inv port map( inb => mult_125_ab_7_15_port, outb => n4469);
U2876 : inv port map( inb => mult_125_ab_8_14_port, outb => n4470);
U2877 : inv port map( inb => mult_125_ab_9_15_port, outb => n4471);
U2878 : inv port map( inb => mult_125_ab_10_14_port, outb => n4472);
U2879 : inv port map( inb => mult_125_ab_11_15_port, outb => n4473);
U2880 : inv port map( inb => mult_125_ab_12_14_port, outb => n4474);
U2881 : nand2 port map( a => mult_125_ab_0_14_port, b =>
mult_125_ab_1_13_port, outb => n1714);
U2882 : aoi22 port map( a => mult_125_ab_2_13_port, b => n4475, c => n1712,
d => n3131, outb => n1717);
U2883 : oai22 port map( a => n1717, b => n1716, c => n4476, d => n3132, outb
=> n1719);
U2884 : aoi22 port map( a => n1719, b => mult_125_ab_4_13_port, c => n4478,
d => n3139, outb => n4477);
U2885 : oai22 port map( a => n4477, b => n4479, c => n1720, d => n3142, outb
=> n1723);
U2886 : aoi22 port map( a => n1723, b => mult_125_ab_6_13_port, c => n4481,
d => n3145, outb => n4480);
U2887 : inv port map( inb => mult_125_ab_7_13_port, outb => n4482);
U2888 : oai22 port map( a => n4480, b => n4482, c => n1724, d => n3148, outb
=> n1727);
U2889 : aoi22 port map( a => n1727, b => mult_125_ab_8_13_port, c => n4484,
d => n3151, outb => n4483);
U2890 : inv port map( inb => mult_125_ab_9_13_port, outb => n4485);
U2891 : oai22 port map( a => n4483, b => n4485, c => n1728, d => n3154, outb
=> n1731);
U2892 : aoi22 port map( a => n1731, b => mult_125_ab_10_13_port, c => n4487,
d => n3157, outb => n4486);
U2893 : inv port map( inb => mult_125_ab_11_13_port, outb => n4488);
U2894 : oai22 port map( a => n4486, b => n4488, c => n1732, d => n3160, outb
=> n1735);
U2895 : aoi22 port map( a => n1735, b => mult_125_ab_12_13_port, c => n4490,
d => n3163, outb => n4489);
U2896 : inv port map( inb => mult_125_ab_13_13_port, outb => n4491);
U2897 : oai22 port map( a => n4489, b => n4491, c => n1736, d => n3166, outb
=> n1739);
U2898 : aoi22 port map( a => n1739, b => mult_125_ab_14_13_port, c => n4493,
d => n3169, outb => n4492);
U2899 : nand2 port map( a => mult_125_ab_0_13_port, b =>
mult_125_ab_1_12_port, outb => n1744);
U2900 : aoi22 port map( a => mult_125_ab_2_12_port, b => n4495, c => n1742,
d => n3134, outb => n4494);
U2901 : oai22 port map( a => n4494, b => n4496, c => n1745, d => n3135, outb
=> n1748);
U2902 : aoi22 port map( a => n1748, b => mult_125_ab_4_12_port, c => n4498,
d => n3177, outb => n4497);
U2903 : aoi22 port map( a => n1750, b => mult_125_ab_5_12_port, c => n4500,
d => n3137, outb => n4499);
U2904 : inv port map( inb => mult_125_ab_6_12_port, outb => n4501);
U2905 : oai22 port map( a => n4499, b => n4501, c => n1751, d => n3140, outb
=> n1754);
U2906 : aoi22 port map( a => n1754, b => mult_125_ab_7_12_port, c => n4503,
d => n3143, outb => n4502);
U2907 : inv port map( inb => mult_125_ab_8_12_port, outb => n4504);
U2908 : oai22 port map( a => n4502, b => n4504, c => n1755, d => n3146, outb
=> n1758);
U2909 : aoi22 port map( a => n1758, b => mult_125_ab_9_12_port, c => n4506,
d => n3149, outb => n4505);
U2910 : inv port map( inb => mult_125_ab_10_12_port, outb => n4507);
U2911 : oai22 port map( a => n4505, b => n4507, c => n1759, d => n3152, outb
=> n1762);
U2912 : aoi22 port map( a => n1762, b => mult_125_ab_11_12_port, c => n4509,
d => n3155, outb => n4508);
U2913 : inv port map( inb => mult_125_ab_12_12_port, outb => n4510);
U2914 : oai22 port map( a => n4508, b => n4510, c => n1763, d => n3158, outb
=> n1766);
U2915 : aoi22 port map( a => n1766, b => mult_125_ab_13_12_port, c => n4512,
d => n3161, outb => n4511);
U2916 : inv port map( inb => mult_125_ab_14_12_port, outb => n4513);
U2917 : oai22 port map( a => n4511, b => n4513, c => n1767, d => n3164, outb
=> n1770);
U2918 : nand2 port map( a => mult_125_ab_0_12_port, b =>
mult_125_ab_1_11_port, outb => n1773);
U2919 : aoi22 port map( a => mult_125_ab_2_11_port, b => n4514, c => n1771,
d => n3172, outb => n1776);
U2920 : oai22 port map( a => n1776, b => n1775, c => n4515, d => n3173, outb
=> n1778);
U2921 : oai22 port map( a => n4516, b => n4517, c => n1777, d => n3183, outb
=> n1780);
U2922 : aoi22 port map( a => n1780, b => mult_125_ab_5_11_port, c => n4519,
d => n3175, outb => n4518);
U2923 : oai22 port map( a => n4518, b => n4520, c => n1781, d => n3186, outb
=> n1784);
U2924 : oai22 port map( a => n4521, b => n4522, c => n1783, d => n3189, outb
=> n1786);
U2925 : aoi22 port map( a => n1786, b => mult_125_ab_8_11_port, c => n4524,
d => n3192, outb => n4523);
U2926 : inv port map( inb => mult_125_ab_9_11_port, outb => n4525);
U2927 : oai22 port map( a => n4523, b => n4525, c => n1787, d => n3195, outb
=> n1790);
U2928 : aoi22 port map( a => n1790, b => mult_125_ab_10_11_port, c => n4527,
d => n3198, outb => n4526);
U2929 : inv port map( inb => mult_125_ab_11_11_port, outb => n4528);
U2930 : oai22 port map( a => n4526, b => n4528, c => n1791, d => n3201, outb
=> n1794);
U2931 : aoi22 port map( a => n1794, b => mult_125_ab_12_11_port, c => n4530,
d => n3204, outb => n4529);
U2932 : inv port map( inb => mult_125_ab_13_11_port, outb => n4531);
U2933 : oai22 port map( a => n4529, b => n4531, c => n1795, d => n3207, outb
=> n1798);
U2934 : aoi22 port map( a => n1798, b => mult_125_ab_14_11_port, c => n4532,
d => n3210, outb => n1801);
U2935 : nand2 port map( a => mult_125_ab_0_11_port, b =>
mult_125_ab_1_10_port, outb => n1804);
U2936 : aoi22 port map( a => mult_125_ab_2_10_port, b => n4534, c => n1802,
d => n3178, outb => n4533);
U2937 : oai22 port map( a => n4533, b => n4535, c => n1805, d => n3179, outb
=> n1808);
U2938 : aoi22 port map( a => n1808, b => mult_125_ab_4_10_port, c => n4536,
d => n3218, outb => n1811);
U2939 : oai22 port map( a => n1811, b => n1810, c => n4537, d => n3181, outb
=> n1813);
U2940 : aoi22 port map( a => n1813, b => mult_125_ab_6_10_port, c => n4539,
d => n3221, outb => n4538);
U2941 : oai22 port map( a => n4538, b => n4540, c => n1814, d => n3184, outb
=> n1817);
U2942 : inv port map( inb => mult_125_ab_8_10_port, outb => n4541);
U2943 : oai22 port map( a => n4542, b => n4541, c => n1816, d => n3187, outb
=> n1819);
U2944 : aoi22 port map( a => n1819, b => mult_125_ab_9_10_port, c => n4544,
d => n3190, outb => n4543);
U2945 : inv port map( inb => mult_125_ab_10_10_port, outb => n4545);
U2946 : oai22 port map( a => n4543, b => n4545, c => n1820, d => n3193, outb
=> n1823);
U2947 : aoi22 port map( a => n1823, b => mult_125_ab_11_10_port, c => n4547,
d => n3196, outb => n4546);
U2948 : inv port map( inb => mult_125_ab_12_10_port, outb => n4548);
U2949 : oai22 port map( a => n4546, b => n4548, c => n1824, d => n3199, outb
=> n1827);
U2950 : aoi22 port map( a => n1827, b => mult_125_ab_13_10_port, c => n4550,
d => n3202, outb => n4549);
U2951 : inv port map( inb => mult_125_ab_14_10_port, outb => n4551);
U2952 : oai22 port map( a => n4549, b => n4551, c => n1828, d => n3205, outb
=> n1831);
U2953 : nand2 port map( a => mult_125_ab_0_10_port, b =>
mult_125_ab_1_9_port, outb => n1834);
U2954 : aoi22 port map( a => mult_125_ab_2_9_port, b => n4553, c => n1832, d
=> n3213, outb => n4552);
U2955 : oai22 port map( a => n4552, b => n4554, c => n1835, d => n3214, outb
=> n1838);
U2956 : oai22 port map( a => n4555, b => n4556, c => n1837, d => n3227, outb
=> n1840);
U2957 : aoi22 port map( a => n1840, b => mult_125_ab_5_9_port, c => n4558, d
=> n3216, outb => n4557);
U2958 : oai22 port map( a => n4557, b => n4559, c => n1841, d => n3230, outb
=> n1844);
U2959 : aoi22 port map( a => n1844, b => mult_125_ab_7_9_port, c => n4561, d
=> n3219, outb => n4560);
U2960 : oai22 port map( a => n4560, b => n4562, c => n1845, d => n3233, outb
=> n1848);
U2961 : oai22 port map( a => n4563, b => n4564, c => n1847, d => n3236, outb
=> n1850);
U2962 : aoi22 port map( a => n1850, b => mult_125_ab_10_9_port, c => n4566,
d => n3239, outb => n4565);
U2963 : inv port map( inb => mult_125_ab_11_9_port, outb => n4567);
U2964 : oai22 port map( a => n4565, b => n4567, c => n1851, d => n3242, outb
=> n1854);
U2965 : aoi22 port map( a => n1854, b => mult_125_ab_12_9_port, c => n4569,
d => n3245, outb => n4568);
U2966 : inv port map( inb => mult_125_ab_13_9_port, outb => n4570);
U2967 : oai22 port map( a => n4568, b => n4570, c => n1855, d => n3248, outb
=> n1858);
U2968 : aoi22 port map( a => n1858, b => mult_125_ab_14_9_port, c => n4571,
d => n3251, outb => n1861);
U2969 : nand2 port map( a => mult_125_ab_0_9_port, b => mult_125_ab_1_8_port
, outb => n1864);
U2970 : aoi22 port map( a => mult_125_ab_2_8_port, b => n4573, c => n1862, d
=> n3222, outb => n4572);
U2971 : oai22 port map( a => n4572, b => n4574, c => n1865, d => n3223, outb
=> n1868);
U2972 : oai22 port map( a => n4575, b => n4576, c => n1867, d => n3259, outb
=> n1870);
U2973 : oai22 port map( a => n4577, b => n4578, c => n1869, d => n3225, outb
=> n1872);
U2974 : aoi22 port map( a => n1872, b => mult_125_ab_6_8_port, c => n4580, d
=> n3262, outb => n4579);
U2975 : oai22 port map( a => n4579, b => n4581, c => n1873, d => n3228, outb
=> n1876);
U2976 : aoi22 port map( a => n1876, b => mult_125_ab_8_8_port, c => n4583, d
=> n3265, outb => n4582);
U2977 : oai22 port map( a => n4582, b => n4584, c => n1877, d => n3231, outb
=> n1880);
U2978 : inv port map( inb => mult_125_ab_10_8_port, outb => n4585);
U2979 : oai22 port map( a => n4586, b => n4585, c => n1879, d => n3234, outb
=> n1882);
U2980 : aoi22 port map( a => n1882, b => mult_125_ab_11_8_port, c => n4588,
d => n3237, outb => n4587);
U2981 : inv port map( inb => mult_125_ab_12_8_port, outb => n4589);
U2982 : oai22 port map( a => n4587, b => n4589, c => n1883, d => n3240, outb
=> n1886);
U2983 : aoi22 port map( a => n1886, b => mult_125_ab_13_8_port, c => n4591,
d => n3243, outb => n4590);
U2984 : inv port map( inb => mult_125_ab_14_8_port, outb => n4592);
U2985 : oai22 port map( a => n4590, b => n4592, c => n1887, d => n3246, outb
=> n1890);
U2986 : nand2 port map( a => mult_125_ab_0_8_port, b => mult_125_ab_1_7_port
, outb => n1893);
U2987 : aoi22 port map( a => mult_125_ab_2_7_port, b => n4593, c => n1891, d
=> n3254, outb => n1896);
U2988 : oai22 port map( a => n1896, b => n1895, c => n4594, d => n3255, outb
=> n1898);
U2989 : oai22 port map( a => n4595, b => n4596, c => n1897, d => n3271, outb
=> n1900);
U2990 : aoi22 port map( a => n1900, b => mult_125_ab_5_7_port, c => n4598, d
=> n3257, outb => n4597);
U2991 : oai22 port map( a => n4597, b => n4599, c => n1901, d => n3274, outb
=> n1904);
U2992 : aoi22 port map( a => n1904, b => mult_125_ab_7_7_port, c => n4601, d
=> n3260, outb => n4600);
U2993 : oai22 port map( a => n4600, b => n4602, c => n1905, d => n3277, outb
=> n1908);
U2994 : aoi22 port map( a => n1908, b => mult_125_ab_9_7_port, c => n4604, d
=> n3263, outb => n4603);
U2995 : oai22 port map( a => n4603, b => n4605, c => n1909, d => n3280, outb
=> n1912);
U2996 : oai22 port map( a => n4606, b => n4607, c => n1911, d => n3283, outb
=> n1914);
U2997 : aoi22 port map( a => n1914, b => mult_125_ab_12_7_port, c => n4609,
d => n3286, outb => n4608);
U2998 : inv port map( inb => mult_125_ab_13_7_port, outb => n4610);
U2999 : oai22 port map( a => n4608, b => n4610, c => n1915, d => n3289, outb
=> n1918);
U3000 : aoi22 port map( a => n1918, b => mult_125_ab_14_7_port, c => n4611,
d => n3292, outb => n1921);
U3001 : nand2 port map( a => mult_125_ab_0_7_port, b => mult_125_ab_1_6_port
, outb => n1924);
U3002 : aoi22 port map( a => mult_125_ab_2_6_port, b => n4613, c => n1922, d
=> n3266, outb => n4612);
U3003 : oai22 port map( a => n4612, b => n4614, c => n1925, d => n3267, outb
=> n1928);
U3004 : aoi22 port map( a => n1928, b => mult_125_ab_4_6_port, c => n4615, d
=> n3300, outb => n1931);
U3005 : oai22 port map( a => n1931, b => n1930, c => n4616, d => n3269, outb
=> n1933);
U3006 : aoi22 port map( a => n1933, b => mult_125_ab_6_6_port, c => n4618, d
=> n3303, outb => n4617);
U3007 : oai22 port map( a => n4617, b => n4619, c => n1934, d => n3272, outb
=> n1937);
U3008 : aoi22 port map( a => n1937, b => mult_125_ab_8_6_port, c => n4620, d
=> n3306, outb => n1940);
U3009 : oai22 port map( a => n1940, b => n1939, c => n4621, d => n3275, outb
=> n1942);
U3010 : aoi22 port map( a => n1942, b => mult_125_ab_10_6_port, c => n4623,
d => n3309, outb => n4622);
U3011 : oai22 port map( a => n4622, b => n4624, c => n1943, d => n3278, outb
=> n1946);
U3012 : inv port map( inb => mult_125_ab_12_6_port, outb => n4625);
U3013 : oai22 port map( a => n4626, b => n4625, c => n1945, d => n3281, outb
=> n1948);
U3014 : aoi22 port map( a => n1948, b => mult_125_ab_13_6_port, c => n4628,
d => n3284, outb => n4627);
U3015 : inv port map( inb => mult_125_ab_14_6_port, outb => n4629);
U3016 : oai22 port map( a => n4627, b => n4629, c => n1949, d => n3287, outb
=> n1952);
U3017 : nand2 port map( a => mult_125_ab_0_6_port, b => mult_125_ab_1_5_port
, outb => n1955);
U3018 : aoi22 port map( a => mult_125_ab_2_5_port, b => n4630, c => n1953, d
=> n3295, outb => n1958);
U3019 : oai22 port map( a => n1958, b => n1957, c => n4631, d => n3296, outb
=> n1960);
U3020 : oai22 port map( a => n4632, b => n4633, c => n1959, d => n3315, outb
=> n1962);
U3021 : aoi22 port map( a => n1962, b => mult_125_ab_5_5_port, c => n4634, d
=> n3298, outb => n1965);
U3022 : oai22 port map( a => n1965, b => n1964, c => n4635, d => n3318, outb
=> n1967);
U3023 : aoi22 port map( a => n1967, b => mult_125_ab_7_5_port, c => n4637, d
=> n3301, outb => n4636);
U3024 : oai22 port map( a => n4636, b => n4638, c => n1968, d => n3321, outb
=> n1971);
U3025 : aoi22 port map( a => n1971, b => mult_125_ab_9_5_port, c => n4640, d
=> n3304, outb => n4639);
U3026 : oai22 port map( a => n4639, b => n4641, c => n1972, d => n3324, outb
=> n1975);
U3027 : aoi22 port map( a => n1975, b => mult_125_ab_11_5_port, c => n4643,
d => n3307, outb => n4642);
U3028 : oai22 port map( a => n4642, b => n4644, c => n1976, d => n3327, outb
=> n1979);
U3029 : oai22 port map( a => n4645, b => n4646, c => n1978, d => n3330, outb
=> n1981);
U3030 : aoi22 port map( a => n1981, b => mult_125_ab_14_5_port, c => n4647,
d => n3333, outb => n1984);
U3031 : nand2 port map( a => mult_125_ab_0_5_port, b => mult_125_ab_1_4_port
, outb => n1987);
U3032 : aoi22 port map( a => mult_125_ab_2_4_port, b => n4649, c => n1985, d
=> n3310, outb => n4648);
U3033 : oai22 port map( a => n4648, b => n4650, c => n1988, d => n3311, outb
=> n1991);
U3034 : aoi22 port map( a => n1991, b => mult_125_ab_4_4_port, c => n4651, d
=> n3341, outb => n1994);
U3035 : oai22 port map( a => n1994, b => n1993, c => n4652, d => n3313, outb
=> n1996);
U3036 : aoi22 port map( a => n1996, b => mult_125_ab_6_4_port, c => n4653, d
=> n3344, outb => n1999);
U3037 : oai22 port map( a => n1999, b => n1998, c => n4654, d => n3316, outb
=> n2001);
U3038 : aoi22 port map( a => n2001, b => mult_125_ab_8_4_port, c => n4656, d
=> n3347, outb => n4655);
U3039 : oai22 port map( a => n4655, b => n4657, c => n2002, d => n3319, outb
=> n2005);
U3040 : aoi22 port map( a => n2005, b => mult_125_ab_10_4_port, c => n4658,
d => n3350, outb => n2008);
U3041 : oai22 port map( a => n2008, b => n2007, c => n4659, d => n3322, outb
=> n2010);
U3042 : aoi22 port map( a => n2010, b => mult_125_ab_12_4_port, c => n4661,
d => n3353, outb => n4660);
U3043 : oai22 port map( a => n4660, b => n4662, c => n2011, d => n3325, outb
=> n2014);
U3044 : aoi22 port map( a => n2014, b => mult_125_ab_14_4_port, c => n4663,
d => n3328, outb => n2017);
U3045 : nand2 port map( a => mult_125_ab_0_4_port, b => mult_125_ab_1_3_port
, outb => n2020);
U3046 : aoi22 port map( a => mult_125_ab_2_3_port, b => n4664, c => n2018, d
=> n3336, outb => n2023);
U3047 : oai22 port map( a => n2023, b => n2022, c => n4665, d => n3337, outb
=> n2025);
U3048 : oai22 port map( a => n4666, b => n4667, c => n2024, d => n3359, outb
=> n2027);
U3049 : aoi22 port map( a => n2027, b => mult_125_ab_5_3_port, c => n4669, d
=> n3339, outb => n4668);
U3050 : oai22 port map( a => n4668, b => n4670, c => n2028, d => n3362, outb
=> n2031);
U3051 : aoi22 port map( a => n2031, b => mult_125_ab_7_3_port, c => n4672, d
=> n3342, outb => n4671);
U3052 : oai22 port map( a => n4671, b => n4673, c => n2032, d => n3365, outb
=> n2035);
U3053 : aoi22 port map( a => n2035, b => mult_125_ab_9_3_port, c => n4675, d
=> n3345, outb => n4674);
U3054 : oai22 port map( a => n4674, b => n4676, c => n2036, d => n3368, outb
=> n2039);
U3055 : aoi22 port map( a => n2039, b => mult_125_ab_11_3_port, c => n4678,
d => n3348, outb => n4677);
U3056 : oai22 port map( a => n4677, b => n4679, c => n2040, d => n3371, outb
=> n2043);
U3057 : aoi22 port map( a => n2043, b => mult_125_ab_13_3_port, c => n4681,
d => n3351, outb => n4680);
U3058 : inv port map( inb => mult_125_ab_14_3_port, outb => n4682);
U3059 : oai22 port map( a => n4680, b => n4682, c => n2044, d => n3374, outb
=> n2047);
U3060 : nand2 port map( a => mult_125_ab_0_3_port, b => mult_125_ab_1_2_port
, outb => n2050);
U3061 : aoi22 port map( a => mult_125_ab_2_2_port, b => n4684, c => n2048, d
=> n3354, outb => n4683);
U3062 : oai22 port map( a => n4683, b => n4685, c => n2051, d => n3355, outb
=> n2054);
U3063 : aoi22 port map( a => n2054, b => mult_125_ab_4_2_port, c => n4687, d
=> n3382, outb => n4686);
U3064 : oai22 port map( a => n4686, b => n4688, c => n2055, d => n3357, outb
=> n2058);
U3065 : aoi22 port map( a => n2058, b => mult_125_ab_6_2_port, c => n4689, d
=> n3385, outb => n2061);
U3066 : oai22 port map( a => n2061, b => n2060, c => n4690, d => n3360, outb
=> n2063);
U3067 : aoi22 port map( a => n2063, b => mult_125_ab_8_2_port, c => n4692, d
=> n3388, outb => n4691);
U3068 : oai22 port map( a => n4691, b => n4693, c => n2064, d => n3363, outb
=> n2067);
U3069 : aoi22 port map( a => n2067, b => mult_125_ab_10_2_port, c => n4695,
d => n3391, outb => n4694);
U3070 : oai22 port map( a => n4694, b => n4696, c => n2068, d => n3366, outb
=> n2071);
U3071 : aoi22 port map( a => n2071, b => mult_125_ab_12_2_port, c => n4698,
d => n3394, outb => n4697);
U3072 : oai22 port map( a => n4697, b => n4699, c => n2072, d => n3369, outb
=> n2075);
U3073 : aoi22 port map( a => n2075, b => mult_125_ab_14_2_port, c => n4701,
d => n3397, outb => n4700);
U3074 : nand2 port map( a => mult_125_ab_0_2_port, b => mult_125_ab_1_1_port
, outb => n2080);
U3075 : aoi22 port map( a => mult_125_ab_2_1_port, b => n4703, c => n2078, d
=> n3377, outb => n4702);
U3076 : oai22 port map( a => n4702, b => n4704, c => n2081, d => n3378, outb
=> n2084);
U3077 : inv port map( inb => mult_125_ab_4_1_port, outb => n4705);
U3078 : oai22 port map( a => n4706, b => n4705, c => n2083, d => n3403, outb
=> n2086);
U3079 : aoi22 port map( a => n2086, b => mult_125_ab_5_1_port, c => n4708, d
=> n3380, outb => n4707);
U3080 : oai22 port map( a => n4707, b => n4709, c => n2087, d => n3406, outb
=> n2090);
U3081 : aoi22 port map( a => n2090, b => mult_125_ab_7_1_port, c => n4711, d
=> n3383, outb => n4710);
U3082 : oai22 port map( a => n4710, b => n4712, c => n2091, d => n3409, outb
=> n2094);
U3083 : aoi22 port map( a => n2094, b => mult_125_ab_9_1_port, c => n4714, d
=> n3386, outb => n4713);
U3084 : oai22 port map( a => n4713, b => n4715, c => n2095, d => n3412, outb
=> n2098);
U3085 : aoi22 port map( a => n2098, b => mult_125_ab_11_1_port, c => n4717,
d => n3389, outb => n4716);
U3086 : oai22 port map( a => n4716, b => n4718, c => n2099, d => n3415, outb
=> n2102);
U3087 : aoi22 port map( a => n2102, b => mult_125_ab_13_1_port, c => n4720,
d => n3392, outb => n4719);
U3088 : inv port map( inb => mult_125_ab_14_1_port, outb => n4721);
U3089 : oai22 port map( a => n4719, b => n4721, c => n2103, d => n3418, outb
=> n2106);
U3090 : nand2 port map( a => mult_125_ab_0_1_port, b => mult_125_ab_1_0_port
, outb => n4722);
U3091 : aoi22 port map( a => mult_125_ab_2_0_port, b => n2108, c => n4724, d
=> n3398, outb => n4723);
U3092 : aoi22 port map( a => n2110, b => mult_125_ab_3_0_port, c => n4726, d
=> n3399, outb => n4725);
U3093 : inv port map( inb => mult_125_ab_4_0_port, outb => n4727);
U3094 : oai22 port map( a => n4725, b => n4727, c => n2111, d => n4728, outb
=> n2114);
U3095 : aoi22 port map( a => n2114, b => mult_125_ab_5_0_port, c => n4730, d
=> n3401, outb => n4729);
U3096 : inv port map( inb => mult_125_ab_6_0_port, outb => n4731);
U3097 : oai22 port map( a => n4729, b => n4731, c => n2115, d => n4732, outb
=> n2118);
U3098 : aoi22 port map( a => n2118, b => mult_125_ab_7_0_port, c => n4734, d
=> n3404, outb => n4733);
U3099 : inv port map( inb => mult_125_ab_8_0_port, outb => n4735);
U3100 : oai22 port map( a => n4733, b => n4735, c => n2119, d => n4736, outb
=> n2122);
U3101 : aoi22 port map( a => n2122, b => mult_125_ab_9_0_port, c => n4738, d
=> n3407, outb => n4737);
U3102 : inv port map( inb => mult_125_ab_10_0_port, outb => n4739);
U3103 : oai22 port map( a => n4737, b => n4739, c => n2123, d => n4740, outb
=> n2126);
U3104 : aoi22 port map( a => n2126, b => mult_125_ab_11_0_port, c => n4742,
d => n3410, outb => n4741);
U3105 : inv port map( inb => mult_125_ab_12_0_port, outb => n4743);
U3106 : oai22 port map( a => n4741, b => n4743, c => n2127, d => n4744, outb
=> n2130);
U3107 : aoi22 port map( a => n2130, b => mult_125_ab_13_0_port, c => n4746,
d => n3413, outb => n4745);
U3108 : inv port map( inb => mult_125_ab_14_0_port, outb => n4747);
U3109 : oai22 port map( a => n4745, b => n4747, c => n2131, d => n4748, outb
=> n2134);
U3110 : inv port map( inb => mult_125_ZB, outb => n308);
U3111 : inv port map( inb => mult_125_ZA, outb => n309);
U3112 : nand2 port map( a => adder_mem_array_3_0_port, b =>
multiplier_sigs_2_0_port, outb => n4749);
U3113 : inv port map( inb => multiplier_sigs_2_2_port, outb => n4750);
U3114 : inv port map( inb => adder_mem_array_3_2_port, outb => n4751);
U3115 : inv port map( inb => multiplier_sigs_2_4_port, outb => n4752);
U3116 : inv port map( inb => adder_mem_array_3_4_port, outb => n4753);
U3117 : inv port map( inb => multiplier_sigs_2_6_port, outb => n4754);
U3118 : inv port map( inb => adder_mem_array_3_6_port, outb => n4755);
U3119 : inv port map( inb => multiplier_sigs_2_8_port, outb => n4756);
U3120 : inv port map( inb => adder_mem_array_3_8_port, outb => n4757);
U3121 : inv port map( inb => multiplier_sigs_2_10_port, outb => n4758);
U3122 : inv port map( inb => adder_mem_array_3_10_port, outb => n4759);
U3123 : inv port map( inb => multiplier_sigs_2_12_port, outb => n4760);
U3124 : inv port map( inb => adder_mem_array_3_12_port, outb => n4761);
U3125 : inv port map( inb => multiplier_sigs_2_14_port, outb => n4762);
U3126 : inv port map( inb => adder_mem_array_3_14_port, outb => n4763);
U3127 : inv port map( inb => multiplier_sigs_2_16_port, outb => n4764);
U3128 : inv port map( inb => adder_mem_array_3_16_port, outb => n4765);
U3129 : inv port map( inb => multiplier_sigs_2_18_port, outb => n4766);
U3130 : inv port map( inb => adder_mem_array_3_18_port, outb => n4767);
U3131 : inv port map( inb => multiplier_sigs_2_20_port, outb => n4768);
U3132 : inv port map( inb => adder_mem_array_3_20_port, outb => n4769);
U3133 : inv port map( inb => multiplier_sigs_2_22_port, outb => n4770);
U3134 : inv port map( inb => adder_mem_array_3_22_port, outb => n4771);
U3135 : inv port map( inb => multiplier_sigs_2_24_port, outb => n4772);
U3136 : inv port map( inb => adder_mem_array_3_24_port, outb => n4773);
U3137 : inv port map( inb => multiplier_sigs_2_26_port, outb => n4774);
U3138 : inv port map( inb => adder_mem_array_3_26_port, outb => n4775);
U3139 : nand2 port map( a => adder_mem_array_1_0_port, b =>
multiplier_sigs_0_0_port, outb => n4776);
U3140 : inv port map( inb => multiplier_sigs_0_2_port, outb => n4777);
U3141 : inv port map( inb => adder_mem_array_1_2_port, outb => n4778);
U3142 : nand2 port map( a => adder_mem_array_2_0_port, b =>
multiplier_sigs_1_0_port, outb => n4779);
U3143 : inv port map( inb => multiplier_sigs_1_2_port, outb => n4780);
U3144 : inv port map( inb => adder_mem_array_2_2_port, outb => n4781);
U3145 : inv port map( inb => multiplier_sigs_1_4_port, outb => n4782);
U3146 : inv port map( inb => adder_mem_array_2_4_port, outb => n4783);
U3147 : inv port map( inb => multiplier_sigs_1_6_port, outb => n4784);
U3148 : inv port map( inb => adder_mem_array_2_6_port, outb => n4785);
U3149 : inv port map( inb => multiplier_sigs_1_8_port, outb => n4786);
U3150 : inv port map( inb => adder_mem_array_2_8_port, outb => n4787);
U3151 : inv port map( inb => multiplier_sigs_1_10_port, outb => n4788);
U3152 : inv port map( inb => adder_mem_array_2_10_port, outb => n4789);
U3153 : inv port map( inb => multiplier_sigs_1_12_port, outb => n4790);
U3154 : inv port map( inb => adder_mem_array_2_12_port, outb => n4791);
U3155 : inv port map( inb => multiplier_sigs_1_14_port, outb => n4792);
U3156 : inv port map( inb => adder_mem_array_2_14_port, outb => n4793);
U3157 : inv port map( inb => multiplier_sigs_1_16_port, outb => n4794);
U3158 : inv port map( inb => adder_mem_array_2_16_port, outb => n4795);
U3159 : inv port map( inb => multiplier_sigs_1_18_port, outb => n4796);
U3160 : inv port map( inb => adder_mem_array_2_18_port, outb => n4797);
U3161 : inv port map( inb => multiplier_sigs_1_20_port, outb => n4798);
U3162 : inv port map( inb => adder_mem_array_2_20_port, outb => n4799);
U3163 : inv port map( inb => multiplier_sigs_1_22_port, outb => n4800);
U3164 : inv port map( inb => adder_mem_array_2_22_port, outb => n4801);
U3165 : inv port map( inb => multiplier_sigs_1_24_port, outb => n4802);
U3166 : inv port map( inb => adder_mem_array_2_24_port, outb => n4803);
U3167 : inv port map( inb => multiplier_sigs_1_26_port, outb => n4804);
U3168 : inv port map( inb => adder_mem_array_2_26_port, outb => n4805);
U3169 : inv port map( inb => multiplier_sigs_1_28_port, outb => n4806);
U3170 : inv port map( inb => adder_mem_array_2_28_port, outb => n4807);
U3171 : inv port map( inb => multiplier_sigs_1_30_port, outb => n4808);
U3172 : inv port map( inb => adder_mem_array_2_30_port, outb => n4809);
U3173 : inv port map( inb => multiplier_sigs_0_4_port, outb => n4810);
U3174 : inv port map( inb => adder_mem_array_1_4_port, outb => n4811);
U3175 : inv port map( inb => multiplier_sigs_0_6_port, outb => n4812);
U3176 : inv port map( inb => adder_mem_array_1_6_port, outb => n4813);
U3177 : inv port map( inb => multiplier_sigs_0_8_port, outb => n4814);
U3178 : inv port map( inb => adder_mem_array_1_8_port, outb => n4815);
U3179 : inv port map( inb => multiplier_sigs_0_10_port, outb => n4816);
U3180 : inv port map( inb => adder_mem_array_1_10_port, outb => n4817);
U3181 : inv port map( inb => multiplier_sigs_0_12_port, outb => n4818);
U3182 : inv port map( inb => adder_mem_array_1_12_port, outb => n4819);
U3183 : inv port map( inb => multiplier_sigs_0_14_port, outb => n4820);
U3184 : inv port map( inb => adder_mem_array_1_14_port, outb => n4821);
U3185 : inv port map( inb => multiplier_sigs_0_16_port, outb => n4822);
U3186 : inv port map( inb => adder_mem_array_1_16_port, outb => n4823);
U3187 : inv port map( inb => multiplier_sigs_0_18_port, outb => n4824);
U3188 : inv port map( inb => adder_mem_array_1_18_port, outb => n4825);
U3189 : inv port map( inb => multiplier_sigs_0_20_port, outb => n4826);
U3190 : inv port map( inb => adder_mem_array_1_20_port, outb => n4827);
U3191 : inv port map( inb => multiplier_sigs_0_22_port, outb => n4828);
U3192 : inv port map( inb => adder_mem_array_1_22_port, outb => n4829);
U3193 : inv port map( inb => multiplier_sigs_0_24_port, outb => n4830);
U3194 : inv port map( inb => adder_mem_array_1_24_port, outb => n4831);
U3195 : inv port map( inb => multiplier_sigs_0_26_port, outb => n4832);
U3196 : inv port map( inb => adder_mem_array_1_26_port, outb => n4833);
U3197 : inv port map( inb => multiplier_sigs_0_28_port, outb => n4834);
U3198 : inv port map( inb => adder_mem_array_1_28_port, outb => n4835);
U3199 : inv port map( inb => multiplier_sigs_0_30_port, outb => n4836);
U3200 : inv port map( inb => adder_mem_array_1_30_port, outb => n4837);
U3201 : inv port map( inb => multiplier_sigs_2_28_port, outb => n4838);
U3202 : inv port map( inb => adder_mem_array_3_28_port, outb => n4839);
U3203 : inv port map( inb => multiplier_sigs_2_30_port, outb => n4840);
U3204 : inv port map( inb => adder_mem_array_3_30_port, outb => n4841);
U3205 : xor2 port map( a => mult_125_G4_ab_0_1_port, b =>
mult_125_G4_ab_1_0_port, outb =>
multiplier_sigs_3_1_port);
U3206 : xor2 port map( a => n3885, b => n4842, outb => mult_125_G4_A1_8_port
);
U3207 : xor2 port map( a => n3881, b => n4843, outb => mult_125_G4_A1_6_port
);
U3208 : xor2 port map( a => n3877, b => n4844, outb => mult_125_G4_A1_4_port
);
U3209 : xor2 port map( a => n3873, b => n4845, outb => mult_125_G4_A1_2_port
);
U3210 : xor2 port map( a => n243, b => n244, outb => mult_125_G4_A1_27_port)
;
U3211 : xor2 port map( a => n247, b => n248, outb => mult_125_G4_A1_25_port)
;
U3212 : xor2 port map( a => n251, b => n252, outb => mult_125_G4_A1_23_port)
;
U3213 : xor2 port map( a => n255, b => n256, outb => mult_125_G4_A1_21_port)
;
U3214 : xor2 port map( a => n259, b => n260, outb => mult_125_G4_A1_19_port)
;
U3215 : xor2 port map( a => n263, b => n264, outb => mult_125_G4_A1_17_port)
;
U3216 : xor2 port map( a => n268, b => n269, outb => mult_125_G4_A1_15_port)
;
U3217 : xor2 port map( a => n270, b => n271, outb => mult_125_G4_A1_14_port)
;
U3218 : xor2 port map( a => n3893, b => n4846, outb =>
mult_125_G4_A1_12_port);
U3219 : xor2 port map( a => n3889, b => n4847, outb =>
mult_125_G4_A1_10_port);
U3220 : xor2 port map( a => n2507, b => n4848, outb => mult_125_G4_A1_0_port
);
U3221 : xor2 port map( a => n4170, b => n4849, outb => mult_125_G3_A1_8_port
);
U3222 : xor2 port map( a => n4166, b => n4850, outb => mult_125_G3_A1_6_port
);
U3223 : xor2 port map( a => n4162, b => n4851, outb => mult_125_G3_A1_4_port
);
U3224 : xor2 port map( a => n4158, b => n4852, outb => mult_125_G3_A1_2_port
);
U3225 : xor2 port map( a => n351, b => n352, outb => mult_125_G3_A1_27_port)
;
U3226 : xor2 port map( a => n355, b => n356, outb => mult_125_G3_A1_25_port)
;
U3227 : xor2 port map( a => n359, b => n360, outb => mult_125_G3_A1_23_port)
;
U3228 : xor2 port map( a => n363, b => n364, outb => mult_125_G3_A1_21_port)
;
U3229 : xor2 port map( a => n367, b => n368, outb => mult_125_G3_A1_19_port)
;
U3230 : xor2 port map( a => n371, b => n372, outb => mult_125_G3_A1_17_port)
;
U3231 : xor2 port map( a => n376, b => n377, outb => mult_125_G3_A1_15_port)
;
U3232 : xor2 port map( a => n378, b => n379, outb => mult_125_G3_A1_14_port)
;
U3233 : xor2 port map( a => n4178, b => n4853, outb =>
mult_125_G3_A1_12_port);
U3234 : xor2 port map( a => n4174, b => n4854, outb =>
mult_125_G3_A1_10_port);
U3235 : xor2 port map( a => n2804, b => n4855, outb => mult_125_G3_A1_0_port
);
U3236 : xor2 port map( a => n4455, b => n4856, outb => mult_125_G2_A1_8_port
);
U3237 : xor2 port map( a => n4451, b => n4857, outb => mult_125_G2_A1_6_port
);
U3238 : xor2 port map( a => n4447, b => n4858, outb => mult_125_G2_A1_4_port
);
U3239 : xor2 port map( a => n4443, b => n4859, outb => mult_125_G2_A1_2_port
);
U3240 : xor2 port map( a => n315, b => n316, outb => mult_125_G2_A1_27_port)
;
U3241 : xor2 port map( a => n319, b => n320, outb => mult_125_G2_A1_25_port)
;
U3242 : xor2 port map( a => n323, b => n324, outb => mult_125_G2_A1_23_port)
;
U3243 : xor2 port map( a => n327, b => n328, outb => mult_125_G2_A1_21_port)
;
U3244 : xor2 port map( a => n331, b => n332, outb => mult_125_G2_A1_19_port)
;
U3245 : xor2 port map( a => n335, b => n336, outb => mult_125_G2_A1_17_port)
;
U3246 : xor2 port map( a => n340, b => n341, outb => mult_125_G2_A1_15_port)
;
U3247 : xor2 port map( a => n342, b => n343, outb => mult_125_G2_A1_14_port)
;
U3248 : xor2 port map( a => n4463, b => n4860, outb =>
mult_125_G2_A1_12_port);
U3249 : xor2 port map( a => n4459, b => n4861, outb =>
mult_125_G2_A1_10_port);
U3250 : xor2 port map( a => n3101, b => n4862, outb => mult_125_G2_A1_0_port
);
U3251 : xor2 port map( a => n4740, b => n4863, outb => mult_125_A1_8_port);
U3252 : xor2 port map( a => n4736, b => n4864, outb => mult_125_A1_6_port);
U3253 : xor2 port map( a => n4732, b => n4865, outb => mult_125_A1_4_port);
U3254 : xor2 port map( a => n4728, b => n4866, outb => mult_125_A1_2_port);
U3255 : xor2 port map( a => n279, b => n280, outb => mult_125_A1_27_port);
U3256 : xor2 port map( a => n283, b => n284, outb => mult_125_A1_25_port);
U3257 : xor2 port map( a => n287, b => n288, outb => mult_125_A1_23_port);
U3258 : xor2 port map( a => n291, b => n292, outb => mult_125_A1_21_port);
U3259 : xor2 port map( a => n295, b => n296, outb => mult_125_A1_19_port);
U3260 : xor2 port map( a => n299, b => n300, outb => mult_125_A1_17_port);
U3261 : xor2 port map( a => n304, b => n305, outb => mult_125_A1_15_port);
U3262 : xor2 port map( a => n306, b => n307, outb => mult_125_A1_14_port);
U3263 : xor2 port map( a => n4748, b => n4867, outb => mult_125_A1_12_port);
U3264 : xor2 port map( a => n4744, b => n4868, outb => mult_125_A1_10_port);
U3265 : xor2 port map( a => n3398, b => n4869, outb => mult_125_A1_0_port);
U3266 : xor2 port map( a => n3426, b => n4870, outb => N73);
U3267 : xor2 port map( a => adder_mem_array_3_0_port, b =>
multiplier_sigs_2_0_port, outb => N72);
U3268 : xor2 port map( a => n3447, b => n4871, outb => N7);
U3269 : xor2 port map( a => adder_mem_array_1_0_port, b =>
multiplier_sigs_0_0_port, outb => N6);
U3270 : xor2 port map( a => n3484, b => n4872, outb => N40);
U3271 : xor2 port map( a => adder_mem_array_2_0_port, b =>
multiplier_sigs_1_0_port, outb => N39);
U3272 : xor2 port map( a => mult_125_G4_QA, b => mult_125_G4_QB, outb =>
n2239);
U3273 : xor2 port map( a => mult_125_G4_ab_3_14_port, b =>
mult_125_G4_ab_2_15_port, outb => n4873);
U3274 : xor2 port map( a => mult_125_G4_ab_5_14_port, b =>
mult_125_G4_ab_4_15_port, outb => n4874);
U3275 : xor2 port map( a => mult_125_G4_ab_7_14_port, b =>
mult_125_G4_ab_6_15_port, outb => n4875);
U3276 : xor2 port map( a => mult_125_G4_ab_9_14_port, b =>
mult_125_G4_ab_8_15_port, outb => n4876);
U3277 : xor2 port map( a => mult_125_G4_ab_11_14_port, b =>
mult_125_G4_ab_10_15_port, outb => n4877);
U3278 : xor2 port map( a => mult_125_G4_ab_13_14_port, b =>
mult_125_G4_ab_12_15_port, outb => n4878);
U3279 : xor2 port map( a => mult_125_G4_ab_15_14_port, b =>
mult_125_G4_ab_14_15_port, outb => n4879);
U3280 : xor2 port map( a => mult_125_G4_ab_10_0_port, b => n3882, outb =>
n4842);
U3281 : xor2 port map( a => mult_125_G4_ab_8_0_port, b => n3878, outb =>
n4843);
U3282 : xor2 port map( a => mult_125_G4_ab_6_0_port, b => n3874, outb =>
n4844);
U3283 : xor2 port map( a => n3872, b => n798, outb => n4845);
U3284 : xor2 port map( a => mult_125_G4_ab_14_0_port, b => n3890, outb =>
n4846);
U3285 : xor2 port map( a => mult_125_G4_ab_12_0_port, b => n3886, outb =>
n4847);
U3286 : xor2 port map( a => n794, b => mult_125_G4_ab_2_0_port, outb =>
n4848);
U3287 : xor2 port map( a => mult_125_G3_QA, b => mult_125_G3_QB, outb =>
n2536);
U3288 : xor2 port map( a => mult_125_G3_ab_3_14_port, b =>
mult_125_G3_ab_2_15_port, outb => n4880);
U3289 : xor2 port map( a => mult_125_G3_ab_5_14_port, b =>
mult_125_G3_ab_4_15_port, outb => n4881);
U3290 : xor2 port map( a => mult_125_G3_ab_7_14_port, b =>
mult_125_G3_ab_6_15_port, outb => n4882);
U3291 : xor2 port map( a => mult_125_G3_ab_9_14_port, b =>
mult_125_G3_ab_8_15_port, outb => n4883);
U3292 : xor2 port map( a => mult_125_G3_ab_11_14_port, b =>
mult_125_G3_ab_10_15_port, outb => n4884);
U3293 : xor2 port map( a => mult_125_G3_ab_13_14_port, b =>
mult_125_G3_ab_12_15_port, outb => n4885);
U3294 : xor2 port map( a => mult_125_G3_ab_15_14_port, b =>
mult_125_G3_ab_14_15_port, outb => n4886);
U3295 : xor2 port map( a => mult_125_G3_ab_10_0_port, b => n4167, outb =>
n4849);
U3296 : xor2 port map( a => mult_125_G3_ab_8_0_port, b => n4163, outb =>
n4850);
U3297 : xor2 port map( a => mult_125_G3_ab_6_0_port, b => n4159, outb =>
n4851);
U3298 : xor2 port map( a => n4157, b => n1236, outb => n4852);
U3299 : xor2 port map( a => mult_125_G3_ab_14_0_port, b => n4175, outb =>
n4853);
U3300 : xor2 port map( a => mult_125_G3_ab_12_0_port, b => n4171, outb =>
n4854);
U3301 : xor2 port map( a => n1232, b => mult_125_G3_ab_2_0_port, outb =>
n4855);
U3302 : xor2 port map( a => mult_125_G2_QA, b => mult_125_G2_QB, outb =>
n2833);
U3303 : xor2 port map( a => mult_125_G2_ab_3_14_port, b =>
mult_125_G2_ab_2_15_port, outb => n4887);
U3304 : xor2 port map( a => mult_125_G2_ab_5_14_port, b =>
mult_125_G2_ab_4_15_port, outb => n4888);
U3305 : xor2 port map( a => mult_125_G2_ab_7_14_port, b =>
mult_125_G2_ab_6_15_port, outb => n4889);
U3306 : xor2 port map( a => mult_125_G2_ab_9_14_port, b =>
mult_125_G2_ab_8_15_port, outb => n4890);
U3307 : xor2 port map( a => mult_125_G2_ab_11_14_port, b =>
mult_125_G2_ab_10_15_port, outb => n4891);
U3308 : xor2 port map( a => mult_125_G2_ab_13_14_port, b =>
mult_125_G2_ab_12_15_port, outb => n4892);
U3309 : xor2 port map( a => mult_125_G2_ab_15_14_port, b =>
mult_125_G2_ab_14_15_port, outb => n4893);
U3310 : xor2 port map( a => mult_125_G2_ab_10_0_port, b => n4452, outb =>
n4856);
U3311 : xor2 port map( a => mult_125_G2_ab_8_0_port, b => n4448, outb =>
n4857);
U3312 : xor2 port map( a => mult_125_G2_ab_6_0_port, b => n4444, outb =>
n4858);
U3313 : xor2 port map( a => n4442, b => n1674, outb => n4859);
U3314 : xor2 port map( a => mult_125_G2_ab_14_0_port, b => n4460, outb =>
n4860);
U3315 : xor2 port map( a => mult_125_G2_ab_12_0_port, b => n4456, outb =>
n4861);
U3316 : xor2 port map( a => n1670, b => mult_125_G2_ab_2_0_port, outb =>
n4862);
U3317 : xor2 port map( a => mult_125_QA, b => mult_125_QB, outb => n3130);
U3318 : xor2 port map( a => mult_125_ab_3_14_port, b =>
mult_125_ab_2_15_port, outb => n4894);
U3319 : xor2 port map( a => mult_125_ab_5_14_port, b =>
mult_125_ab_4_15_port, outb => n4895);
U3320 : xor2 port map( a => mult_125_ab_7_14_port, b =>
mult_125_ab_6_15_port, outb => n4896);
U3321 : xor2 port map( a => mult_125_ab_9_14_port, b =>
mult_125_ab_8_15_port, outb => n4897);
U3322 : xor2 port map( a => mult_125_ab_11_14_port, b =>
mult_125_ab_10_15_port, outb => n4898);
U3323 : xor2 port map( a => mult_125_ab_13_14_port, b =>
mult_125_ab_12_15_port, outb => n4899);
U3324 : xor2 port map( a => mult_125_ab_15_14_port, b =>
mult_125_ab_14_15_port, outb => n4900);
U3325 : xor2 port map( a => mult_125_ab_10_0_port, b => n4737, outb => n4863
);
U3326 : xor2 port map( a => mult_125_ab_8_0_port, b => n4733, outb => n4864)
;
U3327 : xor2 port map( a => mult_125_ab_6_0_port, b => n4729, outb => n4865)
;
U3328 : xor2 port map( a => n4727, b => n2112, outb => n4866);
U3329 : xor2 port map( a => mult_125_ab_14_0_port, b => n4745, outb => n4867
);
U3330 : xor2 port map( a => mult_125_ab_12_0_port, b => n4741, outb => n4868
);
U3331 : xor2 port map( a => n2108, b => mult_125_ab_2_0_port, outb => n4869)
;
U3332 : xor2 port map( a => adder_mem_array_3_27_port, b =>
multiplier_sigs_2_27_port, outb => n3428);
U3333 : xor2 port map( a => adder_mem_array_3_25_port, b =>
multiplier_sigs_2_25_port, outb => n3432);
U3334 : xor2 port map( a => adder_mem_array_3_23_port, b =>
multiplier_sigs_2_23_port, outb => n3436);
U3335 : xor2 port map( a => adder_mem_array_3_21_port, b =>
multiplier_sigs_2_21_port, outb => n3440);
U3336 : xor2 port map( a => adder_mem_array_3_19_port, b =>
multiplier_sigs_2_19_port, outb => n3444);
U3337 : xor2 port map( a => adder_mem_array_1_3_port, b =>
multiplier_sigs_0_3_port, outb => n3449);
U3338 : xor2 port map( a => adder_mem_array_3_17_port, b =>
multiplier_sigs_2_17_port, outb => n3451);
U3339 : xor2 port map( a => adder_mem_array_3_15_port, b =>
multiplier_sigs_2_15_port, outb => n3455);
U3340 : xor2 port map( a => adder_mem_array_3_13_port, b =>
multiplier_sigs_2_13_port, outb => n3459);
U3341 : xor2 port map( a => adder_mem_array_3_11_port, b =>
multiplier_sigs_2_11_port, outb => n3463);
U3342 : xor2 port map( a => adder_mem_array_3_9_port, b =>
multiplier_sigs_2_9_port, outb => n3467);
U3343 : xor2 port map( a => adder_mem_array_3_7_port, b =>
multiplier_sigs_2_7_port, outb => n3473);
U3344 : xor2 port map( a => adder_mem_array_3_5_port, b =>
multiplier_sigs_2_5_port, outb => n3477);
U3345 : xor2 port map( a => adder_mem_array_3_3_port, b =>
multiplier_sigs_2_3_port, outb => n3481);
U3346 : xor2 port map( a => n2137, b => adder_mem_array_3_1_port, outb =>
n4870);
U3347 : xor2 port map( a => adder_mem_array_2_31_port, b =>
multiplier_sigs_1_31_port, outb => n3486);
U3348 : xor2 port map( a => n2164, b => adder_mem_array_1_1_port, outb =>
n4871);
U3349 : xor2 port map( a => adder_mem_array_2_29_port, b =>
multiplier_sigs_1_29_port, outb => n3490);
U3350 : xor2 port map( a => adder_mem_array_2_27_port, b =>
multiplier_sigs_1_27_port, outb => n3494);
U3351 : xor2 port map( a => adder_mem_array_2_25_port, b =>
multiplier_sigs_1_25_port, outb => n3498);
U3352 : xor2 port map( a => adder_mem_array_2_23_port, b =>
multiplier_sigs_1_23_port, outb => n3502);
U3353 : xor2 port map( a => adder_mem_array_2_21_port, b =>
multiplier_sigs_1_21_port, outb => n3506);
U3354 : xor2 port map( a => adder_mem_array_2_19_port, b =>
multiplier_sigs_1_19_port, outb => n3510);
U3355 : xor2 port map( a => adder_mem_array_2_17_port, b =>
multiplier_sigs_1_17_port, outb => n3514);
U3356 : xor2 port map( a => adder_mem_array_2_15_port, b =>
multiplier_sigs_1_15_port, outb => n3518);
U3357 : xor2 port map( a => adder_mem_array_2_13_port, b =>
multiplier_sigs_1_13_port, outb => n3522);
U3358 : xor2 port map( a => adder_mem_array_2_11_port, b =>
multiplier_sigs_1_11_port, outb => n3526);
U3359 : xor2 port map( a => adder_mem_array_2_9_port, b =>
multiplier_sigs_1_9_port, outb => n3530);
U3360 : xor2 port map( a => adder_mem_array_2_7_port, b =>
multiplier_sigs_1_7_port, outb => n3534);
U3361 : xor2 port map( a => adder_mem_array_2_5_port, b =>
multiplier_sigs_1_5_port, outb => n3538);
U3362 : xor2 port map( a => adder_mem_array_2_3_port, b =>
multiplier_sigs_1_3_port, outb => n3542);
U3363 : xor2 port map( a => n2167, b => adder_mem_array_2_1_port, outb =>
n4872);
U3364 : xor2 port map( a => adder_mem_array_1_31_port, b =>
multiplier_sigs_0_31_port, outb => n3546);
U3365 : xor2 port map( a => adder_mem_array_1_29_port, b =>
multiplier_sigs_0_29_port, outb => n3550);
U3366 : xor2 port map( a => adder_mem_array_1_27_port, b =>
multiplier_sigs_0_27_port, outb => n3554);
U3367 : xor2 port map( a => adder_mem_array_1_25_port, b =>
multiplier_sigs_0_25_port, outb => n3558);
U3368 : xor2 port map( a => adder_mem_array_1_23_port, b =>
multiplier_sigs_0_23_port, outb => n3562);
U3369 : xor2 port map( a => adder_mem_array_1_21_port, b =>
multiplier_sigs_0_21_port, outb => n3566);
U3370 : xor2 port map( a => adder_mem_array_1_19_port, b =>
multiplier_sigs_0_19_port, outb => n3570);
U3371 : xor2 port map( a => adder_mem_array_1_17_port, b =>
multiplier_sigs_0_17_port, outb => n3574);
U3372 : xor2 port map( a => adder_mem_array_1_15_port, b =>
multiplier_sigs_0_15_port, outb => n3578);
U3373 : xor2 port map( a => adder_mem_array_1_13_port, b =>
multiplier_sigs_0_13_port, outb => n3582);
U3374 : xor2 port map( a => adder_mem_array_1_11_port, b =>
multiplier_sigs_0_11_port, outb => n3586);
U3375 : xor2 port map( a => adder_mem_array_1_9_port, b =>
multiplier_sigs_0_9_port, outb => n3590);
U3376 : xor2 port map( a => adder_mem_array_1_7_port, b =>
multiplier_sigs_0_7_port, outb => n3594);
U3377 : xor2 port map( a => adder_mem_array_1_5_port, b =>
multiplier_sigs_0_5_port, outb => n3598);
U3378 : xor2 port map( a => adder_mem_array_3_31_port, b =>
multiplier_sigs_2_31_port, outb => n3600);
U3379 : xor2 port map( a => adder_mem_array_3_29_port, b =>
multiplier_sigs_2_29_port, outb => n3604);
U3380 : oai22 port map( a => n4902, b => n4903, c => n384, d => n3609, outb
=> n4901);
U3381 : aoi22 port map( a => mult_125_G4_ab_2_15_port, b =>
mult_125_G4_ab_3_14_port, c => n4901, d => n4905,
outb => n4904);
U3382 : oai22 port map( a => n3610, b => n3611, c => n4904, d => n386, outb
=> n4906);
U3383 : aoi22 port map( a => mult_125_G4_ab_4_15_port, b =>
mult_125_G4_ab_5_14_port, c => n4906, d => n4908,
outb => n4907);
U3384 : oai22 port map( a => n3612, b => n3613, c => n4907, d => n388, outb
=> n4909);
U3385 : aoi22 port map( a => mult_125_G4_ab_6_15_port, b =>
mult_125_G4_ab_7_14_port, c => n4909, d => n4911,
outb => n4910);
U3386 : oai22 port map( a => n3614, b => n3615, c => n4910, d => n390, outb
=> n4912);
U3387 : aoi22 port map( a => mult_125_G4_ab_8_15_port, b =>
mult_125_G4_ab_9_14_port, c => n4912, d => n4914,
outb => n4913);
U3388 : oai22 port map( a => n3616, b => n3617, c => n4913, d => n392, outb
=> n4915);
U3389 : aoi22 port map( a => mult_125_G4_ab_10_15_port, b =>
mult_125_G4_ab_11_14_port, c => n4915, d => n4917,
outb => n4916);
U3390 : oai22 port map( a => n3618, b => n3619, c => n4916, d => n394, outb
=> n4918);
U3391 : aoi22 port map( a => mult_125_G4_ab_12_15_port, b =>
mult_125_G4_ab_13_14_port, c => n4918, d => n4920,
outb => n4919);
U3392 : aoi22 port map( a => mult_125_G4_ab_13_15_port, b =>
mult_125_G4_ab_14_14_port, c => n4922, d => n4923,
outb => n4921);
U3393 : aoi22 port map( a => mult_125_G4_ab_14_15_port, b =>
mult_125_G4_ab_15_14_port, c => n4924, d => n4925,
outb => n241);
U3394 : inv port map( inb => n3637, outb => n427);
U3395 : aoi22 port map( a => n427, b => mult_125_G4_ab_15_13_port, c =>
n4926, d => n2280, outb => n243);
U3396 : aoi22 port map( a => n456, b => mult_125_G4_ab_15_12_port, c =>
n4927, d => n2276, outb => n245);
U3397 : oai22 port map( a => n487, b => n486, c => n4929, d => n2321, outb
=> n4928);
U3398 : inv port map( inb => n503, outb => n3687);
U3399 : aoi22 port map( a => n517, b => mult_125_G4_ab_15_10_port, c =>
n4930, d => n2317, outb => n249);
U3400 : oai22 port map( a => n547, b => n546, c => n4932, d => n2362, outb
=> n4931);
U3401 : inv port map( inb => n566, outb => n3731);
U3402 : aoi22 port map( a => n576, b => mult_125_G4_ab_15_8_port, c => n4933
, d => n2358, outb => n253);
U3403 : oai22 port map( a => n607, b => n606, c => n4935, d => n2403, outb
=> n4934);
U3404 : inv port map( inb => n632, outb => n3771);
U3405 : aoi22 port map( a => n638, b => mult_125_G4_ab_15_6_port, c => n4936
, d => n2399, outb => n257);
U3406 : oai22 port map( a => n670, b => n669, c => n4938, d => n2444, outb
=> n4937);
U3407 : aoi22 port map( a => n4939, b => mult_125_G4_ab_15_4_port, c => n701
, d => n2440, outb => n261);
U3408 : aoi22 port map( a => n733, b => mult_125_G4_ab_15_3_port, c => n4940
, d => n2485, outb => n263);
U3409 : oai22 port map( a => n3845, b => n4941, c => n762, d => n2481, outb
=> n266);
U3410 : aoi22 port map( a => n792, b => mult_125_G4_ab_15_1_port, c => n4942
, d => n2504, outb => n268);
U3411 : aoi22 port map( a => n820, b => mult_125_G4_ab_15_0_port, c => n4943
, d => n4944, outb => n270);
U3412 : xor2 port map( a => n4901, b => n4873, outb => n2248);
U3413 : xor2 port map( a => n4945, b => n4904, outb => n2251);
U3414 : xor2 port map( a => n4906, b => n4874, outb => n2254);
U3415 : xor2 port map( a => n4946, b => n4907, outb => n2257);
U3416 : xor2 port map( a => n4909, b => n4875, outb => n2260);
U3417 : xor2 port map( a => n4947, b => n4910, outb => n2263);
U3418 : xor2 port map( a => n4912, b => n4876, outb => n2266);
U3419 : xor2 port map( a => n4948, b => n4913, outb => n2269);
U3420 : xor2 port map( a => n4915, b => n4877, outb => n2272);
U3421 : xor2 port map( a => n4949, b => n4916, outb => n2275);
U3422 : xor2 port map( a => n4918, b => n4878, outb => n2278);
U3423 : xor2 port map( a => n4950, b => n4922, outb => n2280);
U3424 : xor2 port map( a => n4921, b => n4879, outb => n244);
U3425 : xor2 port map( a => n4951, b => n2241, outb => n2286);
U3426 : xor2 port map( a => n4952, b => n2244, outb => n2292);
U3427 : xor2 port map( a => n4953, b => n2246, outb => n2295);
U3428 : xor2 port map( a => n4954, b => n2249, outb => n2298);
U3429 : xor2 port map( a => n4955, b => n2252, outb => n2301);
U3430 : xor2 port map( a => n4956, b => n2255, outb => n2304);
U3431 : xor2 port map( a => n4957, b => n2258, outb => n2307);
U3432 : xor2 port map( a => n4958, b => n2261, outb => n2310);
U3433 : xor2 port map( a => n4959, b => n2264, outb => n2313);
U3434 : xor2 port map( a => n4960, b => n2267, outb => n2316);
U3435 : xor2 port map( a => n4961, b => n2270, outb => n2319);
U3436 : xor2 port map( a => n4962, b => n2273, outb => n2321);
U3437 : xor2 port map( a => n4963, b => n2276, outb => n248);
U3438 : xor2 port map( a => n4964, b => n2282, outb => n2327);
U3439 : xor2 port map( a => n4965, b => n2284, outb => n2330);
U3440 : xor2 port map( a => n4966, b => n2288, outb => n2336);
U3441 : xor2 port map( a => n4967, b => n2290, outb => n2339);
U3442 : xor2 port map( a => n4968, b => n2293, outb => n2342);
U3443 : xor2 port map( a => n4969, b => n2296, outb => n2345);
U3444 : xor2 port map( a => n4970, b => n2299, outb => n2348);
U3445 : xor2 port map( a => n4971, b => n2302, outb => n2351);
U3446 : xor2 port map( a => n4972, b => n2305, outb => n2354);
U3447 : xor2 port map( a => n4973, b => n2308, outb => n2357);
U3448 : xor2 port map( a => n4974, b => n2311, outb => n2360);
U3449 : xor2 port map( a => n4975, b => n2314, outb => n2362);
U3450 : xor2 port map( a => n4976, b => n2317, outb => n252);
U3451 : xor2 port map( a => n4977, b => n2323, outb => n2368);
U3452 : xor2 port map( a => n4978, b => n2325, outb => n2371);
U3453 : xor2 port map( a => n4979, b => n2328, outb => n2374);
U3454 : xor2 port map( a => n4980, b => n2332, outb => n2380);
U3455 : xor2 port map( a => n4981, b => n2334, outb => n2383);
U3456 : xor2 port map( a => n4982, b => n2337, outb => n2386);
U3457 : xor2 port map( a => n4983, b => n2340, outb => n2389);
U3458 : xor2 port map( a => n4984, b => n2343, outb => n2392);
U3459 : xor2 port map( a => n4985, b => n2346, outb => n2395);
U3460 : xor2 port map( a => n4986, b => n2349, outb => n2398);
U3461 : xor2 port map( a => n4987, b => n2352, outb => n2401);
U3462 : xor2 port map( a => n4988, b => n2355, outb => n2403);
U3463 : xor2 port map( a => n4989, b => n2358, outb => n256);
U3464 : xor2 port map( a => n4990, b => n2364, outb => n2409);
U3465 : xor2 port map( a => n4991, b => n2366, outb => n2412);
U3466 : xor2 port map( a => n4992, b => n2369, outb => n2415);
U3467 : xor2 port map( a => n4993, b => n2372, outb => n2418);
U3468 : xor2 port map( a => n4994, b => n2376, outb => n2424);
U3469 : xor2 port map( a => n4995, b => n2378, outb => n2427);
U3470 : xor2 port map( a => n4996, b => n2381, outb => n2430);
U3471 : xor2 port map( a => n4997, b => n2384, outb => n2433);
U3472 : xor2 port map( a => n4998, b => n2387, outb => n2436);
U3473 : xor2 port map( a => n4999, b => n2390, outb => n2439);
U3474 : xor2 port map( a => n5000, b => n2393, outb => n2442);
U3475 : xor2 port map( a => n5001, b => n2396, outb => n2444);
U3476 : xor2 port map( a => n5002, b => n2399, outb => n260);
U3477 : xor2 port map( a => n5003, b => n2405, outb => n2450);
U3478 : xor2 port map( a => n5004, b => n2407, outb => n2453);
U3479 : xor2 port map( a => n5005, b => n2410, outb => n2456);
U3480 : xor2 port map( a => n5006, b => n2413, outb => n2459);
U3481 : xor2 port map( a => n5007, b => n2416, outb => n2462);
U3482 : xor2 port map( a => n5008, b => n2420, outb => n2468);
U3483 : xor2 port map( a => n5009, b => n2422, outb => n2471);
U3484 : xor2 port map( a => n5010, b => n2425, outb => n2474);
U3485 : xor2 port map( a => n5011, b => n2428, outb => n2477);
U3486 : xor2 port map( a => n5012, b => n2431, outb => n2480);
U3487 : xor2 port map( a => n5013, b => n2434, outb => n2483);
U3488 : xor2 port map( a => n5014, b => n2437, outb => n2485);
U3489 : xor2 port map( a => n5015, b => n2440, outb => n264);
U3490 : xor2 port map( a => n5016, b => n2446, outb => n2491);
U3491 : xor2 port map( a => n5017, b => n2448, outb => n2494);
U3492 : xor2 port map( a => n5018, b => n2451, outb => n2497);
U3493 : xor2 port map( a => n5019, b => n2454, outb => n2500);
U3494 : xor2 port map( a => n5020, b => n2457, outb => n2503);
U3495 : xor2 port map( a => n5021, b => n2460, outb => n2506);
U3496 : xor2 port map( a => n5022, b => n2464, outb => n2512);
U3497 : xor2 port map( a => n5023, b => n2466, outb => n2515);
U3498 : xor2 port map( a => n5024, b => n2469, outb => n2518);
U3499 : xor2 port map( a => n5025, b => n2472, outb => n2521);
U3500 : xor2 port map( a => n5026, b => n2475, outb => n2524);
U3501 : xor2 port map( a => n5027, b => n2478, outb => n2527);
U3502 : xor2 port map( a => n5028, b => n2481, outb => n269);
U3503 : xor2 port map( a => n5029, b => n2487, outb => n3873);
U3504 : xor2 port map( a => n5030, b => n2489, outb => n3877);
U3505 : xor2 port map( a => n5031, b => n2492, outb => n3881);
U3506 : xor2 port map( a => n5032, b => n2495, outb => n3885);
U3507 : xor2 port map( a => n5033, b => n2498, outb => n3889);
U3508 : xor2 port map( a => n5034, b => n2501, outb => n3893);
U3509 : inv port map( inb => n2525, outb => n4944);
U3510 : xor2 port map( a => n5035, b => n2504, outb => n271);
U3511 : xor2 port map( a => n5036, b => n2525, outb => n275);
U3512 : xor2 port map( a => n3609, b => mult_125_G4_ab_2_14_port, outb =>
n2242);
U3513 : xor2 port map( a => n3610, b => n3611, outb => n4945);
U3514 : xor2 port map( a => n3612, b => n3613, outb => n4946);
U3515 : xor2 port map( a => n3614, b => n3615, outb => n4947);
U3516 : xor2 port map( a => n3616, b => n3617, outb => n4948);
U3517 : xor2 port map( a => n3618, b => n3619, outb => n4949);
U3518 : xor2 port map( a => mult_125_G4_ab_13_15_port, b =>
mult_125_G4_ab_14_14_port, outb => n4950);
U3519 : xor2 port map( a => n3620, b => n399, outb => n2245);
U3520 : xor2 port map( a => mult_125_G4_ab_3_13_port, b => n403, outb =>
n4951);
U3521 : xor2 port map( a => mult_125_G4_ab_4_13_port, b => n405, outb =>
n2247);
U3522 : xor2 port map( a => mult_125_G4_ab_5_13_port, b => n407, outb =>
n2250);
U3523 : xor2 port map( a => mult_125_G4_ab_6_13_port, b => n409, outb =>
n2253);
U3524 : xor2 port map( a => n3627, b => n3625, outb => n2256);
U3525 : xor2 port map( a => mult_125_G4_ab_8_13_port, b => n413, outb =>
n2259);
U3526 : xor2 port map( a => n3630, b => n3628, outb => n2262);
U3527 : xor2 port map( a => mult_125_G4_ab_10_13_port, b => n417, outb =>
n2265);
U3528 : xor2 port map( a => n3633, b => n3631, outb => n2268);
U3529 : xor2 port map( a => mult_125_G4_ab_12_13_port, b => n421, outb =>
n2271);
U3530 : xor2 port map( a => n3636, b => n3634, outb => n2274);
U3531 : xor2 port map( a => mult_125_G4_ab_14_13_port, b => n425, outb =>
n2277);
U3532 : xor2 port map( a => mult_125_G4_ab_15_13_port, b => n3637, outb =>
n2279);
U3533 : xor2 port map( a => n430, b => mult_125_G4_ab_2_12_port, outb =>
n2283);
U3534 : xor2 port map( a => n3641, b => n3639, outb => n4952);
U3535 : xor2 port map( a => mult_125_G4_ab_4_12_port, b => n434, outb =>
n2285);
U3536 : xor2 port map( a => mult_125_G4_ab_5_12_port, b => n3642, outb =>
n4953);
U3537 : xor2 port map( a => n3646, b => n3644, outb => n4954);
U3538 : xor2 port map( a => mult_125_G4_ab_7_12_port, b => n440, outb =>
n4955);
U3539 : xor2 port map( a => n3649, b => n3647, outb => n4956);
U3540 : xor2 port map( a => mult_125_G4_ab_9_12_port, b => n444, outb =>
n4957);
U3541 : xor2 port map( a => n3652, b => n3650, outb => n4958);
U3542 : xor2 port map( a => mult_125_G4_ab_11_12_port, b => n448, outb =>
n4959);
U3543 : xor2 port map( a => n3655, b => n3653, outb => n4960);
U3544 : xor2 port map( a => mult_125_G4_ab_13_12_port, b => n452, outb =>
n4961);
U3545 : xor2 port map( a => n3658, b => n3656, outb => n4962);
U3546 : xor2 port map( a => n5037, b => n456, outb => n4963);
U3547 : xor2 port map( a => n459, b => mult_125_G4_ab_2_11_port, outb =>
n2289);
U3548 : xor2 port map( a => mult_125_G4_ab_3_11_port, b => n462, outb =>
n4964);
U3549 : xor2 port map( a => n3662, b => n3661, outb => n2291);
U3550 : xor2 port map( a => mult_125_G4_ab_5_11_port, b => n466, outb =>
n4965);
U3551 : xor2 port map( a => mult_125_G4_ab_6_11_port, b => n468, outb =>
n2294);
U3552 : xor2 port map( a => n3667, b => n3666, outb => n2297);
U3553 : xor2 port map( a => mult_125_G4_ab_8_11_port, b => n472, outb =>
n2300);
U3554 : xor2 port map( a => n3670, b => n3668, outb => n2303);
U3555 : xor2 port map( a => mult_125_G4_ab_10_11_port, b => n476, outb =>
n2306);
U3556 : xor2 port map( a => n3673, b => n3671, outb => n2309);
U3557 : xor2 port map( a => mult_125_G4_ab_12_11_port, b => n480, outb =>
n2312);
U3558 : xor2 port map( a => n3676, b => n3674, outb => n2315);
U3559 : xor2 port map( a => mult_125_G4_ab_14_11_port, b => n484, outb =>
n2318);
U3560 : xor2 port map( a => n486, b => n487, outb => n2320);
U3561 : xor2 port map( a => n490, b => mult_125_G4_ab_2_10_port, outb =>
n2324);
U3562 : xor2 port map( a => n3680, b => n3678, outb => n4966);
U3563 : xor2 port map( a => mult_125_G4_ab_4_10_port, b => n494, outb =>
n2326);
U3564 : xor2 port map( a => n496, b => n497, outb => n4967);
U3565 : xor2 port map( a => mult_125_G4_ab_6_10_port, b => n499, outb =>
n2329);
U3566 : xor2 port map( a => mult_125_G4_ab_7_10_port, b => n501, outb =>
n4968);
U3567 : xor2 port map( a => n3686, b => n3687, outb => n4969);
U3568 : xor2 port map( a => mult_125_G4_ab_9_10_port, b => n505, outb =>
n4970);
U3569 : xor2 port map( a => n3690, b => n3688, outb => n4971);
U3570 : xor2 port map( a => mult_125_G4_ab_11_10_port, b => n509, outb =>
n4972);
U3571 : xor2 port map( a => n3693, b => n3691, outb => n4973);
U3572 : xor2 port map( a => mult_125_G4_ab_13_10_port, b => n513, outb =>
n4974);
U3573 : xor2 port map( a => n3696, b => n3694, outb => n4975);
U3574 : xor2 port map( a => n5038, b => n517, outb => n4976);
U3575 : xor2 port map( a => n520, b => mult_125_G4_ab_2_9_port, outb =>
n2333);
U3576 : xor2 port map( a => n3699, b => n3697, outb => n4977);
U3577 : xor2 port map( a => mult_125_G4_ab_4_9_port, b => n524, outb =>
n2335);
U3578 : xor2 port map( a => mult_125_G4_ab_5_9_port, b => n526, outb =>
n4978);
U3579 : xor2 port map( a => mult_125_G4_ab_6_9_port, b => n528, outb =>
n2338);
U3580 : xor2 port map( a => mult_125_G4_ab_7_9_port, b => n530, outb =>
n4979);
U3581 : xor2 port map( a => n3707, b => n3705, outb => n2341);
U3582 : xor2 port map( a => n3709, b => n3708, outb => n2344);
U3583 : xor2 port map( a => mult_125_G4_ab_10_9_port, b => n536, outb =>
n2347);
U3584 : xor2 port map( a => n3712, b => n3710, outb => n2350);
U3585 : xor2 port map( a => mult_125_G4_ab_12_9_port, b => n540, outb =>
n2353);
U3586 : xor2 port map( a => n3715, b => n3713, outb => n2356);
U3587 : xor2 port map( a => mult_125_G4_ab_14_9_port, b => n544, outb =>
n2359);
U3588 : xor2 port map( a => n546, b => n547, outb => n2361);
U3589 : xor2 port map( a => n550, b => mult_125_G4_ab_2_8_port, outb =>
n2365);
U3590 : xor2 port map( a => n3719, b => n3717, outb => n4980);
U3591 : xor2 port map( a => n3721, b => n554, outb => n2367);
U3592 : xor2 port map( a => n3723, b => n3722, outb => n4981);
U3593 : xor2 port map( a => mult_125_G4_ab_6_8_port, b => n558, outb =>
n2370);
U3594 : xor2 port map( a => n3726, b => n3724, outb => n4982);
U3595 : xor2 port map( a => mult_125_G4_ab_8_8_port, b => n562, outb =>
n2373);
U3596 : xor2 port map( a => mult_125_G4_ab_9_8_port, b => n564, outb =>
n4983);
U3597 : xor2 port map( a => n3730, b => n3731, outb => n4984);
U3598 : xor2 port map( a => mult_125_G4_ab_11_8_port, b => n568, outb =>
n4985);
U3599 : xor2 port map( a => n3734, b => n3732, outb => n4986);
U3600 : xor2 port map( a => mult_125_G4_ab_13_8_port, b => n572, outb =>
n4987);
U3601 : xor2 port map( a => n3737, b => n3735, outb => n4988);
U3602 : xor2 port map( a => n5039, b => n576, outb => n4989);
U3603 : xor2 port map( a => n579, b => mult_125_G4_ab_2_7_port, outb =>
n2377);
U3604 : xor2 port map( a => mult_125_G4_ab_3_7_port, b => n582, outb =>
n4990);
U3605 : xor2 port map( a => n3741, b => n3740, outb => n2379);
U3606 : xor2 port map( a => mult_125_G4_ab_5_7_port, b => n586, outb =>
n4991);
U3607 : xor2 port map( a => n3744, b => n3742, outb => n2382);
U3608 : xor2 port map( a => mult_125_G4_ab_7_7_port, b => n590, outb =>
n4992);
U3609 : xor2 port map( a => n3747, b => n3745, outb => n2385);
U3610 : xor2 port map( a => mult_125_G4_ab_9_7_port, b => n594, outb =>
n4993);
U3611 : xor2 port map( a => n3750, b => n3748, outb => n2388);
U3612 : xor2 port map( a => n3752, b => n3751, outb => n2391);
U3613 : xor2 port map( a => mult_125_G4_ab_12_7_port, b => n600, outb =>
n2394);
U3614 : xor2 port map( a => n3755, b => n3753, outb => n2397);
U3615 : xor2 port map( a => mult_125_G4_ab_14_7_port, b => n604, outb =>
n2400);
U3616 : xor2 port map( a => n606, b => n607, outb => n2402);
U3617 : xor2 port map( a => n610, b => mult_125_G4_ab_2_6_port, outb =>
n2406);
U3618 : xor2 port map( a => n3759, b => n3757, outb => n4994);
U3619 : xor2 port map( a => mult_125_G4_ab_4_6_port, b => n614, outb =>
n2408);
U3620 : xor2 port map( a => n616, b => n617, outb => n4995);
U3621 : xor2 port map( a => mult_125_G4_ab_6_6_port, b => n619, outb =>
n2411);
U3622 : xor2 port map( a => n3764, b => n3762, outb => n4996);
U3623 : xor2 port map( a => mult_125_G4_ab_8_6_port, b => n623, outb =>
n2414);
U3624 : xor2 port map( a => n625, b => n626, outb => n4997);
U3625 : xor2 port map( a => mult_125_G4_ab_10_6_port, b => n628, outb =>
n2417);
U3626 : xor2 port map( a => mult_125_G4_ab_11_6_port, b => n630, outb =>
n4998);
U3627 : xor2 port map( a => n3770, b => n3771, outb => n4999);
U3628 : xor2 port map( a => mult_125_G4_ab_13_6_port, b => n634, outb =>
n5000);
U3629 : xor2 port map( a => n3774, b => n3772, outb => n5001);
U3630 : xor2 port map( a => n5040, b => n638, outb => n5002);
U3631 : xor2 port map( a => n641, b => mult_125_G4_ab_2_5_port, outb =>
n2421);
U3632 : xor2 port map( a => mult_125_G4_ab_3_5_port, b => n644, outb =>
n5003);
U3633 : xor2 port map( a => mult_125_G4_ab_4_5_port, b => n646, outb =>
n2423);
U3634 : xor2 port map( a => mult_125_G4_ab_5_5_port, b => n648, outb =>
n5004);
U3635 : xor2 port map( a => n650, b => n651, outb => n2426);
U3636 : xor2 port map( a => mult_125_G4_ab_7_5_port, b => n653, outb =>
n5005);
U3637 : xor2 port map( a => mult_125_G4_ab_8_5_port, b => n655, outb =>
n2429);
U3638 : xor2 port map( a => mult_125_G4_ab_9_5_port, b => n657, outb =>
n5006);
U3639 : xor2 port map( a => n3786, b => n3784, outb => n2432);
U3640 : xor2 port map( a => mult_125_G4_ab_11_5_port, b => n661, outb =>
n5007);
U3641 : xor2 port map( a => n3789, b => n3787, outb => n2435);
U3642 : xor2 port map( a => n3791, b => n665, outb => n2438);
U3643 : xor2 port map( a => mult_125_G4_ab_14_5_port, b => n667, outb =>
n2441);
U3644 : xor2 port map( a => n669, b => n670, outb => n2443);
U3645 : xor2 port map( a => n673, b => mult_125_G4_ab_2_4_port, outb =>
n2447);
U3646 : xor2 port map( a => n3795, b => n3793, outb => n5008);
U3647 : xor2 port map( a => mult_125_G4_ab_4_4_port, b => n677, outb =>
n2449);
U3648 : xor2 port map( a => n679, b => n680, outb => n5009);
U3649 : xor2 port map( a => mult_125_G4_ab_6_4_port, b => n682, outb =>
n2452);
U3650 : xor2 port map( a => n684, b => n685, outb => n5010);
U3651 : xor2 port map( a => mult_125_G4_ab_8_4_port, b => n687, outb =>
n2455);
U3652 : xor2 port map( a => mult_125_G4_ab_9_4_port, b => n689, outb =>
n5011);
U3653 : xor2 port map( a => mult_125_G4_ab_10_4_port, b => n691, outb =>
n2458);
U3654 : xor2 port map( a => n693, b => n694, outb => n5012);
U3655 : xor2 port map( a => mult_125_G4_ab_12_4_port, b => n696, outb =>
n2461);
U3656 : xor2 port map( a => mult_125_G4_ab_13_4_port, b => n698, outb =>
n5013);
U3657 : xor2 port map( a => mult_125_G4_ab_14_4_port, b => n700, outb =>
n5014);
U3658 : xor2 port map( a => mult_125_G4_ab_15_4_port, b => n703, outb =>
n5015);
U3659 : xor2 port map( a => n706, b => mult_125_G4_ab_2_3_port, outb =>
n2465);
U3660 : xor2 port map( a => mult_125_G4_ab_3_3_port, b => n709, outb =>
n5016);
U3661 : xor2 port map( a => mult_125_G4_ab_4_3_port, b => n711, outb =>
n2467);
U3662 : xor2 port map( a => mult_125_G4_ab_5_3_port, b => n713, outb =>
n5017);
U3663 : xor2 port map( a => mult_125_G4_ab_6_3_port, b => n715, outb =>
n2470);
U3664 : xor2 port map( a => mult_125_G4_ab_7_3_port, b => n717, outb =>
n5018);
U3665 : xor2 port map( a => mult_125_G4_ab_8_3_port, b => n719, outb =>
n2473);
U3666 : xor2 port map( a => mult_125_G4_ab_9_3_port, b => n721, outb =>
n5019);
U3667 : xor2 port map( a => mult_125_G4_ab_10_3_port, b => n723, outb =>
n2476);
U3668 : xor2 port map( a => mult_125_G4_ab_11_3_port, b => n725, outb =>
n5020);
U3669 : xor2 port map( a => n3824, b => n3822, outb => n2479);
U3670 : xor2 port map( a => mult_125_G4_ab_13_3_port, b => n729, outb =>
n5021);
U3671 : xor2 port map( a => mult_125_G4_ab_14_3_port, b => n731, outb =>
n2482);
U3672 : xor2 port map( a => mult_125_G4_ab_15_3_port, b => n733, outb =>
n2484);
U3673 : xor2 port map( a => n736, b => mult_125_G4_ab_2_2_port, outb =>
n2488);
U3674 : xor2 port map( a => n3830, b => n3828, outb => n5022);
U3675 : xor2 port map( a => mult_125_G4_ab_4_2_port, b => n740, outb =>
n2490);
U3676 : xor2 port map( a => mult_125_G4_ab_5_2_port, b => n742, outb =>
n5023);
U3677 : xor2 port map( a => mult_125_G4_ab_6_2_port, b => n744, outb =>
n2493);
U3678 : xor2 port map( a => n746, b => n747, outb => n5024);
U3679 : xor2 port map( a => mult_125_G4_ab_8_2_port, b => n749, outb =>
n2496);
U3680 : xor2 port map( a => mult_125_G4_ab_9_2_port, b => n751, outb =>
n5025);
U3681 : xor2 port map( a => mult_125_G4_ab_10_2_port, b => n753, outb =>
n2499);
U3682 : xor2 port map( a => mult_125_G4_ab_11_2_port, b => n755, outb =>
n5026);
U3683 : xor2 port map( a => mult_125_G4_ab_12_2_port, b => n757, outb =>
n2502);
U3684 : xor2 port map( a => mult_125_G4_ab_13_2_port, b => n759, outb =>
n5027);
U3685 : xor2 port map( a => mult_125_G4_ab_14_2_port, b => n761, outb =>
n2505);
U3686 : xor2 port map( a => n4941, b => n3845, outb => n5028);
U3687 : xor2 port map( a => n3848, b => mult_125_G4_ab_2_1_port, outb =>
n2509);
U3688 : xor2 port map( a => n3849, b => n3847, outb => n5029);
U3689 : xor2 port map( a => mult_125_G4_ab_4_1_port, b => n3851, outb =>
n2511);
U3690 : xor2 port map( a => mult_125_G4_ab_5_1_port, b => n772, outb =>
n5041);
U3691 : xor2 port map( a => n3854, b => n774, outb => n2514);
U3692 : xor2 port map( a => n5042, b => n776, outb => n5031);
U3693 : xor2 port map( a => mult_125_G4_ab_8_1_port, b => n3855, outb =>
n2517);
U3694 : xor2 port map( a => n5043, b => n780, outb => n5032);
U3695 : xor2 port map( a => n3860, b => n782, outb => n2520);
U3696 : xor2 port map( a => n5044, b => n784, outb => n5033);
U3697 : xor2 port map( a => n3863, b => n786, outb => n2523);
U3698 : xor2 port map( a => n5045, b => n788, outb => n5034);
U3699 : xor2 port map( a => n3866, b => n3864, outb => n2526);
U3700 : xor2 port map( a => n5046, b => n792, outb => n5035);
U3701 : xor2 port map( a => mult_125_G4_ab_15_0_port, b => n820, outb =>
n5036);
U3702 : xor2 port map( a => mult_125_G4_ab_11_0_port, b => n812, outb =>
n2528);
U3703 : xor2 port map( a => mult_125_G4_ab_9_0_port, b => n808, outb =>
n2529);
U3704 : xor2 port map( a => mult_125_G4_ab_7_0_port, b => n804, outb =>
n2530);
U3705 : xor2 port map( a => mult_125_G4_ab_5_0_port, b => n800, outb =>
n2531);
U3706 : xor2 port map( a => mult_125_G4_ab_3_0_port, b => n796, outb =>
n2532);
U3707 : xor2 port map( a => n272, b => mult_125_G4_ZA, outb => n2533);
U3708 : xor2 port map( a => mult_125_G4_ab_13_0_port, b => n816, outb =>
n2534);
U3709 : oai22 port map( a => n5048, b => n5049, c => n822, d => n3894, outb
=> n5047);
U3710 : aoi22 port map( a => mult_125_G3_ab_2_15_port, b =>
mult_125_G3_ab_3_14_port, c => n5047, d => n5051,
outb => n5050);
U3711 : oai22 port map( a => n3895, b => n3896, c => n5050, d => n824, outb
=> n5052);
U3712 : aoi22 port map( a => mult_125_G3_ab_4_15_port, b =>
mult_125_G3_ab_5_14_port, c => n5052, d => n5054,
outb => n5053);
U3713 : oai22 port map( a => n3897, b => n3898, c => n5053, d => n826, outb
=> n5055);
U3714 : aoi22 port map( a => mult_125_G3_ab_6_15_port, b =>
mult_125_G3_ab_7_14_port, c => n5055, d => n5057,
outb => n5056);
U3715 : oai22 port map( a => n3899, b => n3900, c => n5056, d => n828, outb
=> n5058);
U3716 : aoi22 port map( a => mult_125_G3_ab_8_15_port, b =>
mult_125_G3_ab_9_14_port, c => n5058, d => n5060,
outb => n5059);
U3717 : oai22 port map( a => n3901, b => n3902, c => n5059, d => n830, outb
=> n5061);
U3718 : aoi22 port map( a => mult_125_G3_ab_10_15_port, b =>
mult_125_G3_ab_11_14_port, c => n5061, d => n5063,
outb => n5062);
U3719 : oai22 port map( a => n3903, b => n3904, c => n5062, d => n832, outb
=> n5064);
U3720 : aoi22 port map( a => mult_125_G3_ab_12_15_port, b =>
mult_125_G3_ab_13_14_port, c => n5064, d => n5066,
outb => n5065);
U3721 : aoi22 port map( a => mult_125_G3_ab_13_15_port, b =>
mult_125_G3_ab_14_14_port, c => n5068, d => n5069,
outb => n5067);
U3722 : aoi22 port map( a => mult_125_G3_ab_14_15_port, b =>
mult_125_G3_ab_15_14_port, c => n5070, d => n5071,
outb => n349);
U3723 : inv port map( inb => n3922, outb => n865);
U3724 : aoi22 port map( a => n865, b => mult_125_G3_ab_15_13_port, c =>
n5072, d => n2577, outb => n351);
U3725 : aoi22 port map( a => n894, b => mult_125_G3_ab_15_12_port, c =>
n5073, d => n2573, outb => n353);
U3726 : oai22 port map( a => n925, b => n924, c => n5075, d => n2618, outb
=> n5074);
U3727 : inv port map( inb => n941, outb => n3972);
U3728 : aoi22 port map( a => n955, b => mult_125_G3_ab_15_10_port, c =>
n5076, d => n2614, outb => n357);
U3729 : oai22 port map( a => n985, b => n984, c => n5078, d => n2659, outb
=> n5077);
U3730 : inv port map( inb => n1004, outb => n4016);
U3731 : aoi22 port map( a => n1014, b => mult_125_G3_ab_15_8_port, c =>
n5079, d => n2655, outb => n361);
U3732 : oai22 port map( a => n1045, b => n1044, c => n5081, d => n2700, outb
=> n5080);
U3733 : inv port map( inb => n1070, outb => n4056);
U3734 : aoi22 port map( a => n1076, b => mult_125_G3_ab_15_6_port, c =>
n5082, d => n2696, outb => n365);
U3735 : oai22 port map( a => n1108, b => n1107, c => n5084, d => n2741, outb
=> n5083);
U3736 : aoi22 port map( a => n5085, b => mult_125_G3_ab_15_4_port, c =>
n1139, d => n2737, outb => n369);
U3737 : aoi22 port map( a => n1171, b => mult_125_G3_ab_15_3_port, c =>
n5086, d => n2782, outb => n371);
U3738 : oai22 port map( a => n4130, b => n5087, c => n1200, d => n2778, outb
=> n374);
U3739 : aoi22 port map( a => n1230, b => mult_125_G3_ab_15_1_port, c =>
n5088, d => n2801, outb => n376);
U3740 : aoi22 port map( a => n1258, b => mult_125_G3_ab_15_0_port, c =>
n5089, d => n5090, outb => n378);
U3741 : aoi22 port map( a => adder_mem_array_3_1_port, b => n2137, c =>
n5091, d => n3426, outb => n3483);
U3742 : oai22 port map( a => n4750, b => n4751, c => n3483, d => n2138, outb
=> n3480);
U3743 : aoi22 port map( a => multiplier_sigs_2_3_port, b =>
adder_mem_array_3_3_port, c => n3480, d => n5092,
outb => n3479);
U3744 : oai22 port map( a => n4752, b => n4753, c => n3479, d => n2140, outb
=> n3476);
U3745 : aoi22 port map( a => multiplier_sigs_2_5_port, b =>
adder_mem_array_3_5_port, c => n3476, d => n5093,
outb => n3475);
U3746 : oai22 port map( a => n4754, b => n4755, c => n3475, d => n2142, outb
=> n3472);
U3747 : aoi22 port map( a => multiplier_sigs_2_7_port, b =>
adder_mem_array_3_7_port, c => n3472, d => n5094,
outb => n3469);
U3748 : oai22 port map( a => n4756, b => n4757, c => n3469, d => n2144, outb
=> n3466);
U3749 : aoi22 port map( a => multiplier_sigs_2_9_port, b =>
adder_mem_array_3_9_port, c => n3466, d => n5095,
outb => n3465);
U3750 : oai22 port map( a => n4758, b => n4759, c => n3465, d => n2146, outb
=> n3462);
U3751 : aoi22 port map( a => multiplier_sigs_2_11_port, b =>
adder_mem_array_3_11_port, c => n3462, d => n5096,
outb => n3461);
U3752 : oai22 port map( a => n4760, b => n4761, c => n3461, d => n2148, outb
=> n3458);
U3753 : aoi22 port map( a => multiplier_sigs_2_13_port, b =>
adder_mem_array_3_13_port, c => n3458, d => n5097,
outb => n3457);
U3754 : oai22 port map( a => n4762, b => n4763, c => n3457, d => n2150, outb
=> n3454);
U3755 : aoi22 port map( a => multiplier_sigs_2_15_port, b =>
adder_mem_array_3_15_port, c => n3454, d => n5098,
outb => n3453);
U3756 : oai22 port map( a => n4764, b => n4765, c => n3453, d => n2152, outb
=> n3450);
U3757 : aoi22 port map( a => multiplier_sigs_2_17_port, b =>
adder_mem_array_3_17_port, c => n3450, d => n5099,
outb => n3446);
U3758 : oai22 port map( a => n4766, b => n4767, c => n3446, d => n2154, outb
=> n3443);
U3759 : aoi22 port map( a => multiplier_sigs_2_19_port, b =>
adder_mem_array_3_19_port, c => n3443, d => n5100,
outb => n3442);
U3760 : oai22 port map( a => n4768, b => n4769, c => n3442, d => n2156, outb
=> n3439);
U3761 : aoi22 port map( a => multiplier_sigs_2_21_port, b =>
adder_mem_array_3_21_port, c => n3439, d => n5101,
outb => n3438);
U3762 : oai22 port map( a => n4770, b => n4771, c => n3438, d => n2158, outb
=> n3435);
U3763 : aoi22 port map( a => multiplier_sigs_2_23_port, b =>
adder_mem_array_3_23_port, c => n3435, d => n5102,
outb => n3434);
U3764 : oai22 port map( a => n4772, b => n4773, c => n3434, d => n2160, outb
=> n3431);
U3765 : aoi22 port map( a => multiplier_sigs_2_25_port, b =>
adder_mem_array_3_25_port, c => n3431, d => n5103,
outb => n3430);
U3766 : oai22 port map( a => n4774, b => n4775, c => n3430, d => n2162, outb
=> n3427);
U3767 : aoi22 port map( a => adder_mem_array_3_27_port, b =>
multiplier_sigs_2_27_port, c => n3427, d => n5104,
outb => n3606);
U3768 : oai22 port map( a => n4838, b => n4839, c => n3606, d => n2232, outb
=> n3603);
U3769 : aoi22 port map( a => multiplier_sigs_2_29_port, b =>
adder_mem_array_3_29_port, c => n3603, d => n5105,
outb => n3602);
U3770 : oai22 port map( a => n4840, b => n4841, c => n3602, d => n2234, outb
=> n2237);
U3771 : nand2 port map( a => n5106, b => n5107, outb => n2236);
U3772 : xor2 port map( a => n5047, b => n4880, outb => n2545);
U3773 : xor2 port map( a => n5108, b => n5050, outb => n2548);
U3774 : xor2 port map( a => n5052, b => n4881, outb => n2551);
U3775 : xor2 port map( a => n5109, b => n5053, outb => n2554);
U3776 : xor2 port map( a => n5055, b => n4882, outb => n2557);
U3777 : xor2 port map( a => n5110, b => n5056, outb => n2560);
U3778 : xor2 port map( a => n5058, b => n4883, outb => n2563);
U3779 : xor2 port map( a => n5111, b => n5059, outb => n2566);
U3780 : xor2 port map( a => n5061, b => n4884, outb => n2569);
U3781 : xor2 port map( a => n5112, b => n5062, outb => n2572);
U3782 : xor2 port map( a => n5064, b => n4885, outb => n2575);
U3783 : xor2 port map( a => n5113, b => n5068, outb => n2577);
U3784 : xor2 port map( a => n5067, b => n4886, outb => n352);
U3785 : xor2 port map( a => n5114, b => n2538, outb => n2583);
U3786 : xor2 port map( a => n5115, b => n2541, outb => n2589);
U3787 : xor2 port map( a => n5116, b => n2543, outb => n2592);
U3788 : xor2 port map( a => n5117, b => n2546, outb => n2595);
U3789 : xor2 port map( a => n5118, b => n2549, outb => n2598);
U3790 : xor2 port map( a => n5119, b => n2552, outb => n2601);
U3791 : xor2 port map( a => n5120, b => n2555, outb => n2604);
U3792 : xor2 port map( a => n5121, b => n2558, outb => n2607);
U3793 : xor2 port map( a => n5122, b => n2561, outb => n2610);
U3794 : xor2 port map( a => n5123, b => n2564, outb => n2613);
U3795 : xor2 port map( a => n5124, b => n2567, outb => n2616);
U3796 : xor2 port map( a => n5125, b => n2570, outb => n2618);
U3797 : xor2 port map( a => n5126, b => n2573, outb => n356);
U3798 : xor2 port map( a => n5127, b => n2579, outb => n2624);
U3799 : xor2 port map( a => n5128, b => n2581, outb => n2627);
U3800 : xor2 port map( a => n5129, b => n2585, outb => n2633);
U3801 : xor2 port map( a => n5130, b => n2587, outb => n2636);
U3802 : xor2 port map( a => n5131, b => n2590, outb => n2639);
U3803 : xor2 port map( a => n5132, b => n2593, outb => n2642);
U3804 : xor2 port map( a => n5133, b => n2596, outb => n2645);
U3805 : xor2 port map( a => n5134, b => n2599, outb => n2648);
U3806 : xor2 port map( a => n5135, b => n2602, outb => n2651);
U3807 : xor2 port map( a => n5136, b => n2605, outb => n2654);
U3808 : xor2 port map( a => n5137, b => n2608, outb => n2657);
U3809 : xor2 port map( a => n5138, b => n2611, outb => n2659);
U3810 : xor2 port map( a => n5139, b => n2614, outb => n360);
U3811 : xor2 port map( a => n5140, b => n2620, outb => n2665);
U3812 : xor2 port map( a => n5141, b => n2622, outb => n2668);
U3813 : xor2 port map( a => n5142, b => n2625, outb => n2671);
U3814 : xor2 port map( a => n5143, b => n2629, outb => n2677);
U3815 : xor2 port map( a => n5144, b => n2631, outb => n2680);
U3816 : xor2 port map( a => n5145, b => n2634, outb => n2683);
U3817 : xor2 port map( a => n5146, b => n2637, outb => n2686);
U3818 : xor2 port map( a => n5147, b => n2640, outb => n2689);
U3819 : xor2 port map( a => n5148, b => n2643, outb => n2692);
U3820 : xor2 port map( a => n5149, b => n2646, outb => n2695);
U3821 : xor2 port map( a => n5150, b => n2649, outb => n2698);
U3822 : xor2 port map( a => n5151, b => n2652, outb => n2700);
U3823 : xor2 port map( a => n5152, b => n2655, outb => n364);
U3824 : xor2 port map( a => n5153, b => n2661, outb => n2706);
U3825 : xor2 port map( a => n5154, b => n2663, outb => n2709);
U3826 : xor2 port map( a => n5155, b => n2666, outb => n2712);
U3827 : xor2 port map( a => n5156, b => n2669, outb => n2715);
U3828 : xor2 port map( a => n5157, b => n2673, outb => n2721);
U3829 : xor2 port map( a => n5158, b => n2675, outb => n2724);
U3830 : xor2 port map( a => n5159, b => n2678, outb => n2727);
U3831 : xor2 port map( a => n5160, b => n2681, outb => n2730);
U3832 : xor2 port map( a => n5161, b => n2684, outb => n2733);
U3833 : xor2 port map( a => n5162, b => n2687, outb => n2736);
U3834 : xor2 port map( a => n5163, b => n2690, outb => n2739);
U3835 : xor2 port map( a => n5164, b => n2693, outb => n2741);
U3836 : xor2 port map( a => n5165, b => n2696, outb => n368);
U3837 : xor2 port map( a => n5166, b => n2702, outb => n2747);
U3838 : xor2 port map( a => n5167, b => n2704, outb => n2750);
U3839 : xor2 port map( a => n5168, b => n2707, outb => n2753);
U3840 : xor2 port map( a => n5169, b => n2710, outb => n2756);
U3841 : xor2 port map( a => n5170, b => n2713, outb => n2759);
U3842 : xor2 port map( a => n5171, b => n2717, outb => n2765);
U3843 : xor2 port map( a => n5172, b => n2719, outb => n2768);
U3844 : xor2 port map( a => n5173, b => n2722, outb => n2771);
U3845 : xor2 port map( a => n5174, b => n2725, outb => n2774);
U3846 : xor2 port map( a => n5175, b => n2728, outb => n2777);
U3847 : xor2 port map( a => n5176, b => n2731, outb => n2780);
U3848 : xor2 port map( a => n5177, b => n2734, outb => n2782);
U3849 : xor2 port map( a => n5178, b => n2737, outb => n372);
U3850 : xor2 port map( a => n5179, b => n2743, outb => n2788);
U3851 : xor2 port map( a => n5180, b => n2745, outb => n2791);
U3852 : xor2 port map( a => n5181, b => n2748, outb => n2794);
U3853 : xor2 port map( a => n5182, b => n2751, outb => n2797);
U3854 : xor2 port map( a => n5183, b => n2754, outb => n2800);
U3855 : xor2 port map( a => n5184, b => n2757, outb => n2803);
U3856 : xor2 port map( a => n5185, b => n2761, outb => n2809);
U3857 : xor2 port map( a => n5186, b => n2763, outb => n2812);
U3858 : xor2 port map( a => n5187, b => n2766, outb => n2815);
U3859 : xor2 port map( a => n5188, b => n2769, outb => n2818);
U3860 : xor2 port map( a => n5189, b => n2772, outb => n2821);
U3861 : xor2 port map( a => n5190, b => n2775, outb => n2824);
U3862 : xor2 port map( a => n5191, b => n2778, outb => n377);
U3863 : xor2 port map( a => n5192, b => n2784, outb => n4158);
U3864 : xor2 port map( a => n5193, b => n2786, outb => n4162);
U3865 : xor2 port map( a => n5194, b => n2789, outb => n4166);
U3866 : xor2 port map( a => n5195, b => n2792, outb => n4170);
U3867 : xor2 port map( a => n5196, b => n2795, outb => n4174);
U3868 : xor2 port map( a => n5197, b => n2798, outb => n4178);
U3869 : inv port map( inb => n2822, outb => n5090);
U3870 : xor2 port map( a => n5198, b => n2801, outb => n379);
U3871 : xor2 port map( a => n5199, b => n2822, outb => n383);
U3872 : xor2 port map( a => n3894, b => mult_125_G3_ab_2_14_port, outb =>
n2539);
U3873 : xor2 port map( a => n3895, b => n3896, outb => n5108);
U3874 : xor2 port map( a => n3897, b => n3898, outb => n5109);
U3875 : xor2 port map( a => n3899, b => n3900, outb => n5110);
U3876 : xor2 port map( a => n3901, b => n3902, outb => n5111);
U3877 : xor2 port map( a => n3903, b => n3904, outb => n5112);
U3878 : xor2 port map( a => mult_125_G3_ab_13_15_port, b =>
mult_125_G3_ab_14_14_port, outb => n5113);
U3879 : xor2 port map( a => n3905, b => n837, outb => n2542);
U3880 : xor2 port map( a => mult_125_G3_ab_3_13_port, b => n841, outb =>
n5114);
U3881 : xor2 port map( a => mult_125_G3_ab_4_13_port, b => n843, outb =>
n2544);
U3882 : xor2 port map( a => mult_125_G3_ab_5_13_port, b => n845, outb =>
n2547);
U3883 : xor2 port map( a => mult_125_G3_ab_6_13_port, b => n847, outb =>
n2550);
U3884 : xor2 port map( a => n3912, b => n3910, outb => n2553);
U3885 : xor2 port map( a => mult_125_G3_ab_8_13_port, b => n851, outb =>
n2556);
U3886 : xor2 port map( a => n3915, b => n3913, outb => n2559);
U3887 : xor2 port map( a => mult_125_G3_ab_10_13_port, b => n855, outb =>
n2562);
U3888 : xor2 port map( a => n3918, b => n3916, outb => n2565);
U3889 : xor2 port map( a => mult_125_G3_ab_12_13_port, b => n859, outb =>
n2568);
U3890 : xor2 port map( a => n3921, b => n3919, outb => n2571);
U3891 : xor2 port map( a => mult_125_G3_ab_14_13_port, b => n863, outb =>
n2574);
U3892 : xor2 port map( a => mult_125_G3_ab_15_13_port, b => n3922, outb =>
n2576);
U3893 : xor2 port map( a => n868, b => mult_125_G3_ab_2_12_port, outb =>
n2580);
U3894 : xor2 port map( a => n3926, b => n3924, outb => n5115);
U3895 : xor2 port map( a => mult_125_G3_ab_4_12_port, b => n872, outb =>
n2582);
U3896 : xor2 port map( a => mult_125_G3_ab_5_12_port, b => n3927, outb =>
n5116);
U3897 : xor2 port map( a => n3931, b => n3929, outb => n5117);
U3898 : xor2 port map( a => mult_125_G3_ab_7_12_port, b => n878, outb =>
n5118);
U3899 : xor2 port map( a => n3934, b => n3932, outb => n5119);
U3900 : xor2 port map( a => mult_125_G3_ab_9_12_port, b => n882, outb =>
n5120);
U3901 : xor2 port map( a => n3937, b => n3935, outb => n5121);
U3902 : xor2 port map( a => mult_125_G3_ab_11_12_port, b => n886, outb =>
n5122);
U3903 : xor2 port map( a => n3940, b => n3938, outb => n5123);
U3904 : xor2 port map( a => mult_125_G3_ab_13_12_port, b => n890, outb =>
n5124);
U3905 : xor2 port map( a => n3943, b => n3941, outb => n5125);
U3906 : xor2 port map( a => n5200, b => n894, outb => n5126);
U3907 : xor2 port map( a => n897, b => mult_125_G3_ab_2_11_port, outb =>
n2586);
U3908 : xor2 port map( a => mult_125_G3_ab_3_11_port, b => n900, outb =>
n5127);
U3909 : xor2 port map( a => n3947, b => n3946, outb => n2588);
U3910 : xor2 port map( a => mult_125_G3_ab_5_11_port, b => n904, outb =>
n5128);
U3911 : xor2 port map( a => mult_125_G3_ab_6_11_port, b => n906, outb =>
n2591);
U3912 : xor2 port map( a => n3952, b => n3951, outb => n2594);
U3913 : xor2 port map( a => mult_125_G3_ab_8_11_port, b => n910, outb =>
n2597);
U3914 : xor2 port map( a => n3955, b => n3953, outb => n2600);
U3915 : xor2 port map( a => mult_125_G3_ab_10_11_port, b => n914, outb =>
n2603);
U3916 : xor2 port map( a => n3958, b => n3956, outb => n2606);
U3917 : xor2 port map( a => mult_125_G3_ab_12_11_port, b => n918, outb =>
n2609);
U3918 : xor2 port map( a => n3961, b => n3959, outb => n2612);
U3919 : xor2 port map( a => mult_125_G3_ab_14_11_port, b => n922, outb =>
n2615);
U3920 : xor2 port map( a => n924, b => n925, outb => n2617);
U3921 : xor2 port map( a => n928, b => mult_125_G3_ab_2_10_port, outb =>
n2621);
U3922 : xor2 port map( a => n3965, b => n3963, outb => n5129);
U3923 : xor2 port map( a => mult_125_G3_ab_4_10_port, b => n932, outb =>
n2623);
U3924 : xor2 port map( a => n934, b => n935, outb => n5130);
U3925 : xor2 port map( a => mult_125_G3_ab_6_10_port, b => n937, outb =>
n2626);
U3926 : xor2 port map( a => mult_125_G3_ab_7_10_port, b => n939, outb =>
n5131);
U3927 : xor2 port map( a => n3971, b => n3972, outb => n5132);
U3928 : xor2 port map( a => mult_125_G3_ab_9_10_port, b => n943, outb =>
n5133);
U3929 : xor2 port map( a => n3975, b => n3973, outb => n5134);
U3930 : xor2 port map( a => mult_125_G3_ab_11_10_port, b => n947, outb =>
n5135);
U3931 : xor2 port map( a => n3978, b => n3976, outb => n5136);
U3932 : xor2 port map( a => mult_125_G3_ab_13_10_port, b => n951, outb =>
n5137);
U3933 : xor2 port map( a => n3981, b => n3979, outb => n5138);
U3934 : xor2 port map( a => n5201, b => n955, outb => n5139);
U3935 : xor2 port map( a => n958, b => mult_125_G3_ab_2_9_port, outb =>
n2630);
U3936 : xor2 port map( a => n3984, b => n3982, outb => n5140);
U3937 : xor2 port map( a => mult_125_G3_ab_4_9_port, b => n962, outb =>
n2632);
U3938 : xor2 port map( a => mult_125_G3_ab_5_9_port, b => n964, outb =>
n5141);
U3939 : xor2 port map( a => mult_125_G3_ab_6_9_port, b => n966, outb =>
n2635);
U3940 : xor2 port map( a => mult_125_G3_ab_7_9_port, b => n968, outb =>
n5142);
U3941 : xor2 port map( a => n3992, b => n3990, outb => n2638);
U3942 : xor2 port map( a => n3994, b => n3993, outb => n2641);
U3943 : xor2 port map( a => mult_125_G3_ab_10_9_port, b => n974, outb =>
n2644);
U3944 : xor2 port map( a => n3997, b => n3995, outb => n2647);
U3945 : xor2 port map( a => mult_125_G3_ab_12_9_port, b => n978, outb =>
n2650);
U3946 : xor2 port map( a => n4000, b => n3998, outb => n2653);
U3947 : xor2 port map( a => mult_125_G3_ab_14_9_port, b => n982, outb =>
n2656);
U3948 : xor2 port map( a => n984, b => n985, outb => n2658);
U3949 : xor2 port map( a => n988, b => mult_125_G3_ab_2_8_port, outb =>
n2662);
U3950 : xor2 port map( a => n4004, b => n4002, outb => n5143);
U3951 : xor2 port map( a => n4006, b => n992, outb => n2664);
U3952 : xor2 port map( a => n4008, b => n4007, outb => n5144);
U3953 : xor2 port map( a => mult_125_G3_ab_6_8_port, b => n996, outb =>
n2667);
U3954 : xor2 port map( a => n4011, b => n4009, outb => n5145);
U3955 : xor2 port map( a => mult_125_G3_ab_8_8_port, b => n1000, outb =>
n2670);
U3956 : xor2 port map( a => mult_125_G3_ab_9_8_port, b => n1002, outb =>
n5146);
U3957 : xor2 port map( a => n4015, b => n4016, outb => n5147);
U3958 : xor2 port map( a => mult_125_G3_ab_11_8_port, b => n1006, outb =>
n5148);
U3959 : xor2 port map( a => n4019, b => n4017, outb => n5149);
U3960 : xor2 port map( a => mult_125_G3_ab_13_8_port, b => n1010, outb =>
n5150);
U3961 : xor2 port map( a => n4022, b => n4020, outb => n5151);
U3962 : xor2 port map( a => n5202, b => n1014, outb => n5152);
U3963 : xor2 port map( a => n1017, b => mult_125_G3_ab_2_7_port, outb =>
n2674);
U3964 : xor2 port map( a => mult_125_G3_ab_3_7_port, b => n1020, outb =>
n5153);
U3965 : xor2 port map( a => n4026, b => n4025, outb => n2676);
U3966 : xor2 port map( a => mult_125_G3_ab_5_7_port, b => n1024, outb =>
n5154);
U3967 : xor2 port map( a => n4029, b => n4027, outb => n2679);
U3968 : xor2 port map( a => mult_125_G3_ab_7_7_port, b => n1028, outb =>
n5155);
U3969 : xor2 port map( a => n4032, b => n4030, outb => n2682);
U3970 : xor2 port map( a => mult_125_G3_ab_9_7_port, b => n1032, outb =>
n5156);
U3971 : xor2 port map( a => n4035, b => n4033, outb => n2685);
U3972 : xor2 port map( a => n4037, b => n4036, outb => n2688);
U3973 : xor2 port map( a => mult_125_G3_ab_12_7_port, b => n1038, outb =>
n2691);
U3974 : xor2 port map( a => n4040, b => n4038, outb => n2694);
U3975 : xor2 port map( a => mult_125_G3_ab_14_7_port, b => n1042, outb =>
n2697);
U3976 : xor2 port map( a => n1044, b => n1045, outb => n2699);
U3977 : xor2 port map( a => n1048, b => mult_125_G3_ab_2_6_port, outb =>
n2703);
U3978 : xor2 port map( a => n4044, b => n4042, outb => n5157);
U3979 : xor2 port map( a => mult_125_G3_ab_4_6_port, b => n1052, outb =>
n2705);
U3980 : xor2 port map( a => n1054, b => n1055, outb => n5158);
U3981 : xor2 port map( a => mult_125_G3_ab_6_6_port, b => n1057, outb =>
n2708);
U3982 : xor2 port map( a => n4049, b => n4047, outb => n5159);
U3983 : xor2 port map( a => mult_125_G3_ab_8_6_port, b => n1061, outb =>
n2711);
U3984 : xor2 port map( a => n1063, b => n1064, outb => n5160);
U3985 : xor2 port map( a => mult_125_G3_ab_10_6_port, b => n1066, outb =>
n2714);
U3986 : xor2 port map( a => mult_125_G3_ab_11_6_port, b => n1068, outb =>
n5161);
U3987 : xor2 port map( a => n4055, b => n4056, outb => n5162);
U3988 : xor2 port map( a => mult_125_G3_ab_13_6_port, b => n1072, outb =>
n5163);
U3989 : xor2 port map( a => n4059, b => n4057, outb => n5164);
U3990 : xor2 port map( a => n5203, b => n1076, outb => n5165);
U3991 : xor2 port map( a => n1079, b => mult_125_G3_ab_2_5_port, outb =>
n2718);
U3992 : xor2 port map( a => mult_125_G3_ab_3_5_port, b => n1082, outb =>
n5166);
U3993 : xor2 port map( a => mult_125_G3_ab_4_5_port, b => n1084, outb =>
n2720);
U3994 : xor2 port map( a => mult_125_G3_ab_5_5_port, b => n1086, outb =>
n5167);
U3995 : xor2 port map( a => n1088, b => n1089, outb => n2723);
U3996 : xor2 port map( a => mult_125_G3_ab_7_5_port, b => n1091, outb =>
n5168);
U3997 : xor2 port map( a => mult_125_G3_ab_8_5_port, b => n1093, outb =>
n2726);
U3998 : xor2 port map( a => mult_125_G3_ab_9_5_port, b => n1095, outb =>
n5169);
U3999 : xor2 port map( a => n4071, b => n4069, outb => n2729);
U4000 : xor2 port map( a => mult_125_G3_ab_11_5_port, b => n1099, outb =>
n5170);
U4001 : xor2 port map( a => n4074, b => n4072, outb => n2732);
U4002 : xor2 port map( a => n4076, b => n1103, outb => n2735);
U4003 : xor2 port map( a => mult_125_G3_ab_14_5_port, b => n1105, outb =>
n2738);
U4004 : xor2 port map( a => n1107, b => n1108, outb => n2740);
U4005 : xor2 port map( a => n1111, b => mult_125_G3_ab_2_4_port, outb =>
n2744);
U4006 : xor2 port map( a => n4080, b => n4078, outb => n5171);
U4007 : xor2 port map( a => mult_125_G3_ab_4_4_port, b => n1115, outb =>
n2746);
U4008 : xor2 port map( a => n1117, b => n1118, outb => n5172);
U4009 : xor2 port map( a => mult_125_G3_ab_6_4_port, b => n1120, outb =>
n2749);
U4010 : xor2 port map( a => n1122, b => n1123, outb => n5173);
U4011 : xor2 port map( a => mult_125_G3_ab_8_4_port, b => n1125, outb =>
n2752);
U4012 : xor2 port map( a => mult_125_G3_ab_9_4_port, b => n1127, outb =>
n5174);
U4013 : xor2 port map( a => mult_125_G3_ab_10_4_port, b => n1129, outb =>
n2755);
U4014 : xor2 port map( a => n1131, b => n1132, outb => n5175);
U4015 : xor2 port map( a => mult_125_G3_ab_12_4_port, b => n1134, outb =>
n2758);
U4016 : xor2 port map( a => mult_125_G3_ab_13_4_port, b => n1136, outb =>
n5176);
U4017 : xor2 port map( a => mult_125_G3_ab_14_4_port, b => n1138, outb =>
n5177);
U4018 : xor2 port map( a => mult_125_G3_ab_15_4_port, b => n1141, outb =>
n5178);
U4019 : xor2 port map( a => n1144, b => mult_125_G3_ab_2_3_port, outb =>
n2762);
U4020 : xor2 port map( a => mult_125_G3_ab_3_3_port, b => n1147, outb =>
n5179);
U4021 : xor2 port map( a => mult_125_G3_ab_4_3_port, b => n1149, outb =>
n2764);
U4022 : xor2 port map( a => mult_125_G3_ab_5_3_port, b => n1151, outb =>
n5180);
U4023 : xor2 port map( a => mult_125_G3_ab_6_3_port, b => n1153, outb =>
n2767);
U4024 : xor2 port map( a => mult_125_G3_ab_7_3_port, b => n1155, outb =>
n5181);
U4025 : xor2 port map( a => mult_125_G3_ab_8_3_port, b => n1157, outb =>
n2770);
U4026 : xor2 port map( a => mult_125_G3_ab_9_3_port, b => n1159, outb =>
n5182);
U4027 : xor2 port map( a => mult_125_G3_ab_10_3_port, b => n1161, outb =>
n2773);
U4028 : xor2 port map( a => mult_125_G3_ab_11_3_port, b => n1163, outb =>
n5183);
U4029 : xor2 port map( a => n4109, b => n4107, outb => n2776);
U4030 : xor2 port map( a => mult_125_G3_ab_13_3_port, b => n1167, outb =>
n5184);
U4031 : xor2 port map( a => mult_125_G3_ab_14_3_port, b => n1169, outb =>
n2779);
U4032 : xor2 port map( a => mult_125_G3_ab_15_3_port, b => n1171, outb =>
n2781);
U4033 : xor2 port map( a => n1174, b => mult_125_G3_ab_2_2_port, outb =>
n2785);
U4034 : xor2 port map( a => n4115, b => n4113, outb => n5185);
U4035 : xor2 port map( a => mult_125_G3_ab_4_2_port, b => n1178, outb =>
n2787);
U4036 : xor2 port map( a => mult_125_G3_ab_5_2_port, b => n1180, outb =>
n5186);
U4037 : xor2 port map( a => mult_125_G3_ab_6_2_port, b => n1182, outb =>
n2790);
U4038 : xor2 port map( a => n1184, b => n1185, outb => n5187);
U4039 : xor2 port map( a => mult_125_G3_ab_8_2_port, b => n1187, outb =>
n2793);
U4040 : xor2 port map( a => mult_125_G3_ab_9_2_port, b => n1189, outb =>
n5188);
U4041 : xor2 port map( a => mult_125_G3_ab_10_2_port, b => n1191, outb =>
n2796);
U4042 : xor2 port map( a => mult_125_G3_ab_11_2_port, b => n1193, outb =>
n5189);
U4043 : xor2 port map( a => mult_125_G3_ab_12_2_port, b => n1195, outb =>
n2799);
U4044 : xor2 port map( a => mult_125_G3_ab_13_2_port, b => n1197, outb =>
n5190);
U4045 : xor2 port map( a => mult_125_G3_ab_14_2_port, b => n1199, outb =>
n2802);
U4046 : xor2 port map( a => n5087, b => n4130, outb => n5191);
U4047 : xor2 port map( a => n4133, b => mult_125_G3_ab_2_1_port, outb =>
n2806);
U4048 : xor2 port map( a => n4134, b => n4132, outb => n5192);
U4049 : xor2 port map( a => mult_125_G3_ab_4_1_port, b => n4136, outb =>
n2808);
U4050 : xor2 port map( a => mult_125_G3_ab_5_1_port, b => n1210, outb =>
n5204);
U4051 : xor2 port map( a => n4139, b => n1212, outb => n2811);
U4052 : xor2 port map( a => n5205, b => n1214, outb => n5194);
U4053 : xor2 port map( a => mult_125_G3_ab_8_1_port, b => n4140, outb =>
n2814);
U4054 : xor2 port map( a => n5206, b => n1218, outb => n5195);
U4055 : xor2 port map( a => n4145, b => n1220, outb => n2817);
U4056 : xor2 port map( a => n5207, b => n1222, outb => n5196);
U4057 : xor2 port map( a => n4148, b => n1224, outb => n2820);
U4058 : xor2 port map( a => n5208, b => n1226, outb => n5197);
U4059 : xor2 port map( a => n4151, b => n4149, outb => n2823);
U4060 : xor2 port map( a => n5209, b => n1230, outb => n5198);
U4061 : xor2 port map( a => mult_125_G3_ab_15_0_port, b => n1258, outb =>
n5199);
U4062 : xor2 port map( a => mult_125_G3_ab_11_0_port, b => n1250, outb =>
n2825);
U4063 : xor2 port map( a => mult_125_G3_ab_9_0_port, b => n1246, outb =>
n2826);
U4064 : xor2 port map( a => mult_125_G3_ab_7_0_port, b => n1242, outb =>
n2827);
U4065 : xor2 port map( a => mult_125_G3_ab_5_0_port, b => n1238, outb =>
n2828);
U4066 : xor2 port map( a => mult_125_G3_ab_3_0_port, b => n1234, outb =>
n2829);
U4067 : xor2 port map( a => n380, b => mult_125_G3_ZA, outb => n2830);
U4068 : xor2 port map( a => mult_125_G3_ab_13_0_port, b => n1254, outb =>
n2831);
U4069 : xor2 port map( a => n4774, b => adder_mem_array_3_26_port, outb =>
n3429);
U4070 : xor2 port map( a => n4772, b => adder_mem_array_3_24_port, outb =>
n3433);
U4071 : xor2 port map( a => n4770, b => adder_mem_array_3_22_port, outb =>
n3437);
U4072 : xor2 port map( a => n4768, b => adder_mem_array_3_20_port, outb =>
n3441);
U4073 : xor2 port map( a => n4766, b => adder_mem_array_3_18_port, outb =>
n3445);
U4074 : xor2 port map( a => n4764, b => adder_mem_array_3_16_port, outb =>
n3452);
U4075 : xor2 port map( a => n4762, b => adder_mem_array_3_14_port, outb =>
n3456);
U4076 : xor2 port map( a => n4760, b => adder_mem_array_3_12_port, outb =>
n3460);
U4077 : xor2 port map( a => n4758, b => adder_mem_array_3_10_port, outb =>
n3464);
U4078 : xor2 port map( a => n4756, b => adder_mem_array_3_8_port, outb =>
n3468);
U4079 : xor2 port map( a => n4754, b => adder_mem_array_3_6_port, outb =>
n3474);
U4080 : xor2 port map( a => n4752, b => adder_mem_array_3_4_port, outb =>
n3478);
U4081 : xor2 port map( a => n4750, b => adder_mem_array_3_2_port, outb =>
n3482);
U4082 : xor2 port map( a => n5107, b => adder_mem_array_3_32_port, outb =>
n3599);
U4083 : xor2 port map( a => n4840, b => adder_mem_array_3_30_port, outb =>
n3601);
U4084 : xor2 port map( a => n4838, b => adder_mem_array_3_28_port, outb =>
n3605);
U4085 : oai22 port map( a => n5211, b => n5212, c => n1260, d => n4179, outb
=> n5210);
U4086 : aoi22 port map( a => mult_125_G2_ab_2_15_port, b =>
mult_125_G2_ab_3_14_port, c => n5210, d => n5214,
outb => n5213);
U4087 : oai22 port map( a => n4180, b => n4181, c => n5213, d => n1262, outb
=> n5215);
U4088 : aoi22 port map( a => mult_125_G2_ab_4_15_port, b =>
mult_125_G2_ab_5_14_port, c => n5215, d => n5217,
outb => n5216);
U4089 : oai22 port map( a => n4182, b => n4183, c => n5216, d => n1264, outb
=> n5218);
U4090 : aoi22 port map( a => mult_125_G2_ab_6_15_port, b =>
mult_125_G2_ab_7_14_port, c => n5218, d => n5220,
outb => n5219);
U4091 : oai22 port map( a => n4184, b => n4185, c => n5219, d => n1266, outb
=> n5221);
U4092 : aoi22 port map( a => mult_125_G2_ab_8_15_port, b =>
mult_125_G2_ab_9_14_port, c => n5221, d => n5223,
outb => n5222);
U4093 : oai22 port map( a => n4186, b => n4187, c => n5222, d => n1268, outb
=> n5224);
U4094 : aoi22 port map( a => mult_125_G2_ab_10_15_port, b =>
mult_125_G2_ab_11_14_port, c => n5224, d => n5226,
outb => n5225);
U4095 : oai22 port map( a => n4188, b => n4189, c => n5225, d => n1270, outb
=> n5227);
U4096 : aoi22 port map( a => mult_125_G2_ab_12_15_port, b =>
mult_125_G2_ab_13_14_port, c => n5227, d => n5229,
outb => n5228);
U4097 : aoi22 port map( a => mult_125_G2_ab_13_15_port, b =>
mult_125_G2_ab_14_14_port, c => n5231, d => n5232,
outb => n5230);
U4098 : aoi22 port map( a => mult_125_G2_ab_14_15_port, b =>
mult_125_G2_ab_15_14_port, c => n5233, d => n5234,
outb => n313);
U4099 : inv port map( inb => n4207, outb => n1303);
U4100 : aoi22 port map( a => n1303, b => mult_125_G2_ab_15_13_port, c =>
n5235, d => n2874, outb => n315);
U4101 : aoi22 port map( a => n1332, b => mult_125_G2_ab_15_12_port, c =>
n5236, d => n2870, outb => n317);
U4102 : oai22 port map( a => n1363, b => n1362, c => n5238, d => n2915, outb
=> n5237);
U4103 : inv port map( inb => n1379, outb => n4257);
U4104 : aoi22 port map( a => n1393, b => mult_125_G2_ab_15_10_port, c =>
n5239, d => n2911, outb => n321);
U4105 : oai22 port map( a => n1423, b => n1422, c => n5241, d => n2956, outb
=> n5240);
U4106 : inv port map( inb => n1442, outb => n4301);
U4107 : aoi22 port map( a => n1452, b => mult_125_G2_ab_15_8_port, c =>
n5242, d => n2952, outb => n325);
U4108 : oai22 port map( a => n1483, b => n1482, c => n5244, d => n2997, outb
=> n5243);
U4109 : inv port map( inb => n1508, outb => n4341);
U4110 : aoi22 port map( a => n1514, b => mult_125_G2_ab_15_6_port, c =>
n5245, d => n2993, outb => n329);
U4111 : oai22 port map( a => n1546, b => n1545, c => n5247, d => n3038, outb
=> n5246);
U4112 : aoi22 port map( a => n5248, b => mult_125_G2_ab_15_4_port, c =>
n1577, d => n3034, outb => n333);
U4113 : aoi22 port map( a => n1609, b => mult_125_G2_ab_15_3_port, c =>
n5249, d => n3079, outb => n335);
U4114 : oai22 port map( a => n4415, b => n5250, c => n1638, d => n3075, outb
=> n338);
U4115 : aoi22 port map( a => n1668, b => mult_125_G2_ab_15_1_port, c =>
n5251, d => n3098, outb => n340);
U4116 : aoi22 port map( a => n1696, b => mult_125_G2_ab_15_0_port, c =>
n5252, d => n5253, outb => n342);
U4117 : aoi22 port map( a => adder_mem_array_2_1_port, b => n2167, c =>
n5254, d => n3484, outb => n3544);
U4118 : oai22 port map( a => n4780, b => n4781, c => n3544, d => n2168, outb
=> n3541);
U4119 : aoi22 port map( a => multiplier_sigs_1_3_port, b =>
adder_mem_array_2_3_port, c => n3541, d => n5255,
outb => n3540);
U4120 : oai22 port map( a => n4782, b => n4783, c => n3540, d => n2170, outb
=> n3537);
U4121 : aoi22 port map( a => multiplier_sigs_1_5_port, b =>
adder_mem_array_2_5_port, c => n3537, d => n5256,
outb => n3536);
U4122 : oai22 port map( a => n4784, b => n4785, c => n3536, d => n2172, outb
=> n3533);
U4123 : aoi22 port map( a => multiplier_sigs_1_7_port, b =>
adder_mem_array_2_7_port, c => n3533, d => n5257,
outb => n3532);
U4124 : oai22 port map( a => n4786, b => n4787, c => n3532, d => n2174, outb
=> n3529);
U4125 : aoi22 port map( a => multiplier_sigs_1_9_port, b =>
adder_mem_array_2_9_port, c => n3529, d => n5258,
outb => n3528);
U4126 : oai22 port map( a => n4788, b => n4789, c => n3528, d => n2176, outb
=> n3525);
U4127 : aoi22 port map( a => multiplier_sigs_1_11_port, b =>
adder_mem_array_2_11_port, c => n3525, d => n5259,
outb => n3524);
U4128 : oai22 port map( a => n4790, b => n4791, c => n3524, d => n2178, outb
=> n3521);
U4129 : aoi22 port map( a => multiplier_sigs_1_13_port, b =>
adder_mem_array_2_13_port, c => n3521, d => n5260,
outb => n3520);
U4130 : oai22 port map( a => n4792, b => n4793, c => n3520, d => n2180, outb
=> n3517);
U4131 : aoi22 port map( a => multiplier_sigs_1_15_port, b =>
adder_mem_array_2_15_port, c => n3517, d => n5261,
outb => n3516);
U4132 : oai22 port map( a => n4794, b => n4795, c => n3516, d => n2182, outb
=> n3513);
U4133 : aoi22 port map( a => multiplier_sigs_1_17_port, b =>
adder_mem_array_2_17_port, c => n3513, d => n5262,
outb => n3512);
U4134 : oai22 port map( a => n4796, b => n4797, c => n3512, d => n2184, outb
=> n3509);
U4135 : aoi22 port map( a => multiplier_sigs_1_19_port, b =>
adder_mem_array_2_19_port, c => n3509, d => n5263,
outb => n3508);
U4136 : oai22 port map( a => n4798, b => n4799, c => n3508, d => n2186, outb
=> n3505);
U4137 : aoi22 port map( a => multiplier_sigs_1_21_port, b =>
adder_mem_array_2_21_port, c => n3505, d => n5264,
outb => n3504);
U4138 : oai22 port map( a => n4800, b => n4801, c => n3504, d => n2188, outb
=> n3501);
U4139 : aoi22 port map( a => multiplier_sigs_1_23_port, b =>
adder_mem_array_2_23_port, c => n3501, d => n5265,
outb => n3500);
U4140 : oai22 port map( a => n4802, b => n4803, c => n3500, d => n2190, outb
=> n3497);
U4141 : aoi22 port map( a => multiplier_sigs_1_25_port, b =>
adder_mem_array_2_25_port, c => n3497, d => n5266,
outb => n3496);
U4142 : oai22 port map( a => n4804, b => n4805, c => n3496, d => n2192, outb
=> n3493);
U4143 : aoi22 port map( a => multiplier_sigs_1_27_port, b =>
adder_mem_array_2_27_port, c => n3493, d => n5267,
outb => n3492);
U4144 : oai22 port map( a => n4806, b => n4807, c => n3492, d => n2194, outb
=> n3489);
U4145 : aoi22 port map( a => multiplier_sigs_1_29_port, b =>
adder_mem_array_2_29_port, c => n3489, d => n5268,
outb => n3488);
U4146 : oai22 port map( a => n4808, b => n4809, c => n3488, d => n2196, outb
=> n2199);
U4147 : nand2 port map( a => n5269, b => n5270, outb => n2198);
U4148 : xor2 port map( a => n5210, b => n4887, outb => n2842);
U4149 : xor2 port map( a => n5271, b => n5213, outb => n2845);
U4150 : xor2 port map( a => n5215, b => n4888, outb => n2848);
U4151 : xor2 port map( a => n5272, b => n5216, outb => n2851);
U4152 : xor2 port map( a => n5218, b => n4889, outb => n2854);
U4153 : xor2 port map( a => n5273, b => n5219, outb => n2857);
U4154 : xor2 port map( a => n5221, b => n4890, outb => n2860);
U4155 : xor2 port map( a => n5274, b => n5222, outb => n2863);
U4156 : xor2 port map( a => n5224, b => n4891, outb => n2866);
U4157 : xor2 port map( a => n5275, b => n5225, outb => n2869);
U4158 : xor2 port map( a => n5227, b => n4892, outb => n2872);
U4159 : xor2 port map( a => n5276, b => n5231, outb => n2874);
U4160 : xor2 port map( a => n5230, b => n4893, outb => n316);
U4161 : xor2 port map( a => n5277, b => n2835, outb => n2880);
U4162 : xor2 port map( a => n5278, b => n2838, outb => n2886);
U4163 : xor2 port map( a => n5279, b => n2840, outb => n2889);
U4164 : xor2 port map( a => n5280, b => n2843, outb => n2892);
U4165 : xor2 port map( a => n5281, b => n2846, outb => n2895);
U4166 : xor2 port map( a => n5282, b => n2849, outb => n2898);
U4167 : xor2 port map( a => n5283, b => n2852, outb => n2901);
U4168 : xor2 port map( a => n5284, b => n2855, outb => n2904);
U4169 : xor2 port map( a => n5285, b => n2858, outb => n2907);
U4170 : xor2 port map( a => n5286, b => n2861, outb => n2910);
U4171 : xor2 port map( a => n5287, b => n2864, outb => n2913);
U4172 : xor2 port map( a => n5288, b => n2867, outb => n2915);
U4173 : xor2 port map( a => n5289, b => n2870, outb => n320);
U4174 : xor2 port map( a => n5290, b => n2876, outb => n2921);
U4175 : xor2 port map( a => n5291, b => n2878, outb => n2924);
U4176 : xor2 port map( a => n5292, b => n2882, outb => n2930);
U4177 : xor2 port map( a => n5293, b => n2884, outb => n2933);
U4178 : xor2 port map( a => n5294, b => n2887, outb => n2936);
U4179 : xor2 port map( a => n5295, b => n2890, outb => n2939);
U4180 : xor2 port map( a => n5296, b => n2893, outb => n2942);
U4181 : xor2 port map( a => n5297, b => n2896, outb => n2945);
U4182 : xor2 port map( a => n5298, b => n2899, outb => n2948);
U4183 : xor2 port map( a => n5299, b => n2902, outb => n2951);
U4184 : xor2 port map( a => n5300, b => n2905, outb => n2954);
U4185 : xor2 port map( a => n5301, b => n2908, outb => n2956);
U4186 : xor2 port map( a => n5302, b => n2911, outb => n324);
U4187 : xor2 port map( a => n5303, b => n2917, outb => n2962);
U4188 : xor2 port map( a => n5304, b => n2919, outb => n2965);
U4189 : xor2 port map( a => n5305, b => n2922, outb => n2968);
U4190 : xor2 port map( a => n5306, b => n2926, outb => n2974);
U4191 : xor2 port map( a => n5307, b => n2928, outb => n2977);
U4192 : xor2 port map( a => n5308, b => n2931, outb => n2980);
U4193 : xor2 port map( a => n5309, b => n2934, outb => n2983);
U4194 : xor2 port map( a => n5310, b => n2937, outb => n2986);
U4195 : xor2 port map( a => n5311, b => n2940, outb => n2989);
U4196 : xor2 port map( a => n5312, b => n2943, outb => n2992);
U4197 : xor2 port map( a => n5313, b => n2946, outb => n2995);
U4198 : xor2 port map( a => n5314, b => n2949, outb => n2997);
U4199 : xor2 port map( a => n5315, b => n2952, outb => n328);
U4200 : xor2 port map( a => n5316, b => n2958, outb => n3003);
U4201 : xor2 port map( a => n5317, b => n2960, outb => n3006);
U4202 : xor2 port map( a => n5318, b => n2963, outb => n3009);
U4203 : xor2 port map( a => n5319, b => n2966, outb => n3012);
U4204 : xor2 port map( a => n5320, b => n2970, outb => n3018);
U4205 : xor2 port map( a => n5321, b => n2972, outb => n3021);
U4206 : xor2 port map( a => n5322, b => n2975, outb => n3024);
U4207 : xor2 port map( a => n5323, b => n2978, outb => n3027);
U4208 : xor2 port map( a => n5324, b => n2981, outb => n3030);
U4209 : xor2 port map( a => n5325, b => n2984, outb => n3033);
U4210 : xor2 port map( a => n5326, b => n2987, outb => n3036);
U4211 : xor2 port map( a => n5327, b => n2990, outb => n3038);
U4212 : xor2 port map( a => n5328, b => n2993, outb => n332);
U4213 : xor2 port map( a => n5329, b => n2999, outb => n3044);
U4214 : xor2 port map( a => n5330, b => n3001, outb => n3047);
U4215 : xor2 port map( a => n5331, b => n3004, outb => n3050);
U4216 : xor2 port map( a => n5332, b => n3007, outb => n3053);
U4217 : xor2 port map( a => n5333, b => n3010, outb => n3056);
U4218 : xor2 port map( a => n5334, b => n3014, outb => n3062);
U4219 : xor2 port map( a => n5335, b => n3016, outb => n3065);
U4220 : xor2 port map( a => n5336, b => n3019, outb => n3068);
U4221 : xor2 port map( a => n5337, b => n3022, outb => n3071);
U4222 : xor2 port map( a => n5338, b => n3025, outb => n3074);
U4223 : xor2 port map( a => n5339, b => n3028, outb => n3077);
U4224 : xor2 port map( a => n5340, b => n3031, outb => n3079);
U4225 : xor2 port map( a => n5341, b => n3034, outb => n336);
U4226 : xor2 port map( a => n5342, b => n3040, outb => n3085);
U4227 : xor2 port map( a => n5343, b => n3042, outb => n3088);
U4228 : xor2 port map( a => n5344, b => n3045, outb => n3091);
U4229 : xor2 port map( a => n5345, b => n3048, outb => n3094);
U4230 : xor2 port map( a => n5346, b => n3051, outb => n3097);
U4231 : xor2 port map( a => n5347, b => n3054, outb => n3100);
U4232 : xor2 port map( a => n5348, b => n3058, outb => n3106);
U4233 : xor2 port map( a => n5349, b => n3060, outb => n3109);
U4234 : xor2 port map( a => n5350, b => n3063, outb => n3112);
U4235 : xor2 port map( a => n5351, b => n3066, outb => n3115);
U4236 : xor2 port map( a => n5352, b => n3069, outb => n3118);
U4237 : xor2 port map( a => n5353, b => n3072, outb => n3121);
U4238 : xor2 port map( a => n5354, b => n3075, outb => n341);
U4239 : xor2 port map( a => n5355, b => n3081, outb => n4443);
U4240 : xor2 port map( a => n5356, b => n3083, outb => n4447);
U4241 : xor2 port map( a => n5357, b => n3086, outb => n4451);
U4242 : xor2 port map( a => n5358, b => n3089, outb => n4455);
U4243 : xor2 port map( a => n5359, b => n3092, outb => n4459);
U4244 : xor2 port map( a => n5360, b => n3095, outb => n4463);
U4245 : inv port map( inb => n3119, outb => n5253);
U4246 : xor2 port map( a => n5361, b => n3098, outb => n343);
U4247 : xor2 port map( a => n5362, b => n3119, outb => n347);
U4248 : xor2 port map( a => n4179, b => mult_125_G2_ab_2_14_port, outb =>
n2836);
U4249 : xor2 port map( a => n4180, b => n4181, outb => n5271);
U4250 : xor2 port map( a => n4182, b => n4183, outb => n5272);
U4251 : xor2 port map( a => n4184, b => n4185, outb => n5273);
U4252 : xor2 port map( a => n4186, b => n4187, outb => n5274);
U4253 : xor2 port map( a => n4188, b => n4189, outb => n5275);
U4254 : xor2 port map( a => mult_125_G2_ab_13_15_port, b =>
mult_125_G2_ab_14_14_port, outb => n5276);
U4255 : xor2 port map( a => n4190, b => n1275, outb => n2839);
U4256 : xor2 port map( a => mult_125_G2_ab_3_13_port, b => n1279, outb =>
n5277);
U4257 : xor2 port map( a => mult_125_G2_ab_4_13_port, b => n1281, outb =>
n2841);
U4258 : xor2 port map( a => mult_125_G2_ab_5_13_port, b => n1283, outb =>
n2844);
U4259 : xor2 port map( a => mult_125_G2_ab_6_13_port, b => n1285, outb =>
n2847);
U4260 : xor2 port map( a => n4197, b => n4195, outb => n2850);
U4261 : xor2 port map( a => mult_125_G2_ab_8_13_port, b => n1289, outb =>
n2853);
U4262 : xor2 port map( a => n4200, b => n4198, outb => n2856);
U4263 : xor2 port map( a => mult_125_G2_ab_10_13_port, b => n1293, outb =>
n2859);
U4264 : xor2 port map( a => n4203, b => n4201, outb => n2862);
U4265 : xor2 port map( a => mult_125_G2_ab_12_13_port, b => n1297, outb =>
n2865);
U4266 : xor2 port map( a => n4206, b => n4204, outb => n2868);
U4267 : xor2 port map( a => mult_125_G2_ab_14_13_port, b => n1301, outb =>
n2871);
U4268 : xor2 port map( a => mult_125_G2_ab_15_13_port, b => n4207, outb =>
n2873);
U4269 : xor2 port map( a => n1306, b => mult_125_G2_ab_2_12_port, outb =>
n2877);
U4270 : xor2 port map( a => n4211, b => n4209, outb => n5278);
U4271 : xor2 port map( a => mult_125_G2_ab_4_12_port, b => n1310, outb =>
n2879);
U4272 : xor2 port map( a => mult_125_G2_ab_5_12_port, b => n4212, outb =>
n5279);
U4273 : xor2 port map( a => n4216, b => n4214, outb => n5280);
U4274 : xor2 port map( a => mult_125_G2_ab_7_12_port, b => n1316, outb =>
n5281);
U4275 : xor2 port map( a => n4219, b => n4217, outb => n5282);
U4276 : xor2 port map( a => mult_125_G2_ab_9_12_port, b => n1320, outb =>
n5283);
U4277 : xor2 port map( a => n4222, b => n4220, outb => n5284);
U4278 : xor2 port map( a => mult_125_G2_ab_11_12_port, b => n1324, outb =>
n5285);
U4279 : xor2 port map( a => n4225, b => n4223, outb => n5286);
U4280 : xor2 port map( a => mult_125_G2_ab_13_12_port, b => n1328, outb =>
n5287);
U4281 : xor2 port map( a => n4228, b => n4226, outb => n5288);
U4282 : xor2 port map( a => n5363, b => n1332, outb => n5289);
U4283 : xor2 port map( a => n1335, b => mult_125_G2_ab_2_11_port, outb =>
n2883);
U4284 : xor2 port map( a => mult_125_G2_ab_3_11_port, b => n1338, outb =>
n5290);
U4285 : xor2 port map( a => n4232, b => n4231, outb => n2885);
U4286 : xor2 port map( a => mult_125_G2_ab_5_11_port, b => n1342, outb =>
n5291);
U4287 : xor2 port map( a => mult_125_G2_ab_6_11_port, b => n1344, outb =>
n2888);
U4288 : xor2 port map( a => n4237, b => n4236, outb => n2891);
U4289 : xor2 port map( a => mult_125_G2_ab_8_11_port, b => n1348, outb =>
n2894);
U4290 : xor2 port map( a => n4240, b => n4238, outb => n2897);
U4291 : xor2 port map( a => mult_125_G2_ab_10_11_port, b => n1352, outb =>
n2900);
U4292 : xor2 port map( a => n4243, b => n4241, outb => n2903);
U4293 : xor2 port map( a => mult_125_G2_ab_12_11_port, b => n1356, outb =>
n2906);
U4294 : xor2 port map( a => n4246, b => n4244, outb => n2909);
U4295 : xor2 port map( a => mult_125_G2_ab_14_11_port, b => n1360, outb =>
n2912);
U4296 : xor2 port map( a => n1362, b => n1363, outb => n2914);
U4297 : xor2 port map( a => n1366, b => mult_125_G2_ab_2_10_port, outb =>
n2918);
U4298 : xor2 port map( a => n4250, b => n4248, outb => n5292);
U4299 : xor2 port map( a => mult_125_G2_ab_4_10_port, b => n1370, outb =>
n2920);
U4300 : xor2 port map( a => n1372, b => n1373, outb => n5293);
U4301 : xor2 port map( a => mult_125_G2_ab_6_10_port, b => n1375, outb =>
n2923);
U4302 : xor2 port map( a => mult_125_G2_ab_7_10_port, b => n1377, outb =>
n5294);
U4303 : xor2 port map( a => n4256, b => n4257, outb => n5295);
U4304 : xor2 port map( a => mult_125_G2_ab_9_10_port, b => n1381, outb =>
n5296);
U4305 : xor2 port map( a => n4260, b => n4258, outb => n5297);
U4306 : xor2 port map( a => mult_125_G2_ab_11_10_port, b => n1385, outb =>
n5298);
U4307 : xor2 port map( a => n4263, b => n4261, outb => n5299);
U4308 : xor2 port map( a => mult_125_G2_ab_13_10_port, b => n1389, outb =>
n5300);
U4309 : xor2 port map( a => n4266, b => n4264, outb => n5301);
U4310 : xor2 port map( a => n5364, b => n1393, outb => n5302);
U4311 : xor2 port map( a => n1396, b => mult_125_G2_ab_2_9_port, outb =>
n2927);
U4312 : xor2 port map( a => n4269, b => n4267, outb => n5303);
U4313 : xor2 port map( a => mult_125_G2_ab_4_9_port, b => n1400, outb =>
n2929);
U4314 : xor2 port map( a => mult_125_G2_ab_5_9_port, b => n1402, outb =>
n5304);
U4315 : xor2 port map( a => mult_125_G2_ab_6_9_port, b => n1404, outb =>
n2932);
U4316 : xor2 port map( a => mult_125_G2_ab_7_9_port, b => n1406, outb =>
n5305);
U4317 : xor2 port map( a => n4277, b => n4275, outb => n2935);
U4318 : xor2 port map( a => n4279, b => n4278, outb => n2938);
U4319 : xor2 port map( a => mult_125_G2_ab_10_9_port, b => n1412, outb =>
n2941);
U4320 : xor2 port map( a => n4282, b => n4280, outb => n2944);
U4321 : xor2 port map( a => mult_125_G2_ab_12_9_port, b => n1416, outb =>
n2947);
U4322 : xor2 port map( a => n4285, b => n4283, outb => n2950);
U4323 : xor2 port map( a => mult_125_G2_ab_14_9_port, b => n1420, outb =>
n2953);
U4324 : xor2 port map( a => n1422, b => n1423, outb => n2955);
U4325 : xor2 port map( a => n1426, b => mult_125_G2_ab_2_8_port, outb =>
n2959);
U4326 : xor2 port map( a => n4289, b => n4287, outb => n5306);
U4327 : xor2 port map( a => n4291, b => n1430, outb => n2961);
U4328 : xor2 port map( a => n4293, b => n4292, outb => n5307);
U4329 : xor2 port map( a => mult_125_G2_ab_6_8_port, b => n1434, outb =>
n2964);
U4330 : xor2 port map( a => n4296, b => n4294, outb => n5308);
U4331 : xor2 port map( a => mult_125_G2_ab_8_8_port, b => n1438, outb =>
n2967);
U4332 : xor2 port map( a => mult_125_G2_ab_9_8_port, b => n1440, outb =>
n5309);
U4333 : xor2 port map( a => n4300, b => n4301, outb => n5310);
U4334 : xor2 port map( a => mult_125_G2_ab_11_8_port, b => n1444, outb =>
n5311);
U4335 : xor2 port map( a => n4304, b => n4302, outb => n5312);
U4336 : xor2 port map( a => mult_125_G2_ab_13_8_port, b => n1448, outb =>
n5313);
U4337 : xor2 port map( a => n4307, b => n4305, outb => n5314);
U4338 : xor2 port map( a => n5365, b => n1452, outb => n5315);
U4339 : xor2 port map( a => n1455, b => mult_125_G2_ab_2_7_port, outb =>
n2971);
U4340 : xor2 port map( a => mult_125_G2_ab_3_7_port, b => n1458, outb =>
n5316);
U4341 : xor2 port map( a => n4311, b => n4310, outb => n2973);
U4342 : xor2 port map( a => mult_125_G2_ab_5_7_port, b => n1462, outb =>
n5317);
U4343 : xor2 port map( a => n4314, b => n4312, outb => n2976);
U4344 : xor2 port map( a => mult_125_G2_ab_7_7_port, b => n1466, outb =>
n5318);
U4345 : xor2 port map( a => n4317, b => n4315, outb => n2979);
U4346 : xor2 port map( a => mult_125_G2_ab_9_7_port, b => n1470, outb =>
n5319);
U4347 : xor2 port map( a => n4320, b => n4318, outb => n2982);
U4348 : xor2 port map( a => n4322, b => n4321, outb => n2985);
U4349 : xor2 port map( a => mult_125_G2_ab_12_7_port, b => n1476, outb =>
n2988);
U4350 : xor2 port map( a => n4325, b => n4323, outb => n2991);
U4351 : xor2 port map( a => mult_125_G2_ab_14_7_port, b => n1480, outb =>
n2994);
U4352 : xor2 port map( a => n1482, b => n1483, outb => n2996);
U4353 : xor2 port map( a => n1486, b => mult_125_G2_ab_2_6_port, outb =>
n3000);
U4354 : xor2 port map( a => n4329, b => n4327, outb => n5320);
U4355 : xor2 port map( a => mult_125_G2_ab_4_6_port, b => n1490, outb =>
n3002);
U4356 : xor2 port map( a => n1492, b => n1493, outb => n5321);
U4357 : xor2 port map( a => mult_125_G2_ab_6_6_port, b => n1495, outb =>
n3005);
U4358 : xor2 port map( a => n4334, b => n4332, outb => n5322);
U4359 : xor2 port map( a => mult_125_G2_ab_8_6_port, b => n1499, outb =>
n3008);
U4360 : xor2 port map( a => n1501, b => n1502, outb => n5323);
U4361 : xor2 port map( a => mult_125_G2_ab_10_6_port, b => n1504, outb =>
n3011);
U4362 : xor2 port map( a => mult_125_G2_ab_11_6_port, b => n1506, outb =>
n5324);
U4363 : xor2 port map( a => n4340, b => n4341, outb => n5325);
U4364 : xor2 port map( a => mult_125_G2_ab_13_6_port, b => n1510, outb =>
n5326);
U4365 : xor2 port map( a => n4344, b => n4342, outb => n5327);
U4366 : xor2 port map( a => n5366, b => n1514, outb => n5328);
U4367 : xor2 port map( a => n1517, b => mult_125_G2_ab_2_5_port, outb =>
n3015);
U4368 : xor2 port map( a => mult_125_G2_ab_3_5_port, b => n1520, outb =>
n5329);
U4369 : xor2 port map( a => mult_125_G2_ab_4_5_port, b => n1522, outb =>
n3017);
U4370 : xor2 port map( a => mult_125_G2_ab_5_5_port, b => n1524, outb =>
n5330);
U4371 : xor2 port map( a => n1526, b => n1527, outb => n3020);
U4372 : xor2 port map( a => mult_125_G2_ab_7_5_port, b => n1529, outb =>
n5331);
U4373 : xor2 port map( a => mult_125_G2_ab_8_5_port, b => n1531, outb =>
n3023);
U4374 : xor2 port map( a => mult_125_G2_ab_9_5_port, b => n1533, outb =>
n5332);
U4375 : xor2 port map( a => n4356, b => n4354, outb => n3026);
U4376 : xor2 port map( a => mult_125_G2_ab_11_5_port, b => n1537, outb =>
n5333);
U4377 : xor2 port map( a => n4359, b => n4357, outb => n3029);
U4378 : xor2 port map( a => n4361, b => n1541, outb => n3032);
U4379 : xor2 port map( a => mult_125_G2_ab_14_5_port, b => n1543, outb =>
n3035);
U4380 : xor2 port map( a => n1545, b => n1546, outb => n3037);
U4381 : xor2 port map( a => n1549, b => mult_125_G2_ab_2_4_port, outb =>
n3041);
U4382 : xor2 port map( a => n4365, b => n4363, outb => n5334);
U4383 : xor2 port map( a => mult_125_G2_ab_4_4_port, b => n1553, outb =>
n3043);
U4384 : xor2 port map( a => n1555, b => n1556, outb => n5335);
U4385 : xor2 port map( a => mult_125_G2_ab_6_4_port, b => n1558, outb =>
n3046);
U4386 : xor2 port map( a => n1560, b => n1561, outb => n5336);
U4387 : xor2 port map( a => mult_125_G2_ab_8_4_port, b => n1563, outb =>
n3049);
U4388 : xor2 port map( a => mult_125_G2_ab_9_4_port, b => n1565, outb =>
n5337);
U4389 : xor2 port map( a => mult_125_G2_ab_10_4_port, b => n1567, outb =>
n3052);
U4390 : xor2 port map( a => n1569, b => n1570, outb => n5338);
U4391 : xor2 port map( a => mult_125_G2_ab_12_4_port, b => n1572, outb =>
n3055);
U4392 : xor2 port map( a => mult_125_G2_ab_13_4_port, b => n1574, outb =>
n5339);
U4393 : xor2 port map( a => mult_125_G2_ab_14_4_port, b => n1576, outb =>
n5340);
U4394 : xor2 port map( a => mult_125_G2_ab_15_4_port, b => n1579, outb =>
n5341);
U4395 : xor2 port map( a => n1582, b => mult_125_G2_ab_2_3_port, outb =>
n3059);
U4396 : xor2 port map( a => mult_125_G2_ab_3_3_port, b => n1585, outb =>
n5342);
U4397 : xor2 port map( a => mult_125_G2_ab_4_3_port, b => n1587, outb =>
n3061);
U4398 : xor2 port map( a => mult_125_G2_ab_5_3_port, b => n1589, outb =>
n5343);
U4399 : xor2 port map( a => mult_125_G2_ab_6_3_port, b => n1591, outb =>
n3064);
U4400 : xor2 port map( a => mult_125_G2_ab_7_3_port, b => n1593, outb =>
n5344);
U4401 : xor2 port map( a => mult_125_G2_ab_8_3_port, b => n1595, outb =>
n3067);
U4402 : xor2 port map( a => mult_125_G2_ab_9_3_port, b => n1597, outb =>
n5345);
U4403 : xor2 port map( a => mult_125_G2_ab_10_3_port, b => n1599, outb =>
n3070);
U4404 : xor2 port map( a => mult_125_G2_ab_11_3_port, b => n1601, outb =>
n5346);
U4405 : xor2 port map( a => n4394, b => n4392, outb => n3073);
U4406 : xor2 port map( a => mult_125_G2_ab_13_3_port, b => n1605, outb =>
n5347);
U4407 : xor2 port map( a => mult_125_G2_ab_14_3_port, b => n1607, outb =>
n3076);
U4408 : xor2 port map( a => mult_125_G2_ab_15_3_port, b => n1609, outb =>
n3078);
U4409 : xor2 port map( a => n1612, b => mult_125_G2_ab_2_2_port, outb =>
n3082);
U4410 : xor2 port map( a => n4400, b => n4398, outb => n5348);
U4411 : xor2 port map( a => mult_125_G2_ab_4_2_port, b => n1616, outb =>
n3084);
U4412 : xor2 port map( a => mult_125_G2_ab_5_2_port, b => n1618, outb =>
n5349);
U4413 : xor2 port map( a => mult_125_G2_ab_6_2_port, b => n1620, outb =>
n3087);
U4414 : xor2 port map( a => n1622, b => n1623, outb => n5350);
U4415 : xor2 port map( a => mult_125_G2_ab_8_2_port, b => n1625, outb =>
n3090);
U4416 : xor2 port map( a => mult_125_G2_ab_9_2_port, b => n1627, outb =>
n5351);
U4417 : xor2 port map( a => mult_125_G2_ab_10_2_port, b => n1629, outb =>
n3093);
U4418 : xor2 port map( a => mult_125_G2_ab_11_2_port, b => n1631, outb =>
n5352);
U4419 : xor2 port map( a => mult_125_G2_ab_12_2_port, b => n1633, outb =>
n3096);
U4420 : xor2 port map( a => mult_125_G2_ab_13_2_port, b => n1635, outb =>
n5353);
U4421 : xor2 port map( a => mult_125_G2_ab_14_2_port, b => n1637, outb =>
n3099);
U4422 : xor2 port map( a => n5250, b => n4415, outb => n5354);
U4423 : xor2 port map( a => n4418, b => mult_125_G2_ab_2_1_port, outb =>
n3103);
U4424 : xor2 port map( a => n4419, b => n4417, outb => n5355);
U4425 : xor2 port map( a => mult_125_G2_ab_4_1_port, b => n4421, outb =>
n3105);
U4426 : xor2 port map( a => mult_125_G2_ab_5_1_port, b => n1648, outb =>
n5367);
U4427 : xor2 port map( a => n4424, b => n1650, outb => n3108);
U4428 : xor2 port map( a => n5368, b => n1652, outb => n5357);
U4429 : xor2 port map( a => mult_125_G2_ab_8_1_port, b => n4425, outb =>
n3111);
U4430 : xor2 port map( a => n5369, b => n1656, outb => n5358);
U4431 : xor2 port map( a => n4430, b => n1658, outb => n3114);
U4432 : xor2 port map( a => n5370, b => n1660, outb => n5359);
U4433 : xor2 port map( a => n4433, b => n1662, outb => n3117);
U4434 : xor2 port map( a => n5371, b => n1664, outb => n5360);
U4435 : xor2 port map( a => n4436, b => n4434, outb => n3120);
U4436 : xor2 port map( a => n5372, b => n1668, outb => n5361);
U4437 : xor2 port map( a => mult_125_G2_ab_15_0_port, b => n1696, outb =>
n5362);
U4438 : xor2 port map( a => mult_125_G2_ab_11_0_port, b => n1688, outb =>
n3122);
U4439 : xor2 port map( a => mult_125_G2_ab_9_0_port, b => n1684, outb =>
n3123);
U4440 : xor2 port map( a => mult_125_G2_ab_7_0_port, b => n1680, outb =>
n3124);
U4441 : xor2 port map( a => mult_125_G2_ab_5_0_port, b => n1676, outb =>
n3125);
U4442 : xor2 port map( a => mult_125_G2_ab_3_0_port, b => n1672, outb =>
n3126);
U4443 : xor2 port map( a => n344, b => mult_125_G2_ZA, outb => n3127);
U4444 : xor2 port map( a => mult_125_G2_ab_13_0_port, b => n1692, outb =>
n3128);
U4445 : xor2 port map( a => n5270, b => adder_mem_array_2_32_port, outb =>
n3485);
U4446 : xor2 port map( a => n4808, b => adder_mem_array_2_30_port, outb =>
n3487);
U4447 : xor2 port map( a => n4806, b => adder_mem_array_2_28_port, outb =>
n3491);
U4448 : xor2 port map( a => n4804, b => adder_mem_array_2_26_port, outb =>
n3495);
U4449 : xor2 port map( a => n4802, b => adder_mem_array_2_24_port, outb =>
n3499);
U4450 : xor2 port map( a => n4800, b => adder_mem_array_2_22_port, outb =>
n3503);
U4451 : xor2 port map( a => n4798, b => adder_mem_array_2_20_port, outb =>
n3507);
U4452 : xor2 port map( a => n4796, b => adder_mem_array_2_18_port, outb =>
n3511);
U4453 : xor2 port map( a => n4794, b => adder_mem_array_2_16_port, outb =>
n3515);
U4454 : xor2 port map( a => n4792, b => adder_mem_array_2_14_port, outb =>
n3519);
U4455 : xor2 port map( a => n4790, b => adder_mem_array_2_12_port, outb =>
n3523);
U4456 : xor2 port map( a => n4788, b => adder_mem_array_2_10_port, outb =>
n3527);
U4457 : xor2 port map( a => n4786, b => adder_mem_array_2_8_port, outb =>
n3531);
U4458 : xor2 port map( a => n4784, b => adder_mem_array_2_6_port, outb =>
n3535);
U4459 : xor2 port map( a => n4782, b => adder_mem_array_2_4_port, outb =>
n3539);
U4460 : xor2 port map( a => n4780, b => adder_mem_array_2_2_port, outb =>
n3543);
U4461 : oai22 port map( a => n5374, b => n5375, c => n1698, d => n4464, outb
=> n5373);
U4462 : aoi22 port map( a => mult_125_ab_2_15_port, b =>
mult_125_ab_3_14_port, c => n5373, d => n5377, outb
=> n5376);
U4463 : oai22 port map( a => n4465, b => n4466, c => n5376, d => n1700, outb
=> n5378);
U4464 : aoi22 port map( a => mult_125_ab_4_15_port, b =>
mult_125_ab_5_14_port, c => n5378, d => n5380, outb
=> n5379);
U4465 : oai22 port map( a => n4467, b => n4468, c => n5379, d => n1702, outb
=> n5381);
U4466 : aoi22 port map( a => mult_125_ab_6_15_port, b =>
mult_125_ab_7_14_port, c => n5381, d => n5383, outb
=> n5382);
U4467 : oai22 port map( a => n4469, b => n4470, c => n5382, d => n1704, outb
=> n5384);
U4468 : aoi22 port map( a => mult_125_ab_8_15_port, b =>
mult_125_ab_9_14_port, c => n5384, d => n5386, outb
=> n5385);
U4469 : oai22 port map( a => n4471, b => n4472, c => n5385, d => n1706, outb
=> n5387);
U4470 : aoi22 port map( a => mult_125_ab_10_15_port, b =>
mult_125_ab_11_14_port, c => n5387, d => n5389, outb
=> n5388);
U4471 : oai22 port map( a => n4473, b => n4474, c => n5388, d => n1708, outb
=> n5390);
U4472 : aoi22 port map( a => mult_125_ab_12_15_port, b =>
mult_125_ab_13_14_port, c => n5390, d => n5392, outb
=> n5391);
U4473 : aoi22 port map( a => mult_125_ab_13_15_port, b =>
mult_125_ab_14_14_port, c => n5394, d => n5395, outb
=> n5393);
U4474 : aoi22 port map( a => mult_125_ab_14_15_port, b =>
mult_125_ab_15_14_port, c => n5396, d => n5397, outb
=> n277);
U4475 : inv port map( inb => n4492, outb => n1741);
U4476 : aoi22 port map( a => n1741, b => mult_125_ab_15_13_port, c => n5398,
d => n3171, outb => n279);
U4477 : aoi22 port map( a => n1770, b => mult_125_ab_15_12_port, c => n5399,
d => n3167, outb => n281);
U4478 : oai22 port map( a => n1801, b => n1800, c => n5401, d => n3212, outb
=> n5400);
U4479 : inv port map( inb => n1817, outb => n4542);
U4480 : aoi22 port map( a => n1831, b => mult_125_ab_15_10_port, c => n5402,
d => n3208, outb => n285);
U4481 : oai22 port map( a => n1861, b => n1860, c => n5404, d => n3253, outb
=> n5403);
U4482 : inv port map( inb => n1880, outb => n4586);
U4483 : aoi22 port map( a => n1890, b => mult_125_ab_15_8_port, c => n5405,
d => n3249, outb => n289);
U4484 : oai22 port map( a => n1921, b => n1920, c => n5407, d => n3294, outb
=> n5406);
U4485 : inv port map( inb => n1946, outb => n4626);
U4486 : aoi22 port map( a => n1952, b => mult_125_ab_15_6_port, c => n5408,
d => n3290, outb => n293);
U4487 : oai22 port map( a => n1984, b => n1983, c => n5410, d => n3335, outb
=> n5409);
U4488 : aoi22 port map( a => n5411, b => mult_125_ab_15_4_port, c => n2015,
d => n3331, outb => n297);
U4489 : aoi22 port map( a => n2047, b => mult_125_ab_15_3_port, c => n5412,
d => n3376, outb => n299);
U4490 : oai22 port map( a => n4700, b => n5413, c => n2076, d => n3372, outb
=> n302);
U4491 : aoi22 port map( a => n2106, b => mult_125_ab_15_1_port, c => n5414,
d => n3395, outb => n304);
U4492 : aoi22 port map( a => n2134, b => mult_125_ab_15_0_port, c => n5415,
d => n5416, outb => n306);
U4493 : aoi22 port map( a => adder_mem_array_1_1_port, b => n2164, c =>
n5417, d => n3447, outb => n3471);
U4494 : oai22 port map( a => n4777, b => n4778, c => n3471, d => n2165, outb
=> n3448);
U4495 : aoi22 port map( a => adder_mem_array_1_3_port, b =>
multiplier_sigs_0_3_port, c => n3448, d => n5418,
outb => n3608);
U4496 : oai22 port map( a => n4810, b => n4811, c => n3608, d => n2201, outb
=> n3597);
U4497 : aoi22 port map( a => multiplier_sigs_0_5_port, b =>
adder_mem_array_1_5_port, c => n3597, d => n5419,
outb => n3596);
U4498 : oai22 port map( a => n4812, b => n4813, c => n3596, d => n2203, outb
=> n3593);
U4499 : aoi22 port map( a => multiplier_sigs_0_7_port, b =>
adder_mem_array_1_7_port, c => n3593, d => n5420,
outb => n3592);
U4500 : oai22 port map( a => n4814, b => n4815, c => n3592, d => n2205, outb
=> n3589);
U4501 : aoi22 port map( a => multiplier_sigs_0_9_port, b =>
adder_mem_array_1_9_port, c => n3589, d => n5421,
outb => n3588);
U4502 : oai22 port map( a => n4816, b => n4817, c => n3588, d => n2207, outb
=> n3585);
U4503 : aoi22 port map( a => multiplier_sigs_0_11_port, b =>
adder_mem_array_1_11_port, c => n3585, d => n5422,
outb => n3584);
U4504 : oai22 port map( a => n4818, b => n4819, c => n3584, d => n2209, outb
=> n3581);
U4505 : aoi22 port map( a => multiplier_sigs_0_13_port, b =>
adder_mem_array_1_13_port, c => n3581, d => n5423,
outb => n3580);
U4506 : oai22 port map( a => n4820, b => n4821, c => n3580, d => n2211, outb
=> n3577);
U4507 : aoi22 port map( a => multiplier_sigs_0_15_port, b =>
adder_mem_array_1_15_port, c => n3577, d => n5424,
outb => n3576);
U4508 : oai22 port map( a => n4822, b => n4823, c => n3576, d => n2213, outb
=> n3573);
U4509 : aoi22 port map( a => multiplier_sigs_0_17_port, b =>
adder_mem_array_1_17_port, c => n3573, d => n5425,
outb => n3572);
U4510 : oai22 port map( a => n4824, b => n4825, c => n3572, d => n2215, outb
=> n3569);
U4511 : aoi22 port map( a => multiplier_sigs_0_19_port, b =>
adder_mem_array_1_19_port, c => n3569, d => n5426,
outb => n3568);
U4512 : oai22 port map( a => n4826, b => n4827, c => n3568, d => n2217, outb
=> n3565);
U4513 : aoi22 port map( a => multiplier_sigs_0_21_port, b =>
adder_mem_array_1_21_port, c => n3565, d => n5427,
outb => n3564);
U4514 : oai22 port map( a => n4828, b => n4829, c => n3564, d => n2219, outb
=> n3561);
U4515 : aoi22 port map( a => multiplier_sigs_0_23_port, b =>
adder_mem_array_1_23_port, c => n3561, d => n5428,
outb => n3560);
U4516 : oai22 port map( a => n4830, b => n4831, c => n3560, d => n2221, outb
=> n3557);
U4517 : aoi22 port map( a => multiplier_sigs_0_25_port, b =>
adder_mem_array_1_25_port, c => n3557, d => n5429,
outb => n3556);
U4518 : oai22 port map( a => n4832, b => n4833, c => n3556, d => n2223, outb
=> n3553);
U4519 : aoi22 port map( a => multiplier_sigs_0_27_port, b =>
adder_mem_array_1_27_port, c => n3553, d => n5430,
outb => n3552);
U4520 : oai22 port map( a => n4834, b => n4835, c => n3552, d => n2225, outb
=> n3549);
U4521 : aoi22 port map( a => multiplier_sigs_0_29_port, b =>
adder_mem_array_1_29_port, c => n3549, d => n5431,
outb => n3548);
U4522 : oai22 port map( a => n4836, b => n4837, c => n3548, d => n2227, outb
=> n2230);
U4523 : nand2 port map( a => n5432, b => n5433, outb => n2229);
U4524 : xor2 port map( a => n5373, b => n4894, outb => n3139);
U4525 : xor2 port map( a => n5434, b => n5376, outb => n3142);
U4526 : xor2 port map( a => n5378, b => n4895, outb => n3145);
U4527 : xor2 port map( a => n5435, b => n5379, outb => n3148);
U4528 : xor2 port map( a => n5381, b => n4896, outb => n3151);
U4529 : xor2 port map( a => n5436, b => n5382, outb => n3154);
U4530 : xor2 port map( a => n5384, b => n4897, outb => n3157);
U4531 : xor2 port map( a => n5437, b => n5385, outb => n3160);
U4532 : xor2 port map( a => n5387, b => n4898, outb => n3163);
U4533 : xor2 port map( a => n5438, b => n5388, outb => n3166);
U4534 : xor2 port map( a => n5390, b => n4899, outb => n3169);
U4535 : xor2 port map( a => n5439, b => n5394, outb => n3171);
U4536 : xor2 port map( a => n5393, b => n4900, outb => n280);
U4537 : xor2 port map( a => n5440, b => n3132, outb => n3177);
U4538 : xor2 port map( a => n5441, b => n3135, outb => n3183);
U4539 : xor2 port map( a => n5442, b => n3137, outb => n3186);
U4540 : xor2 port map( a => n5443, b => n3140, outb => n3189);
U4541 : xor2 port map( a => n5444, b => n3143, outb => n3192);
U4542 : xor2 port map( a => n5445, b => n3146, outb => n3195);
U4543 : xor2 port map( a => n5446, b => n3149, outb => n3198);
U4544 : xor2 port map( a => n5447, b => n3152, outb => n3201);
U4545 : xor2 port map( a => n5448, b => n3155, outb => n3204);
U4546 : xor2 port map( a => n5449, b => n3158, outb => n3207);
U4547 : xor2 port map( a => n5450, b => n3161, outb => n3210);
U4548 : xor2 port map( a => n5451, b => n3164, outb => n3212);
U4549 : xor2 port map( a => n5452, b => n3167, outb => n284);
U4550 : xor2 port map( a => n5453, b => n3173, outb => n3218);
U4551 : xor2 port map( a => n5454, b => n3175, outb => n3221);
U4552 : xor2 port map( a => n5455, b => n3179, outb => n3227);
U4553 : xor2 port map( a => n5456, b => n3181, outb => n3230);
U4554 : xor2 port map( a => n5457, b => n3184, outb => n3233);
U4555 : xor2 port map( a => n5458, b => n3187, outb => n3236);
U4556 : xor2 port map( a => n5459, b => n3190, outb => n3239);
U4557 : xor2 port map( a => n5460, b => n3193, outb => n3242);
U4558 : xor2 port map( a => n5461, b => n3196, outb => n3245);
U4559 : xor2 port map( a => n5462, b => n3199, outb => n3248);
U4560 : xor2 port map( a => n5463, b => n3202, outb => n3251);
U4561 : xor2 port map( a => n5464, b => n3205, outb => n3253);
U4562 : xor2 port map( a => n5465, b => n3208, outb => n288);
U4563 : xor2 port map( a => n5466, b => n3214, outb => n3259);
U4564 : xor2 port map( a => n5467, b => n3216, outb => n3262);
U4565 : xor2 port map( a => n5468, b => n3219, outb => n3265);
U4566 : xor2 port map( a => n5469, b => n3223, outb => n3271);
U4567 : xor2 port map( a => n5470, b => n3225, outb => n3274);
U4568 : xor2 port map( a => n5471, b => n3228, outb => n3277);
U4569 : xor2 port map( a => n5472, b => n3231, outb => n3280);
U4570 : xor2 port map( a => n5473, b => n3234, outb => n3283);
U4571 : xor2 port map( a => n5474, b => n3237, outb => n3286);
U4572 : xor2 port map( a => n5475, b => n3240, outb => n3289);
U4573 : xor2 port map( a => n5476, b => n3243, outb => n3292);
U4574 : xor2 port map( a => n5477, b => n3246, outb => n3294);
U4575 : xor2 port map( a => n5478, b => n3249, outb => n292);
U4576 : xor2 port map( a => n5479, b => n3255, outb => n3300);
U4577 : xor2 port map( a => n5480, b => n3257, outb => n3303);
U4578 : xor2 port map( a => n5481, b => n3260, outb => n3306);
U4579 : xor2 port map( a => n5482, b => n3263, outb => n3309);
U4580 : xor2 port map( a => n5483, b => n3267, outb => n3315);
U4581 : xor2 port map( a => n5484, b => n3269, outb => n3318);
U4582 : xor2 port map( a => n5485, b => n3272, outb => n3321);
U4583 : xor2 port map( a => n5486, b => n3275, outb => n3324);
U4584 : xor2 port map( a => n5487, b => n3278, outb => n3327);
U4585 : xor2 port map( a => n5488, b => n3281, outb => n3330);
U4586 : xor2 port map( a => n5489, b => n3284, outb => n3333);
U4587 : xor2 port map( a => n5490, b => n3287, outb => n3335);
U4588 : xor2 port map( a => n5491, b => n3290, outb => n296);
U4589 : xor2 port map( a => n5492, b => n3296, outb => n3341);
U4590 : xor2 port map( a => n5493, b => n3298, outb => n3344);
U4591 : xor2 port map( a => n5494, b => n3301, outb => n3347);
U4592 : xor2 port map( a => n5495, b => n3304, outb => n3350);
U4593 : xor2 port map( a => n5496, b => n3307, outb => n3353);
U4594 : xor2 port map( a => n5497, b => n3311, outb => n3359);
U4595 : xor2 port map( a => n5498, b => n3313, outb => n3362);
U4596 : xor2 port map( a => n5499, b => n3316, outb => n3365);
U4597 : xor2 port map( a => n5500, b => n3319, outb => n3368);
U4598 : xor2 port map( a => n5501, b => n3322, outb => n3371);
U4599 : xor2 port map( a => n5502, b => n3325, outb => n3374);
U4600 : xor2 port map( a => n5503, b => n3328, outb => n3376);
U4601 : xor2 port map( a => n5504, b => n3331, outb => n300);
U4602 : xor2 port map( a => n5505, b => n3337, outb => n3382);
U4603 : xor2 port map( a => n5506, b => n3339, outb => n3385);
U4604 : xor2 port map( a => n5507, b => n3342, outb => n3388);
U4605 : xor2 port map( a => n5508, b => n3345, outb => n3391);
U4606 : xor2 port map( a => n5509, b => n3348, outb => n3394);
U4607 : xor2 port map( a => n5510, b => n3351, outb => n3397);
U4608 : xor2 port map( a => n5511, b => n3355, outb => n3403);
U4609 : xor2 port map( a => n5512, b => n3357, outb => n3406);
U4610 : xor2 port map( a => n5513, b => n3360, outb => n3409);
U4611 : xor2 port map( a => n5514, b => n3363, outb => n3412);
U4612 : xor2 port map( a => n5515, b => n3366, outb => n3415);
U4613 : xor2 port map( a => n5516, b => n3369, outb => n3418);
U4614 : xor2 port map( a => n5517, b => n3372, outb => n305);
U4615 : xor2 port map( a => n5518, b => n3378, outb => n4728);
U4616 : xor2 port map( a => n5519, b => n3380, outb => n4732);
U4617 : xor2 port map( a => n5520, b => n3383, outb => n4736);
U4618 : xor2 port map( a => n5521, b => n3386, outb => n4740);
U4619 : xor2 port map( a => n5522, b => n3389, outb => n4744);
U4620 : xor2 port map( a => n5523, b => n3392, outb => n4748);
U4621 : inv port map( inb => n3416, outb => n5416);
U4622 : xor2 port map( a => n5524, b => n3395, outb => n307);
U4623 : xor2 port map( a => n5525, b => n3416, outb => n311);
U4624 : xor2 port map( a => n4464, b => mult_125_ab_2_14_port, outb => n3133
);
U4625 : xor2 port map( a => n4465, b => n4466, outb => n5434);
U4626 : xor2 port map( a => n4467, b => n4468, outb => n5435);
U4627 : xor2 port map( a => n4469, b => n4470, outb => n5436);
U4628 : xor2 port map( a => n4471, b => n4472, outb => n5437);
U4629 : xor2 port map( a => n4473, b => n4474, outb => n5438);
U4630 : xor2 port map( a => mult_125_ab_13_15_port, b =>
mult_125_ab_14_14_port, outb => n5439);
U4631 : xor2 port map( a => n4475, b => n1713, outb => n3136);
U4632 : xor2 port map( a => mult_125_ab_3_13_port, b => n1717, outb => n5440
);
U4633 : xor2 port map( a => mult_125_ab_4_13_port, b => n1719, outb => n3138
);
U4634 : xor2 port map( a => mult_125_ab_5_13_port, b => n1721, outb => n3141
);
U4635 : xor2 port map( a => mult_125_ab_6_13_port, b => n1723, outb => n3144
);
U4636 : xor2 port map( a => n4482, b => n4480, outb => n3147);
U4637 : xor2 port map( a => mult_125_ab_8_13_port, b => n1727, outb => n3150
);
U4638 : xor2 port map( a => n4485, b => n4483, outb => n3153);
U4639 : xor2 port map( a => mult_125_ab_10_13_port, b => n1731, outb =>
n3156);
U4640 : xor2 port map( a => n4488, b => n4486, outb => n3159);
U4641 : xor2 port map( a => mult_125_ab_12_13_port, b => n1735, outb =>
n3162);
U4642 : xor2 port map( a => n4491, b => n4489, outb => n3165);
U4643 : xor2 port map( a => mult_125_ab_14_13_port, b => n1739, outb =>
n3168);
U4644 : xor2 port map( a => mult_125_ab_15_13_port, b => n4492, outb =>
n3170);
U4645 : xor2 port map( a => n1744, b => mult_125_ab_2_12_port, outb => n3174
);
U4646 : xor2 port map( a => n4496, b => n4494, outb => n5441);
U4647 : xor2 port map( a => mult_125_ab_4_12_port, b => n1748, outb => n3176
);
U4648 : xor2 port map( a => mult_125_ab_5_12_port, b => n4497, outb => n5442
);
U4649 : xor2 port map( a => n4501, b => n4499, outb => n5443);
U4650 : xor2 port map( a => mult_125_ab_7_12_port, b => n1754, outb => n5444
);
U4651 : xor2 port map( a => n4504, b => n4502, outb => n5445);
U4652 : xor2 port map( a => mult_125_ab_9_12_port, b => n1758, outb => n5446
);
U4653 : xor2 port map( a => n4507, b => n4505, outb => n5447);
U4654 : xor2 port map( a => mult_125_ab_11_12_port, b => n1762, outb =>
n5448);
U4655 : xor2 port map( a => n4510, b => n4508, outb => n5449);
U4656 : xor2 port map( a => mult_125_ab_13_12_port, b => n1766, outb =>
n5450);
U4657 : xor2 port map( a => n4513, b => n4511, outb => n5451);
U4658 : xor2 port map( a => n5526, b => n1770, outb => n5452);
U4659 : xor2 port map( a => n1773, b => mult_125_ab_2_11_port, outb => n3180
);
U4660 : xor2 port map( a => mult_125_ab_3_11_port, b => n1776, outb => n5453
);
U4661 : xor2 port map( a => n4517, b => n4516, outb => n3182);
U4662 : xor2 port map( a => mult_125_ab_5_11_port, b => n1780, outb => n5454
);
U4663 : xor2 port map( a => mult_125_ab_6_11_port, b => n1782, outb => n3185
);
U4664 : xor2 port map( a => n4522, b => n4521, outb => n3188);
U4665 : xor2 port map( a => mult_125_ab_8_11_port, b => n1786, outb => n3191
);
U4666 : xor2 port map( a => n4525, b => n4523, outb => n3194);
U4667 : xor2 port map( a => mult_125_ab_10_11_port, b => n1790, outb =>
n3197);
U4668 : xor2 port map( a => n4528, b => n4526, outb => n3200);
U4669 : xor2 port map( a => mult_125_ab_12_11_port, b => n1794, outb =>
n3203);
U4670 : xor2 port map( a => n4531, b => n4529, outb => n3206);
U4671 : xor2 port map( a => mult_125_ab_14_11_port, b => n1798, outb =>
n3209);
U4672 : xor2 port map( a => n1800, b => n1801, outb => n3211);
U4673 : xor2 port map( a => n1804, b => mult_125_ab_2_10_port, outb => n3215
);
U4674 : xor2 port map( a => n4535, b => n4533, outb => n5455);
U4675 : xor2 port map( a => mult_125_ab_4_10_port, b => n1808, outb => n3217
);
U4676 : xor2 port map( a => n1810, b => n1811, outb => n5456);
U4677 : xor2 port map( a => mult_125_ab_6_10_port, b => n1813, outb => n3220
);
U4678 : xor2 port map( a => mult_125_ab_7_10_port, b => n1815, outb => n5457
);
U4679 : xor2 port map( a => n4541, b => n4542, outb => n5458);
U4680 : xor2 port map( a => mult_125_ab_9_10_port, b => n1819, outb => n5459
);
U4681 : xor2 port map( a => n4545, b => n4543, outb => n5460);
U4682 : xor2 port map( a => mult_125_ab_11_10_port, b => n1823, outb =>
n5461);
U4683 : xor2 port map( a => n4548, b => n4546, outb => n5462);
U4684 : xor2 port map( a => mult_125_ab_13_10_port, b => n1827, outb =>
n5463);
U4685 : xor2 port map( a => n4551, b => n4549, outb => n5464);
U4686 : xor2 port map( a => n5527, b => n1831, outb => n5465);
U4687 : xor2 port map( a => n1834, b => mult_125_ab_2_9_port, outb => n3224)
;
U4688 : xor2 port map( a => n4554, b => n4552, outb => n5466);
U4689 : xor2 port map( a => mult_125_ab_4_9_port, b => n1838, outb => n3226)
;
U4690 : xor2 port map( a => mult_125_ab_5_9_port, b => n1840, outb => n5467)
;
U4691 : xor2 port map( a => mult_125_ab_6_9_port, b => n1842, outb => n3229)
;
U4692 : xor2 port map( a => mult_125_ab_7_9_port, b => n1844, outb => n5468)
;
U4693 : xor2 port map( a => n4562, b => n4560, outb => n3232);
U4694 : xor2 port map( a => n4564, b => n4563, outb => n3235);
U4695 : xor2 port map( a => mult_125_ab_10_9_port, b => n1850, outb => n3238
);
U4696 : xor2 port map( a => n4567, b => n4565, outb => n3241);
U4697 : xor2 port map( a => mult_125_ab_12_9_port, b => n1854, outb => n3244
);
U4698 : xor2 port map( a => n4570, b => n4568, outb => n3247);
U4699 : xor2 port map( a => mult_125_ab_14_9_port, b => n1858, outb => n3250
);
U4700 : xor2 port map( a => n1860, b => n1861, outb => n3252);
U4701 : xor2 port map( a => n1864, b => mult_125_ab_2_8_port, outb => n3256)
;
U4702 : xor2 port map( a => n4574, b => n4572, outb => n5469);
U4703 : xor2 port map( a => n4576, b => n1868, outb => n3258);
U4704 : xor2 port map( a => n4578, b => n4577, outb => n5470);
U4705 : xor2 port map( a => mult_125_ab_6_8_port, b => n1872, outb => n3261)
;
U4706 : xor2 port map( a => n4581, b => n4579, outb => n5471);
U4707 : xor2 port map( a => mult_125_ab_8_8_port, b => n1876, outb => n3264)
;
U4708 : xor2 port map( a => mult_125_ab_9_8_port, b => n1878, outb => n5472)
;
U4709 : xor2 port map( a => n4585, b => n4586, outb => n5473);
U4710 : xor2 port map( a => mult_125_ab_11_8_port, b => n1882, outb => n5474
);
U4711 : xor2 port map( a => n4589, b => n4587, outb => n5475);
U4712 : xor2 port map( a => mult_125_ab_13_8_port, b => n1886, outb => n5476
);
U4713 : xor2 port map( a => n4592, b => n4590, outb => n5477);
U4714 : xor2 port map( a => n5528, b => n1890, outb => n5478);
U4715 : xor2 port map( a => n1893, b => mult_125_ab_2_7_port, outb => n3268)
;
U4716 : xor2 port map( a => mult_125_ab_3_7_port, b => n1896, outb => n5479)
;
U4717 : xor2 port map( a => n4596, b => n4595, outb => n3270);
U4718 : xor2 port map( a => mult_125_ab_5_7_port, b => n1900, outb => n5480)
;
U4719 : xor2 port map( a => n4599, b => n4597, outb => n3273);
U4720 : xor2 port map( a => mult_125_ab_7_7_port, b => n1904, outb => n5481)
;
U4721 : xor2 port map( a => n4602, b => n4600, outb => n3276);
U4722 : xor2 port map( a => mult_125_ab_9_7_port, b => n1908, outb => n5482)
;
U4723 : xor2 port map( a => n4605, b => n4603, outb => n3279);
U4724 : xor2 port map( a => n4607, b => n4606, outb => n3282);
U4725 : xor2 port map( a => mult_125_ab_12_7_port, b => n1914, outb => n3285
);
U4726 : xor2 port map( a => n4610, b => n4608, outb => n3288);
U4727 : xor2 port map( a => mult_125_ab_14_7_port, b => n1918, outb => n3291
);
U4728 : xor2 port map( a => n1920, b => n1921, outb => n3293);
U4729 : xor2 port map( a => n1924, b => mult_125_ab_2_6_port, outb => n3297)
;
U4730 : xor2 port map( a => n4614, b => n4612, outb => n5483);
U4731 : xor2 port map( a => mult_125_ab_4_6_port, b => n1928, outb => n3299)
;
U4732 : xor2 port map( a => n1930, b => n1931, outb => n5484);
U4733 : xor2 port map( a => mult_125_ab_6_6_port, b => n1933, outb => n3302)
;
U4734 : xor2 port map( a => n4619, b => n4617, outb => n5485);
U4735 : xor2 port map( a => mult_125_ab_8_6_port, b => n1937, outb => n3305)
;
U4736 : xor2 port map( a => n1939, b => n1940, outb => n5486);
U4737 : xor2 port map( a => mult_125_ab_10_6_port, b => n1942, outb => n3308
);
U4738 : xor2 port map( a => mult_125_ab_11_6_port, b => n1944, outb => n5487
);
U4739 : xor2 port map( a => n4625, b => n4626, outb => n5488);
U4740 : xor2 port map( a => mult_125_ab_13_6_port, b => n1948, outb => n5489
);
U4741 : xor2 port map( a => n4629, b => n4627, outb => n5490);
U4742 : xor2 port map( a => n5529, b => n1952, outb => n5491);
U4743 : xor2 port map( a => n1955, b => mult_125_ab_2_5_port, outb => n3312)
;
U4744 : xor2 port map( a => mult_125_ab_3_5_port, b => n1958, outb => n5492)
;
U4745 : xor2 port map( a => mult_125_ab_4_5_port, b => n1960, outb => n3314)
;
U4746 : xor2 port map( a => mult_125_ab_5_5_port, b => n1962, outb => n5493)
;
U4747 : xor2 port map( a => n1964, b => n1965, outb => n3317);
U4748 : xor2 port map( a => mult_125_ab_7_5_port, b => n1967, outb => n5494)
;
U4749 : xor2 port map( a => mult_125_ab_8_5_port, b => n1969, outb => n3320)
;
U4750 : xor2 port map( a => mult_125_ab_9_5_port, b => n1971, outb => n5495)
;
U4751 : xor2 port map( a => n4641, b => n4639, outb => n3323);
U4752 : xor2 port map( a => mult_125_ab_11_5_port, b => n1975, outb => n5496
);
U4753 : xor2 port map( a => n4644, b => n4642, outb => n3326);
U4754 : xor2 port map( a => n4646, b => n1979, outb => n3329);
U4755 : xor2 port map( a => mult_125_ab_14_5_port, b => n1981, outb => n3332
);
U4756 : xor2 port map( a => n1983, b => n1984, outb => n3334);
U4757 : xor2 port map( a => n1987, b => mult_125_ab_2_4_port, outb => n3338)
;
U4758 : xor2 port map( a => n4650, b => n4648, outb => n5497);
U4759 : xor2 port map( a => mult_125_ab_4_4_port, b => n1991, outb => n3340)
;
U4760 : xor2 port map( a => n1993, b => n1994, outb => n5498);
U4761 : xor2 port map( a => mult_125_ab_6_4_port, b => n1996, outb => n3343)
;
U4762 : xor2 port map( a => n1998, b => n1999, outb => n5499);
U4763 : xor2 port map( a => mult_125_ab_8_4_port, b => n2001, outb => n3346)
;
U4764 : xor2 port map( a => mult_125_ab_9_4_port, b => n2003, outb => n5500)
;
U4765 : xor2 port map( a => mult_125_ab_10_4_port, b => n2005, outb => n3349
);
U4766 : xor2 port map( a => n2007, b => n2008, outb => n5501);
U4767 : xor2 port map( a => mult_125_ab_12_4_port, b => n2010, outb => n3352
);
U4768 : xor2 port map( a => mult_125_ab_13_4_port, b => n2012, outb => n5502
);
U4769 : xor2 port map( a => mult_125_ab_14_4_port, b => n2014, outb => n5503
);
U4770 : xor2 port map( a => mult_125_ab_15_4_port, b => n2017, outb => n5504
);
U4771 : xor2 port map( a => n2020, b => mult_125_ab_2_3_port, outb => n3356)
;
U4772 : xor2 port map( a => mult_125_ab_3_3_port, b => n2023, outb => n5505)
;
U4773 : xor2 port map( a => mult_125_ab_4_3_port, b => n2025, outb => n3358)
;
U4774 : xor2 port map( a => mult_125_ab_5_3_port, b => n2027, outb => n5506)
;
U4775 : xor2 port map( a => mult_125_ab_6_3_port, b => n2029, outb => n3361)
;
U4776 : xor2 port map( a => mult_125_ab_7_3_port, b => n2031, outb => n5507)
;
U4777 : xor2 port map( a => mult_125_ab_8_3_port, b => n2033, outb => n3364)
;
U4778 : xor2 port map( a => mult_125_ab_9_3_port, b => n2035, outb => n5508)
;
U4779 : xor2 port map( a => mult_125_ab_10_3_port, b => n2037, outb => n3367
);
U4780 : xor2 port map( a => mult_125_ab_11_3_port, b => n2039, outb => n5509
);
U4781 : xor2 port map( a => n4679, b => n4677, outb => n3370);
U4782 : xor2 port map( a => mult_125_ab_13_3_port, b => n2043, outb => n5510
);
U4783 : xor2 port map( a => mult_125_ab_14_3_port, b => n2045, outb => n3373
);
U4784 : xor2 port map( a => mult_125_ab_15_3_port, b => n2047, outb => n3375
);
U4785 : xor2 port map( a => n2050, b => mult_125_ab_2_2_port, outb => n3379)
;
U4786 : xor2 port map( a => n4685, b => n4683, outb => n5511);
U4787 : xor2 port map( a => mult_125_ab_4_2_port, b => n2054, outb => n3381)
;
U4788 : xor2 port map( a => mult_125_ab_5_2_port, b => n2056, outb => n5512)
;
U4789 : xor2 port map( a => mult_125_ab_6_2_port, b => n2058, outb => n3384)
;
U4790 : xor2 port map( a => n2060, b => n2061, outb => n5513);
U4791 : xor2 port map( a => mult_125_ab_8_2_port, b => n2063, outb => n3387)
;
U4792 : xor2 port map( a => mult_125_ab_9_2_port, b => n2065, outb => n5514)
;
U4793 : xor2 port map( a => mult_125_ab_10_2_port, b => n2067, outb => n3390
);
U4794 : xor2 port map( a => mult_125_ab_11_2_port, b => n2069, outb => n5515
);
U4795 : xor2 port map( a => mult_125_ab_12_2_port, b => n2071, outb => n3393
);
U4796 : xor2 port map( a => mult_125_ab_13_2_port, b => n2073, outb => n5516
);
U4797 : xor2 port map( a => mult_125_ab_14_2_port, b => n2075, outb => n3396
);
U4798 : xor2 port map( a => n5413, b => n4700, outb => n5517);
U4799 : xor2 port map( a => n4703, b => mult_125_ab_2_1_port, outb => n3400)
;
U4800 : xor2 port map( a => n4704, b => n4702, outb => n5518);
U4801 : xor2 port map( a => mult_125_ab_4_1_port, b => n4706, outb => n3402)
;
U4802 : xor2 port map( a => mult_125_ab_5_1_port, b => n2086, outb => n5530)
;
U4803 : xor2 port map( a => n4709, b => n2088, outb => n3405);
U4804 : xor2 port map( a => n5531, b => n2090, outb => n5520);
U4805 : xor2 port map( a => mult_125_ab_8_1_port, b => n4710, outb => n3408)
;
U4806 : xor2 port map( a => n5532, b => n2094, outb => n5521);
U4807 : xor2 port map( a => n4715, b => n2096, outb => n3411);
U4808 : xor2 port map( a => n5533, b => n2098, outb => n5522);
U4809 : xor2 port map( a => n4718, b => n2100, outb => n3414);
U4810 : xor2 port map( a => n5534, b => n2102, outb => n5523);
U4811 : xor2 port map( a => n4721, b => n4719, outb => n3417);
U4812 : xor2 port map( a => n5535, b => n2106, outb => n5524);
U4813 : xor2 port map( a => mult_125_ab_15_0_port, b => n2134, outb => n5525
);
U4814 : xor2 port map( a => mult_125_ab_11_0_port, b => n2126, outb => n3419
);
U4815 : xor2 port map( a => mult_125_ab_9_0_port, b => n2122, outb => n3420)
;
U4816 : xor2 port map( a => mult_125_ab_7_0_port, b => n2118, outb => n3421)
;
U4817 : xor2 port map( a => mult_125_ab_5_0_port, b => n2114, outb => n3422)
;
U4818 : xor2 port map( a => mult_125_ab_3_0_port, b => n2110, outb => n3423)
;
U4819 : xor2 port map( a => n308, b => mult_125_ZA, outb => n3424);
U4820 : xor2 port map( a => mult_125_ab_13_0_port, b => n2130, outb => n3425
);
U4821 : xor2 port map( a => n4777, b => adder_mem_array_1_2_port, outb =>
n3470);
U4822 : xor2 port map( a => n5433, b => adder_mem_array_1_32_port, outb =>
n3545);
U4823 : xor2 port map( a => n4836, b => adder_mem_array_1_30_port, outb =>
n3547);
U4824 : xor2 port map( a => n4834, b => adder_mem_array_1_28_port, outb =>
n3551);
U4825 : xor2 port map( a => n4832, b => adder_mem_array_1_26_port, outb =>
n3555);
U4826 : xor2 port map( a => n4830, b => adder_mem_array_1_24_port, outb =>
n3559);
U4827 : xor2 port map( a => n4828, b => adder_mem_array_1_22_port, outb =>
n3563);
U4828 : xor2 port map( a => n4826, b => adder_mem_array_1_20_port, outb =>
n3567);
U4829 : xor2 port map( a => n4824, b => adder_mem_array_1_18_port, outb =>
n3571);
U4830 : xor2 port map( a => n4822, b => adder_mem_array_1_16_port, outb =>
n3575);
U4831 : xor2 port map( a => n4820, b => adder_mem_array_1_14_port, outb =>
n3579);
U4832 : xor2 port map( a => n4818, b => adder_mem_array_1_12_port, outb =>
n3583);
U4833 : xor2 port map( a => n4816, b => adder_mem_array_1_10_port, outb =>
n3587);
U4834 : xor2 port map( a => n4814, b => adder_mem_array_1_8_port, outb =>
n3591);
U4835 : xor2 port map( a => n4812, b => adder_mem_array_1_6_port, outb =>
n3595);
U4836 : xor2 port map( a => n4810, b => adder_mem_array_1_4_port, outb =>
n3607);
U4837 : inv port map( inb => n385, outb => n4905);
U4838 : inv port map( inb => n387, outb => n4908);
U4839 : inv port map( inb => n389, outb => n4911);
U4840 : inv port map( inb => n391, outb => n4914);
U4841 : inv port map( inb => n393, outb => n4917);
U4842 : inv port map( inb => n395, outb => n4920);
U4843 : inv port map( inb => n397, outb => n4925);
U4844 : inv port map( inb => n430, outb => n3640);
U4845 : inv port map( inb => n459, outb => n3659);
U4846 : inv port map( inb => n490, outb => n3679);
U4847 : inv port map( inb => n520, outb => n3698);
U4848 : inv port map( inb => n550, outb => n3718);
U4849 : inv port map( inb => n579, outb => n3738);
U4850 : inv port map( inb => n610, outb => n3758);
U4851 : inv port map( inb => n641, outb => n3775);
U4852 : inv port map( inb => n673, outb => n3794);
U4853 : inv port map( inb => n706, outb => n3809);
U4854 : inv port map( inb => n736, outb => n3829);
U4855 : inv port map( inb => n766, outb => n3848);
U4856 : inv port map( inb => n3867, outb => n794);
U4857 : inv port map( inb => n3868, outb => n796);
U4858 : inv port map( inb => n819, outb => n4943);
U4859 : inv port map( inb => n823, outb => n5051);
U4860 : inv port map( inb => n825, outb => n5054);
U4861 : inv port map( inb => n827, outb => n5057);
U4862 : inv port map( inb => n829, outb => n5060);
U4863 : inv port map( inb => n831, outb => n5063);
U4864 : inv port map( inb => n833, outb => n5066);
U4865 : inv port map( inb => n835, outb => n5071);
U4866 : inv port map( inb => n868, outb => n3925);
U4867 : inv port map( inb => n897, outb => n3944);
U4868 : inv port map( inb => n928, outb => n3964);
U4869 : inv port map( inb => n958, outb => n3983);
U4870 : inv port map( inb => n988, outb => n4003);
U4871 : inv port map( inb => n1017, outb => n4023);
U4872 : inv port map( inb => n1048, outb => n4043);
U4873 : inv port map( inb => n1079, outb => n4060);
U4874 : inv port map( inb => n1111, outb => n4079);
U4875 : inv port map( inb => n1144, outb => n4094);
U4876 : inv port map( inb => n1174, outb => n4114);
U4877 : inv port map( inb => n1204, outb => n4133);
U4878 : inv port map( inb => n4152, outb => n1232);
U4879 : inv port map( inb => n4153, outb => n1234);
U4880 : inv port map( inb => n1257, outb => n5089);
U4881 : inv port map( inb => n1261, outb => n5214);
U4882 : inv port map( inb => n1263, outb => n5217);
U4883 : inv port map( inb => n1265, outb => n5220);
U4884 : inv port map( inb => n1267, outb => n5223);
U4885 : inv port map( inb => n1269, outb => n5226);
U4886 : inv port map( inb => n1271, outb => n5229);
U4887 : inv port map( inb => n1273, outb => n5234);
U4888 : inv port map( inb => n1306, outb => n4210);
U4889 : inv port map( inb => n1335, outb => n4229);
U4890 : inv port map( inb => n1366, outb => n4249);
U4891 : inv port map( inb => n1396, outb => n4268);
U4892 : inv port map( inb => n1426, outb => n4288);
U4893 : inv port map( inb => n1455, outb => n4308);
U4894 : inv port map( inb => n1486, outb => n4328);
U4895 : inv port map( inb => n1517, outb => n4345);
U4896 : inv port map( inb => n1549, outb => n4364);
U4897 : inv port map( inb => n1582, outb => n4379);
U4898 : inv port map( inb => n1612, outb => n4399);
U4899 : inv port map( inb => n1642, outb => n4418);
U4900 : inv port map( inb => n4437, outb => n1670);
U4901 : inv port map( inb => n4438, outb => n1672);
U4902 : inv port map( inb => n1695, outb => n5252);
U4903 : inv port map( inb => n1699, outb => n5377);
U4904 : inv port map( inb => n1701, outb => n5380);
U4905 : inv port map( inb => n1703, outb => n5383);
U4906 : inv port map( inb => n1705, outb => n5386);
U4907 : inv port map( inb => n1707, outb => n5389);
U4908 : inv port map( inb => n1709, outb => n5392);
U4909 : inv port map( inb => n1711, outb => n5397);
U4910 : inv port map( inb => n1744, outb => n4495);
U4911 : inv port map( inb => n1773, outb => n4514);
U4912 : inv port map( inb => n1804, outb => n4534);
U4913 : inv port map( inb => n1834, outb => n4553);
U4914 : inv port map( inb => n1864, outb => n4573);
U4915 : inv port map( inb => n1893, outb => n4593);
U4916 : inv port map( inb => n1924, outb => n4613);
U4917 : inv port map( inb => n1955, outb => n4630);
U4918 : inv port map( inb => n1987, outb => n4649);
U4919 : inv port map( inb => n2020, outb => n4664);
U4920 : inv port map( inb => n2050, outb => n4684);
U4921 : inv port map( inb => n2080, outb => n4703);
U4922 : inv port map( inb => n4722, outb => n2108);
U4923 : inv port map( inb => n4723, outb => n2110);
U4924 : inv port map( inb => n2133, outb => n5415);
U4925 : inv port map( inb => n4749, outb => n2137);
U4926 : inv port map( inb => n2139, outb => n5092);
U4927 : inv port map( inb => n2141, outb => n5093);
U4928 : inv port map( inb => n2143, outb => n5094);
U4929 : inv port map( inb => n2145, outb => n5095);
U4930 : inv port map( inb => n2147, outb => n5096);
U4931 : inv port map( inb => n2149, outb => n5097);
U4932 : inv port map( inb => n2151, outb => n5098);
U4933 : inv port map( inb => n2153, outb => n5099);
U4934 : inv port map( inb => n2155, outb => n5100);
U4935 : inv port map( inb => n2157, outb => n5101);
U4936 : inv port map( inb => n2159, outb => n5102);
U4937 : inv port map( inb => n2161, outb => n5103);
U4938 : inv port map( inb => n4776, outb => n2164);
U4939 : inv port map( inb => n4779, outb => n2167);
U4940 : inv port map( inb => n2169, outb => n5255);
U4941 : inv port map( inb => n2171, outb => n5256);
U4942 : inv port map( inb => n2173, outb => n5257);
U4943 : inv port map( inb => n2175, outb => n5258);
U4944 : inv port map( inb => n2177, outb => n5259);
U4945 : inv port map( inb => n2179, outb => n5260);
U4946 : inv port map( inb => n2181, outb => n5261);
U4947 : inv port map( inb => n2183, outb => n5262);
U4948 : inv port map( inb => n2185, outb => n5263);
U4949 : inv port map( inb => n2187, outb => n5264);
U4950 : inv port map( inb => n2189, outb => n5265);
U4951 : inv port map( inb => n2191, outb => n5266);
U4952 : inv port map( inb => n2193, outb => n5267);
U4953 : inv port map( inb => n2195, outb => n5268);
U4954 : inv port map( inb => n2200, outb => n5418);
U4955 : inv port map( inb => n2202, outb => n5419);
U4956 : inv port map( inb => n2204, outb => n5420);
U4957 : inv port map( inb => n2206, outb => n5421);
U4958 : inv port map( inb => n2208, outb => n5422);
U4959 : inv port map( inb => n2210, outb => n5423);
U4960 : inv port map( inb => n2212, outb => n5424);
U4961 : inv port map( inb => n2214, outb => n5425);
U4962 : inv port map( inb => n2216, outb => n5426);
U4963 : inv port map( inb => n2218, outb => n5427);
U4964 : inv port map( inb => n2220, outb => n5428);
U4965 : inv port map( inb => n2222, outb => n5429);
U4966 : inv port map( inb => n2224, outb => n5430);
U4967 : inv port map( inb => n2226, outb => n5431);
U4968 : inv port map( inb => n2231, outb => n5104);
U4969 : inv port map( inb => n2233, outb => n5105);
U4970 : inv port map( inb => mult_125_G4_ab_1_15_port, outb => n4902);
U4971 : inv port map( inb => mult_125_G4_ab_2_14_port, outb => n4903);
U4972 : inv port map( inb => n408, outb => n3626);
U4973 : inv port map( inb => n412, outb => n3629);
U4974 : inv port map( inb => n416, outb => n3632);
U4975 : inv port map( inb => n420, outb => n3635);
U4976 : inv port map( inb => n424, outb => n3638);
U4977 : inv port map( inb => mult_125_G4_ab_3_12_port, outb => n3641);
U4978 : inv port map( inb => n439, outb => n3648);
U4979 : inv port map( inb => n443, outb => n3651);
U4980 : inv port map( inb => n447, outb => n3654);
U4981 : inv port map( inb => n451, outb => n3657);
U4982 : inv port map( inb => mult_125_G4_ab_3_11_port, outb => n461);
U4983 : inv port map( inb => n471, outb => n3669);
U4984 : inv port map( inb => n475, outb => n3672);
U4985 : inv port map( inb => n479, outb => n3675);
U4986 : inv port map( inb => n483, outb => n3677);
U4987 : inv port map( inb => mult_125_G4_ab_3_10_port, outb => n3680);
U4988 : inv port map( inb => n504, outb => n3689);
U4989 : inv port map( inb => n508, outb => n3692);
U4990 : inv port map( inb => n512, outb => n3695);
U4991 : inv port map( inb => mult_125_G4_ab_3_9_port, outb => n3699);
U4992 : inv port map( inb => n535, outb => n3711);
U4993 : inv port map( inb => n539, outb => n3714);
U4994 : inv port map( inb => n543, outb => n3716);
U4995 : inv port map( inb => mult_125_G4_ab_3_8_port, outb => n3719);
U4996 : inv port map( inb => n567, outb => n3733);
U4997 : inv port map( inb => n571, outb => n3736);
U4998 : inv port map( inb => mult_125_G4_ab_3_7_port, outb => n581);
U4999 : inv port map( inb => n599, outb => n3754);
U5000 : inv port map( inb => n603, outb => n3756);
U5001 : inv port map( inb => mult_125_G4_ab_3_6_port, outb => n3759);
U5002 : inv port map( inb => n633, outb => n3773);
U5003 : inv port map( inb => mult_125_G4_ab_3_5_port, outb => n643);
U5004 : inv port map( inb => n666, outb => n3792);
U5005 : inv port map( inb => mult_125_G4_ab_3_4_port, outb => n3795);
U5006 : inv port map( inb => mult_125_G4_ab_3_3_port, outb => n708);
U5007 : inv port map( inb => mult_125_G4_ab_3_2_port, outb => n3830);
U5008 : inv port map( inb => mult_125_G4_ab_3_1_port, outb => n3849);
U5009 : inv port map( inb => n770, outb => n3851);
U5010 : inv port map( inb => n799, outb => n3875);
U5011 : inv port map( inb => n803, outb => n3879);
U5012 : inv port map( inb => n807, outb => n3883);
U5013 : inv port map( inb => n811, outb => n3887);
U5014 : inv port map( inb => n815, outb => n3891);
U5015 : inv port map( inb => mult_125_G3_ab_1_15_port, outb => n5048);
U5016 : inv port map( inb => mult_125_G3_ab_2_14_port, outb => n5049);
U5017 : inv port map( inb => n846, outb => n3911);
U5018 : inv port map( inb => n850, outb => n3914);
U5019 : inv port map( inb => n854, outb => n3917);
U5020 : inv port map( inb => n858, outb => n3920);
U5021 : inv port map( inb => n862, outb => n3923);
U5022 : inv port map( inb => mult_125_G3_ab_3_12_port, outb => n3926);
U5023 : inv port map( inb => n877, outb => n3933);
U5024 : inv port map( inb => n881, outb => n3936);
U5025 : inv port map( inb => n885, outb => n3939);
U5026 : inv port map( inb => n889, outb => n3942);
U5027 : inv port map( inb => mult_125_G3_ab_3_11_port, outb => n899);
U5028 : inv port map( inb => n909, outb => n3954);
U5029 : inv port map( inb => n913, outb => n3957);
U5030 : inv port map( inb => n917, outb => n3960);
U5031 : inv port map( inb => n921, outb => n3962);
U5032 : inv port map( inb => mult_125_G3_ab_3_10_port, outb => n3965);
U5033 : inv port map( inb => n942, outb => n3974);
U5034 : inv port map( inb => n946, outb => n3977);
U5035 : inv port map( inb => n950, outb => n3980);
U5036 : inv port map( inb => mult_125_G3_ab_3_9_port, outb => n3984);
U5037 : inv port map( inb => n973, outb => n3996);
U5038 : inv port map( inb => n977, outb => n3999);
U5039 : inv port map( inb => n981, outb => n4001);
U5040 : inv port map( inb => mult_125_G3_ab_3_8_port, outb => n4004);
U5041 : inv port map( inb => n1005, outb => n4018);
U5042 : inv port map( inb => n1009, outb => n4021);
U5043 : inv port map( inb => mult_125_G3_ab_3_7_port, outb => n1019);
U5044 : inv port map( inb => n1037, outb => n4039);
U5045 : inv port map( inb => n1041, outb => n4041);
U5046 : inv port map( inb => mult_125_G3_ab_3_6_port, outb => n4044);
U5047 : inv port map( inb => n1071, outb => n4058);
U5048 : inv port map( inb => mult_125_G3_ab_3_5_port, outb => n1081);
U5049 : inv port map( inb => n1104, outb => n4077);
U5050 : inv port map( inb => mult_125_G3_ab_3_4_port, outb => n4080);
U5051 : inv port map( inb => mult_125_G3_ab_3_3_port, outb => n1146);
U5052 : inv port map( inb => mult_125_G3_ab_3_2_port, outb => n4115);
U5053 : inv port map( inb => mult_125_G3_ab_3_1_port, outb => n4134);
U5054 : inv port map( inb => n1208, outb => n4136);
U5055 : inv port map( inb => n1237, outb => n4160);
U5056 : inv port map( inb => n1241, outb => n4164);
U5057 : inv port map( inb => n1245, outb => n4168);
U5058 : inv port map( inb => n1249, outb => n4172);
U5059 : inv port map( inb => n1253, outb => n4176);
U5060 : inv port map( inb => mult_125_G2_ab_1_15_port, outb => n5211);
U5061 : inv port map( inb => mult_125_G2_ab_2_14_port, outb => n5212);
U5062 : inv port map( inb => n1284, outb => n4196);
U5063 : inv port map( inb => n1288, outb => n4199);
U5064 : inv port map( inb => n1292, outb => n4202);
U5065 : inv port map( inb => n1296, outb => n4205);
U5066 : inv port map( inb => n1300, outb => n4208);
U5067 : inv port map( inb => mult_125_G2_ab_3_12_port, outb => n4211);
U5068 : inv port map( inb => n1315, outb => n4218);
U5069 : inv port map( inb => n1319, outb => n4221);
U5070 : inv port map( inb => n1323, outb => n4224);
U5071 : inv port map( inb => n1327, outb => n4227);
U5072 : inv port map( inb => mult_125_G2_ab_3_11_port, outb => n1337);
U5073 : inv port map( inb => n1347, outb => n4239);
U5074 : inv port map( inb => n1351, outb => n4242);
U5075 : inv port map( inb => n1355, outb => n4245);
U5076 : inv port map( inb => n1359, outb => n4247);
U5077 : inv port map( inb => mult_125_G2_ab_3_10_port, outb => n4250);
U5078 : inv port map( inb => n1380, outb => n4259);
U5079 : inv port map( inb => n1384, outb => n4262);
U5080 : inv port map( inb => n1388, outb => n4265);
U5081 : inv port map( inb => mult_125_G2_ab_3_9_port, outb => n4269);
U5082 : inv port map( inb => n1411, outb => n4281);
U5083 : inv port map( inb => n1415, outb => n4284);
U5084 : inv port map( inb => n1419, outb => n4286);
U5085 : inv port map( inb => mult_125_G2_ab_3_8_port, outb => n4289);
U5086 : inv port map( inb => n1443, outb => n4303);
U5087 : inv port map( inb => n1447, outb => n4306);
U5088 : inv port map( inb => mult_125_G2_ab_3_7_port, outb => n1457);
U5089 : inv port map( inb => n1475, outb => n4324);
U5090 : inv port map( inb => n1479, outb => n4326);
U5091 : inv port map( inb => mult_125_G2_ab_3_6_port, outb => n4329);
U5092 : inv port map( inb => n1509, outb => n4343);
U5093 : inv port map( inb => mult_125_G2_ab_3_5_port, outb => n1519);
U5094 : inv port map( inb => n1542, outb => n4362);
U5095 : inv port map( inb => mult_125_G2_ab_3_4_port, outb => n4365);
U5096 : inv port map( inb => mult_125_G2_ab_3_3_port, outb => n1584);
U5097 : inv port map( inb => mult_125_G2_ab_3_2_port, outb => n4400);
U5098 : inv port map( inb => mult_125_G2_ab_3_1_port, outb => n4419);
U5099 : inv port map( inb => n1646, outb => n4421);
U5100 : inv port map( inb => n1675, outb => n4445);
U5101 : inv port map( inb => n1679, outb => n4449);
U5102 : inv port map( inb => n1683, outb => n4453);
U5103 : inv port map( inb => n1687, outb => n4457);
U5104 : inv port map( inb => n1691, outb => n4461);
U5105 : inv port map( inb => mult_125_ab_1_15_port, outb => n5374);
U5106 : inv port map( inb => mult_125_ab_2_14_port, outb => n5375);
U5107 : inv port map( inb => n1722, outb => n4481);
U5108 : inv port map( inb => n1726, outb => n4484);
U5109 : inv port map( inb => n1730, outb => n4487);
U5110 : inv port map( inb => n1734, outb => n4490);
U5111 : inv port map( inb => n1738, outb => n4493);
U5112 : inv port map( inb => mult_125_ab_3_12_port, outb => n4496);
U5113 : inv port map( inb => n1753, outb => n4503);
U5114 : inv port map( inb => n1757, outb => n4506);
U5115 : inv port map( inb => n1761, outb => n4509);
U5116 : inv port map( inb => n1765, outb => n4512);
U5117 : inv port map( inb => mult_125_ab_3_11_port, outb => n1775);
U5118 : inv port map( inb => n1785, outb => n4524);
U5119 : inv port map( inb => n1789, outb => n4527);
U5120 : inv port map( inb => n1793, outb => n4530);
U5121 : inv port map( inb => n1797, outb => n4532);
U5122 : inv port map( inb => mult_125_ab_3_10_port, outb => n4535);
U5123 : inv port map( inb => n1818, outb => n4544);
U5124 : inv port map( inb => n1822, outb => n4547);
U5125 : inv port map( inb => n1826, outb => n4550);
U5126 : inv port map( inb => mult_125_ab_3_9_port, outb => n4554);
U5127 : inv port map( inb => n1849, outb => n4566);
U5128 : inv port map( inb => n1853, outb => n4569);
U5129 : inv port map( inb => n1857, outb => n4571);
U5130 : inv port map( inb => mult_125_ab_3_8_port, outb => n4574);
U5131 : inv port map( inb => n1881, outb => n4588);
U5132 : inv port map( inb => n1885, outb => n4591);
U5133 : inv port map( inb => mult_125_ab_3_7_port, outb => n1895);
U5134 : inv port map( inb => n1913, outb => n4609);
U5135 : inv port map( inb => n1917, outb => n4611);
U5136 : inv port map( inb => mult_125_ab_3_6_port, outb => n4614);
U5137 : inv port map( inb => n1947, outb => n4628);
U5138 : inv port map( inb => mult_125_ab_3_5_port, outb => n1957);
U5139 : inv port map( inb => n1980, outb => n4647);
U5140 : inv port map( inb => mult_125_ab_3_4_port, outb => n4650);
U5141 : inv port map( inb => mult_125_ab_3_3_port, outb => n2022);
U5142 : inv port map( inb => mult_125_ab_3_2_port, outb => n4685);
U5143 : inv port map( inb => mult_125_ab_3_1_port, outb => n4704);
U5144 : inv port map( inb => n2084, outb => n4706);
U5145 : inv port map( inb => n2113, outb => n4730);
U5146 : inv port map( inb => n2117, outb => n4734);
U5147 : inv port map( inb => n2121, outb => n4738);
U5148 : inv port map( inb => n2125, outb => n4742);
U5149 : inv port map( inb => n2129, outb => n4746);
U5150 : inv port map( inb => mult_125_G4_ab_5_13_port, outb => n3624);
U5151 : inv port map( inb => n4921, outb => n4924);
U5152 : inv port map( inb => mult_125_G4_ab_7_11_port, outb => n3667);
U5153 : inv port map( inb => mult_125_G4_ab_5_10_port, outb => n496);
U5154 : inv port map( inb => mult_125_G4_ab_7_10_port, outb => n3685);
U5155 : inv port map( inb => mult_125_G4_ab_9_9_port, outb => n3709);
U5156 : inv port map( inb => mult_125_G4_ab_7_8_port, outb => n3726);
U5157 : inv port map( inb => mult_125_G4_ab_9_8_port, outb => n3729);
U5158 : inv port map( inb => mult_125_G4_ab_11_7_port, outb => n3752);
U5159 : inv port map( inb => mult_125_G4_ab_9_6_port, outb => n625);
U5160 : inv port map( inb => mult_125_G4_ab_11_6_port, outb => n3769);
U5161 : inv port map( inb => mult_125_G4_ab_13_5_port, outb => n3791);
U5162 : inv port map( inb => mult_125_G4_ab_11_4_port, outb => n693);
U5163 : inv port map( inb => mult_125_G4_ab_13_4_port, outb => n3807);
U5164 : inv port map( inb => mult_125_G3_ab_5_13_port, outb => n3909);
U5165 : inv port map( inb => n5067, outb => n5070);
U5166 : inv port map( inb => mult_125_G3_ab_7_11_port, outb => n3952);
U5167 : inv port map( inb => mult_125_G3_ab_5_10_port, outb => n934);
U5168 : inv port map( inb => mult_125_G3_ab_7_10_port, outb => n3970);
U5169 : inv port map( inb => mult_125_G3_ab_9_9_port, outb => n3994);
U5170 : inv port map( inb => mult_125_G3_ab_7_8_port, outb => n4011);
U5171 : inv port map( inb => mult_125_G3_ab_9_8_port, outb => n4014);
U5172 : inv port map( inb => mult_125_G3_ab_11_7_port, outb => n4037);
U5173 : inv port map( inb => mult_125_G3_ab_9_6_port, outb => n1063);
U5174 : inv port map( inb => mult_125_G3_ab_11_6_port, outb => n4054);
U5175 : inv port map( inb => mult_125_G3_ab_13_5_port, outb => n4076);
U5176 : inv port map( inb => mult_125_G3_ab_11_4_port, outb => n1131);
U5177 : inv port map( inb => mult_125_G3_ab_13_4_port, outb => n4092);
U5178 : inv port map( inb => mult_125_G2_ab_5_13_port, outb => n4194);
U5179 : inv port map( inb => n5230, outb => n5233);
U5180 : inv port map( inb => mult_125_G2_ab_7_11_port, outb => n4237);
U5181 : inv port map( inb => mult_125_G2_ab_5_10_port, outb => n1372);
U5182 : inv port map( inb => mult_125_G2_ab_7_10_port, outb => n4255);
U5183 : inv port map( inb => mult_125_G2_ab_9_9_port, outb => n4279);
U5184 : inv port map( inb => mult_125_G2_ab_7_8_port, outb => n4296);
U5185 : inv port map( inb => mult_125_G2_ab_9_8_port, outb => n4299);
U5186 : inv port map( inb => mult_125_G2_ab_11_7_port, outb => n4322);
U5187 : inv port map( inb => mult_125_G2_ab_9_6_port, outb => n1501);
U5188 : inv port map( inb => mult_125_G2_ab_11_6_port, outb => n4339);
U5189 : inv port map( inb => mult_125_G2_ab_13_5_port, outb => n4361);
U5190 : inv port map( inb => mult_125_G2_ab_11_4_port, outb => n1569);
U5191 : inv port map( inb => mult_125_G2_ab_13_4_port, outb => n4377);
U5192 : inv port map( inb => mult_125_ab_5_13_port, outb => n4479);
U5193 : inv port map( inb => n5393, outb => n5396);
U5194 : inv port map( inb => mult_125_ab_7_11_port, outb => n4522);
U5195 : inv port map( inb => mult_125_ab_5_10_port, outb => n1810);
U5196 : inv port map( inb => mult_125_ab_7_10_port, outb => n4540);
U5197 : inv port map( inb => mult_125_ab_9_9_port, outb => n4564);
U5198 : inv port map( inb => mult_125_ab_7_8_port, outb => n4581);
U5199 : inv port map( inb => mult_125_ab_9_8_port, outb => n4584);
U5200 : inv port map( inb => mult_125_ab_11_7_port, outb => n4607);
U5201 : inv port map( inb => mult_125_ab_9_6_port, outb => n1939);
U5202 : inv port map( inb => mult_125_ab_11_6_port, outb => n4624);
U5203 : inv port map( inb => mult_125_ab_13_5_port, outb => n4646);
U5204 : inv port map( inb => mult_125_ab_11_4_port, outb => n2007);
U5205 : inv port map( inb => mult_125_ab_13_4_port, outb => n4662);
U5206 : inv port map( inb => n4919, outb => n4922);
U5207 : inv port map( inb => n396, outb => n4923);
U5208 : inv port map( inb => n498, outb => n3684);
U5209 : inv port map( inb => n561, outb => n3728);
U5210 : inv port map( inb => n627, outb => n3768);
U5211 : inv port map( inb => n695, outb => n3806);
U5212 : inv port map( inb => n5065, outb => n5068);
U5213 : inv port map( inb => n834, outb => n5069);
U5214 : inv port map( inb => n936, outb => n3969);
U5215 : inv port map( inb => n999, outb => n4013);
U5216 : inv port map( inb => n1065, outb => n4053);
U5217 : inv port map( inb => n1133, outb => n4091);
U5218 : inv port map( inb => n5228, outb => n5231);
U5219 : inv port map( inb => n1272, outb => n5232);
U5220 : inv port map( inb => n1374, outb => n4254);
U5221 : inv port map( inb => n1437, outb => n4298);
U5222 : inv port map( inb => n1503, outb => n4338);
U5223 : inv port map( inb => n1571, outb => n4376);
U5224 : inv port map( inb => n5391, outb => n5394);
U5225 : inv port map( inb => n1710, outb => n5395);
U5226 : inv port map( inb => n1812, outb => n4539);
U5227 : inv port map( inb => n1875, outb => n4583);
U5228 : inv port map( inb => n1941, outb => n4623);
U5229 : inv port map( inb => n2009, outb => n4661);
U5230 : inv port map( inb => n400, outb => n3620);
U5231 : inv port map( inb => n433, outb => n3643);
U5232 : inv port map( inb => n470, outb => n3666);
U5233 : inv port map( inb => n534, outb => n3708);
U5234 : inv port map( inb => n598, outb => n3751);
U5235 : inv port map( inb => n665, outb => n3790);
U5236 : inv port map( inb => n703, outb => n4939);
U5237 : inv port map( inb => n838, outb => n3905);
U5238 : inv port map( inb => n871, outb => n3928);
U5239 : inv port map( inb => n908, outb => n3951);
U5240 : inv port map( inb => n972, outb => n3993);
U5241 : inv port map( inb => n1036, outb => n4036);
U5242 : inv port map( inb => n1103, outb => n4075);
U5243 : inv port map( inb => n1141, outb => n5085);
U5244 : inv port map( inb => n1276, outb => n4190);
U5245 : inv port map( inb => n1309, outb => n4213);
U5246 : inv port map( inb => n1346, outb => n4236);
U5247 : inv port map( inb => n1410, outb => n4278);
U5248 : inv port map( inb => n1474, outb => n4321);
U5249 : inv port map( inb => n1541, outb => n4360);
U5250 : inv port map( inb => n1579, outb => n5248);
U5251 : inv port map( inb => n1714, outb => n4475);
U5252 : inv port map( inb => n1747, outb => n4498);
U5253 : inv port map( inb => n1784, outb => n4521);
U5254 : inv port map( inb => n1848, outb => n4563);
U5255 : inv port map( inb => n1912, outb => n4606);
U5256 : inv port map( inb => n1979, outb => n4645);
U5257 : inv port map( inb => n2017, outb => n5411);
U5258 : inv port map( inb => mult_125_G4_ab_3_13_port, outb => n402);
U5259 : inv port map( inb => n464, outb => n3661);
U5260 : inv port map( inb => mult_125_G4_ab_4_11_port, outb => n3662);
U5261 : inv port map( inb => mult_125_G4_ab_6_11_port, outb => n3665);
U5262 : inv port map( inb => mult_125_G4_ab_6_9_port, outb => n3704);
U5263 : inv port map( inb => n529, outb => n3706);
U5264 : inv port map( inb => mult_125_G4_ab_8_9_port, outb => n3707);
U5265 : inv port map( inb => mult_125_G4_ab_6_7_port, outb => n3744);
U5266 : inv port map( inb => mult_125_G4_ab_8_7_port, outb => n3747);
U5267 : inv port map( inb => n593, outb => n3749);
U5268 : inv port map( inb => mult_125_G4_ab_10_7_port, outb => n3750);
U5269 : inv port map( inb => mult_125_G4_ab_8_5_port, outb => n3783);
U5270 : inv port map( inb => mult_125_G4_ab_10_5_port, outb => n3786);
U5271 : inv port map( inb => n660, outb => n3788);
U5272 : inv port map( inb => mult_125_G4_ab_12_5_port, outb => n3789);
U5273 : inv port map( inb => n699, outb => n3808);
U5274 : inv port map( inb => mult_125_G4_ab_10_3_port, outb => n3821);
U5275 : inv port map( inb => mult_125_G4_ab_12_3_port, outb => n3824);
U5276 : inv port map( inb => n728, outb => n3826);
U5277 : inv port map( inb => mult_125_G4_ab_6_1_port, outb => n3854);
U5278 : inv port map( inb => mult_125_G4_ab_8_1_port, outb => n3857);
U5279 : inv port map( inb => mult_125_G4_ab_10_1_port, outb => n3860);
U5280 : inv port map( inb => mult_125_G4_ab_12_1_port, outb => n3863);
U5281 : inv port map( inb => mult_125_G3_ab_3_13_port, outb => n840);
U5282 : inv port map( inb => n902, outb => n3946);
U5283 : inv port map( inb => mult_125_G3_ab_4_11_port, outb => n3947);
U5284 : inv port map( inb => mult_125_G3_ab_6_11_port, outb => n3950);
U5285 : inv port map( inb => mult_125_G3_ab_6_9_port, outb => n3989);
U5286 : inv port map( inb => n967, outb => n3991);
U5287 : inv port map( inb => mult_125_G3_ab_8_9_port, outb => n3992);
U5288 : inv port map( inb => mult_125_G3_ab_6_7_port, outb => n4029);
U5289 : inv port map( inb => mult_125_G3_ab_8_7_port, outb => n4032);
U5290 : inv port map( inb => n1031, outb => n4034);
U5291 : inv port map( inb => mult_125_G3_ab_10_7_port, outb => n4035);
U5292 : inv port map( inb => mult_125_G3_ab_8_5_port, outb => n4068);
U5293 : inv port map( inb => mult_125_G3_ab_10_5_port, outb => n4071);
U5294 : inv port map( inb => n1098, outb => n4073);
U5295 : inv port map( inb => mult_125_G3_ab_12_5_port, outb => n4074);
U5296 : inv port map( inb => n1137, outb => n4093);
U5297 : inv port map( inb => mult_125_G3_ab_10_3_port, outb => n4106);
U5298 : inv port map( inb => mult_125_G3_ab_12_3_port, outb => n4109);
U5299 : inv port map( inb => n1166, outb => n4111);
U5300 : inv port map( inb => mult_125_G3_ab_6_1_port, outb => n4139);
U5301 : inv port map( inb => mult_125_G3_ab_8_1_port, outb => n4142);
U5302 : inv port map( inb => mult_125_G3_ab_10_1_port, outb => n4145);
U5303 : inv port map( inb => mult_125_G3_ab_12_1_port, outb => n4148);
U5304 : inv port map( inb => mult_125_G2_ab_3_13_port, outb => n1278);
U5305 : inv port map( inb => n1340, outb => n4231);
U5306 : inv port map( inb => mult_125_G2_ab_4_11_port, outb => n4232);
U5307 : inv port map( inb => mult_125_G2_ab_6_11_port, outb => n4235);
U5308 : inv port map( inb => mult_125_G2_ab_6_9_port, outb => n4274);
U5309 : inv port map( inb => n1405, outb => n4276);
U5310 : inv port map( inb => mult_125_G2_ab_8_9_port, outb => n4277);
U5311 : inv port map( inb => mult_125_G2_ab_6_7_port, outb => n4314);
U5312 : inv port map( inb => mult_125_G2_ab_8_7_port, outb => n4317);
U5313 : inv port map( inb => n1469, outb => n4319);
U5314 : inv port map( inb => mult_125_G2_ab_10_7_port, outb => n4320);
U5315 : inv port map( inb => mult_125_G2_ab_8_5_port, outb => n4353);
U5316 : inv port map( inb => mult_125_G2_ab_10_5_port, outb => n4356);
U5317 : inv port map( inb => n1536, outb => n4358);
U5318 : inv port map( inb => mult_125_G2_ab_12_5_port, outb => n4359);
U5319 : inv port map( inb => n1575, outb => n4378);
U5320 : inv port map( inb => mult_125_G2_ab_10_3_port, outb => n4391);
U5321 : inv port map( inb => mult_125_G2_ab_12_3_port, outb => n4394);
U5322 : inv port map( inb => n1604, outb => n4396);
U5323 : inv port map( inb => mult_125_G2_ab_6_1_port, outb => n4424);
U5324 : inv port map( inb => mult_125_G2_ab_8_1_port, outb => n4427);
U5325 : inv port map( inb => mult_125_G2_ab_10_1_port, outb => n4430);
U5326 : inv port map( inb => mult_125_G2_ab_12_1_port, outb => n4433);
U5327 : inv port map( inb => mult_125_ab_3_13_port, outb => n1716);
U5328 : inv port map( inb => n1778, outb => n4516);
U5329 : inv port map( inb => mult_125_ab_4_11_port, outb => n4517);
U5330 : inv port map( inb => mult_125_ab_6_11_port, outb => n4520);
U5331 : inv port map( inb => mult_125_ab_6_9_port, outb => n4559);
U5332 : inv port map( inb => n1843, outb => n4561);
U5333 : inv port map( inb => mult_125_ab_8_9_port, outb => n4562);
U5334 : inv port map( inb => mult_125_ab_6_7_port, outb => n4599);
U5335 : inv port map( inb => mult_125_ab_8_7_port, outb => n4602);
U5336 : inv port map( inb => n1907, outb => n4604);
U5337 : inv port map( inb => mult_125_ab_10_7_port, outb => n4605);
U5338 : inv port map( inb => mult_125_ab_8_5_port, outb => n4638);
U5339 : inv port map( inb => mult_125_ab_10_5_port, outb => n4641);
U5340 : inv port map( inb => n1974, outb => n4643);
U5341 : inv port map( inb => mult_125_ab_12_5_port, outb => n4644);
U5342 : inv port map( inb => n2013, outb => n4663);
U5343 : inv port map( inb => mult_125_ab_10_3_port, outb => n4676);
U5344 : inv port map( inb => mult_125_ab_12_3_port, outb => n4679);
U5345 : inv port map( inb => n2042, outb => n4681);
U5346 : inv port map( inb => mult_125_ab_6_1_port, outb => n4709);
U5347 : inv port map( inb => mult_125_ab_8_1_port, outb => n4712);
U5348 : inv port map( inb => mult_125_ab_10_1_port, outb => n4715);
U5349 : inv port map( inb => mult_125_ab_12_1_port, outb => n4718);
U5350 : inv port map( inb => n3642, outb => n436);
U5351 : inv port map( inb => n465, outb => n3664);
U5352 : inv port map( inb => mult_125_G4_ab_13_2_port, outb => n3844);
U5353 : inv port map( inb => n3927, outb => n874);
U5354 : inv port map( inb => n903, outb => n3949);
U5355 : inv port map( inb => mult_125_G3_ab_13_2_port, outb => n4129);
U5356 : inv port map( inb => n4212, outb => n1312);
U5357 : inv port map( inb => n1341, outb => n4234);
U5358 : inv port map( inb => mult_125_G2_ab_13_2_port, outb => n4414);
U5359 : inv port map( inb => n4497, outb => n1750);
U5360 : inv port map( inb => n1779, outb => n4519);
U5361 : inv port map( inb => mult_125_ab_13_2_port, outb => n4699);
U5362 : inv port map( inb => n404, outb => n3623);
U5363 : inv port map( inb => n493, outb => n3681);
U5364 : inv port map( inb => n589, outb => n3746);
U5365 : inv port map( inb => n656, outb => n3785);
U5366 : inv port map( inb => n760, outb => n3846);
U5367 : inv port map( inb => mult_125_G4_ab_15_2_port, outb => n4941);
U5368 : inv port map( inb => n842, outb => n3908);
U5369 : inv port map( inb => n931, outb => n3966);
U5370 : inv port map( inb => n1027, outb => n4031);
U5371 : inv port map( inb => n1094, outb => n4070);
U5372 : inv port map( inb => n1198, outb => n4131);
U5373 : inv port map( inb => mult_125_G3_ab_15_2_port, outb => n5087);
U5374 : inv port map( inb => n1280, outb => n4193);
U5375 : inv port map( inb => n1369, outb => n4251);
U5376 : inv port map( inb => n1465, outb => n4316);
U5377 : inv port map( inb => n1532, outb => n4355);
U5378 : inv port map( inb => n1636, outb => n4416);
U5379 : inv port map( inb => mult_125_G2_ab_15_2_port, outb => n5250);
U5380 : inv port map( inb => n1718, outb => n4478);
U5381 : inv port map( inb => n1807, outb => n4536);
U5382 : inv port map( inb => n1903, outb => n4601);
U5383 : inv port map( inb => n1970, outb => n4640);
U5384 : inv port map( inb => n2074, outb => n4701);
U5385 : inv port map( inb => mult_125_ab_15_2_port, outb => n5413);
U5386 : inv port map( inb => mult_125_G4_ab_5_8_port, outb => n3723);
U5387 : inv port map( inb => n557, outb => n3725);
U5388 : inv port map( inb => mult_125_G4_ab_5_6_port, outb => n616);
U5389 : inv port map( inb => mult_125_G4_ab_7_6_port, outb => n3764);
U5390 : inv port map( inb => mult_125_G4_ab_5_4_port, outb => n679);
U5391 : inv port map( inb => mult_125_G4_ab_7_4_port, outb => n684);
U5392 : inv port map( inb => mult_125_G4_ab_9_4_port, outb => n3802);
U5393 : inv port map( inb => mult_125_G4_ab_5_2_port, outb => n3833);
U5394 : inv port map( inb => mult_125_G4_ab_7_2_port, outb => n746);
U5395 : inv port map( inb => mult_125_G4_ab_9_2_port, outb => n3838);
U5396 : inv port map( inb => mult_125_G4_ab_11_2_port, outb => n3841);
U5397 : inv port map( inb => mult_125_G3_ab_5_8_port, outb => n4008);
U5398 : inv port map( inb => n995, outb => n4010);
U5399 : inv port map( inb => mult_125_G3_ab_5_6_port, outb => n1054);
U5400 : inv port map( inb => mult_125_G3_ab_7_6_port, outb => n4049);
U5401 : inv port map( inb => mult_125_G3_ab_5_4_port, outb => n1117);
U5402 : inv port map( inb => mult_125_G3_ab_7_4_port, outb => n1122);
U5403 : inv port map( inb => mult_125_G3_ab_9_4_port, outb => n4087);
U5404 : inv port map( inb => mult_125_G3_ab_5_2_port, outb => n4118);
U5405 : inv port map( inb => mult_125_G3_ab_7_2_port, outb => n1184);
U5406 : inv port map( inb => mult_125_G3_ab_9_2_port, outb => n4123);
U5407 : inv port map( inb => mult_125_G3_ab_11_2_port, outb => n4126);
U5408 : inv port map( inb => mult_125_G2_ab_5_8_port, outb => n4293);
U5409 : inv port map( inb => n1433, outb => n4295);
U5410 : inv port map( inb => mult_125_G2_ab_5_6_port, outb => n1492);
U5411 : inv port map( inb => mult_125_G2_ab_7_6_port, outb => n4334);
U5412 : inv port map( inb => mult_125_G2_ab_5_4_port, outb => n1555);
U5413 : inv port map( inb => mult_125_G2_ab_7_4_port, outb => n1560);
U5414 : inv port map( inb => mult_125_G2_ab_9_4_port, outb => n4372);
U5415 : inv port map( inb => mult_125_G2_ab_5_2_port, outb => n4403);
U5416 : inv port map( inb => mult_125_G2_ab_7_2_port, outb => n1622);
U5417 : inv port map( inb => mult_125_G2_ab_9_2_port, outb => n4408);
U5418 : inv port map( inb => mult_125_G2_ab_11_2_port, outb => n4411);
U5419 : inv port map( inb => mult_125_ab_5_8_port, outb => n4578);
U5420 : inv port map( inb => n1871, outb => n4580);
U5421 : inv port map( inb => mult_125_ab_5_6_port, outb => n1930);
U5422 : inv port map( inb => mult_125_ab_7_6_port, outb => n4619);
U5423 : inv port map( inb => mult_125_ab_5_4_port, outb => n1993);
U5424 : inv port map( inb => mult_125_ab_7_4_port, outb => n1998);
U5425 : inv port map( inb => mult_125_ab_9_4_port, outb => n4657);
U5426 : inv port map( inb => mult_125_ab_5_2_port, outb => n4688);
U5427 : inv port map( inb => mult_125_ab_7_2_port, outb => n2060);
U5428 : inv port map( inb => mult_125_ab_9_2_port, outb => n4693);
U5429 : inv port map( inb => mult_125_ab_11_2_port, outb => n4696);
U5430 : inv port map( inb => n622, outb => n3765);
U5431 : inv port map( inb => n686, outb => n3801);
U5432 : inv port map( inb => n690, outb => n3803);
U5433 : inv port map( inb => n732, outb => n4940);
U5434 : inv port map( inb => n739, outb => n3832);
U5435 : inv port map( inb => n748, outb => n3837);
U5436 : inv port map( inb => n752, outb => n3840);
U5437 : inv port map( inb => n756, outb => n3843);
U5438 : inv port map( inb => n1060, outb => n4050);
U5439 : inv port map( inb => n1124, outb => n4086);
U5440 : inv port map( inb => n1128, outb => n4088);
U5441 : inv port map( inb => n1170, outb => n5086);
U5442 : inv port map( inb => n1177, outb => n4117);
U5443 : inv port map( inb => n1186, outb => n4122);
U5444 : inv port map( inb => n1190, outb => n4125);
U5445 : inv port map( inb => n1194, outb => n4128);
U5446 : inv port map( inb => n1498, outb => n4335);
U5447 : inv port map( inb => n1562, outb => n4371);
U5448 : inv port map( inb => n1566, outb => n4373);
U5449 : inv port map( inb => n1608, outb => n5249);
U5450 : inv port map( inb => n1615, outb => n4402);
U5451 : inv port map( inb => n1624, outb => n4407);
U5452 : inv port map( inb => n1628, outb => n4410);
U5453 : inv port map( inb => n1632, outb => n4413);
U5454 : inv port map( inb => n1936, outb => n4620);
U5455 : inv port map( inb => n2000, outb => n4656);
U5456 : inv port map( inb => n2004, outb => n4658);
U5457 : inv port map( inb => n2046, outb => n5412);
U5458 : inv port map( inb => n2053, outb => n4687);
U5459 : inv port map( inb => n2062, outb => n4692);
U5460 : inv port map( inb => n2066, outb => n4695);
U5461 : inv port map( inb => n2070, outb => n4698);
U5462 : inv port map( inb => n556, outb => n3722);
U5463 : inv port map( inb => n618, outb => n3763);
U5464 : inv port map( inb => n265, outb => mult_125_G4_A2_17_port);
U5465 : inv port map( inb => n994, outb => n4007);
U5466 : inv port map( inb => n1056, outb => n4048);
U5467 : inv port map( inb => n373, outb => mult_125_G3_A2_17_port);
U5468 : inv port map( inb => n1432, outb => n4292);
U5469 : inv port map( inb => n1494, outb => n4333);
U5470 : inv port map( inb => n337, outb => mult_125_G2_A2_17_port);
U5471 : inv port map( inb => n1870, outb => n4577);
U5472 : inv port map( inb => n1932, outb => n4618);
U5473 : inv port map( inb => n301, outb => mult_125_A2_17_port);
U5474 : inv port map( inb => n525, outb => n3703);
U5475 : inv port map( inb => n584, outb => n3740);
U5476 : inv port map( inb => mult_125_G4_ab_4_7_port, outb => n3741);
U5477 : inv port map( inb => n585, outb => n3743);
U5478 : inv port map( inb => mult_125_G4_ab_6_5_port, outb => n650);
U5479 : inv port map( inb => n963, outb => n3988);
U5480 : inv port map( inb => n1022, outb => n4025);
U5481 : inv port map( inb => mult_125_G3_ab_4_7_port, outb => n4026);
U5482 : inv port map( inb => n1023, outb => n4028);
U5483 : inv port map( inb => mult_125_G3_ab_6_5_port, outb => n1088);
U5484 : inv port map( inb => n1401, outb => n4273);
U5485 : inv port map( inb => n1460, outb => n4310);
U5486 : inv port map( inb => mult_125_G2_ab_4_7_port, outb => n4311);
U5487 : inv port map( inb => n1461, outb => n4313);
U5488 : inv port map( inb => mult_125_G2_ab_6_5_port, outb => n1526);
U5489 : inv port map( inb => n1839, outb => n4558);
U5490 : inv port map( inb => n1898, outb => n4595);
U5491 : inv port map( inb => mult_125_ab_4_7_port, outb => n4596);
U5492 : inv port map( inb => n1899, outb => n4598);
U5493 : inv port map( inb => mult_125_ab_6_5_port, outb => n1964);
U5494 : inv port map( inb => n524, outb => n3700);
U5495 : inv port map( inb => mult_125_G4_ab_4_9_port, outb => n3701);
U5496 : inv port map( inb => n652, outb => n3782);
U5497 : inv port map( inb => n724, outb => n3823);
U5498 : inv port map( inb => n962, outb => n3985);
U5499 : inv port map( inb => mult_125_G3_ab_4_9_port, outb => n3986);
U5500 : inv port map( inb => n1090, outb => n4067);
U5501 : inv port map( inb => n1162, outb => n4108);
U5502 : inv port map( inb => n1400, outb => n4270);
U5503 : inv port map( inb => mult_125_G2_ab_4_9_port, outb => n4271);
U5504 : inv port map( inb => n1528, outb => n4352);
U5505 : inv port map( inb => n1600, outb => n4393);
U5506 : inv port map( inb => n1838, outb => n4555);
U5507 : inv port map( inb => mult_125_ab_4_9_port, outb => n4556);
U5508 : inv port map( inb => n1966, outb => n4637);
U5509 : inv port map( inb => n2038, outb => n4678);
U5510 : inv port map( inb => mult_125_G4_ab_4_8_port, outb => n3721);
U5511 : inv port map( inb => n681, outb => n3798);
U5512 : inv port map( inb => n720, outb => n3820);
U5513 : inv port map( inb => n743, outb => n3834);
U5514 : inv port map( inb => mult_125_G3_ab_4_8_port, outb => n4006);
U5515 : inv port map( inb => n1119, outb => n4083);
U5516 : inv port map( inb => n1158, outb => n4105);
U5517 : inv port map( inb => n1181, outb => n4119);
U5518 : inv port map( inb => mult_125_G2_ab_4_8_port, outb => n4291);
U5519 : inv port map( inb => n1557, outb => n4368);
U5520 : inv port map( inb => n1596, outb => n4390);
U5521 : inv port map( inb => n1619, outb => n4404);
U5522 : inv port map( inb => mult_125_ab_4_8_port, outb => n4576);
U5523 : inv port map( inb => n1995, outb => n4653);
U5524 : inv port map( inb => n2034, outb => n4675);
U5525 : inv port map( inb => n2057, outb => n4689);
U5526 : inv port map( inb => n554, outb => n3720);
U5527 : inv port map( inb => n646, outb => n3777);
U5528 : inv port map( inb => mult_125_G4_ab_4_5_port, outb => n3778);
U5529 : inv port map( inb => n711, outb => n3811);
U5530 : inv port map( inb => mult_125_G4_ab_4_3_port, outb => n3812);
U5531 : inv port map( inb => mult_125_G4_ab_6_3_port, outb => n3815);
U5532 : inv port map( inb => mult_125_G4_ab_8_3_port, outb => n3818);
U5533 : inv port map( inb => n992, outb => n4005);
U5534 : inv port map( inb => n1084, outb => n4062);
U5535 : inv port map( inb => mult_125_G3_ab_4_5_port, outb => n4063);
U5536 : inv port map( inb => n1149, outb => n4096);
U5537 : inv port map( inb => mult_125_G3_ab_4_3_port, outb => n4097);
U5538 : inv port map( inb => mult_125_G3_ab_6_3_port, outb => n4100);
U5539 : inv port map( inb => mult_125_G3_ab_8_3_port, outb => n4103);
U5540 : inv port map( inb => n1430, outb => n4290);
U5541 : inv port map( inb => n1522, outb => n4347);
U5542 : inv port map( inb => mult_125_G2_ab_4_5_port, outb => n4348);
U5543 : inv port map( inb => n1587, outb => n4381);
U5544 : inv port map( inb => mult_125_G2_ab_4_3_port, outb => n4382);
U5545 : inv port map( inb => mult_125_G2_ab_6_3_port, outb => n4385);
U5546 : inv port map( inb => mult_125_G2_ab_8_3_port, outb => n4388);
U5547 : inv port map( inb => n1868, outb => n4575);
U5548 : inv port map( inb => n1960, outb => n4632);
U5549 : inv port map( inb => mult_125_ab_4_5_port, outb => n4633);
U5550 : inv port map( inb => n2025, outb => n4666);
U5551 : inv port map( inb => mult_125_ab_4_3_port, outb => n4667);
U5552 : inv port map( inb => mult_125_ab_6_3_port, outb => n4670);
U5553 : inv port map( inb => mult_125_ab_8_3_port, outb => n4673);
U5554 : inv port map( inb => n647, outb => n3779);
U5555 : inv port map( inb => n716, outb => n3817);
U5556 : inv port map( inb => n1085, outb => n4064);
U5557 : inv port map( inb => n1154, outb => n4102);
U5558 : inv port map( inb => n1523, outb => n4349);
U5559 : inv port map( inb => n1592, outb => n4387);
U5560 : inv port map( inb => n1961, outb => n4634);
U5561 : inv port map( inb => n2030, outb => n4672);
U5562 : inv port map( inb => n613, outb => n3760);
U5563 : inv port map( inb => n676, outb => n3796);
U5564 : inv port map( inb => n1051, outb => n4045);
U5565 : inv port map( inb => n1114, outb => n4081);
U5566 : inv port map( inb => n1489, outb => n4330);
U5567 : inv port map( inb => n1552, outb => n4366);
U5568 : inv port map( inb => n1927, outb => n4615);
U5569 : inv port map( inb => n1990, outb => n4651);
U5570 : inv port map( inb => n455, outb => n4927);
U5571 : inv port map( inb => n516, outb => n4930);
U5572 : inv port map( inb => n575, outb => n4933);
U5573 : inv port map( inb => n637, outb => n4936);
U5574 : inv port map( inb => n712, outb => n3814);
U5575 : inv port map( inb => n775, outb => n3856);
U5576 : inv port map( inb => n779, outb => n3859);
U5577 : inv port map( inb => n783, outb => n3862);
U5578 : inv port map( inb => n787, outb => n3865);
U5579 : inv port map( inb => n791, outb => n4942);
U5580 : inv port map( inb => n893, outb => n5073);
U5581 : inv port map( inb => n954, outb => n5076);
U5582 : inv port map( inb => n1013, outb => n5079);
U5583 : inv port map( inb => n1075, outb => n5082);
U5584 : inv port map( inb => n1150, outb => n4099);
U5585 : inv port map( inb => n1213, outb => n4141);
U5586 : inv port map( inb => n1217, outb => n4144);
U5587 : inv port map( inb => n1221, outb => n4147);
U5588 : inv port map( inb => n1225, outb => n4150);
U5589 : inv port map( inb => n1229, outb => n5088);
U5590 : inv port map( inb => n1331, outb => n5236);
U5591 : inv port map( inb => n1392, outb => n5239);
U5592 : inv port map( inb => n1451, outb => n5242);
U5593 : inv port map( inb => n1513, outb => n5245);
U5594 : inv port map( inb => n1588, outb => n4384);
U5595 : inv port map( inb => n1651, outb => n4426);
U5596 : inv port map( inb => n1655, outb => n4429);
U5597 : inv port map( inb => n1659, outb => n4432);
U5598 : inv port map( inb => n1663, outb => n4435);
U5599 : inv port map( inb => n1667, outb => n5251);
U5600 : inv port map( inb => n1769, outb => n5399);
U5601 : inv port map( inb => n1830, outb => n5402);
U5602 : inv port map( inb => n1889, outb => n5405);
U5603 : inv port map( inb => n1951, outb => n5408);
U5604 : inv port map( inb => n2026, outb => n4669);
U5605 : inv port map( inb => n2089, outb => n4711);
U5606 : inv port map( inb => n2093, outb => n4714);
U5607 : inv port map( inb => n2097, outb => n4717);
U5608 : inv port map( inb => n2101, outb => n4720);
U5609 : inv port map( inb => n2105, outb => n5414);
U5610 : inv port map( inb => n3625, outb => n411);
U5611 : inv port map( inb => n3628, outb => n415);
U5612 : inv port map( inb => n3631, outb => n419);
U5613 : inv port map( inb => n3634, outb => n423);
U5614 : inv port map( inb => mult_125_G4_ab_2_12_port, outb => n429);
U5615 : inv port map( inb => n3639, outb => n432);
U5616 : inv port map( inb => n3644, outb => n438);
U5617 : inv port map( inb => n3647, outb => n442);
U5618 : inv port map( inb => n3650, outb => n446);
U5619 : inv port map( inb => n3653, outb => n450);
U5620 : inv port map( inb => n3656, outb => n454);
U5621 : inv port map( inb => mult_125_G4_ab_2_11_port, outb => n458);
U5622 : inv port map( inb => n3668, outb => n474);
U5623 : inv port map( inb => n3671, outb => n478);
U5624 : inv port map( inb => n3674, outb => n482);
U5625 : inv port map( inb => mult_125_G4_ab_15_11_port, outb => n486);
U5626 : inv port map( inb => mult_125_G4_ab_2_10_port, outb => n489);
U5627 : inv port map( inb => n3678, outb => n492);
U5628 : inv port map( inb => n3688, outb => n507);
U5629 : inv port map( inb => n3691, outb => n511);
U5630 : inv port map( inb => n3694, outb => n515);
U5631 : inv port map( inb => mult_125_G4_ab_2_9_port, outb => n519);
U5632 : inv port map( inb => n3697, outb => n522);
U5633 : inv port map( inb => n3705, outb => n532);
U5634 : inv port map( inb => n3710, outb => n538);
U5635 : inv port map( inb => n3713, outb => n542);
U5636 : inv port map( inb => mult_125_G4_ab_15_9_port, outb => n546);
U5637 : inv port map( inb => mult_125_G4_ab_2_8_port, outb => n549);
U5638 : inv port map( inb => n3717, outb => n552);
U5639 : inv port map( inb => n3724, outb => n560);
U5640 : inv port map( inb => n3732, outb => n570);
U5641 : inv port map( inb => n3735, outb => n574);
U5642 : inv port map( inb => mult_125_G4_ab_2_7_port, outb => n578);
U5643 : inv port map( inb => n3742, outb => n588);
U5644 : inv port map( inb => n3745, outb => n592);
U5645 : inv port map( inb => n3748, outb => n596);
U5646 : inv port map( inb => n3753, outb => n602);
U5647 : inv port map( inb => mult_125_G4_ab_15_7_port, outb => n606);
U5648 : inv port map( inb => mult_125_G4_ab_2_6_port, outb => n609);
U5649 : inv port map( inb => n3757, outb => n612);
U5650 : inv port map( inb => n3762, outb => n621);
U5651 : inv port map( inb => n3772, outb => n636);
U5652 : inv port map( inb => mult_125_G4_ab_2_5_port, outb => n640);
U5653 : inv port map( inb => n3784, outb => n659);
U5654 : inv port map( inb => n3787, outb => n663);
U5655 : inv port map( inb => mult_125_G4_ab_15_5_port, outb => n669);
U5656 : inv port map( inb => mult_125_G4_ab_2_4_port, outb => n672);
U5657 : inv port map( inb => n3793, outb => n675);
U5658 : inv port map( inb => mult_125_G4_ab_15_4_port, outb => n702);
U5659 : inv port map( inb => mult_125_G4_ab_2_3_port, outb => n705);
U5660 : inv port map( inb => n3822, outb => n727);
U5661 : inv port map( inb => mult_125_G4_ab_2_2_port, outb => n735);
U5662 : inv port map( inb => n3828, outb => n738);
U5663 : inv port map( inb => n3845, outb => n763);
U5664 : inv port map( inb => mult_125_G4_ab_2_1_port, outb => n765);
U5665 : inv port map( inb => n3847, outb => n768);
U5666 : inv port map( inb => n771, outb => n3853);
U5667 : inv port map( inb => n3855, outb => n778);
U5668 : inv port map( inb => n3864, outb => n790);
U5669 : inv port map( inb => n3874, outb => n802);
U5670 : inv port map( inb => n3878, outb => n806);
U5671 : inv port map( inb => n3882, outb => n810);
U5672 : inv port map( inb => n3886, outb => n814);
U5673 : inv port map( inb => n3890, outb => n818);
U5674 : inv port map( inb => n821, outb => n240);
U5675 : inv port map( inb => n3910, outb => n849);
U5676 : inv port map( inb => n3913, outb => n853);
U5677 : inv port map( inb => n3916, outb => n857);
U5678 : inv port map( inb => n3919, outb => n861);
U5679 : inv port map( inb => mult_125_G3_ab_2_12_port, outb => n867);
U5680 : inv port map( inb => n3924, outb => n870);
U5681 : inv port map( inb => n3929, outb => n876);
U5682 : inv port map( inb => n3932, outb => n880);
U5683 : inv port map( inb => n3935, outb => n884);
U5684 : inv port map( inb => n3938, outb => n888);
U5685 : inv port map( inb => n3941, outb => n892);
U5686 : inv port map( inb => mult_125_G3_ab_2_11_port, outb => n896);
U5687 : inv port map( inb => n3953, outb => n912);
U5688 : inv port map( inb => n3956, outb => n916);
U5689 : inv port map( inb => n3959, outb => n920);
U5690 : inv port map( inb => mult_125_G3_ab_15_11_port, outb => n924);
U5691 : inv port map( inb => mult_125_G3_ab_2_10_port, outb => n927);
U5692 : inv port map( inb => n3963, outb => n930);
U5693 : inv port map( inb => n3973, outb => n945);
U5694 : inv port map( inb => n3976, outb => n949);
U5695 : inv port map( inb => n3979, outb => n953);
U5696 : inv port map( inb => mult_125_G3_ab_2_9_port, outb => n957);
U5697 : inv port map( inb => n3982, outb => n960);
U5698 : inv port map( inb => n3990, outb => n970);
U5699 : inv port map( inb => n3995, outb => n976);
U5700 : inv port map( inb => n3998, outb => n980);
U5701 : inv port map( inb => mult_125_G3_ab_15_9_port, outb => n984);
U5702 : inv port map( inb => mult_125_G3_ab_2_8_port, outb => n987);
U5703 : inv port map( inb => n4002, outb => n990);
U5704 : inv port map( inb => n4009, outb => n998);
U5705 : inv port map( inb => n4017, outb => n1008);
U5706 : inv port map( inb => n4020, outb => n1012);
U5707 : inv port map( inb => mult_125_G3_ab_2_7_port, outb => n1016);
U5708 : inv port map( inb => n4027, outb => n1026);
U5709 : inv port map( inb => n4030, outb => n1030);
U5710 : inv port map( inb => n4033, outb => n1034);
U5711 : inv port map( inb => n4038, outb => n1040);
U5712 : inv port map( inb => mult_125_G3_ab_15_7_port, outb => n1044);
U5713 : inv port map( inb => mult_125_G3_ab_2_6_port, outb => n1047);
U5714 : inv port map( inb => n4042, outb => n1050);
U5715 : inv port map( inb => n4047, outb => n1059);
U5716 : inv port map( inb => n4057, outb => n1074);
U5717 : inv port map( inb => mult_125_G3_ab_2_5_port, outb => n1078);
U5718 : inv port map( inb => n4069, outb => n1097);
U5719 : inv port map( inb => n4072, outb => n1101);
U5720 : inv port map( inb => mult_125_G3_ab_15_5_port, outb => n1107);
U5721 : inv port map( inb => mult_125_G3_ab_2_4_port, outb => n1110);
U5722 : inv port map( inb => n4078, outb => n1113);
U5723 : inv port map( inb => mult_125_G3_ab_15_4_port, outb => n1140);
U5724 : inv port map( inb => mult_125_G3_ab_2_3_port, outb => n1143);
U5725 : inv port map( inb => n4107, outb => n1165);
U5726 : inv port map( inb => mult_125_G3_ab_2_2_port, outb => n1173);
U5727 : inv port map( inb => n4113, outb => n1176);
U5728 : inv port map( inb => n4130, outb => n1201);
U5729 : inv port map( inb => mult_125_G3_ab_2_1_port, outb => n1203);
U5730 : inv port map( inb => n4132, outb => n1206);
U5731 : inv port map( inb => n1209, outb => n4138);
U5732 : inv port map( inb => n4140, outb => n1216);
U5733 : inv port map( inb => n4149, outb => n1228);
U5734 : inv port map( inb => n4159, outb => n1240);
U5735 : inv port map( inb => n4163, outb => n1244);
U5736 : inv port map( inb => n4167, outb => n1248);
U5737 : inv port map( inb => n4171, outb => n1252);
U5738 : inv port map( inb => n4175, outb => n1256);
U5739 : inv port map( inb => n1259, outb => n348);
U5740 : inv port map( inb => n4195, outb => n1287);
U5741 : inv port map( inb => n4198, outb => n1291);
U5742 : inv port map( inb => n4201, outb => n1295);
U5743 : inv port map( inb => n4204, outb => n1299);
U5744 : inv port map( inb => mult_125_G2_ab_2_12_port, outb => n1305);
U5745 : inv port map( inb => n4209, outb => n1308);
U5746 : inv port map( inb => n4214, outb => n1314);
U5747 : inv port map( inb => n4217, outb => n1318);
U5748 : inv port map( inb => n4220, outb => n1322);
U5749 : inv port map( inb => n4223, outb => n1326);
U5750 : inv port map( inb => n4226, outb => n1330);
U5751 : inv port map( inb => mult_125_G2_ab_2_11_port, outb => n1334);
U5752 : inv port map( inb => n4238, outb => n1350);
U5753 : inv port map( inb => n4241, outb => n1354);
U5754 : inv port map( inb => n4244, outb => n1358);
U5755 : inv port map( inb => mult_125_G2_ab_15_11_port, outb => n1362);
U5756 : inv port map( inb => mult_125_G2_ab_2_10_port, outb => n1365);
U5757 : inv port map( inb => n4248, outb => n1368);
U5758 : inv port map( inb => n4258, outb => n1383);
U5759 : inv port map( inb => n4261, outb => n1387);
U5760 : inv port map( inb => n4264, outb => n1391);
U5761 : inv port map( inb => mult_125_G2_ab_2_9_port, outb => n1395);
U5762 : inv port map( inb => n4267, outb => n1398);
U5763 : inv port map( inb => n4275, outb => n1408);
U5764 : inv port map( inb => n4280, outb => n1414);
U5765 : inv port map( inb => n4283, outb => n1418);
U5766 : inv port map( inb => mult_125_G2_ab_15_9_port, outb => n1422);
U5767 : inv port map( inb => mult_125_G2_ab_2_8_port, outb => n1425);
U5768 : inv port map( inb => n4287, outb => n1428);
U5769 : inv port map( inb => n4294, outb => n1436);
U5770 : inv port map( inb => n4302, outb => n1446);
U5771 : inv port map( inb => n4305, outb => n1450);
U5772 : inv port map( inb => mult_125_G2_ab_2_7_port, outb => n1454);
U5773 : inv port map( inb => n4312, outb => n1464);
U5774 : inv port map( inb => n4315, outb => n1468);
U5775 : inv port map( inb => n4318, outb => n1472);
U5776 : inv port map( inb => n4323, outb => n1478);
U5777 : inv port map( inb => mult_125_G2_ab_15_7_port, outb => n1482);
U5778 : inv port map( inb => mult_125_G2_ab_2_6_port, outb => n1485);
U5779 : inv port map( inb => n4327, outb => n1488);
U5780 : inv port map( inb => n4332, outb => n1497);
U5781 : inv port map( inb => n4342, outb => n1512);
U5782 : inv port map( inb => mult_125_G2_ab_2_5_port, outb => n1516);
U5783 : inv port map( inb => n4354, outb => n1535);
U5784 : inv port map( inb => n4357, outb => n1539);
U5785 : inv port map( inb => mult_125_G2_ab_15_5_port, outb => n1545);
U5786 : inv port map( inb => mult_125_G2_ab_2_4_port, outb => n1548);
U5787 : inv port map( inb => n4363, outb => n1551);
U5788 : inv port map( inb => mult_125_G2_ab_15_4_port, outb => n1578);
U5789 : inv port map( inb => mult_125_G2_ab_2_3_port, outb => n1581);
U5790 : inv port map( inb => n4392, outb => n1603);
U5791 : inv port map( inb => mult_125_G2_ab_2_2_port, outb => n1611);
U5792 : inv port map( inb => n4398, outb => n1614);
U5793 : inv port map( inb => n4415, outb => n1639);
U5794 : inv port map( inb => mult_125_G2_ab_2_1_port, outb => n1641);
U5795 : inv port map( inb => n4417, outb => n1644);
U5796 : inv port map( inb => n1647, outb => n4423);
U5797 : inv port map( inb => n4425, outb => n1654);
U5798 : inv port map( inb => n4434, outb => n1666);
U5799 : inv port map( inb => n4444, outb => n1678);
U5800 : inv port map( inb => n4448, outb => n1682);
U5801 : inv port map( inb => n4452, outb => n1686);
U5802 : inv port map( inb => n4456, outb => n1690);
U5803 : inv port map( inb => n4460, outb => n1694);
U5804 : inv port map( inb => n1697, outb => n312);
U5805 : inv port map( inb => n4480, outb => n1725);
U5806 : inv port map( inb => n4483, outb => n1729);
U5807 : inv port map( inb => n4486, outb => n1733);
U5808 : inv port map( inb => n4489, outb => n1737);
U5809 : inv port map( inb => mult_125_ab_2_12_port, outb => n1743);
U5810 : inv port map( inb => n4494, outb => n1746);
U5811 : inv port map( inb => n4499, outb => n1752);
U5812 : inv port map( inb => n4502, outb => n1756);
U5813 : inv port map( inb => n4505, outb => n1760);
U5814 : inv port map( inb => n4508, outb => n1764);
U5815 : inv port map( inb => n4511, outb => n1768);
U5816 : inv port map( inb => mult_125_ab_2_11_port, outb => n1772);
U5817 : inv port map( inb => n4523, outb => n1788);
U5818 : inv port map( inb => n4526, outb => n1792);
U5819 : inv port map( inb => n4529, outb => n1796);
U5820 : inv port map( inb => mult_125_ab_15_11_port, outb => n1800);
U5821 : inv port map( inb => mult_125_ab_2_10_port, outb => n1803);
U5822 : inv port map( inb => n4533, outb => n1806);
U5823 : inv port map( inb => n4543, outb => n1821);
U5824 : inv port map( inb => n4546, outb => n1825);
U5825 : inv port map( inb => n4549, outb => n1829);
U5826 : inv port map( inb => mult_125_ab_2_9_port, outb => n1833);
U5827 : inv port map( inb => n4552, outb => n1836);
U5828 : inv port map( inb => n4560, outb => n1846);
U5829 : inv port map( inb => n4565, outb => n1852);
U5830 : inv port map( inb => n4568, outb => n1856);
U5831 : inv port map( inb => mult_125_ab_15_9_port, outb => n1860);
U5832 : inv port map( inb => mult_125_ab_2_8_port, outb => n1863);
U5833 : inv port map( inb => n4572, outb => n1866);
U5834 : inv port map( inb => n4579, outb => n1874);
U5835 : inv port map( inb => n4587, outb => n1884);
U5836 : inv port map( inb => n4590, outb => n1888);
U5837 : inv port map( inb => mult_125_ab_2_7_port, outb => n1892);
U5838 : inv port map( inb => n4597, outb => n1902);
U5839 : inv port map( inb => n4600, outb => n1906);
U5840 : inv port map( inb => n4603, outb => n1910);
U5841 : inv port map( inb => n4608, outb => n1916);
U5842 : inv port map( inb => mult_125_ab_15_7_port, outb => n1920);
U5843 : inv port map( inb => mult_125_ab_2_6_port, outb => n1923);
U5844 : inv port map( inb => n4612, outb => n1926);
U5845 : inv port map( inb => n4617, outb => n1935);
U5846 : inv port map( inb => n4627, outb => n1950);
U5847 : inv port map( inb => mult_125_ab_2_5_port, outb => n1954);
U5848 : inv port map( inb => n4639, outb => n1973);
U5849 : inv port map( inb => n4642, outb => n1977);
U5850 : inv port map( inb => mult_125_ab_15_5_port, outb => n1983);
U5851 : inv port map( inb => mult_125_ab_2_4_port, outb => n1986);
U5852 : inv port map( inb => n4648, outb => n1989);
U5853 : inv port map( inb => mult_125_ab_15_4_port, outb => n2016);
U5854 : inv port map( inb => mult_125_ab_2_3_port, outb => n2019);
U5855 : inv port map( inb => n4677, outb => n2041);
U5856 : inv port map( inb => mult_125_ab_2_2_port, outb => n2049);
U5857 : inv port map( inb => n4683, outb => n2052);
U5858 : inv port map( inb => n4700, outb => n2077);
U5859 : inv port map( inb => mult_125_ab_2_1_port, outb => n2079);
U5860 : inv port map( inb => n4702, outb => n2082);
U5861 : inv port map( inb => n2085, outb => n4708);
U5862 : inv port map( inb => n4710, outb => n2092);
U5863 : inv port map( inb => n4719, outb => n2104);
U5864 : inv port map( inb => n4729, outb => n2116);
U5865 : inv port map( inb => n4733, outb => n2120);
U5866 : inv port map( inb => n4737, outb => n2124);
U5867 : inv port map( inb => n4741, outb => n2128);
U5868 : inv port map( inb => n4745, outb => n2132);
U5869 : inv port map( inb => n2135, outb => n276);
U5870 : inv port map( inb => multiplier_sigs_1_31_port, outb => n5270);
U5871 : inv port map( inb => adder_mem_array_2_31_port, outb => n5269);
U5872 : inv port map( inb => multiplier_sigs_0_31_port, outb => n5433);
U5873 : inv port map( inb => adder_mem_array_1_31_port, outb => n5432);
U5874 : inv port map( inb => multiplier_sigs_2_31_port, outb => n5107);
U5875 : inv port map( inb => adder_mem_array_3_31_port, outb => n5106);
U5876 : inv port map( inb => n2238, outb => n242);
U5877 : inv port map( inb => mult_125_G4_ab_2_13_port, outb => n399);
U5878 : inv port map( inb => n401, outb => n3621);
U5879 : inv port map( inb => n3622, outb => n407);
U5880 : inv port map( inb => n426, outb => n4926);
U5881 : inv port map( inb => n435, outb => n3645);
U5882 : inv port map( inb => n460, outb => n3660);
U5883 : inv port map( inb => n3663, outb => n468);
U5884 : inv port map( inb => n485, outb => n4929);
U5885 : inv port map( inb => n4928, outb => n247);
U5886 : inv port map( inb => mult_125_G4_ab_15_12_port, outb => n5037);
U5887 : inv port map( inb => n495, outb => n3682);
U5888 : inv port map( inb => n3683, outb => n501);
U5889 : inv port map( inb => n3702, outb => n528);
U5890 : inv port map( inb => n545, outb => n4932);
U5891 : inv port map( inb => n4931, outb => n251);
U5892 : inv port map( inb => mult_125_G4_ab_15_10_port, outb => n5038);
U5893 : inv port map( inb => n3727, outb => n564);
U5894 : inv port map( inb => n580, outb => n3739);
U5895 : inv port map( inb => n605, outb => n4935);
U5896 : inv port map( inb => n4934, outb => n255);
U5897 : inv port map( inb => mult_125_G4_ab_15_8_port, outb => n5039);
U5898 : inv port map( inb => n615, outb => n3761);
U5899 : inv port map( inb => n624, outb => n3766);
U5900 : inv port map( inb => n3767, outb => n630);
U5901 : inv port map( inb => n642, outb => n3776);
U5902 : inv port map( inb => n649, outb => n3780);
U5903 : inv port map( inb => n3781, outb => n655);
U5904 : inv port map( inb => n668, outb => n4938);
U5905 : inv port map( inb => n4937, outb => n259);
U5906 : inv port map( inb => mult_125_G4_ab_15_6_port, outb => n5040);
U5907 : inv port map( inb => n678, outb => n3797);
U5908 : inv port map( inb => n683, outb => n3799);
U5909 : inv port map( inb => n3800, outb => n689);
U5910 : inv port map( inb => n692, outb => n3804);
U5911 : inv port map( inb => n3805, outb => n698);
U5912 : inv port map( inb => n707, outb => n3810);
U5913 : inv port map( inb => n3813, outb => n715);
U5914 : inv port map( inb => n3816, outb => n719);
U5915 : inv port map( inb => n3819, outb => n723);
U5916 : inv port map( inb => n3825, outb => n731);
U5917 : inv port map( inb => n3831, outb => n742);
U5918 : inv port map( inb => n745, outb => n3835);
U5919 : inv port map( inb => n3836, outb => n751);
U5920 : inv port map( inb => n3839, outb => n755);
U5921 : inv port map( inb => n3842, outb => n759);
U5922 : inv port map( inb => n3852, outb => n774);
U5923 : inv port map( inb => n3858, outb => n782);
U5924 : inv port map( inb => n3861, outb => n786);
U5925 : inv port map( inb => n793, outb => n3869);
U5926 : inv port map( inb => n795, outb => n3871);
U5927 : inv port map( inb => n3870, outb => n798);
U5928 : inv port map( inb => n5041, outb => n5030);
U5929 : inv port map( inb => mult_125_G4_ab_7_1_port, outb => n5042);
U5930 : inv port map( inb => mult_125_G4_ab_9_1_port, outb => n5043);
U5931 : inv port map( inb => mult_125_G4_ab_11_1_port, outb => n5044);
U5932 : inv port map( inb => mult_125_G4_ab_13_1_port, outb => n5045);
U5933 : inv port map( inb => mult_125_G4_ab_15_1_port, outb => n5046);
U5934 : inv port map( inb => n2535, outb => n350);
U5935 : inv port map( inb => mult_125_G3_ab_2_13_port, outb => n837);
U5936 : inv port map( inb => n839, outb => n3906);
U5937 : inv port map( inb => n3907, outb => n845);
U5938 : inv port map( inb => n864, outb => n5072);
U5939 : inv port map( inb => n873, outb => n3930);
U5940 : inv port map( inb => n898, outb => n3945);
U5941 : inv port map( inb => n3948, outb => n906);
U5942 : inv port map( inb => n923, outb => n5075);
U5943 : inv port map( inb => n5074, outb => n355);
U5944 : inv port map( inb => mult_125_G3_ab_15_12_port, outb => n5200);
U5945 : inv port map( inb => n933, outb => n3967);
U5946 : inv port map( inb => n3968, outb => n939);
U5947 : inv port map( inb => n3987, outb => n966);
U5948 : inv port map( inb => n983, outb => n5078);
U5949 : inv port map( inb => n5077, outb => n359);
U5950 : inv port map( inb => mult_125_G3_ab_15_10_port, outb => n5201);
U5951 : inv port map( inb => n4012, outb => n1002);
U5952 : inv port map( inb => n1018, outb => n4024);
U5953 : inv port map( inb => n1043, outb => n5081);
U5954 : inv port map( inb => n5080, outb => n363);
U5955 : inv port map( inb => mult_125_G3_ab_15_8_port, outb => n5202);
U5956 : inv port map( inb => n1053, outb => n4046);
U5957 : inv port map( inb => n1062, outb => n4051);
U5958 : inv port map( inb => n4052, outb => n1068);
U5959 : inv port map( inb => n1080, outb => n4061);
U5960 : inv port map( inb => n1087, outb => n4065);
U5961 : inv port map( inb => n4066, outb => n1093);
U5962 : inv port map( inb => n1106, outb => n5084);
U5963 : inv port map( inb => n5083, outb => n367);
U5964 : inv port map( inb => mult_125_G3_ab_15_6_port, outb => n5203);
U5965 : inv port map( inb => n1116, outb => n4082);
U5966 : inv port map( inb => n1121, outb => n4084);
U5967 : inv port map( inb => n4085, outb => n1127);
U5968 : inv port map( inb => n1130, outb => n4089);
U5969 : inv port map( inb => n4090, outb => n1136);
U5970 : inv port map( inb => n1145, outb => n4095);
U5971 : inv port map( inb => n4098, outb => n1153);
U5972 : inv port map( inb => n4101, outb => n1157);
U5973 : inv port map( inb => n4104, outb => n1161);
U5974 : inv port map( inb => n4110, outb => n1169);
U5975 : inv port map( inb => n4116, outb => n1180);
U5976 : inv port map( inb => n1183, outb => n4120);
U5977 : inv port map( inb => n4121, outb => n1189);
U5978 : inv port map( inb => n4124, outb => n1193);
U5979 : inv port map( inb => n4127, outb => n1197);
U5980 : inv port map( inb => n4137, outb => n1212);
U5981 : inv port map( inb => n4143, outb => n1220);
U5982 : inv port map( inb => n4146, outb => n1224);
U5983 : inv port map( inb => n1231, outb => n4154);
U5984 : inv port map( inb => n1233, outb => n4156);
U5985 : inv port map( inb => n4155, outb => n1236);
U5986 : inv port map( inb => n5204, outb => n5193);
U5987 : inv port map( inb => mult_125_G3_ab_7_1_port, outb => n5205);
U5988 : inv port map( inb => mult_125_G3_ab_9_1_port, outb => n5206);
U5989 : inv port map( inb => mult_125_G3_ab_11_1_port, outb => n5207);
U5990 : inv port map( inb => mult_125_G3_ab_13_1_port, outb => n5208);
U5991 : inv port map( inb => mult_125_G3_ab_15_1_port, outb => n5209);
U5992 : inv port map( inb => n2832, outb => n314);
U5993 : inv port map( inb => mult_125_G2_ab_2_13_port, outb => n1275);
U5994 : inv port map( inb => n1277, outb => n4191);
U5995 : inv port map( inb => n4192, outb => n1283);
U5996 : inv port map( inb => n1302, outb => n5235);
U5997 : inv port map( inb => n1311, outb => n4215);
U5998 : inv port map( inb => n1336, outb => n4230);
U5999 : inv port map( inb => n4233, outb => n1344);
U6000 : inv port map( inb => n1361, outb => n5238);
U6001 : inv port map( inb => n5237, outb => n319);
U6002 : inv port map( inb => mult_125_G2_ab_15_12_port, outb => n5363);
U6003 : inv port map( inb => n1371, outb => n4252);
U6004 : inv port map( inb => n4253, outb => n1377);
U6005 : inv port map( inb => n4272, outb => n1404);
U6006 : inv port map( inb => n1421, outb => n5241);
U6007 : inv port map( inb => n5240, outb => n323);
U6008 : inv port map( inb => mult_125_G2_ab_15_10_port, outb => n5364);
U6009 : inv port map( inb => n4297, outb => n1440);
U6010 : inv port map( inb => n1456, outb => n4309);
U6011 : inv port map( inb => n1481, outb => n5244);
U6012 : inv port map( inb => n5243, outb => n327);
U6013 : inv port map( inb => mult_125_G2_ab_15_8_port, outb => n5365);
U6014 : inv port map( inb => n1491, outb => n4331);
U6015 : inv port map( inb => n1500, outb => n4336);
U6016 : inv port map( inb => n4337, outb => n1506);
U6017 : inv port map( inb => n1518, outb => n4346);
U6018 : inv port map( inb => n1525, outb => n4350);
U6019 : inv port map( inb => n4351, outb => n1531);
U6020 : inv port map( inb => n1544, outb => n5247);
U6021 : inv port map( inb => n5246, outb => n331);
U6022 : inv port map( inb => mult_125_G2_ab_15_6_port, outb => n5366);
U6023 : inv port map( inb => n1554, outb => n4367);
U6024 : inv port map( inb => n1559, outb => n4369);
U6025 : inv port map( inb => n4370, outb => n1565);
U6026 : inv port map( inb => n1568, outb => n4374);
U6027 : inv port map( inb => n4375, outb => n1574);
U6028 : inv port map( inb => n1583, outb => n4380);
U6029 : inv port map( inb => n4383, outb => n1591);
U6030 : inv port map( inb => n4386, outb => n1595);
U6031 : inv port map( inb => n4389, outb => n1599);
U6032 : inv port map( inb => n4395, outb => n1607);
U6033 : inv port map( inb => n4401, outb => n1618);
U6034 : inv port map( inb => n1621, outb => n4405);
U6035 : inv port map( inb => n4406, outb => n1627);
U6036 : inv port map( inb => n4409, outb => n1631);
U6037 : inv port map( inb => n4412, outb => n1635);
U6038 : inv port map( inb => n4422, outb => n1650);
U6039 : inv port map( inb => n4428, outb => n1658);
U6040 : inv port map( inb => n4431, outb => n1662);
U6041 : inv port map( inb => n1669, outb => n4439);
U6042 : inv port map( inb => n1671, outb => n4441);
U6043 : inv port map( inb => n4440, outb => n1674);
U6044 : inv port map( inb => n5367, outb => n5356);
U6045 : inv port map( inb => mult_125_G2_ab_7_1_port, outb => n5368);
U6046 : inv port map( inb => mult_125_G2_ab_9_1_port, outb => n5369);
U6047 : inv port map( inb => mult_125_G2_ab_11_1_port, outb => n5370);
U6048 : inv port map( inb => mult_125_G2_ab_13_1_port, outb => n5371);
U6049 : inv port map( inb => mult_125_G2_ab_15_1_port, outb => n5372);
U6050 : inv port map( inb => n3129, outb => n278);
U6051 : inv port map( inb => mult_125_ab_2_13_port, outb => n1713);
U6052 : inv port map( inb => n1715, outb => n4476);
U6053 : inv port map( inb => n4477, outb => n1721);
U6054 : inv port map( inb => n1740, outb => n5398);
U6055 : inv port map( inb => n1749, outb => n4500);
U6056 : inv port map( inb => n1774, outb => n4515);
U6057 : inv port map( inb => n4518, outb => n1782);
U6058 : inv port map( inb => n1799, outb => n5401);
U6059 : inv port map( inb => n5400, outb => n283);
U6060 : inv port map( inb => mult_125_ab_15_12_port, outb => n5526);
U6061 : inv port map( inb => n1809, outb => n4537);
U6062 : inv port map( inb => n4538, outb => n1815);
U6063 : inv port map( inb => n4557, outb => n1842);
U6064 : inv port map( inb => n1859, outb => n5404);
U6065 : inv port map( inb => n5403, outb => n287);
U6066 : inv port map( inb => mult_125_ab_15_10_port, outb => n5527);
U6067 : inv port map( inb => n4582, outb => n1878);
U6068 : inv port map( inb => n1894, outb => n4594);
U6069 : inv port map( inb => n1919, outb => n5407);
U6070 : inv port map( inb => n5406, outb => n291);
U6071 : inv port map( inb => mult_125_ab_15_8_port, outb => n5528);
U6072 : inv port map( inb => n1929, outb => n4616);
U6073 : inv port map( inb => n1938, outb => n4621);
U6074 : inv port map( inb => n4622, outb => n1944);
U6075 : inv port map( inb => n1956, outb => n4631);
U6076 : inv port map( inb => n1963, outb => n4635);
U6077 : inv port map( inb => n4636, outb => n1969);
U6078 : inv port map( inb => n1982, outb => n5410);
U6079 : inv port map( inb => n5409, outb => n295);
U6080 : inv port map( inb => mult_125_ab_15_6_port, outb => n5529);
U6081 : inv port map( inb => n1992, outb => n4652);
U6082 : inv port map( inb => n1997, outb => n4654);
U6083 : inv port map( inb => n4655, outb => n2003);
U6084 : inv port map( inb => n2006, outb => n4659);
U6085 : inv port map( inb => n4660, outb => n2012);
U6086 : inv port map( inb => n2021, outb => n4665);
U6087 : inv port map( inb => n4668, outb => n2029);
U6088 : inv port map( inb => n4671, outb => n2033);
U6089 : inv port map( inb => n4674, outb => n2037);
U6090 : inv port map( inb => n4680, outb => n2045);
U6091 : inv port map( inb => n4686, outb => n2056);
U6092 : inv port map( inb => n2059, outb => n4690);
U6093 : inv port map( inb => n4691, outb => n2065);
U6094 : inv port map( inb => n4694, outb => n2069);
U6095 : inv port map( inb => n4697, outb => n2073);
U6096 : inv port map( inb => n4707, outb => n2088);
U6097 : inv port map( inb => n4713, outb => n2096);
U6098 : inv port map( inb => n4716, outb => n2100);
U6099 : inv port map( inb => n2107, outb => n4724);
U6100 : inv port map( inb => n2109, outb => n4726);
U6101 : inv port map( inb => n4725, outb => n2112);
U6102 : inv port map( inb => n5530, outb => n5519);
U6103 : inv port map( inb => mult_125_ab_7_1_port, outb => n5531);
U6104 : inv port map( inb => mult_125_ab_9_1_port, outb => n5532);
U6105 : inv port map( inb => mult_125_ab_11_1_port, outb => n5533);
U6106 : inv port map( inb => mult_125_ab_13_1_port, outb => n5534);
U6107 : inv port map( inb => mult_125_ab_15_1_port, outb => n5535);
U6108 : inv port map( inb => n2136, outb => n5091);
U6109 : inv port map( inb => n2163, outb => n5417);
U6110 : inv port map( inb => n2166, outb => n5254);
U6111 : inv port map( inb => n5536, outb => mult_125_G4_ZB);
U6112 : inv port map( inb => n5537, outb => mult_125_G4_ZA);
U6113 : inv port map( inb => n5538, outb => mult_125_G4_QB);
U6114 : inv port map( inb => n5539, outb => mult_125_G4_QA);
U6115 : inv port map( inb => mult_125_G4_A1_0_port, outb => n5540);
U6116 : inv port map( inb => n5541, outb => multiplier_sigs_3_2_port);
U6117 : inv port map( inb => mult_125_G4_A1_1_port, outb => n5542);
U6118 : inv port map( inb => n5543, outb => multiplier_sigs_3_3_port);
U6119 : inv port map( inb => mult_125_G4_A1_2_port, outb => n5544);
U6120 : inv port map( inb => n5545, outb => multiplier_sigs_3_4_port);
U6121 : inv port map( inb => mult_125_G4_A1_3_port, outb => n5546);
U6122 : inv port map( inb => n5547, outb => multiplier_sigs_3_5_port);
U6123 : inv port map( inb => mult_125_G4_A1_4_port, outb => n5548);
U6124 : inv port map( inb => n5549, outb => multiplier_sigs_3_6_port);
U6125 : inv port map( inb => mult_125_G4_A1_5_port, outb => n5550);
U6126 : inv port map( inb => n5551, outb => multiplier_sigs_3_7_port);
U6127 : inv port map( inb => mult_125_G4_A1_6_port, outb => n5552);
U6128 : inv port map( inb => n5553, outb => multiplier_sigs_3_8_port);
U6129 : inv port map( inb => mult_125_G4_A1_7_port, outb => n5554);
U6130 : inv port map( inb => n5555, outb => multiplier_sigs_3_9_port);
U6131 : inv port map( inb => mult_125_G4_A1_8_port, outb => n5556);
U6132 : inv port map( inb => n5557, outb => multiplier_sigs_3_10_port);
U6133 : inv port map( inb => mult_125_G4_A1_9_port, outb => n5558);
U6134 : inv port map( inb => n5559, outb => multiplier_sigs_3_11_port);
U6135 : inv port map( inb => mult_125_G4_A1_10_port, outb => n5560);
U6136 : inv port map( inb => n5561, outb => multiplier_sigs_3_12_port);
U6137 : inv port map( inb => mult_125_G4_A1_11_port, outb => n5562);
U6138 : inv port map( inb => n5563, outb => multiplier_sigs_3_13_port);
U6139 : inv port map( inb => mult_125_G4_A1_12_port, outb => n5564);
U6140 : inv port map( inb => n5565, outb => multiplier_sigs_3_14_port);
U6141 : inv port map( inb => mult_125_G4_A1_13_port, outb => n5566);
U6142 : inv port map( inb => n5567, outb => multiplier_sigs_3_15_port);
U6143 : inv port map( inb => mult_125_G4_A1_14_port, outb => n5568);
U6144 : inv port map( inb => mult_125_G4_A2_14_port, outb => n5569);
U6145 : inv port map( inb => n5570, outb => multiplier_sigs_3_16_port);
U6146 : inv port map( inb => mult_125_G4_A1_15_port, outb => n5571);
U6147 : inv port map( inb => mult_125_G4_A2_15_port, outb => n5572);
U6148 : inv port map( inb => n5573, outb =>
mult_125_G4_FS_1_PG_int_0_3_3_port);
U6149 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_3_2_port, outb =>
n5574);
U6150 : inv port map( inb => mult_125_G4_FS_1_P_0_3_3_port, outb => n5575);
U6151 : inv port map( inb => mult_125_G4_A1_16_port, outb => n5576);
U6152 : inv port map( inb => mult_125_G4_A2_16_port, outb => n5577);
U6153 : inv port map( inb => n5578, outb =>
mult_125_G4_FS_1_PG_int_0_4_0_port);
U6154 : inv port map( inb => mult_125_G4_A1_17_port, outb => n5579);
U6155 : inv port map( inb => mult_125_G4_A2_17_port, outb => n5580);
U6156 : inv port map( inb => n5581, outb =>
mult_125_G4_FS_1_PG_int_0_4_1_port);
U6157 : inv port map( inb => n5582, outb =>
mult_125_G4_FS_1_TEMP_P_0_4_1_port);
U6158 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_4_0_port, outb =>
n5583);
U6159 : inv port map( inb => mult_125_G4_A1_18_port, outb => n5584);
U6160 : inv port map( inb => mult_125_G4_A2_18_port, outb => n5585);
U6161 : inv port map( inb => n5586, outb =>
mult_125_G4_FS_1_PG_int_0_4_2_port);
U6162 : inv port map( inb => n5587, outb =>
mult_125_G4_FS_1_TEMP_P_0_4_2_port);
U6163 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_4_1_port, outb =>
n5588);
U6164 : inv port map( inb => mult_125_G4_FS_1_C_1_4_1_port, outb => n5589);
U6165 : inv port map( inb => mult_125_G4_FS_1_P_0_4_1_port, outb => n5590);
U6166 : inv port map( inb => mult_125_G4_A1_19_port, outb => n5591);
U6167 : inv port map( inb => mult_125_G4_A2_19_port, outb => n5592);
U6168 : inv port map( inb => n5593, outb =>
mult_125_G4_FS_1_PG_int_0_4_3_port);
U6169 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_4_2_port, outb =>
n5594);
U6170 : inv port map( inb => mult_125_G4_FS_1_P_0_4_3_port, outb => n5595);
U6171 : inv port map( inb => mult_125_G4_FS_1_C_1_4_2_port, outb => n5596);
U6172 : inv port map( inb => mult_125_G4_FS_1_P_0_4_2_port, outb => n5597);
U6173 : inv port map( inb => mult_125_G4_A1_20_port, outb => n5598);
U6174 : inv port map( inb => mult_125_G4_A2_20_port, outb => n5599);
U6175 : inv port map( inb => n5600, outb =>
mult_125_G4_FS_1_PG_int_0_5_0_port);
U6176 : inv port map( inb => mult_125_G4_A1_21_port, outb => n5601);
U6177 : inv port map( inb => mult_125_G4_A2_21_port, outb => n5602);
U6178 : inv port map( inb => n5603, outb =>
mult_125_G4_FS_1_PG_int_0_5_1_port);
U6179 : inv port map( inb => n5604, outb =>
mult_125_G4_FS_1_TEMP_P_0_5_1_port);
U6180 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_5_0_port, outb =>
n5605);
U6181 : inv port map( inb => mult_125_G4_A1_22_port, outb => n5606);
U6182 : inv port map( inb => mult_125_G4_A2_22_port, outb => n5607);
U6183 : inv port map( inb => n5608, outb =>
mult_125_G4_FS_1_PG_int_0_5_2_port);
U6184 : inv port map( inb => n5609, outb =>
mult_125_G4_FS_1_TEMP_P_0_5_2_port);
U6185 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_5_1_port, outb =>
n5610);
U6186 : inv port map( inb => mult_125_G4_FS_1_C_1_5_1_port, outb => n5611);
U6187 : inv port map( inb => mult_125_G4_FS_1_P_0_5_1_port, outb => n5612);
U6188 : inv port map( inb => mult_125_G4_A1_23_port, outb => n5613);
U6189 : inv port map( inb => mult_125_G4_A2_23_port, outb => n5614);
U6190 : inv port map( inb => n5615, outb =>
mult_125_G4_FS_1_PG_int_0_5_3_port);
U6191 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_5_2_port, outb =>
n5616);
U6192 : inv port map( inb => mult_125_G4_FS_1_P_0_5_3_port, outb => n5617);
U6193 : inv port map( inb => mult_125_G4_FS_1_C_1_5_2_port, outb => n5618);
U6194 : inv port map( inb => mult_125_G4_FS_1_P_0_5_2_port, outb => n5619);
U6195 : inv port map( inb => mult_125_G4_A1_24_port, outb => n5620);
U6196 : inv port map( inb => mult_125_G4_A2_24_port, outb => n5621);
U6197 : inv port map( inb => n5622, outb =>
mult_125_G4_FS_1_PG_int_0_6_0_port);
U6198 : inv port map( inb => mult_125_G4_A1_25_port, outb => n5623);
U6199 : inv port map( inb => mult_125_G4_A2_25_port, outb => n5624);
U6200 : inv port map( inb => n5625, outb =>
mult_125_G4_FS_1_PG_int_0_6_1_port);
U6201 : inv port map( inb => n5626, outb =>
mult_125_G4_FS_1_TEMP_P_0_6_1_port);
U6202 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_6_0_port, outb =>
n5627);
U6203 : inv port map( inb => mult_125_G4_A1_26_port, outb => n5628);
U6204 : inv port map( inb => mult_125_G4_A2_26_port, outb => n5629);
U6205 : inv port map( inb => n5630, outb =>
mult_125_G4_FS_1_PG_int_0_6_2_port);
U6206 : inv port map( inb => n5631, outb =>
mult_125_G4_FS_1_TEMP_P_0_6_2_port);
U6207 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_6_1_port, outb =>
n5632);
U6208 : inv port map( inb => mult_125_G4_FS_1_C_1_6_1_port, outb => n5633);
U6209 : inv port map( inb => mult_125_G4_FS_1_P_0_6_1_port, outb => n5634);
U6210 : inv port map( inb => mult_125_G4_A1_27_port, outb => n5635);
U6211 : inv port map( inb => mult_125_G4_A2_27_port, outb => n5636);
U6212 : inv port map( inb => n5637, outb =>
mult_125_G4_FS_1_PG_int_0_6_3_port);
U6213 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_6_2_port, outb =>
n5638);
U6214 : inv port map( inb => mult_125_G4_FS_1_P_0_6_3_port, outb => n5639);
U6215 : inv port map( inb => mult_125_G4_FS_1_C_1_6_2_port, outb => n5640);
U6216 : inv port map( inb => mult_125_G4_FS_1_P_0_6_2_port, outb => n5641);
U6217 : inv port map( inb => mult_125_G4_A1_28_port, outb => n5642);
U6218 : inv port map( inb => mult_125_G4_A2_28_port, outb => n5643);
U6219 : inv port map( inb => n5644, outb =>
mult_125_G4_FS_1_PG_int_0_7_0_port);
U6220 : inv port map( inb => mult_125_G4_A1_29_port, outb => n5645);
U6221 : inv port map( inb => mult_125_G4_A2_29_port, outb => n5646);
U6222 : inv port map( inb => n5647, outb =>
mult_125_G4_FS_1_PG_int_0_7_1_port);
U6223 : inv port map( inb => mult_125_G4_FS_1_C_1_7_0_port, outb => n5648);
U6224 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_7_0_port, outb =>
n5649);
U6225 : inv port map( inb => mult_125_G4_FS_1_G_1_0_3_port, outb => n5650);
U6226 : inv port map( inb => mult_125_G4_FS_1_C_1_4_0_port, outb => n5651);
U6227 : inv port map( inb => mult_125_G4_FS_1_G_1_1_0_port, outb => n5653);
U6228 : inv port map( inb => mult_125_G4_FS_1_C_1_5_0_port, outb => n5654);
U6229 : inv port map( inb => mult_125_G4_FS_1_G_1_1_1_port, outb => n5656);
U6230 : inv port map( inb => mult_125_G4_FS_1_C_1_6_0_port, outb => n5657);
U6231 : inv port map( inb => mult_125_G4_FS_1_G_1_1_2_port, outb => n5659);
U6232 : inv port map( inb => mult_125_G4_FS_1_G_2_0_0_port, outb => n5660);
U6233 : inv port map( inb => n5661, outb => mult_125_ZB);
U6234 : inv port map( inb => n5662, outb => mult_125_ZA);
U6235 : inv port map( inb => n5663, outb => mult_125_QB);
U6236 : inv port map( inb => n5664, outb => mult_125_QA);
U6237 : inv port map( inb => mult_125_A1_0_port, outb => n5665);
U6238 : inv port map( inb => n5666, outb => multiplier_sigs_0_2_port);
U6239 : inv port map( inb => mult_125_A1_1_port, outb => n5667);
U6240 : inv port map( inb => n5668, outb => multiplier_sigs_0_3_port);
U6241 : inv port map( inb => mult_125_A1_2_port, outb => n5669);
U6242 : inv port map( inb => n5670, outb => multiplier_sigs_0_4_port);
U6243 : inv port map( inb => mult_125_A1_3_port, outb => n5671);
U6244 : inv port map( inb => n5672, outb => multiplier_sigs_0_5_port);
U6245 : inv port map( inb => mult_125_A1_4_port, outb => n5673);
U6246 : inv port map( inb => n5674, outb => multiplier_sigs_0_6_port);
U6247 : inv port map( inb => mult_125_A1_5_port, outb => n5675);
U6248 : inv port map( inb => n5676, outb => multiplier_sigs_0_7_port);
U6249 : inv port map( inb => mult_125_A1_6_port, outb => n5677);
U6250 : inv port map( inb => n5678, outb => multiplier_sigs_0_8_port);
U6251 : inv port map( inb => mult_125_A1_7_port, outb => n5679);
U6252 : inv port map( inb => n5680, outb => multiplier_sigs_0_9_port);
U6253 : inv port map( inb => mult_125_A1_8_port, outb => n5681);
U6254 : inv port map( inb => n5682, outb => multiplier_sigs_0_10_port);
U6255 : inv port map( inb => mult_125_A1_9_port, outb => n5683);
U6256 : inv port map( inb => n5684, outb => multiplier_sigs_0_11_port);
U6257 : inv port map( inb => mult_125_A1_10_port, outb => n5685);
U6258 : inv port map( inb => n5686, outb => multiplier_sigs_0_12_port);
U6259 : inv port map( inb => mult_125_A1_11_port, outb => n5687);
U6260 : inv port map( inb => n5688, outb => multiplier_sigs_0_13_port);
U6261 : inv port map( inb => mult_125_A1_12_port, outb => n5689);
U6262 : inv port map( inb => n5690, outb => multiplier_sigs_0_14_port);
U6263 : inv port map( inb => mult_125_A1_13_port, outb => n5691);
U6264 : inv port map( inb => n5692, outb => multiplier_sigs_0_15_port);
U6265 : inv port map( inb => mult_125_A1_14_port, outb => n5693);
U6266 : inv port map( inb => mult_125_A2_14_port, outb => n5694);
U6267 : inv port map( inb => n5695, outb => multiplier_sigs_0_16_port);
U6268 : inv port map( inb => mult_125_A1_15_port, outb => n5696);
U6269 : inv port map( inb => mult_125_A2_15_port, outb => n5697);
U6270 : inv port map( inb => n5698, outb => mult_125_FS_1_PG_int_0_3_3_port)
;
U6271 : inv port map( inb => mult_125_FS_1_TEMP_G_0_3_2_port, outb => n5699)
;
U6272 : inv port map( inb => mult_125_FS_1_P_0_3_3_port, outb => n5700);
U6273 : inv port map( inb => mult_125_A1_16_port, outb => n5701);
U6274 : inv port map( inb => mult_125_A2_16_port, outb => n5702);
U6275 : inv port map( inb => n5703, outb => mult_125_FS_1_PG_int_0_4_0_port)
;
U6276 : inv port map( inb => mult_125_A1_17_port, outb => n5704);
U6277 : inv port map( inb => mult_125_A2_17_port, outb => n5705);
U6278 : inv port map( inb => n5706, outb => mult_125_FS_1_PG_int_0_4_1_port)
;
U6279 : inv port map( inb => n5707, outb => mult_125_FS_1_TEMP_P_0_4_1_port)
;
U6280 : inv port map( inb => mult_125_FS_1_TEMP_P_0_4_0_port, outb => n5708)
;
U6281 : inv port map( inb => mult_125_A1_18_port, outb => n5709);
U6282 : inv port map( inb => mult_125_A2_18_port, outb => n5710);
U6283 : inv port map( inb => n5711, outb => mult_125_FS_1_PG_int_0_4_2_port)
;
U6284 : inv port map( inb => n5712, outb => mult_125_FS_1_TEMP_P_0_4_2_port)
;
U6285 : inv port map( inb => mult_125_FS_1_TEMP_G_0_4_1_port, outb => n5713)
;
U6286 : inv port map( inb => mult_125_FS_1_C_1_4_1_port, outb => n5714);
U6287 : inv port map( inb => mult_125_FS_1_P_0_4_1_port, outb => n5715);
U6288 : inv port map( inb => mult_125_A1_19_port, outb => n5716);
U6289 : inv port map( inb => mult_125_A2_19_port, outb => n5717);
U6290 : inv port map( inb => n5718, outb => mult_125_FS_1_PG_int_0_4_3_port)
;
U6291 : inv port map( inb => mult_125_FS_1_TEMP_G_0_4_2_port, outb => n5719)
;
U6292 : inv port map( inb => mult_125_FS_1_P_0_4_3_port, outb => n5720);
U6293 : inv port map( inb => mult_125_FS_1_C_1_4_2_port, outb => n5721);
U6294 : inv port map( inb => mult_125_FS_1_P_0_4_2_port, outb => n5722);
U6295 : inv port map( inb => mult_125_A1_20_port, outb => n5723);
U6296 : inv port map( inb => mult_125_A2_20_port, outb => n5724);
U6297 : inv port map( inb => n5725, outb => mult_125_FS_1_PG_int_0_5_0_port)
;
U6298 : inv port map( inb => mult_125_A1_21_port, outb => n5726);
U6299 : inv port map( inb => mult_125_A2_21_port, outb => n5727);
U6300 : inv port map( inb => n5728, outb => mult_125_FS_1_PG_int_0_5_1_port)
;
U6301 : inv port map( inb => n5729, outb => mult_125_FS_1_TEMP_P_0_5_1_port)
;
U6302 : inv port map( inb => mult_125_FS_1_TEMP_P_0_5_0_port, outb => n5730)
;
U6303 : inv port map( inb => mult_125_A1_22_port, outb => n5731);
U6304 : inv port map( inb => mult_125_A2_22_port, outb => n5732);
U6305 : inv port map( inb => n5733, outb => mult_125_FS_1_PG_int_0_5_2_port)
;
U6306 : inv port map( inb => n5734, outb => mult_125_FS_1_TEMP_P_0_5_2_port)
;
U6307 : inv port map( inb => mult_125_FS_1_TEMP_G_0_5_1_port, outb => n5735)
;
U6308 : inv port map( inb => mult_125_FS_1_C_1_5_1_port, outb => n5736);
U6309 : inv port map( inb => mult_125_FS_1_P_0_5_1_port, outb => n5737);
U6310 : inv port map( inb => mult_125_A1_23_port, outb => n5738);
U6311 : inv port map( inb => mult_125_A2_23_port, outb => n5739);
U6312 : inv port map( inb => n5740, outb => mult_125_FS_1_PG_int_0_5_3_port)
;
U6313 : inv port map( inb => mult_125_FS_1_TEMP_G_0_5_2_port, outb => n5741)
;
U6314 : inv port map( inb => mult_125_FS_1_P_0_5_3_port, outb => n5742);
U6315 : inv port map( inb => mult_125_FS_1_C_1_5_2_port, outb => n5743);
U6316 : inv port map( inb => mult_125_FS_1_P_0_5_2_port, outb => n5744);
U6317 : inv port map( inb => mult_125_A1_24_port, outb => n5745);
U6318 : inv port map( inb => mult_125_A2_24_port, outb => n5746);
U6319 : inv port map( inb => n5747, outb => mult_125_FS_1_PG_int_0_6_0_port)
;
U6320 : inv port map( inb => mult_125_A1_25_port, outb => n5748);
U6321 : inv port map( inb => mult_125_A2_25_port, outb => n5749);
U6322 : inv port map( inb => n5750, outb => mult_125_FS_1_PG_int_0_6_1_port)
;
U6323 : inv port map( inb => n5751, outb => mult_125_FS_1_TEMP_P_0_6_1_port)
;
U6324 : inv port map( inb => mult_125_FS_1_TEMP_P_0_6_0_port, outb => n5752)
;
U6325 : inv port map( inb => mult_125_A1_26_port, outb => n5753);
U6326 : inv port map( inb => mult_125_A2_26_port, outb => n5754);
U6327 : inv port map( inb => n5755, outb => mult_125_FS_1_PG_int_0_6_2_port)
;
U6328 : inv port map( inb => n5756, outb => mult_125_FS_1_TEMP_P_0_6_2_port)
;
U6329 : inv port map( inb => mult_125_FS_1_TEMP_G_0_6_1_port, outb => n5757)
;
U6330 : inv port map( inb => mult_125_FS_1_C_1_6_1_port, outb => n5758);
U6331 : inv port map( inb => mult_125_FS_1_P_0_6_1_port, outb => n5759);
U6332 : inv port map( inb => mult_125_A1_27_port, outb => n5760);
U6333 : inv port map( inb => mult_125_A2_27_port, outb => n5761);
U6334 : inv port map( inb => n5762, outb => mult_125_FS_1_PG_int_0_6_3_port)
;
U6335 : inv port map( inb => mult_125_FS_1_TEMP_G_0_6_2_port, outb => n5763)
;
U6336 : inv port map( inb => mult_125_FS_1_P_0_6_3_port, outb => n5764);
U6337 : inv port map( inb => mult_125_FS_1_C_1_6_2_port, outb => n5765);
U6338 : inv port map( inb => mult_125_FS_1_P_0_6_2_port, outb => n5766);
U6339 : inv port map( inb => mult_125_A1_28_port, outb => n5767);
U6340 : inv port map( inb => mult_125_A2_28_port, outb => n5768);
U6341 : inv port map( inb => n5769, outb => mult_125_FS_1_PG_int_0_7_0_port)
;
U6342 : inv port map( inb => mult_125_A1_29_port, outb => n5770);
U6343 : inv port map( inb => mult_125_A2_29_port, outb => n5771);
U6344 : inv port map( inb => n5772, outb => mult_125_FS_1_PG_int_0_7_1_port)
;
U6345 : inv port map( inb => mult_125_FS_1_C_1_7_0_port, outb => n5773);
U6346 : inv port map( inb => mult_125_FS_1_TEMP_P_0_7_0_port, outb => n5774)
;
U6347 : inv port map( inb => mult_125_FS_1_G_1_0_3_port, outb => n5775);
U6348 : inv port map( inb => mult_125_FS_1_C_1_4_0_port, outb => n5776);
U6349 : inv port map( inb => mult_125_FS_1_G_1_1_0_port, outb => n5778);
U6350 : inv port map( inb => mult_125_FS_1_C_1_5_0_port, outb => n5779);
U6351 : inv port map( inb => mult_125_FS_1_G_1_1_1_port, outb => n5781);
U6352 : inv port map( inb => mult_125_FS_1_C_1_6_0_port, outb => n5782);
U6353 : inv port map( inb => mult_125_FS_1_G_1_1_2_port, outb => n5784);
U6354 : inv port map( inb => mult_125_FS_1_G_2_0_0_port, outb => n5785);
U6355 : inv port map( inb => n5786, outb => mult_125_G2_ZB);
U6356 : inv port map( inb => n5787, outb => mult_125_G2_ZA);
U6357 : inv port map( inb => n5788, outb => mult_125_G2_QB);
U6358 : inv port map( inb => n5789, outb => mult_125_G2_QA);
U6359 : inv port map( inb => mult_125_G2_A1_0_port, outb => n5790);
U6360 : inv port map( inb => n5791, outb => multiplier_sigs_1_2_port);
U6361 : inv port map( inb => mult_125_G2_A1_1_port, outb => n5792);
U6362 : inv port map( inb => n5793, outb => multiplier_sigs_1_3_port);
U6363 : inv port map( inb => mult_125_G2_A1_2_port, outb => n5794);
U6364 : inv port map( inb => n5795, outb => multiplier_sigs_1_4_port);
U6365 : inv port map( inb => mult_125_G2_A1_3_port, outb => n5796);
U6366 : inv port map( inb => n5797, outb => multiplier_sigs_1_5_port);
U6367 : inv port map( inb => mult_125_G2_A1_4_port, outb => n5798);
U6368 : inv port map( inb => n5799, outb => multiplier_sigs_1_6_port);
U6369 : inv port map( inb => mult_125_G2_A1_5_port, outb => n5800);
U6370 : inv port map( inb => n5801, outb => multiplier_sigs_1_7_port);
U6371 : inv port map( inb => mult_125_G2_A1_6_port, outb => n5802);
U6372 : inv port map( inb => n5803, outb => multiplier_sigs_1_8_port);
U6373 : inv port map( inb => mult_125_G2_A1_7_port, outb => n5804);
U6374 : inv port map( inb => n5805, outb => multiplier_sigs_1_9_port);
U6375 : inv port map( inb => mult_125_G2_A1_8_port, outb => n5806);
U6376 : inv port map( inb => n5807, outb => multiplier_sigs_1_10_port);
U6377 : inv port map( inb => mult_125_G2_A1_9_port, outb => n5808);
U6378 : inv port map( inb => n5809, outb => multiplier_sigs_1_11_port);
U6379 : inv port map( inb => mult_125_G2_A1_10_port, outb => n5810);
U6380 : inv port map( inb => n5811, outb => multiplier_sigs_1_12_port);
U6381 : inv port map( inb => mult_125_G2_A1_11_port, outb => n5812);
U6382 : inv port map( inb => n5813, outb => multiplier_sigs_1_13_port);
U6383 : inv port map( inb => mult_125_G2_A1_12_port, outb => n5814);
U6384 : inv port map( inb => n5815, outb => multiplier_sigs_1_14_port);
U6385 : inv port map( inb => mult_125_G2_A1_13_port, outb => n5816);
U6386 : inv port map( inb => n5817, outb => multiplier_sigs_1_15_port);
U6387 : inv port map( inb => mult_125_G2_A1_14_port, outb => n5818);
U6388 : inv port map( inb => mult_125_G2_A2_14_port, outb => n5819);
U6389 : inv port map( inb => n5820, outb => multiplier_sigs_1_16_port);
U6390 : inv port map( inb => mult_125_G2_A1_15_port, outb => n5821);
U6391 : inv port map( inb => mult_125_G2_A2_15_port, outb => n5822);
U6392 : inv port map( inb => n5823, outb =>
mult_125_G2_FS_1_PG_int_0_3_3_port);
U6393 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_3_2_port, outb =>
n5824);
U6394 : inv port map( inb => mult_125_G2_FS_1_P_0_3_3_port, outb => n5825);
U6395 : inv port map( inb => mult_125_G2_A1_16_port, outb => n5826);
U6396 : inv port map( inb => mult_125_G2_A2_16_port, outb => n5827);
U6397 : inv port map( inb => n5828, outb =>
mult_125_G2_FS_1_PG_int_0_4_0_port);
U6398 : inv port map( inb => mult_125_G2_A1_17_port, outb => n5829);
U6399 : inv port map( inb => mult_125_G2_A2_17_port, outb => n5830);
U6400 : inv port map( inb => n5831, outb =>
mult_125_G2_FS_1_PG_int_0_4_1_port);
U6401 : inv port map( inb => n5832, outb =>
mult_125_G2_FS_1_TEMP_P_0_4_1_port);
U6402 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_4_0_port, outb =>
n5833);
U6403 : inv port map( inb => mult_125_G2_A1_18_port, outb => n5834);
U6404 : inv port map( inb => mult_125_G2_A2_18_port, outb => n5835);
U6405 : inv port map( inb => n5836, outb =>
mult_125_G2_FS_1_PG_int_0_4_2_port);
U6406 : inv port map( inb => n5837, outb =>
mult_125_G2_FS_1_TEMP_P_0_4_2_port);
U6407 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_4_1_port, outb =>
n5838);
U6408 : inv port map( inb => mult_125_G2_FS_1_C_1_4_1_port, outb => n5839);
U6409 : inv port map( inb => mult_125_G2_FS_1_P_0_4_1_port, outb => n5840);
U6410 : inv port map( inb => mult_125_G2_A1_19_port, outb => n5841);
U6411 : inv port map( inb => mult_125_G2_A2_19_port, outb => n5842);
U6412 : inv port map( inb => n5843, outb =>
mult_125_G2_FS_1_PG_int_0_4_3_port);
U6413 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_4_2_port, outb =>
n5844);
U6414 : inv port map( inb => mult_125_G2_FS_1_P_0_4_3_port, outb => n5845);
U6415 : inv port map( inb => mult_125_G2_FS_1_C_1_4_2_port, outb => n5846);
U6416 : inv port map( inb => mult_125_G2_FS_1_P_0_4_2_port, outb => n5847);
U6417 : inv port map( inb => mult_125_G2_A1_20_port, outb => n5848);
U6418 : inv port map( inb => mult_125_G2_A2_20_port, outb => n5849);
U6419 : inv port map( inb => n5850, outb =>
mult_125_G2_FS_1_PG_int_0_5_0_port);
U6420 : inv port map( inb => mult_125_G2_A1_21_port, outb => n5851);
U6421 : inv port map( inb => mult_125_G2_A2_21_port, outb => n5852);
U6422 : inv port map( inb => n5853, outb =>
mult_125_G2_FS_1_PG_int_0_5_1_port);
U6423 : inv port map( inb => n5854, outb =>
mult_125_G2_FS_1_TEMP_P_0_5_1_port);
U6424 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_5_0_port, outb =>
n5855);
U6425 : inv port map( inb => mult_125_G2_A1_22_port, outb => n5856);
U6426 : inv port map( inb => mult_125_G2_A2_22_port, outb => n5857);
U6427 : inv port map( inb => n5858, outb =>
mult_125_G2_FS_1_PG_int_0_5_2_port);
U6428 : inv port map( inb => n5859, outb =>
mult_125_G2_FS_1_TEMP_P_0_5_2_port);
U6429 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_5_1_port, outb =>
n5860);
U6430 : inv port map( inb => mult_125_G2_FS_1_C_1_5_1_port, outb => n5861);
U6431 : inv port map( inb => mult_125_G2_FS_1_P_0_5_1_port, outb => n5862);
U6432 : inv port map( inb => mult_125_G2_A1_23_port, outb => n5863);
U6433 : inv port map( inb => mult_125_G2_A2_23_port, outb => n5864);
U6434 : inv port map( inb => n5865, outb =>
mult_125_G2_FS_1_PG_int_0_5_3_port);
U6435 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_5_2_port, outb =>
n5866);
U6436 : inv port map( inb => mult_125_G2_FS_1_P_0_5_3_port, outb => n5867);
U6437 : inv port map( inb => mult_125_G2_FS_1_C_1_5_2_port, outb => n5868);
U6438 : inv port map( inb => mult_125_G2_FS_1_P_0_5_2_port, outb => n5869);
U6439 : inv port map( inb => mult_125_G2_A1_24_port, outb => n5870);
U6440 : inv port map( inb => mult_125_G2_A2_24_port, outb => n5871);
U6441 : inv port map( inb => n5872, outb =>
mult_125_G2_FS_1_PG_int_0_6_0_port);
U6442 : inv port map( inb => mult_125_G2_A1_25_port, outb => n5873);
U6443 : inv port map( inb => mult_125_G2_A2_25_port, outb => n5874);
U6444 : inv port map( inb => n5875, outb =>
mult_125_G2_FS_1_PG_int_0_6_1_port);
U6445 : inv port map( inb => n5876, outb =>
mult_125_G2_FS_1_TEMP_P_0_6_1_port);
U6446 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_6_0_port, outb =>
n5877);
U6447 : inv port map( inb => mult_125_G2_A1_26_port, outb => n5878);
U6448 : inv port map( inb => mult_125_G2_A2_26_port, outb => n5879);
U6449 : inv port map( inb => n5880, outb =>
mult_125_G2_FS_1_PG_int_0_6_2_port);
U6450 : inv port map( inb => n5881, outb =>
mult_125_G2_FS_1_TEMP_P_0_6_2_port);
U6451 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_6_1_port, outb =>
n5882);
U6452 : inv port map( inb => mult_125_G2_FS_1_C_1_6_1_port, outb => n5883);
U6453 : inv port map( inb => mult_125_G2_FS_1_P_0_6_1_port, outb => n5884);
U6454 : inv port map( inb => mult_125_G2_A1_27_port, outb => n5885);
U6455 : inv port map( inb => mult_125_G2_A2_27_port, outb => n5886);
U6456 : inv port map( inb => n5887, outb =>
mult_125_G2_FS_1_PG_int_0_6_3_port);
U6457 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_6_2_port, outb =>
n5888);
U6458 : inv port map( inb => mult_125_G2_FS_1_P_0_6_3_port, outb => n5889);
U6459 : inv port map( inb => mult_125_G2_FS_1_C_1_6_2_port, outb => n5890);
U6460 : inv port map( inb => mult_125_G2_FS_1_P_0_6_2_port, outb => n5891);
U6461 : inv port map( inb => mult_125_G2_A1_28_port, outb => n5892);
U6462 : inv port map( inb => mult_125_G2_A2_28_port, outb => n5893);
U6463 : inv port map( inb => n5894, outb =>
mult_125_G2_FS_1_PG_int_0_7_0_port);
U6464 : inv port map( inb => mult_125_G2_A1_29_port, outb => n5895);
U6465 : inv port map( inb => mult_125_G2_A2_29_port, outb => n5896);
U6466 : inv port map( inb => n5897, outb =>
mult_125_G2_FS_1_PG_int_0_7_1_port);
U6467 : inv port map( inb => mult_125_G2_FS_1_C_1_7_0_port, outb => n5898);
U6468 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_7_0_port, outb =>
n5899);
U6469 : inv port map( inb => mult_125_G2_FS_1_G_1_0_3_port, outb => n5900);
U6470 : inv port map( inb => mult_125_G2_FS_1_C_1_4_0_port, outb => n5901);
U6471 : inv port map( inb => mult_125_G2_FS_1_G_1_1_0_port, outb => n5903);
U6472 : inv port map( inb => mult_125_G2_FS_1_C_1_5_0_port, outb => n5904);
U6473 : inv port map( inb => mult_125_G2_FS_1_G_1_1_1_port, outb => n5906);
U6474 : inv port map( inb => mult_125_G2_FS_1_C_1_6_0_port, outb => n5907);
U6475 : inv port map( inb => mult_125_G2_FS_1_G_1_1_2_port, outb => n5909);
U6476 : inv port map( inb => mult_125_G2_FS_1_G_2_0_0_port, outb => n5910);
U6477 : inv port map( inb => n5911, outb => mult_125_G3_ZB);
U6478 : inv port map( inb => n5912, outb => mult_125_G3_ZA);
U6479 : inv port map( inb => n5913, outb => mult_125_G3_QB);
U6480 : inv port map( inb => n5914, outb => mult_125_G3_QA);
U6481 : inv port map( inb => mult_125_G3_A1_0_port, outb => n5915);
U6482 : inv port map( inb => n5916, outb => multiplier_sigs_2_2_port);
U6483 : inv port map( inb => mult_125_G3_A1_1_port, outb => n5917);
U6484 : inv port map( inb => n5918, outb => multiplier_sigs_2_3_port);
U6485 : inv port map( inb => mult_125_G3_A1_2_port, outb => n5919);
U6486 : inv port map( inb => n5920, outb => multiplier_sigs_2_4_port);
U6487 : inv port map( inb => mult_125_G3_A1_3_port, outb => n5921);
U6488 : inv port map( inb => n5922, outb => multiplier_sigs_2_5_port);
U6489 : inv port map( inb => mult_125_G3_A1_4_port, outb => n5923);
U6490 : inv port map( inb => n5924, outb => multiplier_sigs_2_6_port);
U6491 : inv port map( inb => mult_125_G3_A1_5_port, outb => n5925);
U6492 : inv port map( inb => n5926, outb => multiplier_sigs_2_7_port);
U6493 : inv port map( inb => mult_125_G3_A1_6_port, outb => n5927);
U6494 : inv port map( inb => n5928, outb => multiplier_sigs_2_8_port);
U6495 : inv port map( inb => mult_125_G3_A1_7_port, outb => n5929);
U6496 : inv port map( inb => n5930, outb => multiplier_sigs_2_9_port);
U6497 : inv port map( inb => mult_125_G3_A1_8_port, outb => n5931);
U6498 : inv port map( inb => n5932, outb => multiplier_sigs_2_10_port);
U6499 : inv port map( inb => mult_125_G3_A1_9_port, outb => n5933);
U6500 : inv port map( inb => n5934, outb => multiplier_sigs_2_11_port);
U6501 : inv port map( inb => mult_125_G3_A1_10_port, outb => n5935);
U6502 : inv port map( inb => n5936, outb => multiplier_sigs_2_12_port);
U6503 : inv port map( inb => mult_125_G3_A1_11_port, outb => n5937);
U6504 : inv port map( inb => n5938, outb => multiplier_sigs_2_13_port);
U6505 : inv port map( inb => mult_125_G3_A1_12_port, outb => n5939);
U6506 : inv port map( inb => n5940, outb => multiplier_sigs_2_14_port);
U6507 : inv port map( inb => mult_125_G3_A1_13_port, outb => n5941);
U6508 : inv port map( inb => n5942, outb => multiplier_sigs_2_15_port);
U6509 : inv port map( inb => mult_125_G3_A1_14_port, outb => n5943);
U6510 : inv port map( inb => mult_125_G3_A2_14_port, outb => n5944);
U6511 : inv port map( inb => n5945, outb => multiplier_sigs_2_16_port);
U6512 : inv port map( inb => mult_125_G3_A1_15_port, outb => n5946);
U6513 : inv port map( inb => mult_125_G3_A2_15_port, outb => n5947);
U6514 : inv port map( inb => n5948, outb =>
mult_125_G3_FS_1_PG_int_0_3_3_port);
U6515 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_3_2_port, outb =>
n5949);
U6516 : inv port map( inb => mult_125_G3_FS_1_P_0_3_3_port, outb => n5950);
U6517 : inv port map( inb => mult_125_G3_A1_16_port, outb => n5951);
U6518 : inv port map( inb => mult_125_G3_A2_16_port, outb => n5952);
U6519 : inv port map( inb => n5953, outb =>
mult_125_G3_FS_1_PG_int_0_4_0_port);
U6520 : inv port map( inb => mult_125_G3_A1_17_port, outb => n5954);
U6521 : inv port map( inb => mult_125_G3_A2_17_port, outb => n5955);
U6522 : inv port map( inb => n5956, outb =>
mult_125_G3_FS_1_PG_int_0_4_1_port);
U6523 : inv port map( inb => n5957, outb =>
mult_125_G3_FS_1_TEMP_P_0_4_1_port);
U6524 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_4_0_port, outb =>
n5958);
U6525 : inv port map( inb => mult_125_G3_A1_18_port, outb => n5959);
U6526 : inv port map( inb => mult_125_G3_A2_18_port, outb => n5960);
U6527 : inv port map( inb => n5961, outb =>
mult_125_G3_FS_1_PG_int_0_4_2_port);
U6528 : inv port map( inb => n5962, outb =>
mult_125_G3_FS_1_TEMP_P_0_4_2_port);
U6529 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_4_1_port, outb =>
n5963);
U6530 : inv port map( inb => mult_125_G3_FS_1_C_1_4_1_port, outb => n5964);
U6531 : inv port map( inb => mult_125_G3_FS_1_P_0_4_1_port, outb => n5965);
U6532 : inv port map( inb => mult_125_G3_A1_19_port, outb => n5966);
U6533 : inv port map( inb => mult_125_G3_A2_19_port, outb => n5967);
U6534 : inv port map( inb => n5968, outb =>
mult_125_G3_FS_1_PG_int_0_4_3_port);
U6535 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_4_2_port, outb =>
n5969);
U6536 : inv port map( inb => mult_125_G3_FS_1_P_0_4_3_port, outb => n5970);
U6537 : inv port map( inb => mult_125_G3_FS_1_C_1_4_2_port, outb => n5971);
U6538 : inv port map( inb => mult_125_G3_FS_1_P_0_4_2_port, outb => n5972);
U6539 : inv port map( inb => mult_125_G3_A1_20_port, outb => n5973);
U6540 : inv port map( inb => mult_125_G3_A2_20_port, outb => n5974);
U6541 : inv port map( inb => n5975, outb =>
mult_125_G3_FS_1_PG_int_0_5_0_port);
U6542 : inv port map( inb => mult_125_G3_A1_21_port, outb => n5976);
U6543 : inv port map( inb => mult_125_G3_A2_21_port, outb => n5977);
U6544 : inv port map( inb => n5978, outb =>
mult_125_G3_FS_1_PG_int_0_5_1_port);
U6545 : inv port map( inb => n5979, outb =>
mult_125_G3_FS_1_TEMP_P_0_5_1_port);
U6546 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_5_0_port, outb =>
n5980);
U6547 : inv port map( inb => mult_125_G3_A1_22_port, outb => n5981);
U6548 : inv port map( inb => mult_125_G3_A2_22_port, outb => n5982);
U6549 : inv port map( inb => n5983, outb =>
mult_125_G3_FS_1_PG_int_0_5_2_port);
U6550 : inv port map( inb => n5984, outb =>
mult_125_G3_FS_1_TEMP_P_0_5_2_port);
U6551 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_5_1_port, outb =>
n5985);
U6552 : inv port map( inb => mult_125_G3_FS_1_C_1_5_1_port, outb => n5986);
U6553 : inv port map( inb => mult_125_G3_FS_1_P_0_5_1_port, outb => n5987);
U6554 : inv port map( inb => mult_125_G3_A1_23_port, outb => n5988);
U6555 : inv port map( inb => mult_125_G3_A2_23_port, outb => n5989);
U6556 : inv port map( inb => n5990, outb =>
mult_125_G3_FS_1_PG_int_0_5_3_port);
U6557 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_5_2_port, outb =>
n5991);
U6558 : inv port map( inb => mult_125_G3_FS_1_P_0_5_3_port, outb => n5992);
U6559 : inv port map( inb => mult_125_G3_FS_1_C_1_5_2_port, outb => n5993);
U6560 : inv port map( inb => mult_125_G3_FS_1_P_0_5_2_port, outb => n5994);
U6561 : inv port map( inb => mult_125_G3_A1_24_port, outb => n5995);
U6562 : inv port map( inb => mult_125_G3_A2_24_port, outb => n5996);
U6563 : inv port map( inb => n5997, outb =>
mult_125_G3_FS_1_PG_int_0_6_0_port);
U6564 : inv port map( inb => mult_125_G3_A1_25_port, outb => n5998);
U6565 : inv port map( inb => mult_125_G3_A2_25_port, outb => n5999);
U6566 : inv port map( inb => n6000, outb =>
mult_125_G3_FS_1_PG_int_0_6_1_port);
U6567 : inv port map( inb => n6001, outb =>
mult_125_G3_FS_1_TEMP_P_0_6_1_port);
U6568 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_6_0_port, outb =>
n6002);
U6569 : inv port map( inb => mult_125_G3_A1_26_port, outb => n6003);
U6570 : inv port map( inb => mult_125_G3_A2_26_port, outb => n6004);
U6571 : inv port map( inb => n6005, outb =>
mult_125_G3_FS_1_PG_int_0_6_2_port);
U6572 : inv port map( inb => n6006, outb =>
mult_125_G3_FS_1_TEMP_P_0_6_2_port);
U6573 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_6_1_port, outb =>
n6007);
U6574 : inv port map( inb => mult_125_G3_FS_1_C_1_6_1_port, outb => n6008);
U6575 : inv port map( inb => mult_125_G3_FS_1_P_0_6_1_port, outb => n6009);
U6576 : inv port map( inb => mult_125_G3_A1_27_port, outb => n6010);
U6577 : inv port map( inb => mult_125_G3_A2_27_port, outb => n6011);
U6578 : inv port map( inb => n6012, outb =>
mult_125_G3_FS_1_PG_int_0_6_3_port);
U6579 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_6_2_port, outb =>
n6013);
U6580 : inv port map( inb => mult_125_G3_FS_1_P_0_6_3_port, outb => n6014);
U6581 : inv port map( inb => mult_125_G3_FS_1_C_1_6_2_port, outb => n6015);
U6582 : inv port map( inb => mult_125_G3_FS_1_P_0_6_2_port, outb => n6016);
U6583 : inv port map( inb => mult_125_G3_A1_28_port, outb => n6017);
U6584 : inv port map( inb => mult_125_G3_A2_28_port, outb => n6018);
U6585 : inv port map( inb => n6019, outb =>
mult_125_G3_FS_1_PG_int_0_7_0_port);
U6586 : inv port map( inb => mult_125_G3_A1_29_port, outb => n6020);
U6587 : inv port map( inb => mult_125_G3_A2_29_port, outb => n6021);
U6588 : inv port map( inb => n6022, outb =>
mult_125_G3_FS_1_PG_int_0_7_1_port);
U6589 : inv port map( inb => mult_125_G3_FS_1_C_1_7_0_port, outb => n6023);
U6590 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_7_0_port, outb =>
n6024);
U6591 : inv port map( inb => mult_125_G3_FS_1_G_1_0_3_port, outb => n6025);
U6592 : inv port map( inb => mult_125_G3_FS_1_C_1_4_0_port, outb => n6026);
U6593 : inv port map( inb => mult_125_G3_FS_1_G_1_1_0_port, outb => n6028);
U6594 : inv port map( inb => mult_125_G3_FS_1_C_1_5_0_port, outb => n6029);
U6595 : inv port map( inb => mult_125_G3_FS_1_G_1_1_1_port, outb => n6031);
U6596 : inv port map( inb => mult_125_G3_FS_1_C_1_6_0_port, outb => n6032);
U6597 : inv port map( inb => mult_125_G3_FS_1_G_1_1_2_port, outb => n6034);
U6598 : inv port map( inb => mult_125_G3_FS_1_G_2_0_0_port, outb => n6035);
end SYN_fir_rtl_arch;
|
-- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_n - syn
-- Description: Genric width Gray code counter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 6 5 305MHz/ 3.28ns
-- 5 8 6 286MHz/ 2.85ns
-- 8 13 9 234MHz/ 4.26ns
-- 16 56 17 149MHz/ 6.67ns
-- 32 95 33 161MHz/ 6.19ns
-- 64 188 68 126MHz/ 7.90ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
entity gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_n;
architecture syn of gray_cnt_n is
signal R_AUX : slbit := '1';
signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
assert DWIDTH>=3
report "assert(DWIDTH>=3): only 3 bit or larger supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_AUX <= '1';
R_DATA <= (others=>'0');
elsif CE = '1' then
R_AUX <= not R_AUX;
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_AUX, R_DATA)
variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
variable s : slbit := '0';
begin
r := R_DATA;
n := R_DATA;
s := '1';
if R_AUX = '1' then
n(0) := not r(0);
else
for i in 1 to DWIDTH-2 loop
if s='1' and r(i-1)='1' then
n(i) := not r(i);
end if;
s := s and not r(i-1);
end loop;
if s = '1' then
n(DWIDTH-1) := r(DWIDTH-2);
end if;
end if;
N_DATA <= n;
end process proc_next;
DATA <= R_DATA;
end syn;
|
-- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_n - syn
-- Description: Genric width Gray code counter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 6 5 305MHz/ 3.28ns
-- 5 8 6 286MHz/ 2.85ns
-- 8 13 9 234MHz/ 4.26ns
-- 16 56 17 149MHz/ 6.67ns
-- 32 95 33 161MHz/ 6.19ns
-- 64 188 68 126MHz/ 7.90ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
entity gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_n;
architecture syn of gray_cnt_n is
signal R_AUX : slbit := '1';
signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
assert DWIDTH>=3
report "assert(DWIDTH>=3): only 3 bit or larger supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_AUX <= '1';
R_DATA <= (others=>'0');
elsif CE = '1' then
R_AUX <= not R_AUX;
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_AUX, R_DATA)
variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
variable s : slbit := '0';
begin
r := R_DATA;
n := R_DATA;
s := '1';
if R_AUX = '1' then
n(0) := not r(0);
else
for i in 1 to DWIDTH-2 loop
if s='1' and r(i-1)='1' then
n(i) := not r(i);
end if;
s := s and not r(i-1);
end loop;
if s = '1' then
n(DWIDTH-1) := r(DWIDTH-2);
end if;
end if;
N_DATA <= n;
end process proc_next;
DATA <= R_DATA;
end syn;
|
-- file: clk_wiz_v3_6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___320.000______0.000______50.0______100.024_____96.948
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________125.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clk_wiz_v3_6;
architecture xilinx of clk_wiz_v3_6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=8.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 3.125,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 8.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Parameter memory
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.endianness_pkg.all;
use work.io_bus_pkg.all;
entity floppy_param_mem is
generic (
g_big_endian : boolean );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
track : in unsigned(6 downto 0);
side : in std_logic := '0';
bit_time : out unsigned(9 downto 0);
track_start : out std_logic_vector(25 downto 0);
max_offset : out std_logic_vector(13 downto 0) );
end floppy_param_mem;
architecture gideon of floppy_param_mem is
signal toggle : std_logic;
signal param_addr : std_logic_vector(8 downto 0);
signal param_data : std_logic_vector(31 downto 0);
signal ram_data : std_logic_vector(31 downto 0);
signal cpu_ram_en : std_logic;
signal cpu_ram_en_d : std_logic;
signal cpu_rdata : std_logic_vector(7 downto 0);
begin
cpu_ram_en <= io_req.read or io_req.write;
cpu_ram_en_d <= cpu_ram_en when rising_edge(clock);
io_resp.ack <= cpu_ram_en_d;
io_resp.data <= cpu_rdata when cpu_ram_en_d = '1' else X"00";
ram: RAMB16_S9_S36
port map (
CLKA => clock,
SSRA => reset,
ENA => cpu_ram_en,
WEA => io_req.write,
ADDRA => std_logic_vector(io_req.address(10 downto 0)),
DIA => io_req.data,
DIPA => "0",
DOA => cpu_rdata,
DOPA => open,
CLKB => clock,
SSRB => reset,
ENB => '1',
WEB => '0',
ADDRB => param_addr,
DIB => X"00000000",
DIPB => X"0",
DOB => ram_data,
DOPB => open );
param_addr <= side & std_logic_vector(track) & toggle;
param_data <= byte_swap(ram_data, g_big_endian);
process(clock)
begin
if rising_edge(clock) then
if toggle='1' then -- even addresses (one clock later)
track_start <= param_data(track_start'range);
else
max_offset <= param_data(max_offset'range);
bit_time <= unsigned(param_data(bit_time'high+16 downto 16));
end if;
if reset='1' then
toggle <= '0';
else
toggle <= not toggle;
end if;
end if;
end process;
end gideon;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_cos_hdl.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_modulator_cos_hdl
-- Source Path: hdl_modulator/wave_generator/sincos hdl/cos_hdl
-- Hierarchy Level: 4
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_modulator_hdl_modulator_pkg.ALL;
ENTITY hdl_modulator_cos_hdl IS
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END hdl_modulator_cos_hdl;
ARCHITECTURE rtl OF hdl_modulator_cos_hdl IS
-- Constants
CONSTANT nc : vector_of_signed16(0 TO 511) :=
(to_signed(16#0000#, 16), to_signed(16#0032#, 16), to_signed(16#0065#, 16), to_signed(16#0097#, 16),
to_signed(16#00C9#, 16), to_signed(16#00FC#, 16), to_signed(16#012E#, 16), to_signed(16#0161#, 16),
to_signed(16#0193#, 16), to_signed(16#01C5#, 16), to_signed(16#01F8#, 16), to_signed(16#022A#, 16),
to_signed(16#025C#, 16), to_signed(16#028F#, 16), to_signed(16#02C1#, 16), to_signed(16#02F3#, 16),
to_signed(16#0325#, 16), to_signed(16#0358#, 16), to_signed(16#038A#, 16), to_signed(16#03BC#, 16),
to_signed(16#03EF#, 16), to_signed(16#0421#, 16), to_signed(16#0453#, 16), to_signed(16#0485#, 16),
to_signed(16#04B8#, 16), to_signed(16#04EA#, 16), to_signed(16#051C#, 16), to_signed(16#054E#, 16),
to_signed(16#0580#, 16), to_signed(16#05B3#, 16), to_signed(16#05E5#, 16), to_signed(16#0617#, 16),
to_signed(16#0649#, 16), to_signed(16#067B#, 16), to_signed(16#06AD#, 16), to_signed(16#06DF#, 16),
to_signed(16#0711#, 16), to_signed(16#0743#, 16), to_signed(16#0775#, 16), to_signed(16#07A7#, 16),
to_signed(16#07D9#, 16), to_signed(16#080B#, 16), to_signed(16#083D#, 16), to_signed(16#086F#, 16),
to_signed(16#08A1#, 16), to_signed(16#08D3#, 16), to_signed(16#0905#, 16), to_signed(16#0937#, 16),
to_signed(16#0969#, 16), to_signed(16#099B#, 16), to_signed(16#09CC#, 16), to_signed(16#09FE#, 16),
to_signed(16#0A30#, 16), to_signed(16#0A61#, 16), to_signed(16#0A93#, 16), to_signed(16#0AC5#, 16),
to_signed(16#0AF6#, 16), to_signed(16#0B28#, 16), to_signed(16#0B5A#, 16), to_signed(16#0B8B#, 16),
to_signed(16#0BBD#, 16), to_signed(16#0BEE#, 16), to_signed(16#0C20#, 16), to_signed(16#0C51#, 16),
to_signed(16#0C83#, 16), to_signed(16#0CB4#, 16), to_signed(16#0CE5#, 16), to_signed(16#0D17#, 16),
to_signed(16#0D48#, 16), to_signed(16#0D79#, 16), to_signed(16#0DAA#, 16), to_signed(16#0DDC#, 16),
to_signed(16#0E0D#, 16), to_signed(16#0E3E#, 16), to_signed(16#0E6F#, 16), to_signed(16#0EA0#, 16),
to_signed(16#0ED1#, 16), to_signed(16#0F02#, 16), to_signed(16#0F33#, 16), to_signed(16#0F64#, 16),
to_signed(16#0F95#, 16), to_signed(16#0FC5#, 16), to_signed(16#0FF6#, 16), to_signed(16#1027#, 16),
to_signed(16#1058#, 16), to_signed(16#1088#, 16), to_signed(16#10B9#, 16), to_signed(16#10EA#, 16),
to_signed(16#111A#, 16), to_signed(16#114B#, 16), to_signed(16#117B#, 16), to_signed(16#11AC#, 16),
to_signed(16#11DC#, 16), to_signed(16#120C#, 16), to_signed(16#123D#, 16), to_signed(16#126D#, 16),
to_signed(16#129D#, 16), to_signed(16#12CD#, 16), to_signed(16#12FD#, 16), to_signed(16#132D#, 16),
to_signed(16#135D#, 16), to_signed(16#138D#, 16), to_signed(16#13BD#, 16), to_signed(16#13ED#, 16),
to_signed(16#141D#, 16), to_signed(16#144D#, 16), to_signed(16#147D#, 16), to_signed(16#14AC#, 16),
to_signed(16#14DC#, 16), to_signed(16#150C#, 16), to_signed(16#153B#, 16), to_signed(16#156B#, 16),
to_signed(16#159A#, 16), to_signed(16#15C9#, 16), to_signed(16#15F9#, 16), to_signed(16#1628#, 16),
to_signed(16#1657#, 16), to_signed(16#1686#, 16), to_signed(16#16B5#, 16), to_signed(16#16E5#, 16),
to_signed(16#1714#, 16), to_signed(16#1742#, 16), to_signed(16#1771#, 16), to_signed(16#17A0#, 16),
to_signed(16#17CF#, 16), to_signed(16#17FE#, 16), to_signed(16#182C#, 16), to_signed(16#185B#, 16),
to_signed(16#188A#, 16), to_signed(16#18B8#, 16), to_signed(16#18E6#, 16), to_signed(16#1915#, 16),
to_signed(16#1943#, 16), to_signed(16#1971#, 16), to_signed(16#19A0#, 16), to_signed(16#19CE#, 16),
to_signed(16#19FC#, 16), to_signed(16#1A2A#, 16), to_signed(16#1A58#, 16), to_signed(16#1A85#, 16),
to_signed(16#1AB3#, 16), to_signed(16#1AE1#, 16), to_signed(16#1B0F#, 16), to_signed(16#1B3C#, 16),
to_signed(16#1B6A#, 16), to_signed(16#1B97#, 16), to_signed(16#1BC5#, 16), to_signed(16#1BF2#, 16),
to_signed(16#1C1F#, 16), to_signed(16#1C4D#, 16), to_signed(16#1C7A#, 16), to_signed(16#1CA7#, 16),
to_signed(16#1CD4#, 16), to_signed(16#1D01#, 16), to_signed(16#1D2E#, 16), to_signed(16#1D5A#, 16),
to_signed(16#1D87#, 16), to_signed(16#1DB4#, 16), to_signed(16#1DE0#, 16), to_signed(16#1E0D#, 16),
to_signed(16#1E39#, 16), to_signed(16#1E66#, 16), to_signed(16#1E92#, 16), to_signed(16#1EBE#, 16),
to_signed(16#1EEA#, 16), to_signed(16#1F16#, 16), to_signed(16#1F42#, 16), to_signed(16#1F6E#, 16),
to_signed(16#1F9A#, 16), to_signed(16#1FC6#, 16), to_signed(16#1FF1#, 16), to_signed(16#201D#, 16),
to_signed(16#2049#, 16), to_signed(16#2074#, 16), to_signed(16#209F#, 16), to_signed(16#20CB#, 16),
to_signed(16#20F6#, 16), to_signed(16#2121#, 16), to_signed(16#214C#, 16), to_signed(16#2177#, 16),
to_signed(16#21A2#, 16), to_signed(16#21CD#, 16), to_signed(16#21F7#, 16), to_signed(16#2222#, 16),
to_signed(16#224D#, 16), to_signed(16#2277#, 16), to_signed(16#22A2#, 16), to_signed(16#22CC#, 16),
to_signed(16#22F6#, 16), to_signed(16#2320#, 16), to_signed(16#234A#, 16), to_signed(16#2374#, 16),
to_signed(16#239E#, 16), to_signed(16#23C8#, 16), to_signed(16#23F2#, 16), to_signed(16#241B#, 16),
to_signed(16#2445#, 16), to_signed(16#246E#, 16), to_signed(16#2498#, 16), to_signed(16#24C1#, 16),
to_signed(16#24EA#, 16), to_signed(16#2513#, 16), to_signed(16#253C#, 16), to_signed(16#2565#, 16),
to_signed(16#258E#, 16), to_signed(16#25B7#, 16), to_signed(16#25DF#, 16), to_signed(16#2608#, 16),
to_signed(16#2630#, 16), to_signed(16#2659#, 16), to_signed(16#2681#, 16), to_signed(16#26A9#, 16),
to_signed(16#26D1#, 16), to_signed(16#26F9#, 16), to_signed(16#2721#, 16), to_signed(16#2749#, 16),
to_signed(16#2771#, 16), to_signed(16#2798#, 16), to_signed(16#27C0#, 16), to_signed(16#27E7#, 16),
to_signed(16#280F#, 16), to_signed(16#2836#, 16), to_signed(16#285D#, 16), to_signed(16#2884#, 16),
to_signed(16#28AB#, 16), to_signed(16#28D2#, 16), to_signed(16#28F9#, 16), to_signed(16#291F#, 16),
to_signed(16#2946#, 16), to_signed(16#296C#, 16), to_signed(16#2992#, 16), to_signed(16#29B9#, 16),
to_signed(16#29DF#, 16), to_signed(16#2A05#, 16), to_signed(16#2A2B#, 16), to_signed(16#2A51#, 16),
to_signed(16#2A76#, 16), to_signed(16#2A9C#, 16), to_signed(16#2AC2#, 16), to_signed(16#2AE7#, 16),
to_signed(16#2B0C#, 16), to_signed(16#2B32#, 16), to_signed(16#2B57#, 16), to_signed(16#2B7C#, 16),
to_signed(16#2BA1#, 16), to_signed(16#2BC5#, 16), to_signed(16#2BEA#, 16), to_signed(16#2C0F#, 16),
to_signed(16#2C33#, 16), to_signed(16#2C57#, 16), to_signed(16#2C7C#, 16), to_signed(16#2CA0#, 16),
to_signed(16#2CC4#, 16), to_signed(16#2CE8#, 16), to_signed(16#2D0C#, 16), to_signed(16#2D2F#, 16),
to_signed(16#2D53#, 16), to_signed(16#2D77#, 16), to_signed(16#2D9A#, 16), to_signed(16#2DBD#, 16),
to_signed(16#2DE0#, 16), to_signed(16#2E03#, 16), to_signed(16#2E26#, 16), to_signed(16#2E49#, 16),
to_signed(16#2E6C#, 16), to_signed(16#2E8F#, 16), to_signed(16#2EB1#, 16), to_signed(16#2ED3#, 16),
to_signed(16#2EF6#, 16), to_signed(16#2F18#, 16), to_signed(16#2F3A#, 16), to_signed(16#2F5C#, 16),
to_signed(16#2F7E#, 16), to_signed(16#2F9F#, 16), to_signed(16#2FC1#, 16), to_signed(16#2FE2#, 16),
to_signed(16#3004#, 16), to_signed(16#3025#, 16), to_signed(16#3046#, 16), to_signed(16#3067#, 16),
to_signed(16#3088#, 16), to_signed(16#30A9#, 16), to_signed(16#30CA#, 16), to_signed(16#30EA#, 16),
to_signed(16#310A#, 16), to_signed(16#312B#, 16), to_signed(16#314B#, 16), to_signed(16#316B#, 16),
to_signed(16#318B#, 16), to_signed(16#31AB#, 16), to_signed(16#31CA#, 16), to_signed(16#31EA#, 16),
to_signed(16#320A#, 16), to_signed(16#3229#, 16), to_signed(16#3248#, 16), to_signed(16#3267#, 16),
to_signed(16#3286#, 16), to_signed(16#32A5#, 16), to_signed(16#32C4#, 16), to_signed(16#32E2#, 16),
to_signed(16#3301#, 16), to_signed(16#331F#, 16), to_signed(16#333D#, 16), to_signed(16#335C#, 16),
to_signed(16#337A#, 16), to_signed(16#3397#, 16), to_signed(16#33B5#, 16), to_signed(16#33D3#, 16),
to_signed(16#33F0#, 16), to_signed(16#340E#, 16), to_signed(16#342B#, 16), to_signed(16#3448#, 16),
to_signed(16#3465#, 16), to_signed(16#3482#, 16), to_signed(16#349F#, 16), to_signed(16#34BB#, 16),
to_signed(16#34D8#, 16), to_signed(16#34F4#, 16), to_signed(16#3510#, 16), to_signed(16#352C#, 16),
to_signed(16#3548#, 16), to_signed(16#3564#, 16), to_signed(16#3580#, 16), to_signed(16#359B#, 16),
to_signed(16#35B7#, 16), to_signed(16#35D2#, 16), to_signed(16#35ED#, 16), to_signed(16#3608#, 16),
to_signed(16#3623#, 16), to_signed(16#363E#, 16), to_signed(16#3659#, 16), to_signed(16#3673#, 16),
to_signed(16#368E#, 16), to_signed(16#36A8#, 16), to_signed(16#36C2#, 16), to_signed(16#36DC#, 16),
to_signed(16#36F6#, 16), to_signed(16#3710#, 16), to_signed(16#3729#, 16), to_signed(16#3743#, 16),
to_signed(16#375C#, 16), to_signed(16#3775#, 16), to_signed(16#378E#, 16), to_signed(16#37A7#, 16),
to_signed(16#37C0#, 16), to_signed(16#37D9#, 16), to_signed(16#37F1#, 16), to_signed(16#380A#, 16),
to_signed(16#3822#, 16), to_signed(16#383A#, 16), to_signed(16#3852#, 16), to_signed(16#386A#, 16),
to_signed(16#3882#, 16), to_signed(16#3899#, 16), to_signed(16#38B1#, 16), to_signed(16#38C8#, 16),
to_signed(16#38DF#, 16), to_signed(16#38F6#, 16), to_signed(16#390D#, 16), to_signed(16#3924#, 16),
to_signed(16#393A#, 16), to_signed(16#3951#, 16), to_signed(16#3967#, 16), to_signed(16#397D#, 16),
to_signed(16#3994#, 16), to_signed(16#39A9#, 16), to_signed(16#39BF#, 16), to_signed(16#39D5#, 16),
to_signed(16#39EA#, 16), to_signed(16#3A00#, 16), to_signed(16#3A15#, 16), to_signed(16#3A2A#, 16),
to_signed(16#3A3F#, 16), to_signed(16#3A54#, 16), to_signed(16#3A68#, 16), to_signed(16#3A7D#, 16),
to_signed(16#3A91#, 16), to_signed(16#3AA6#, 16), to_signed(16#3ABA#, 16), to_signed(16#3ACE#, 16),
to_signed(16#3AE1#, 16), to_signed(16#3AF5#, 16), to_signed(16#3B09#, 16), to_signed(16#3B1C#, 16),
to_signed(16#3B2F#, 16), to_signed(16#3B42#, 16), to_signed(16#3B55#, 16), to_signed(16#3B68#, 16),
to_signed(16#3B7B#, 16), to_signed(16#3B8D#, 16), to_signed(16#3BA0#, 16), to_signed(16#3BB2#, 16),
to_signed(16#3BC4#, 16), to_signed(16#3BD6#, 16), to_signed(16#3BE8#, 16), to_signed(16#3BF9#, 16),
to_signed(16#3C0B#, 16), to_signed(16#3C1C#, 16), to_signed(16#3C2D#, 16), to_signed(16#3C3F#, 16),
to_signed(16#3C4F#, 16), to_signed(16#3C60#, 16), to_signed(16#3C71#, 16), to_signed(16#3C81#, 16),
to_signed(16#3C92#, 16), to_signed(16#3CA2#, 16), to_signed(16#3CB2#, 16), to_signed(16#3CC2#, 16),
to_signed(16#3CD2#, 16), to_signed(16#3CE1#, 16), to_signed(16#3CF1#, 16), to_signed(16#3D00#, 16),
to_signed(16#3D0F#, 16), to_signed(16#3D1E#, 16), to_signed(16#3D2D#, 16), to_signed(16#3D3C#, 16),
to_signed(16#3D4A#, 16), to_signed(16#3D59#, 16), to_signed(16#3D67#, 16), to_signed(16#3D75#, 16),
to_signed(16#3D83#, 16), to_signed(16#3D91#, 16), to_signed(16#3D9F#, 16), to_signed(16#3DAC#, 16),
to_signed(16#3DBA#, 16), to_signed(16#3DC7#, 16), to_signed(16#3DD4#, 16), to_signed(16#3DE1#, 16),
to_signed(16#3DEE#, 16), to_signed(16#3DFA#, 16), to_signed(16#3E07#, 16), to_signed(16#3E13#, 16),
to_signed(16#3E1F#, 16), to_signed(16#3E2B#, 16), to_signed(16#3E37#, 16), to_signed(16#3E43#, 16),
to_signed(16#3E4F#, 16), to_signed(16#3E5A#, 16), to_signed(16#3E65#, 16), to_signed(16#3E70#, 16),
to_signed(16#3E7B#, 16), to_signed(16#3E86#, 16), to_signed(16#3E91#, 16), to_signed(16#3E9B#, 16),
to_signed(16#3EA6#, 16), to_signed(16#3EB0#, 16), to_signed(16#3EBA#, 16), to_signed(16#3EC4#, 16),
to_signed(16#3ECE#, 16), to_signed(16#3ED7#, 16), to_signed(16#3EE1#, 16), to_signed(16#3EEA#, 16),
to_signed(16#3EF3#, 16), to_signed(16#3EFC#, 16), to_signed(16#3F05#, 16), to_signed(16#3F0E#, 16),
to_signed(16#3F16#, 16), to_signed(16#3F1F#, 16), to_signed(16#3F27#, 16), to_signed(16#3F2F#, 16),
to_signed(16#3F37#, 16), to_signed(16#3F3F#, 16), to_signed(16#3F46#, 16), to_signed(16#3F4E#, 16),
to_signed(16#3F55#, 16), to_signed(16#3F5C#, 16), to_signed(16#3F63#, 16), to_signed(16#3F6A#, 16),
to_signed(16#3F71#, 16), to_signed(16#3F78#, 16), to_signed(16#3F7E#, 16), to_signed(16#3F84#, 16),
to_signed(16#3F8A#, 16), to_signed(16#3F90#, 16), to_signed(16#3F96#, 16), to_signed(16#3F9C#, 16),
to_signed(16#3FA1#, 16), to_signed(16#3FA7#, 16), to_signed(16#3FAC#, 16), to_signed(16#3FB1#, 16),
to_signed(16#3FB6#, 16), to_signed(16#3FBA#, 16), to_signed(16#3FBF#, 16), to_signed(16#3FC3#, 16),
to_signed(16#3FC8#, 16), to_signed(16#3FCC#, 16), to_signed(16#3FD0#, 16), to_signed(16#3FD3#, 16),
to_signed(16#3FD7#, 16), to_signed(16#3FDB#, 16), to_signed(16#3FDE#, 16), to_signed(16#3FE1#, 16),
to_signed(16#3FE4#, 16), to_signed(16#3FE7#, 16), to_signed(16#3FEA#, 16), to_signed(16#3FEC#, 16),
to_signed(16#3FEF#, 16), to_signed(16#3FF1#, 16), to_signed(16#3FF3#, 16), to_signed(16#3FF5#, 16),
to_signed(16#3FF7#, 16), to_signed(16#3FF8#, 16), to_signed(16#3FFA#, 16), to_signed(16#3FFB#, 16),
to_signed(16#3FFC#, 16), to_signed(16#3FFD#, 16), to_signed(16#3FFE#, 16), to_signed(16#3FFF#, 16),
to_signed(16#3FFF#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16)); -- sfix16 [512]
-- Signals
SIGNAL In1_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL insig_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL Point25_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_relop1 : std_logic;
SIGNAL Point75_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL GTEp75_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL GTEp75_relop1 : std_logic;
SIGNAL alpha1st_or_4th_Quad_bool : std_logic;
SIGNAL alpha1st_or_4th_Quad_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL pow2switch_out1 : std_logic;
SIGNAL Point50_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL p75mA_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p75mA_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p75mA_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL LTEp50_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_relop1 : std_logic;
SIGNAL QuadHandle1b_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1b_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle1a_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1a_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle2_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL CastU16En1_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL CastU16En3_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL x4_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL CastU16En2_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Switch_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_k : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Negate_cast : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_cast_1 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Cosine : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- (C) 2016 Mathworks, Inc
In1_signed <= signed(In1);
insig_out1 <= unsigned(In1_signed(13 DOWNTO 5));
Point25_out1 <= to_unsigned(16#4000#, 16);
LTEp25_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp25_relop1 <= '1' WHEN LTEp25_1_cast <= Point25_out1 ELSE
'0';
Point75_out1 <= to_unsigned(16#C000#, 16);
GTEp75_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
GTEp75_relop1 <= '1' WHEN GTEp75_1_cast >= Point75_out1 ELSE
'0';
alpha1st_or_4th_Quad_bool <= LTEp25_relop1 OR GTEp75_relop1;
alpha1st_or_4th_Quad_out1 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & alpha1st_or_4th_Quad_bool;
pow2switch_out1 <= '0';
Point50_out1 <= to_unsigned(16#8000#, 16);
p75mA_sub_cast <= signed(resize(Point75_out1, 17));
p75mA_sub_cast_1 <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
p75mA_out1 <= p75mA_sub_cast - p75mA_sub_cast_1;
Amp75_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp75_sub_cast_1 <= signed(resize(Point75_out1, 17));
Amp75_out1 <= Amp75_sub_cast - Amp75_sub_cast_1;
Amp25_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp25_sub_cast_1 <= signed(resize(Point25_out1, 17));
Amp25_out1 <= Amp25_sub_cast - Amp25_sub_cast_1;
p25mA_sub_cast <= signed(resize(Point25_out1, 17));
p25mA_sub_cast_1 <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
p25mA_out1 <= p25mA_sub_cast - p25mA_sub_cast_1;
LTEp50_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp50_relop1 <= '1' WHEN LTEp50_1_cast <= Point50_out1 ELSE
'0';
QuadHandle1b_out1 <= p75mA_out1 WHEN GTEp75_relop1 = '0' ELSE
Amp75_out1;
QuadHandle1b_out1_dtc <= "111111111" WHEN (QuadHandle1b_out1(16) = '0') AND (QuadHandle1b_out1(15 DOWNTO 7) = "111111111") ELSE
"000000000" WHEN QuadHandle1b_out1(16) = '1' ELSE
unsigned(QuadHandle1b_out1(15 DOWNTO 7));
QuadHandle1a_out1 <= Amp25_out1 WHEN LTEp25_relop1 = '0' ELSE
p25mA_out1;
QuadHandle1a_out1_dtc <= "111111111" WHEN (QuadHandle1a_out1(16) = '0') AND (QuadHandle1a_out1(15 DOWNTO 7) = "111111111") ELSE
"000000000" WHEN QuadHandle1a_out1(16) = '1' ELSE
unsigned(QuadHandle1a_out1(15 DOWNTO 7));
QuadHandle2_out1 <= QuadHandle1b_out1_dtc WHEN LTEp50_relop1 = '0' ELSE
QuadHandle1a_out1_dtc;
CastU16En1_out1 <= QuadHandle2_out1;
CastU16En3_out1 <= resize(CastU16En1_out1, 10);
-- equivalent to multiply
-- by 4 with saturation
x4_out1 <= CastU16En3_out1 sll 2;
-- saturation block maybe optimized away
-- if the NumDataPoints is a power of 2
CastU16En2_out1 <= "111111111" WHEN x4_out1(9) /= '0' ELSE
x4_out1(8 DOWNTO 0);
Switch_out1 <= CastU16En2_out1 WHEN pow2switch_out1 = '0' ELSE
CastU16En2_out1;
Look_Up_Table_k <= to_unsigned(16#000#, 9) WHEN Switch_out1 = to_unsigned(16#000#, 9) ELSE
to_unsigned(16#1FF#, 9) WHEN Switch_out1 = to_unsigned(16#1FF#, 9) ELSE
Switch_out1;
Look_Up_Table_out1 <= nc(to_integer(Look_Up_Table_k));
Negate_cast <= resize(Look_Up_Table_out1, 17);
Negate_cast_1 <= - (Negate_cast);
Negate_out1 <= Negate_cast_1(15 DOWNTO 0);
Cosine <= Negate_out1 WHEN alpha1st_or_4th_Quad_out1 = to_unsigned(16#00#, 8) ELSE
Look_Up_Table_out1;
x <= std_logic_vector(Cosine);
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end test;
architecture a of test is
signal bt_addr : unsigned(6 downto 0) := "1010101";
alias dw_addr : unsigned(4 downto 0) is bt_addr(6 downto 2 ) ;
signal s64 : std_logic_vector(63 downto 0) := (others => '0');
alias a32 : std_logic_vector(31 downto 0) is s64(31 downto 0);
begin
s64 <= X"fedcba9876543210";
dw_addr <= "00000", "01010" after 1 ns, "11111" after 2 ns;
process(a32, bt_addr) is
begin
report "A32 = " & integer'image(to_integer(unsigned(a32))) severity note;
report "bt_addr = " & integer'image(to_integer(bt_addr)) severity note;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end test;
architecture a of test is
signal bt_addr : unsigned(6 downto 0) := "1010101";
alias dw_addr : unsigned(4 downto 0) is bt_addr(6 downto 2 ) ;
signal s64 : std_logic_vector(63 downto 0) := (others => '0');
alias a32 : std_logic_vector(31 downto 0) is s64(31 downto 0);
begin
s64 <= X"fedcba9876543210";
dw_addr <= "00000", "01010" after 1 ns, "11111" after 2 ns;
process(a32, bt_addr) is
begin
report "A32 = " & integer'image(to_integer(unsigned(a32))) severity note;
report "bt_addr = " & integer'image(to_integer(bt_addr)) severity note;
end process;
end a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end test;
architecture a of test is
signal bt_addr : unsigned(6 downto 0) := "1010101";
alias dw_addr : unsigned(4 downto 0) is bt_addr(6 downto 2 ) ;
signal s64 : std_logic_vector(63 downto 0) := (others => '0');
alias a32 : std_logic_vector(31 downto 0) is s64(31 downto 0);
begin
s64 <= X"fedcba9876543210";
dw_addr <= "00000", "01010" after 1 ns, "11111" after 2 ns;
process(a32, bt_addr) is
begin
report "A32 = " & integer'image(to_integer(unsigned(a32))) severity note;
report "bt_addr = " & integer'image(to_integer(bt_addr)) severity note;
end process;
end a;
|
-- $Id: tb_artys7_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_artys7_dram - sim
-- Description: Test bench for artys7 (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_artys7_core
-- serport/tb/serport_master_tb
-- artys7_dram_aif [UUT]
--
-- To test: generic, any artys7_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (derived from tb_artya7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artys7lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_artys7_dram is
end tb_artys7_dram;
architecture sim of tb_artys7_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal IO_DDR3_DQ : slv16 := (others=>'Z');
signal IO_DDR3_DQS_P : slv2 := (others=>'Z');
signal IO_DDR3_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYS7CORE : entity work.tb_artys7_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : artys7_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
DDR3_DQ => IO_DDR3_DQ,
DDR3_DQS_P => IO_DDR3_DQS_P,
DDR3_DQS_N => IO_DDR3_DQS_N,
DDR3_ADDR => open,
DDR3_BA => open,
DDR3_RAS_N => open,
DDR3_CAS_N => open,
DDR3_WE_N => open,
DDR3_RESET_N => open,
DDR3_CK_P => open,
DDR3_CK_N => open,
DDR3_CKE => open,
DDR3_CS_N => open,
DDR3_DM => open,
DDR3_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most artys7 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delayline is
generic (
length : integer
);
port ( clk_i : in std_logic;
rst_i : in std_logic;
async_i : in std_logic;
line_o : out std_logic_vector(length-1 downto 0);
signal_o : out std_logic
);
end entity;
architecture rtl of delayline is
signal delay_line : std_logic_vector(length downto 0);
signal line_buffer_snap : std_logic_vector(length downto 0);
signal line_buffer : std_logic_vector(length downto 0);
signal edge_buffer : std_logic_vector(length-1 downto 0);
attribute KEEP : string;
attribute KEEP of delay_line : signal is "true";
begin
process(clk_i) is
begin
if rising_edge(clk_i) then
line_buffer_snap <= delay_line;
for i in edge_buffer'range loop
edge_buffer(i) <= (not line_buffer_snap(i+1) xor line_buffer_snap(i));
end loop;
line_buffer <= line_buffer_snap;
if unsigned(edge_buffer) /= 0 then
line_o <= line_buffer(length downto 1);
signal_o <= '1';
else
line_o <= (others => '0');
signal_o <= '0';
end if;
end if;
end process;
process (delay_line, async_i)
begin
for i in delay_line'range loop
if i = delay_line'left then
delay_line(i) <= async_i;
else
delay_line(i) <= not delay_line(i+1) after 330 ps;
end if;
end loop;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
entity foo is
port(a, b: out bit);
end entity foo;
architecture bug of foo is
begin
a <= '0', '1' after 1 ns, '0' after 2 ns, '1' after 3 ns;
process(a)
begin
b <= not a;
end process;
end architecture bug;
|
entity foo is
port(a, b: out bit);
end entity foo;
architecture bug of foo is
begin
a <= '0', '1' after 1 ns, '0' after 2 ns, '1' after 3 ns;
process(a)
begin
b <= not a;
end process;
end architecture bug;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output -pi/2 to pi/2
ENTITY fp_asin IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_asin;
ARCHITECTURE rtl OF fp_asin IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type asin_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (45 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (50 DOWNTO 1);
signal asin_sumff : asin_sumfftype;
signal asin_shift, asin_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal asin_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal asin_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentadjustnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
piovertwo <= x"6487ED511";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
asin_sum <= piovertwo - acos_fixedpoint;
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>51)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentinff <= "00000000";
FOR k IN 1 TO 50 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff <= exponentin;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 50 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 45 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
asin_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
asin_sumff(1)(k) <= '0';
asin_sumff(2)(k) <= '0';
asin_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 45 LOOP
signff(k) <= signff(k-1);
END LOOP;
asin_sumff(1)(36 DOWNTO 1) <= asin_sum; -- level 50
asin_sumff(2)(36 DOWNTO 1) <= asin_sumff(1)(36 DOWNTO 1); -- level 51
asin_shiftff <= asin_shift; -- level 51
FOR k IN 1 TO 12 LOOP
asin_mantissaff(k) <= asin_mantissabus(k) AND NOT(small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 23 LOOP
asin_mantissaff(k+12) <= (asin_mantissabus(k+12) AND NOT(small_inputff(50))) OR
(small_mantissa(k) AND small_inputff(50));
END LOOP;
asin_mantissaff(36) <= asin_mantissabus (36);
-- check for overflow not needed?
mantissaoutff <= asin_mantissaff(35 DOWNTO 13) + asin_mantissaff(12); -- level 52
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= (exponentadjustnode(k) AND NOT(small_inputff(50))) OR
(small_exponent(k) AND small_inputff(50)); -- level 52
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
exponentadjustnode <= 128 - ("00" & asin_shiftff);
czo: fp_clz36
PORT MAP (mantissa=>asin_sumff(1)(36 DOWNTO 1),
leading=>asin_shift);
clso: fp_lsft36
PORT MAP (inbus=>asin_sumff(2)(36 DOWNTO 1),
shift=>asin_shiftff,
outbus=>asin_mantissabus);
--*** OUTPUTS ***
signout <= signff(45);
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: side_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY side_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END side_exdes;
ARCHITECTURE xilinx OF side_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT side IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : side
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
q : out std_logic
);
end;
architecture a of ent is
signal s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
s <= '0';
elsif enable /= '1' then
-- [nothing]
elsif rising_edge(clk) then
s <= not s;
end if;
end process;
q <= s;
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_fYi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_fYi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000111",
4 => "00001001", 5 => "00001011", 6 => "00001101", 7 => "00001111",
8 => "00010001", 9 => "00010011", 10 => "00010110", 11 => "00011000",
12 => "00011010", 13 => "00011100", 14 => "00011110", 15 => "00100000",
16 => "00100010", 17 => "00100100", 18 => "00100110", 19 => "00101000",
20 => "00101010", 21 => "00101100", 22 => "00101110", 23 => "00110000",
24 => "00110010", 25 => "00110100", 26 => "00110110", 27 => "00111000",
28 => "00111010", 29 => "00111100", 30 => "00111110", 31 => "01000000",
32 => "01000010", 33 => "01000011", 34 => "01000101", 35 => "01000111",
36 => "01001001", 37 => "01001011", 38 => "01001101", 39 => "01001111",
40 => "01010000", 41 => "01010010", 42 => "01010100", 43 => "01010110",
44 => "01011000", 45 => "01011001", 46 => "01011011", 47 => "01011101",
48 => "01011111", 49 => "01100001", 50 => "01100010", 51 => "01100100",
52 => "01100110", 53 => "01100111", 54 => "01101001", 55 => "01101011",
56 => "01101100", 57 => "01101110", 58 => "01110000", 59 => "01110001",
60 => "01110011", 61 => "01110101", 62 => "01110110", 63 => "01111000",
64 => "01111010", 65 => "01111011", 66 => "01111101", 67 => "01111110",
68 => "10000000", 69 => "10000001", 70 => "10000011", 71 => "10000100",
72 => "10000110", 73 => "10001000", 74 => "10001001", 75 => "10001011",
76 => "10001100", 77 => "10001101", 78 => "10001111", 79 => "10010000",
80 => "10010010", 81 => "10010011", 82 => "10010101", 83 => "10010110",
84 => "10011000", 85 => "10011001", 86 => "10011010", 87 => "10011100",
88 => "10011101", 89 => "10011111", 90 => "10100000", 91 => "10100001",
92 => "10100011", 93 => "10100100", 94 => "10100101", 95 => "10100111",
96 => "10101000", 97 => "10101001", 98 => "10101010", 99 => "10101100",
100 => "10101101", 101 => "10101110", 102 => "10101111", 103 => "10110001",
104 => "10110010", 105 => "10110011", 106 => "10110100", 107 => "10110110",
108 => "10110111", 109 => "10111000", 110 => "10111001", 111 => "10111010",
112 => "10111011", 113 => "10111101", 114 => "10111110", 115 => "10111111",
116 => "11000000", 117 => "11000001", 118 => "11000010", 119 => "11000011",
120 => "11000100", 121 => "11000101", 122 => "11000110", 123 => "11000111",
124 => "11001000", 125 => "11001001", 126 => "11001010", 127 => "11001011",
128 => "11001100", 129 => "11001101", 130 => "11001110", 131 => "11001111",
132 => "11010000", 133 => "11010001", 134 => "11010010", 135 => "11010011",
136 => "11010100", 137 => "11010101", 138 => "11010110", 139 => "11010111",
140 => "11011000", 141 => "11011001", 142 to 143=> "11011010", 144 => "11011011",
145 => "11011100", 146 => "11011101", 147 => "11011110", 148 to 149=> "11011111",
150 => "11100000", 151 => "11100001", 152 to 153=> "11100010", 154 => "11100011",
155 => "11100100", 156 to 157=> "11100101", 158 => "11100110", 159 => "11100111",
160 to 161=> "11101000", 162 => "11101001", 163 to 164=> "11101010", 165 => "11101011",
166 to 167=> "11101100", 168 to 169=> "11101101", 170 => "11101110", 171 to 172=> "11101111",
173 to 174=> "11110000", 175 to 176=> "11110001", 177 to 178=> "11110010", 179 => "11110011",
180 to 181=> "11110100", 182 to 184=> "11110101", 185 to 186=> "11110110", 187 to 188=> "11110111",
189 to 190=> "11111000", 191 to 193=> "11111001", 194 to 196=> "11111010", 197 to 199=> "11111011",
200 to 202=> "11111100", 203 to 205=> "11111101", 206 to 210=> "11111110", 211 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_fYi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_fYi is
component Loop_loop_height_fYi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_fYi_rom_U : component Loop_loop_height_fYi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Move_FIFO_4KB_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Move_FIFO_4KB_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end Move_FIFO_4KB_top;
architecture xilinx of Move_FIFO_4KB_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component Move_FIFO_4KB is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : Move_FIFO_4KB PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor : in std_logic;
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled and c2n_motor;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif enabled='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if diff > 2040 then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Types.all;
use ieee.std_logic_unsigned.all;
entity clk1Hz is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end;
architecture Behavioral of clk1Hz is
signal temporal: STD_LOGIC;
constant HalfPeriod : positive := 25000000;
signal counter : word(bits(HalfPeriod)-1 downto 0);
begin
freq_divider: process (reset, clk) begin
if (reset = '0') then
temporal <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if (counter = HalfPeriod) then
temporal <= not temporal;
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; |
--------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description:
-- Copy input data to output.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
entity proc_memcpy is
port (
clk : in std_logic;
en : in std_logic;
idata : in std_logic_vector(0 to 511);
ivalid : in std_logic;
idone : in std_logic;
iready : out std_logic;
odata : out std_logic_vector(0 to 511);
ovalid : out std_logic;
odirty : out std_logic;
oready : in std_logic;
odone : out std_logic;
len : in unsigned(0 to 31)
);
end entity proc_memcpy;
architecture main of proc_memcpy is
signal fifo_rst : std_logic;
signal fifo_write : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
begin
fifo_rst <= not en;
fifo_write <= ivalid and not fifo_full;
iready <= not fifo_full;
odirty <= '0';
FIFO: entity capi.sync_fifo_fwft
generic map (
WRITE_SLACK => 2,
DATA_BITS => idata'length,
ADDR_BITS => 3)
port map (
clk => clk,
rst => fifo_rst,
write => fifo_write,
write_data => idata,
full => fifo_full,
read => oready,
read_valid => ovalid,
read_data => odata,
empty => fifo_empty);
DONE_P: process (clk) is
begin
if rising_edge(clk) then
odone <= fifo_empty and not ivalid and en and idone;
end if;
end process DONE_P;
end architecture main;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: testmem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY testmem_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE testmem_synth_ARCH OF testmem_synth IS
COMPONENT testmem_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: testmem_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity RECEIVER is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
SCAN_CODE : out std_logic_vector ( 7 downto 0 );
NEW_SC : out std_logic
);
end RECEIVER;
architecture RECEIVER_BODY of RECEIVER is
type T_STATE is ( W_START, R_START, W_0, R_0, W_1, R_1, W_2, R_2, W_3, R_3, W_4, R_4, W_5, R_5, W_6, R_6, W_7, R_7, W_PAR, R_PAR, W_END, R_END, VALID );
signal STATE, NEXT_STATE : T_STATE;
signal PAR, PS2_PAR, PS2_END : std_logic;
signal SC : std_logic_vector ( 7 downto 0 );
signal SC_LOAD : std_logic;
signal SC_RESET : std_logic;
signal PAR_LOAD : std_logic;
signal END_LOAD : std_logic;
signal SC_OUT : std_logic;
begin
SCPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
SC <= "00000000";
elsif SC_LOAD = '1' then
SC <= PS2_DATA & SC ( 7 downto 1 ) ;
end if;
end if;
end process;
PARPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' or SC_RESET = '1' then
PAR <= '1';
elsif SC_LOAD = '1' then
if PS2_DATA = '1' then
PAR <= not PAR;
else
PAR <= PAR;
end if;
end if;
end if;
end process;
PS2_PARPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' or SC_RESET = '1' then
PS2_PAR <= '0';
elsif PAR_LOAD = '1' then
PS2_PAR <= PS2_DATA;
else
PS2_PAR <= PS2_PAR;
end if;
end if;
end process;
ENDPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' or SC_RESET = '1' then
PS2_END <= '0';
elsif END_LOAD = '1' then
PS2_END <= PS2_DATA;
else
PS2_END <= PS2_END;
end if;
end if;
end process;
SC_OUT_PR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
SCAN_CODE <= "00000000";
elsif SC_OUT = '1' then
SCAN_CODE <= SC;
end if;
end if;
end process;
TRANP : process ( STATE, PS2_DATA, PS2_CLK, PAR, PS2_PAR, PS2_END )
begin
case STATE is
when W_START => if PS2_CLK = '1' then
NEXT_STATE <= W_START;
else
NEXT_STATE <= R_START;
end if;
when R_START => if PS2_CLK = '0' then
NEXT_STATE <= R_START;
else
NEXT_STATE <= W_0;
end if;
when W_0 => if PS2_CLK = '1' then
NEXT_STATE <= W_0;
else
NEXT_STATE <= R_0;
end if;
when R_0 => if PS2_CLK = '0' then
NEXT_STATE <= R_0;
else
NEXT_STATE <= W_1;
end if;
when W_1 => if PS2_CLK = '1' then
NEXT_STATE <= W_1;
else
NEXT_STATE <= R_1;
end if;
when R_1 => if PS2_CLK = '0' then
NEXT_STATE <= R_1;
else
NEXT_STATE <= W_2;
end if;
when W_2 => if PS2_CLK = '1' then
NEXT_STATE <= W_2;
else
NEXT_STATE <= R_2;
end if;
when R_2 => if PS2_CLK = '0' then
NEXT_STATE <= R_2;
else
NEXT_STATE <= W_3;
end if;
when W_3 => if PS2_CLK = '1' then
NEXT_STATE <= W_3;
else
NEXT_STATE <= R_3;
end if;
when R_3 => if PS2_CLK = '0' then
NEXT_STATE <= R_3;
else
NEXT_STATE <= W_4;
end if;
when W_4 => if PS2_CLK = '1' then
NEXT_STATE <= W_4;
else
NEXT_STATE <= R_4;
end if;
when R_4 => if PS2_CLK = '0' then
NEXT_STATE <= R_4;
else
NEXT_STATE <= W_5;
end if;
when W_5 => if PS2_CLK = '1' then
NEXT_STATE <= W_5;
else
NEXT_STATE <= R_5;
end if;
when R_5 => if PS2_CLK = '0' then
NEXT_STATE <= R_5;
else
NEXT_STATE <= W_6;
end if;
when W_6 => if PS2_CLK = '1' then
NEXT_STATE <= W_6;
else
NEXT_STATE <= R_6;
end if;
when R_6 => if PS2_CLK = '0' then
NEXT_STATE <= R_6;
else
NEXT_STATE <= W_7;
end if;
when W_7 => if PS2_CLK = '1' then
NEXT_STATE <= W_7;
else
NEXT_STATE <= R_7;
end if;
when R_7 => if PS2_CLK = '0' then
NEXT_STATE <= R_7;
else
NEXT_STATE <= W_PAR;
end if;
when W_PAR => if PS2_CLK = '1' then
NEXT_STATE <= W_PAR;
else
NEXT_STATE <= R_PAR;
end if;
when R_PAR => if PS2_CLK = '0' then
NEXT_STATE <= R_PAR;
else
NEXT_STATE <= W_END;
end if;
when W_END => if PS2_CLK = '1' then
NEXT_STATE <= W_END;
else
NEXT_STATE <= R_END;
end if;
when R_END => if PS2_CLK = '0' then
NEXT_STATE <= R_END;
else
if PAR = PS2_PAR and PS2_END = '1' then
NEXT_STATE <= VALID;
else
NEXT_STATE <= W_START;
end if;
end if;
when VALID => NEXT_STATE <= W_START;
end case;
end process;
STATEP : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
STATE <= W_START;
else
STATE <= NEXT_STATE;
end if;
end if;
end process;
OUTP : process ( STATE, PS2_DATA, PS2_CLK, PAR, PS2_PAR, PS2_END, SC )
begin
case STATE is
when W_START => NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when R_START => NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '1';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when W_0 | W_1 | W_2 | W_3 | W_4 | W_5 | W_6 | W_7 => if PS2_CLK = '0' then
SC_LOAD <= '1';
else
SC_LOAD <= '0';
end if;
NEW_SC <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when W_PAR => if PS2_CLK = '0' then
PAR_LOAD <= '1';
else
PAR_LOAD <= '0';
end if;
NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when W_END => if PS2_CLK = '0' then
END_LOAD <= '1';
else
END_LOAD <= '0';
end if;
NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
SC_OUT <= '0';
when R_END => if PS2_CLK = '1' and PAR = PS2_PAR and PS2_END = '1' then
SC_OUT <= '1';
else
SC_OUT <= '0';
end if;
NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
when VALID => NEW_SC <= '1';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when others => NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
end case;
end process;
end RECEIVER_BODY;
|
--------------------------------------------------------------------------------
-- Title : WBB to VME Bridge
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : wbb2vme_top.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13/01/12
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The IP-core WBB2VME is used for interfacing the VME bus as master and as
-- slave. It is able to control external driver chips as 74VMEH22501 or 74ABT125.
-- An external SRAM is used for shared memory applications and can be accessed
-- from CPU and VME side.
-- The main functions of the 16z002-01 are:
-- o Wishbone to VME access: VME master D08(EO):D16:D32:D64:A16:A24:A32; BLT;
-- non-privileged program/data; supervisory
-- o VME to Wishbone access: VME slave D08(EO):D16:D32:D64:A16:A24:A32; BLT
-- o VME slave access routing to SRAM or other bus via Wishbone bus (e.g. PCI)
-- o VME Slot1 function with auto-detection
-- o VME Interrupter D08(O):I(7-1):ROAK
-- o VME Interrupt Handler D08(O):IH(7-1)
-- o VME Bus requester
-- o ROR (release on request);
-- o RWD (release-when done);
-- o SGL (single level 3 fair requester)
-- o VME multi-level 0-3 bus arbiter
-- o BTO VME Bus time out
-- o ADO VME Address only cycles
-- o mailbox functionality
-- o VME location monitor A16:A24:A32
-- o DMA controller with scatter gather capabilities (A24; A32; D32; D64;
-- non-privileged; supervisory)
-- o DMA access capabilities VME, SRAM and other bus via Wishbone bus (e.g. PCI)
-- o VME utility functions
-- o access to 1 MByte local SRAM accessible via Wishbone bus
-- o VME Slot geographical addressing
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_ctrl
-- vme_du
-- vme_au
-- vme_locmon
-- vme_mailbox
-- vme_master
-- vme_slave
-- vme_requester
-- vme_bustimer
-- vme_sys_arbiter
-- vme_arbiter
-- vme_wbm
-- vme_wbs
-- vme_dma
-- vme_dma_mstr
-- vme_dma_slv
-- vme_dma_arbiter
-- vme_dma_du
-- vme_dma_au
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.7 $
--
-- $Log: wbb2vme_top.vhd,v $
-- Revision 1.7 2015/09/16 09:19:48 mwawrik
-- Added generics A16_REG_MAPPING and USE_LONGADD
--
-- Revision 1.6 2014/04/17 07:35:18 MMiehling
-- added generic LONGADD_SIZE
-- added status outputs vme_berr and vme_mstr_busy
-- added signal prevent_sysrst
--
-- Revision 1.5 2013/09/12 08:45:19 mmiehling
-- added bit 8 of tga for address modifier extension
--
-- Revision 1.4 2012/11/15 09:43:50 MMiehling
-- connected each interrupt source to interface in order to support edge triggered msi
--
-- Revision 1.3 2012/09/25 11:21:37 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:00 MMiehling
-- changed comments
--
-- Revision 1.1 2012/03/29 10:14:27 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_pkg.all;
ENTITY wbb2vme_top IS
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
dma_irq : OUT std_logic; -- interrupt request dma to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_ctrl_stb_o : OUT std_logic;
wbm_ctrl_ack_i : IN std_logic;
wbm_ctrl_err_i : IN std_logic;
wbm_ctrl_we_o : OUT std_logic;
wbm_ctrl_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_ctrl_cyc_sram : OUT std_logic;
wbm_ctrl_cyc_pci : OUT std_logic;
wbm_ctrl_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbm_dma_stb_o : OUT std_logic;
wbm_dma_ack_i : IN std_logic;
wbm_dma_we_o : OUT std_logic;
wbm_dma_cti : OUT std_logic_vector(2 DOWNTO 0);
wbm_dma_tga_o : OUT std_logic_vector(8 DOWNTO 0);
wbm_dma_err_i : IN std_logic;
wbm_dma_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_dma_cyc_sram : OUT std_logic;
wbm_dma_cyc_vme : OUT std_logic;
wbm_dma_cyc_pci : OUT std_logic;
wbm_dma_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vmebus
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
bclr_i_n : IN std_logic; -- bus clear input
bclr_o_n : OUT std_logic; -- bus clear output
retry_i_n : IN std_logic; -- bus retry input
retry_o_n : OUT std_logic; -- bus retry output
retry_oe_n : OUT std_logic; -- bus retry output enable
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END wbb2vme_top;
ARCHITECTURE wbb2vme_top_arch OF wbb2vme_top IS
COMPONENT vme_ctrl
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : OUT std_logic;
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0);
vme_cyc_sram : OUT std_logic;
vme_cyc_pci : OUT std_logic;
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- the VME signals:
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END COMPONENT;
COMPONENT vme_dma
PORT (
rst : IN std_logic;
clk : IN std_logic;
irq_o : OUT std_logic;
-- vme_du
dma_sta : IN std_logic_vector(9 DOWNTO 0);
clr_dma_en : OUT std_logic;
set_dma_err : OUT std_logic;
dma_act_bd : OUT std_logic_vector(7 DOWNTO 4);
-- wb-slave
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
sel_i : IN std_logic_vector(3 DOWNTO 0);
adr_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
-- wb-master
stb_o : OUT std_logic;
ack_i : IN std_logic;
we_o : OUT std_logic;
cti : OUT std_logic_vector(2 DOWNTO 0);
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
err_i : IN std_logic;
cyc_o_sram : OUT std_logic;
cyc_o_vme : OUT std_logic;
cyc_o_pci : OUT std_logic;
sel_o : OUT std_logic_vector(3 DOWNTO 0);
adr_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL dma_sta : std_logic_vector(9 DOWNTO 0);
SIGNAL clr_dma_en : std_logic;
SIGNAL set_dma_err : std_logic;
SIGNAL dma_act_bd : std_logic_vector(7 DOWNTO 4);
BEGIN
bclr_o_n <= '1';
retry_o_n <= '1';
retry_oe_n <= '1';
vmectrl: vme_ctrl
GENERIC MAP (
A16_REG_MAPPING => A16_REG_MAPPING,
LONGADD_SIZE => LONGADD_SIZE,
USE_LONGADD => USE_LONGADD
)
PORT MAP(
clk => clk ,
rst => rst ,
startup_rst => startup_rst,
postwr => postwr ,
vme_irq => vme_irq ,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
prevent_sysrst => prevent_sysrst,
test_vec => test_vec ,
dma_sta => dma_sta ,
clr_dma_en => clr_dma_en ,
set_dma_err => set_dma_err ,
dma_act_bd => dma_act_bd ,
wbs_stb_i => wbs_stb_i ,
wbs_ack_o => wbs_ack_o ,
wbs_err_o => wbs_err_o ,
wbs_we_i => wbs_we_i ,
wbs_sel_i => wbs_sel_i ,
wbs_cyc_i => wbs_cyc_i ,
wbs_adr_i => wbs_adr_i ,
wbs_dat_o => wbs_dat_o ,
wbs_dat_i => wbs_dat_i ,
wbs_tga_i => wbs_tga_i ,
wbm_stb_o => wbm_ctrl_stb_o ,
wbm_ack_i => wbm_ctrl_ack_i ,
wbm_err_i => wbm_ctrl_err_i ,
wbm_we_o => wbm_ctrl_we_o ,
wbm_sel_o => wbm_ctrl_sel_o ,
vme_cyc_sram => wbm_ctrl_cyc_sram ,
vme_cyc_pci => wbm_ctrl_cyc_pci ,
wbm_adr_o => wbm_ctrl_adr_o ,
wbm_dat_o => wbm_ctrl_dat_o ,
wbm_dat_i => wbm_ctrl_dat_i ,
va => va ,
vd => vd ,
vam => vam ,
writen => writen ,
iackn => iackn ,
irq_i_n => irq_i_n ,
irq_o_n => irq_o_n ,
as_o_n => as_o_n ,
as_oe_n => as_oe_n ,
as_i_n => as_i_n ,
sysresn => sysresn ,
sysresin => sysresin ,
ds_o_n => ds_o_n ,
ds_i_n => ds_i_n ,
ds_oe_n => ds_oe_n ,
berrn => berrn ,
berrin => berrin ,
dtackn => dtackn ,
dtackin => dtackin ,
slot01n => slot01n ,
sysfail_i_n => sysfail_i_n,
sysfail_o_n => sysfail_o_n,
bbsyn => bbsyn ,
bbsyin => bbsyin ,
br_i_n => br_i_n ,
br_o_n => br_o_n ,
iackin => iackin ,
iackoutn => iackoutn ,
acfailn => acfailn ,
bg_i_n => bg_i_n ,
bg_o_n => bg_o_n ,
ga => ga ,
gap => gap,
vme_berr => vme_berr ,
vme_mstr_busy => vme_mstr_busy,
d_dir => d_dir ,
d_oe_n => d_oe_n ,
am_dir => am_dir ,
am_oe_n => am_oe_n ,
a_dir => a_dir ,
a_oe_n => a_oe_n ,
v2p_rst => v2p_rst
);
vmedma: vme_dma
PORT MAP (
rst => rst ,
clk => clk ,
irq_o => dma_irq ,
dma_sta => dma_sta ,
clr_dma_en => clr_dma_en ,
set_dma_err => set_dma_err,
dma_act_bd => dma_act_bd ,
stb_i => '0' ,
ack_o => open ,
we_i => '0' ,
cyc_i => '0' ,
sel_i => (OTHERS => '0') ,
adr_i => (OTHERS => '0') ,
slv_dat_i => (OTHERS => '0') ,
slv_dat_o => open ,
stb_o => wbm_dma_stb_o ,
ack_i => wbm_dma_ack_i ,
we_o => wbm_dma_we_o ,
cti => wbm_dma_cti,
tga_o => wbm_dma_tga_o ,
err_i => wbm_dma_err_i ,
cyc_o_sram => wbm_dma_cyc_sram ,
cyc_o_vme => wbm_dma_cyc_vme ,
cyc_o_pci => wbm_dma_cyc_pci ,
sel_o => wbm_dma_sel_o ,
adr_o => wbm_dma_adr_o ,
mstr_dat_o => wbm_dma_dat_o ,
mstr_dat_i => wbm_dma_dat_i
);
END wbb2vme_top_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity tieee2 is
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_mBuf_128x72_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_mBuf_128x72_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_mBuf_128x72_pkg;
PACKAGE BODY k7_mBuf_128x72_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_mBuf_128x72_pkg;
|
architecture RTL of ENTITY1 is
signal instruction : bit_vector(15 downto 0);
alias opcode : bit_vector(3 downto 0) is instruction(15 downto 12);
signal data : std_logic_vector(opcode'range);
begin
data <= opcode;
PROC_NAME : process () is
begin
data <= opcode;
if (opcode = "0110") then
data <= opcode;
end if;
end process PROC_NAME;
end architecture RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_arch OF rom IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF rom_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "rom.mif",
C_INIT_FILE => "rom.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 30720,
C_READ_DEPTH_A => 30720,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 30720,
C_READ_DEPTH_B => 30720,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.252613 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END rom_arch;
|
-------------------------------------------------------------------------------
-- lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of lmb_bram_wrapper : entity is "yes";
end lmb_bram_wrapper;
architecture STRUCTURE of lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "spartan6"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
|
--
-- uartrx-tb.vhd
--
-- Test Bench for UART receiver.
--
-- This is not an exhaustive testbench; it simply clocks data into the UART
-- reciever (including one character with an invalid stop bit), and ensures
-- that the correct data comes out the other side. It also tests to make sure
-- that invalid data will not stop the receiver from running.
--
-- The testbench assumes that the receiver interprets data as MSB first.
--
-- Revision History:
-- 21 Apr 2015 Brian Kubisiak Initial revision.
-- 22 Apr 2015 Brian Kubisiak Updated documentation.
--
library ieee;
use ieee.std_logic_1164.all;
-- Our testbench entity has no ports; it is completely self-contained.
entity uartrx_tb is
end uartrx_tb;
architecture TB_ARCHITECTURE of uartrx_tb is
--
-- uartrx
--
-- This component is the unit-under-test. It is an asynchronous receiver for
-- the UART design. It takes in serial data at the baud rate determined by the
-- clock, and outputs the data in parallel.
--
-- Parameters:
-- N (integer) Number of bits per character.
--
-- Inputs:
-- reset (std_logic) Active-low line to reset the UART receiver.
-- clk (std_logic) Baud rate clock. The UART will sample the input
-- signal on every rising edge of the clock.
-- rx (std_logic) Receive line carrying the serial data.
--
-- Outputs:
-- data (std_logic_vector) Last character received over the UART.
-- rdy (std_logic) Active-low line indicating when the data is
-- ready. Once a character is received, this will
-- pulse low for one clock.
-- err (std_logic) Active-low signal indicating an error occurred.
-- Currently, this means that the stop bit was not
-- high.
component uartrx is
generic ( N : integer := 8 );
port (
reset : in std_logic; -- Reset the UART
clk : in std_logic; -- Baud clock
rx : in std_logic; -- Serial data in
data : out std_logic_vector(N-1 downto 0); -- Parallel data out
rdy : out std_logic; -- New data ready
err : out std_logic -- Error occurred
);
end component;
-- Stimulus signals - signals mapped to the input ports of tested entity
signal clk : std_logic; -- System clock
signal reset : std_logic; -- Reset receiver, preparing it for new data
signal rx : std_logic; -- Serial data input to receiver
-- Outputs - signals that are checked against the expected outputs of the
-- test bench.
signal data : std_logic_vector(7 downto 0); -- Data received by UART
signal rdy : std_logic; -- Data from UART ready for reading
signal err : std_logic; -- UART read invalid data
-- Indicates that the simulation has finished
signal END_SIM : boolean := FALSE;
-- This signal holds the test pattern to shift into the receiver. It has a
-- couple of bits at the beginning to allow the UART to reset, followed by
-- 2 valid bytes, then an invalid, then another valid.
constant data_in: std_logic_vector(0 to 10*4 + 1) :=
"11" & "0010101011" & "0101010101" & "0110011010" & "0001100101";
-- Type for holding the output vectors. We need this because VHDL won't
-- declare an array of std_logic_vector without a new type.
type OutData is array (0 to 3) of std_logic_vector(7 downto 0);
-- We should see the following data output from the UART:
constant data_out: OutData :=
("01010101", "10101010", "11001101", "00110010");
-- The 'rdy' signal should exhibit this pattern. For the third pattern, the
-- 'err' signal will be pulsed instead of the 'rdy' signal.
constant rdy_sig: std_logic_vector(0 to 3) := "0010";
begin
-- Declare the unit-under-test and wire up all its inputs to stimulus
-- signals and outputs to tested signals.
UUT: uartrx
generic map ( N => 8 )
port map (
-- Map inputs to stimulus signals:
clk => clk,
reset => reset,
rx => rx,
-- Map outputs to tested signals:
data => data,
rdy => rdy,
err => err
);
-- This process will reset the UART for a couple of clocks, then stimulate
-- the serial data input with the test signal. Once all the test bits have
-- been 'transmitted', then simulation will end.
StimulateInputs: process
begin
-- Reset the UART
reset <= '0';
-- Set stop bit so UART doesn't begin reading immediately.
rx <= '1';
-- Wait a couple of clock cycles to the UART to reset.
wait until clk = '1';
wait until clk = '0';
wait until clk = '1';
wait until clk = '0';
-- Start running the receiver
reset <= '1';
for i in 0 to 41 loop
-- Wait for the next rising edge
wait until clk = '1';
-- Output the next bit in the stimulus sequence with a short delay
-- after the clock.
rx <= data_in(i) after 1 ns;
-- Hold here for the clock to go low again.
wait until clk = '0';
end loop;
-- Wait a couple more clocks to make sure the data propagates through
wait until clk = '1';
wait until clk = '0';
wait until clk = '1';
wait until clk = '0';
-- Simulation is over
END_SIM <= TRUE;
wait;
end process;
-- This process will wait until the receiver indicates that it has data,
-- then check to make sure that the data is correct.
TestOutputs: process
begin
for i in 0 to 3 loop
-- Wait until a new byte is received (whether in error or not)
wait until (rdy = '0' or err = '0');
-- Check data on the next rising edge of the clock
wait until (clk'event and clk = '1');
-- Check to make sure that the byte is correct and errors are found
-- only at the proper times
assert (data = data_out(i) and rdy = rdy_sig(i))
report "Wrong data on output."
severity ERROR;
-- Wait for the signal to be reset
wait until (rdy = '1' and err = '1');
end loop;
-- Notify the simulation once all tests have passed.
assert (FALSE) report "All outputs tested." severity NOTE;
wait;
end process;
-- This process will generate a clock with a 20 ns period and a 50% duty
-- cycle. Once the end of the simulation has been reached (END_SIM = TRUE),
-- then the clock will stop oscillating.
GenClock: process
begin
-- this process generates a 20 ns 50% duty cycle clock
-- stop the clock when the end of the simulation is reached
if END_SIM = FALSE then
clk <= '0';
wait for 10 ns;
else
wait;
end if;
if END_SIM = FALSE then
clk <= '1';
wait for 10 ns;
else
wait;
end if;
end process;
end TB_ARCHITECTURE;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
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`protect key_block
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FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
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3cUTC8DOVlYTmsH8E8e97xR1idQzbJfZm37XC0QbEnjsRezRsysghBAFJBnKBGL1JAz+dn+idtL4
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ltBc4VLB03Sb3jxROIkOgl0jFc8tU3vV1DedBE5eUEYNUoj3FE2lWCezPh6TLGpFW0AZL2c2XyR0
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kRbtXndaoG00bNcmy5EETYlc5Gy7konGos1dR+etHPLZovwSbizfcFI0cLNUpePWEXb5vQeqYH3h
As6tcl3ifrJQMHPvbo/plfu2EjGPIr+j5NezpFahnI+AmyZ5C7HVe6zBNQaPMpLrDQB9wfRuD1gB
UPdAJKzMjinpMSO778gTPh4FUIDMvf1huoM96axvN6iLeIfs4HxpWgszJJe5ycqSxl62+QIqe+rv
9KcVEOcYsTWzmIQXdgsyOZ0Dc8RvhGvHkAH+s9i25Ix4ArAB/ksT4R/P//pFLdGEwDtm5hr/vvn1
YKvbYP0kqJTd0oMpo228dY0GRQU2q0Z/unCli6dzuVSittBJm8W+RUXWo0rR3vcorJNB8aqnVc33
ABYZTjX2Wuvd5R0tLEvQ4yAN2Aw1kX8t3Ee3iG8MZQlVgUnh0rFJVfIIW8dfgmRjnlJpOuVuRBL5
cITe2YfSmFSpF/xCkBmp9z9Y6l+xWLBlLkaFSATZOA==
`protect end_protected
|
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