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-------------------------------------------------------------------------------
-- lmb_bram_if_cntlr.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => false) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_TARGET => C_TARGET,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => true) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_TARGET => C_TARGET,
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
-------------------------------------------------------------------------------
-- lmb_bram_if_cntlr.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => false) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_TARGET => C_TARGET,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => true) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_TARGET => C_TARGET,
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
-------------------------------------------------------------------------------
-- lmb_bram_if_cntlr.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => false) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_TARGET => C_TARGET,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => true) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_TARGET => C_TARGET,
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block1.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block1
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_5_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_6_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_6_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_5_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block1 IS
-- Signals
SIGNAL twdlXdin_3_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_3_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_11_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_11_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_5_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_5_im_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_6_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_6_im_tmp : signed(17 DOWNTO 0); -- sfix18
BEGIN
twdlXdin_3_re_signed <= signed(twdlXdin_3_re);
twdlXdin_3_im_signed <= signed(twdlXdin_3_im);
twdlXdin_11_re_signed <= signed(twdlXdin_11_re);
twdlXdin_11_im_signed <= signed(twdlXdin_11_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_3_re_signed,
twdlXdin_3_im_signed, twdlXdin_11_re_signed, twdlXdin_11_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_3_re_signed, 19) + resize(twdlXdin_11_re_signed, 19);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_3_re_signed, 19) - resize(twdlXdin_11_re_signed, 19);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_3_im_signed, 19) + resize(twdlXdin_11_im_signed, 19);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_3_im_signed, 19) - resize(twdlXdin_11_im_signed, 19);
END IF;
dout_5_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(17 DOWNTO 0);
dout_5_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(17 DOWNTO 0);
dout_6_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(17 DOWNTO 0);
dout_6_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(17 DOWNTO 0);
dout_5_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_5_re <= std_logic_vector(dout_5_re_tmp);
dout_5_im <= std_logic_vector(dout_5_im_tmp);
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
END rtl;
|
package conv1 is
end package;
package body conv1 is
type rec is record
x : integer;
end record;
type rec_array is array (natural range <>) of rec;
function get(a : rec_array) return real is
begin
return real(a(0).x); -- Must reify a(0).x
end function;
end package body;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.words.all;
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity cpu;
-- not in book
architecture behavioral of cpu is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.words.all;
entity memory is
port ( address : in uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity memory;
-- not in book
architecture behavioral of memory is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.words.all;
entity ROM is
port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
end entity ROM;
architecture behavioral of ROM is
begin
end architecture behavioral;
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
use work.words.all;
signal address : uword;
signal data : word;
-- . . .
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- code from book (in text)
-- boot_rom : entity work.ROM(behavioral)
-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
-- -- not in book
-- other_port => open );
-- -- end not in book
-- end code from book
end architecture top_level;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.words.all;
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity cpu;
-- not in book
architecture behavioral of cpu is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.words.all;
entity memory is
port ( address : in uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity memory;
-- not in book
architecture behavioral of memory is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.words.all;
entity ROM is
port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
end entity ROM;
architecture behavioral of ROM is
begin
end architecture behavioral;
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
use work.words.all;
signal address : uword;
signal data : word;
-- . . .
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- code from book (in text)
-- boot_rom : entity work.ROM(behavioral)
-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
-- -- not in book
-- other_port => open );
-- -- end not in book
-- end code from book
end architecture top_level;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.words.all;
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity cpu;
-- not in book
architecture behavioral of cpu is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.words.all;
entity memory is
port ( address : in uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity memory;
-- not in book
architecture behavioral of memory is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.words.all;
entity ROM is
port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
end entity ROM;
architecture behavioral of ROM is
begin
end architecture behavioral;
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
use work.words.all;
signal address : uword;
signal data : word;
-- . . .
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- code from book (in text)
-- boot_rom : entity work.ROM(behavioral)
-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
-- -- not in book
-- other_port => open );
-- -- end not in book
-- end code from book
end architecture top_level;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1983.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01983ent IS
type color is (red, green, blue);
constant azure : color := blue;
constant first : color := color'low;
END c07s02b02x00p02n01i01983ent;
ARCHITECTURE c07s02b02x00p02n01i01983arch OF c07s02b02x00p02n01i01983ent IS
BEGIN
TESTING: PROCESS
variable A1, A2 : color;
variable A3 : color := blue;
alias AA1 :color is A1;
BEGIN
AA1:= first;
A2 := color'succ(A1);
assert NOT( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***PASSED TEST: c07s02b02x00p02n01i01983"
severity NOTE;
assert ( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***FAILED TEST: c07s02b02x00p02n01i01983 - Relational operators truth table test for data type of Enumeration failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01983arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1983.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01983ent IS
type color is (red, green, blue);
constant azure : color := blue;
constant first : color := color'low;
END c07s02b02x00p02n01i01983ent;
ARCHITECTURE c07s02b02x00p02n01i01983arch OF c07s02b02x00p02n01i01983ent IS
BEGIN
TESTING: PROCESS
variable A1, A2 : color;
variable A3 : color := blue;
alias AA1 :color is A1;
BEGIN
AA1:= first;
A2 := color'succ(A1);
assert NOT( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***PASSED TEST: c07s02b02x00p02n01i01983"
severity NOTE;
assert ( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***FAILED TEST: c07s02b02x00p02n01i01983 - Relational operators truth table test for data type of Enumeration failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01983arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1983.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01983ent IS
type color is (red, green, blue);
constant azure : color := blue;
constant first : color := color'low;
END c07s02b02x00p02n01i01983ent;
ARCHITECTURE c07s02b02x00p02n01i01983arch OF c07s02b02x00p02n01i01983ent IS
BEGIN
TESTING: PROCESS
variable A1, A2 : color;
variable A3 : color := blue;
alias AA1 :color is A1;
BEGIN
AA1:= first;
A2 := color'succ(A1);
assert NOT( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***PASSED TEST: c07s02b02x00p02n01i01983"
severity NOTE;
assert ( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***FAILED TEST: c07s02b02x00p02n01i01983 - Relational operators truth table test for data type of Enumeration failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01983arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity conv_coder_tb is
end conv_coder_tb;
architecture tb of conv_coder_tb is
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal d : std_logic := '0';
signal x : std_logic;
signal y : std_logic;
-- number of bits to check
constant n_bit : positive := 1000;
-- test vector
signal rand_vector : std_logic_vector(0 to n_bit + 6) := (others => '0');
signal x_test : std_logic;
signal y_test : std_logic;
begin
dut : entity work.conv_coder
port map(clk => clk, rst => rst, clk_en => clk_en, d => d, x => x, y => y);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
prepare : process
variable seed1, seed2 : positive;
variable rand : real;
variable rand_unsigned : std_logic_vector(0 downto 0);
begin
for i in 0 to n_bit-1 loop
uniform(seed1, seed2, rand);
rand_unsigned := std_logic_vector(to_unsigned(integer(round(rand)),1));
rand_vector(6 + i) <= rand_unsigned(0);
end loop;
wait;
end process;
test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until rising_edge(clk);
for i in 6 to n_bit + 6 - 1 loop
clk_en <= '1';
d <= rand_vector(i);
x_test <= (rand_vector(i) xor
rand_vector(i-1) xor
rand_vector(i-2) xor
rand_vector(i-3) xor
rand_vector(i-6));
y_test <= (rand_vector(i) xor
rand_vector(i-2) xor
rand_vector(i-3) xor
rand_vector(i-5) xor
rand_vector(i-6));
wait until rising_edge(clk);
wait until falling_edge(clk);
assert x = x_test
report "X output error."
severity failure;
assert y = y_test
report "Y output error."
severity failure;
end loop;
end process;
end tb;
|
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate0.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate0 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END altaccumulate0;
ARCHITECTURE SYN OF altaccumulate0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
result <= sub_wire1(15 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 8,
width_out => 16
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
cout => sub_wire0,
result => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "1"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "16"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0_inst.vhd TRUE
|
---------------------------------------------------------------------------------------------------------
-- MMU in
-- This block handles input values for the DRAM, to perform read/write operation.
-- It is in charge for translating virtual aligned address in physical uniligned addresses and feed
-- the DRAM with the correct data. In case of unaligned access to memory unaligned control signal is
-- asserted
---------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
---------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------
entity mmu_in_dram is
port (
--INPUTS
mem_op : in std_logic_vector(5 downto 0); -- control signal which groups the control signals directed to the memory (sb, sw, lbu, lw, lhu, lb)
aligned_address : in std_logic_vector(31 downto 0); -- aligned access to be translated
data : in std_logic_vector(31 downto 0); -- data to be written at the address specified in aligned address
--OUTPUTS
unaligned : out std_logic; -- signal directed to the PSW, asserted in case of unaligned access to the memory
nibble : out std_logic_vector(1 downto 0); -- last two bit of the incoming address in case of lb, sb, lbu, lhu
write_op : out std_logic; -- write signal to the memory
read_op : out std_logic; -- read signal to the memory
mem_address : out std_logic_vector(31 downto 0); -- physical address to memory
mem_data : out std_logic_vector(31 downto 0); -- data to written in the right format
write_byte : out std_logic -- Inform DRAM that we want to write a byte
);
end mmu_in_dram;
------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------
architecture behavioral of mmu_in_dram is
begin
-----------------------
-- Name: Comb Logic
-- Type: Combinational
-- Purpose: Implement
-- the combinational
-- logic of the MMU
-----------------------
comb_logic:process(mem_op, aligned_address, data)
begin
case mem_op is
when "000100" => -- lw
-- check address alignement
if (aligned_address(1 downto 0) = "00") then
unaligned <= '0';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0'); -- not used here
else
-- raise exception
unaligned <= '1';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
end if;
when "000010" => -- lhu2
-- check address alignement
if (aligned_address(0) = '0') then
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
write_byte <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0'); -- not used here
else
unaligned <= '1';
nibble <= "00";
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
end if;
when "000001" => -- lb
-- unaligned access are allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
when "001000" => -- lbu
-- unaligned access are allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
when "010000" => -- sw
-- check for alignement
if (aligned_address(1 downto 0) = "00") then
unaligned <= '0';
nibble <= "00";
write_op <= '1';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= data;
write_byte <= '0';
else
-- raise exception, write is not performed
unaligned <= '1';
nibble <= "00";
write_op <= '0';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
end if;
when "100000" => -- sb
-- unaligned access is allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '1';
write_byte <= '1';
read_op <= '0';
mem_data(7 downto 0) <= data(7 downto 0);
mem_data(31 downto 8) <= (others => '0');
mem_address <= "00" & aligned_address(31 downto 2);
when others =>
unaligned <= '0';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '0';
mem_data <= (others => '0');
mem_address <= (others => '0');
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity repro3 is
generic (
constant DIN_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 12
);
end repro3;
architecture Behav of repro3 is
type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DIN_WIDTH - 1 downto 0);
signal FIFO_ROW_1 : FIFO_Memory;
begin
FIFO_ROW_1<= (FIFO_ROW_1 'range=> (FIFO_ROW_1 'range=>'0'));
end Behav;
|
entity bug8 is
end entity bug8;
architecture x of bug8 is
type bit_position is (msb);
signal test : real;
begin
test <= msb;
end architecture x;
|
entity bug8 is
end entity bug8;
architecture x of bug8 is
type bit_position is (msb);
signal test : real;
begin
test <= msb;
end architecture x;
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_randomizer
---- Version: 1.0.0
---- Description:
---- Randomize input data with LFSR output sequence
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx randomizer inputs and outputs
--=============================================================================
entity ccsds_tx_randomizer is
generic(
constant CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_randomizer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_randomizer is
component ccsds_rxtx_lfsr is
generic(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal randomizer_sequence: std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
signal wire_lfsr_valid: std_logic;
-- components instanciation and mapping
begin
tx_randomizer_lfsr: ccsds_rxtx_lfsr
generic map(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE => CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_o => wire_lfsr_valid,
dat_o => randomizer_sequence
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of randp
-- Randomize data using LFSR register
--=============================================================================
-- read: rst_i, dat_val_i, dat_i, randomizer_sequence, wire_lfsr_valid
-- write: dat_o, dat_val_o
-- r/w:
RANDP: process (clk_i)
variable data_randomized: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
data_randomized := '0';
dat_val_o <= '0';
else
if (dat_val_i = '1') and (wire_lfsr_valid = '1') then
dat_val_o <= '1';
dat_o <= dat_i xor randomizer_sequence;
data_randomized := '1';
else
dat_val_o <= '0';
if (data_randomized = '0') then
dat_o <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end structure;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
--TODO: add some comments in signal assignment
entity jump_logic is
generic (
SIZE : integer := 32
);
port (
NPCF_i : in std_logic_vector(SIZE - 1 downto 0);
IR_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
A_o : out std_logic_vector(SIZE - 1 downto 0);
rA_o : out std_logic_vector(4 downto 0);
rB_o : out std_logic_vector(4 downto 0);
rC_o : out std_logic_vector(4 downto 0);
branch_target_o : out std_logic_vector(SIZE - 1 downto 0);
sum_addr_o : out std_logic_vector(SIZE - 1 downto 0);
extended_imm : out std_logic_vector(SIZE - 1 downto 0);
taken_o : out std_logic; --was the branch taken or not?
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_Adec_i : in std_logic_vector(1 downto 0);
S_EXT_i : in std_logic;
S_EXT_SIGN_i : in std_logic;
S_MUX_LINK_i : in std_logic;
S_EQ_NEQ_i : in std_logic
);
end jump_logic;
architecture struct of jump_logic is
-- component basicadd
-- port(
-- IN1 : in unsigned(SIZE - 1 downto 0);
-- IN2 : in unsigned(SIZE - 1 downto 0);
-- OUT1 : out unsigned(SIZE - 1 downto 0)
-- );
-- end component;
component p4add
generic (
N : integer := 32;
logN : integer := 5);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
sign : In std_logic;
S : out std_logic_vector(N-1 downto 0);
Cout : out std_logic);
end component;
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer :=5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component extender_32
port(
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component zerocheck
port(
IN0 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0, out 1 if not equal . when 1 out 1 if equal
OUT1 : out std_logic
);
end component;
component add4
port(
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end component;
signal ext_imm : std_logic_vector (SIZE - 1 downto 0);
signal sum_addr : std_logic_vector(SIZE - 1 downto 0);
signal branch_sel : std_logic;
signal FW_MUX_OUT : std_logic_vector(SIZE - 1 downto 0);
begin
EXTENDER: extender_32 port map(
IN1 => IR_i,
CTRL => S_EXT_i,
SIGN => S_EXT_SIGN_i,
OUT1 => ext_imm);
JUMPADDER: p4add
generic map (
N => 32,
logN => 5
)
port map (
A => NPCF_i,
B => ext_imm,
Cin => '0',
sign => '0',
S => sum_addr,
Cout => open
);
BRANCHMUX: mux21 port map(
IN0 => sum_addr,
IN1 => NPCF_i,
CTRL => branch_sel,
OUT1 => branch_target_o);
ZC: zerocheck port map(
IN0 => FW_MUX_OUT,
CTRL => S_EQ_NEQ_i,
OUT1 => branch_sel);
MUXLINK: mux21 port map(
IN0 => ext_imm,
IN1 => NPCF_i,
CTRL => S_MUX_LINK_i,
OUT1 => extended_imm);
MUX_FWA: mux41
generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "00000000000000000000000000000000",
CTRL => S_FW_Adec_i,
OUT1 => FW_MUX_OUT
);
rA_o <= IR_i(25 downto 21);
rB_o <= IR_i(20 downto 16);
rC_o <= IR_i(15 downto 11);
A_o <= FW_MUX_OUT;
sum_addr_o <= sum_addr;
taken_o <= not(branch_sel);
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
--TODO: add some comments in signal assignment
entity jump_logic is
generic (
SIZE : integer := 32
);
port (
NPCF_i : in std_logic_vector(SIZE - 1 downto 0);
IR_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
A_o : out std_logic_vector(SIZE - 1 downto 0);
rA_o : out std_logic_vector(4 downto 0);
rB_o : out std_logic_vector(4 downto 0);
rC_o : out std_logic_vector(4 downto 0);
branch_target_o : out std_logic_vector(SIZE - 1 downto 0);
sum_addr_o : out std_logic_vector(SIZE - 1 downto 0);
extended_imm : out std_logic_vector(SIZE - 1 downto 0);
taken_o : out std_logic; --was the branch taken or not?
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_Adec_i : in std_logic_vector(1 downto 0);
S_EXT_i : in std_logic;
S_EXT_SIGN_i : in std_logic;
S_MUX_LINK_i : in std_logic;
S_EQ_NEQ_i : in std_logic
);
end jump_logic;
architecture struct of jump_logic is
-- component basicadd
-- port(
-- IN1 : in unsigned(SIZE - 1 downto 0);
-- IN2 : in unsigned(SIZE - 1 downto 0);
-- OUT1 : out unsigned(SIZE - 1 downto 0)
-- );
-- end component;
component p4add
generic (
N : integer := 32;
logN : integer := 5);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
sign : In std_logic;
S : out std_logic_vector(N-1 downto 0);
Cout : out std_logic);
end component;
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer :=5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component extender_32
port(
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component zerocheck
port(
IN0 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0, out 1 if not equal . when 1 out 1 if equal
OUT1 : out std_logic
);
end component;
component add4
port(
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end component;
signal ext_imm : std_logic_vector (SIZE - 1 downto 0);
signal sum_addr : std_logic_vector(SIZE - 1 downto 0);
signal branch_sel : std_logic;
signal FW_MUX_OUT : std_logic_vector(SIZE - 1 downto 0);
begin
EXTENDER: extender_32 port map(
IN1 => IR_i,
CTRL => S_EXT_i,
SIGN => S_EXT_SIGN_i,
OUT1 => ext_imm);
JUMPADDER: p4add
generic map (
N => 32,
logN => 5
)
port map (
A => NPCF_i,
B => ext_imm,
Cin => '0',
sign => '0',
S => sum_addr,
Cout => open
);
BRANCHMUX: mux21 port map(
IN0 => sum_addr,
IN1 => NPCF_i,
CTRL => branch_sel,
OUT1 => branch_target_o);
ZC: zerocheck port map(
IN0 => FW_MUX_OUT,
CTRL => S_EQ_NEQ_i,
OUT1 => branch_sel);
MUXLINK: mux21 port map(
IN0 => ext_imm,
IN1 => NPCF_i,
CTRL => S_MUX_LINK_i,
OUT1 => extended_imm);
MUX_FWA: mux41
generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "00000000000000000000000000000000",
CTRL => S_FW_Adec_i,
OUT1 => FW_MUX_OUT
);
rA_o <= IR_i(25 downto 21);
rB_o <= IR_i(20 downto 16);
rC_o <= IR_i(15 downto 11);
A_o <= FW_MUX_OUT;
sum_addr_o <= sum_addr;
taken_o <= not(branch_sel);
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity data_sink is
port (
CLK : in std_logic;
RST_n : in std_logic;
VIN : in std_logic;
DIN : in std_logic_vector(17 downto 0));
end data_sink;
architecture beh of data_sink is
begin -- beh
process (CLK, RST_n)
file res_fp : text open WRITE_MODE is "./results.txt";
variable line_out : line;
begin -- process
if RST_n = '0' then -- asynchronous reset (active low)
null;
elsif CLK'event and CLK = '1' then -- rising clock edge
if (VIN = '1') then
write(line_out, conv_integer(signed(DIN)));
writeline(res_fp, line_out);
end if;
end if;
end process;
end beh;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allclkgen
-- File: allclkgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex7
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 25000);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkand_ut90nhbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkrand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_rh_lib18t
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut130hbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut90nhbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_fusion
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_fusion
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3e
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3l
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_rhumc
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_saed32
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_saed32
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_saed32
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_saed32
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_dare
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_dare
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhumc
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_dare
generic (
noclkfb : integer := 1
);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clk8x : out std_logic
);
end component;
component clkgen_easic90
generic (
clk_mul : integer;
clk_div : integer;
freq : integer;
pcisysclk : integer;
pcien : integer);
port (
clkin : in std_ulogic;
pciclkin : in std_ulogic;
clk : out std_ulogic;
clk2x : out std_ulogic;
clk4x : out std_ulogic;
clkn : out std_ulogic;
lock : out std_ulogic);
end component;
component clkmux_dare
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkmux_rhlib18t
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_n2x
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_n2x
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_n2x
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk270en : integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic; -- unscaled 2X clock
clk270 : out std_ulogic -- clk shifted 270 degrees
);
end component;
component clkgen_ut130hbd
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
clk4x : out std_ulogic;
clk8x : out std_ulogic;
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component clkgen_ut90nhbd is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
end;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity tute1_tb is end entity;
architecture testbench of tute1_tb is
signal success, done, error : std_ulogic := '0';
signal reset_n, clk : std_ulogic := '0';
signal counter : integer := 0;
signal oout : u8;
begin
success <= done and (not error);
process begin
clk <= '0'; wait for 5 ps;
clk <= '1'; wait for 5 ps;
end process;
process begin
wait until rising_edge(clk);
counter <= counter + 1;
if counter >= 10 then
reset_n <= '1';
end if;
end process;
test: entity work.tute1 port map(
clk_clk => clk, clk_reset_n => reset_n,
oout => oout
);
end;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:14 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_xbar_0_stub.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[23:0],m_axi_awaddr[63:0],m_axi_awlen[15:0],m_axi_awsize[5:0],m_axi_awburst[3:0],m_axi_awlock[1:0],m_axi_awcache[7:0],m_axi_awprot[5:0],m_axi_awregion[7:0],m_axi_awqos[7:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[1:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bid[23:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_arid[23:0],m_axi_araddr[63:0],m_axi_arlen[15:0],m_axi_arsize[5:0],m_axi_arburst[3:0],m_axi_arlock[1:0],m_axi_arcache[7:0],m_axi_arprot[5:0],m_axi_arregion[7:0],m_axi_arqos[7:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rid[23:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rlast[1:0],m_axi_rvalid[1:0],m_axi_rready[1:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
begin
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF cmdfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF cmdfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF cmdfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jul 8 09:01:52 2016
-- Host : jalapeno running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
-- Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/pcie_recv_fifo_stub.vhdl}
-- Design : pcie_recv_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pcie_recv_fifo is
Port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end pcie_recv_fifo;
architecture stub of pcie_recv_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,srst,din[127:0],wr_en,rd_en,dout[127:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_0_1,Vivado 2015.4";
begin
end;
|
-- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for a_clk
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-e.vhd,v 1.1 2004/04/06 10:44:17 wig Exp $
-- $Date: 2004/04/06 10:44:17 $
-- $Log: a_clk-e.vhd,v $
-- Revision 1.1 2004/04/06 10:44:17 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity a_clk
--
entity a_clk is
-- Generics:
-- No Generated Generics for Entity a_clk
-- Generated Port Declaration:
port(
-- Generated Port for Entity a_clk
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
display_ls_hr : out std_ulogic_vector(6 downto 0);
display_ls_min : out std_ulogic_vector(6 downto 0);
display_ms_hr : out std_ulogic_vector(6 downto 0);
display_ms_min : out std_ulogic_vector(6 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity a_clk
);
end a_clk;
--
-- End of Generated Entity a_clk
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc962.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p03n01i00962ent IS
END c06s03b00x00p03n01i00962ent;
ARCHITECTURE c06s03b00x00p03n01i00962arch OF c06s03b00x00p03n01i00962ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12.S2 := 10 ; -- No_Failure_here
wait for 10 ns;
assert NOT( V1.S12.S2 = 10 )
report "***PASSED TEST: c06s03b00x00p03n01i00962"
severity NOTE;
assert ( V1.S12.S2 = 10 )
report "***FAILED TEST: c06s03b00x00p03n01i00962 - The suffix of a selected name can be a simple name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p03n01i00962arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc962.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p03n01i00962ent IS
END c06s03b00x00p03n01i00962ent;
ARCHITECTURE c06s03b00x00p03n01i00962arch OF c06s03b00x00p03n01i00962ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12.S2 := 10 ; -- No_Failure_here
wait for 10 ns;
assert NOT( V1.S12.S2 = 10 )
report "***PASSED TEST: c06s03b00x00p03n01i00962"
severity NOTE;
assert ( V1.S12.S2 = 10 )
report "***FAILED TEST: c06s03b00x00p03n01i00962 - The suffix of a selected name can be a simple name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p03n01i00962arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc962.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p03n01i00962ent IS
END c06s03b00x00p03n01i00962ent;
ARCHITECTURE c06s03b00x00p03n01i00962arch OF c06s03b00x00p03n01i00962ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12.S2 := 10 ; -- No_Failure_here
wait for 10 ns;
assert NOT( V1.S12.S2 = 10 )
report "***PASSED TEST: c06s03b00x00p03n01i00962"
severity NOTE;
assert ( V1.S12.S2 = 10 )
report "***FAILED TEST: c06s03b00x00p03n01i00962 - The suffix of a selected name can be a simple name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p03n01i00962arch;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "pwm_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pwm_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity pwm_module_tb is
end pwm_module_tb;
-------------------------------------------------------------------------------
architecture tb of pwm_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16;
constant WIDTH : positive := 12;
constant PRESCALER : positive := 2;
-- component ports
signal pwm_p : std_logic;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reset : std_logic;
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : pwm_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
pwm_p => pwm_p,
bus_o => bus_o,
bus_i => bus_i,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- reset generation
reset <= '1', '0' after 50 ns;
waveform : process
begin
wait until falling_edge(reset);
wait for 20 us;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(20, 15));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 us;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16, 15));
bus_i.data <= x"07ff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 us;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(10, 15));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process waveform;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "pwm_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pwm_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity pwm_module_tb is
end pwm_module_tb;
-------------------------------------------------------------------------------
architecture tb of pwm_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16;
constant WIDTH : positive := 12;
constant PRESCALER : positive := 2;
-- component ports
signal pwm_p : std_logic;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reset : std_logic;
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : pwm_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
pwm_p => pwm_p,
bus_o => bus_o,
bus_i => bus_i,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- reset generation
reset <= '1', '0' after 50 ns;
waveform : process
begin
wait until falling_edge(reset);
wait for 20 us;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(20, 15));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 us;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16, 15));
bus_i.data <= x"07ff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 us;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(10, 15));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process waveform;
end tb;
|
-- name can be any name chosen for this entity
-- MODE specifies the port direction, and is one of the following:
-- in: a port that can be read from but not written to
-- out: a port that can be written to but not read from
-- in/out: a port that can be read and written to (tristate buses)
-- buffer: an out port whose current value can be read from
-- TYPE specifies the data type, and is one of the following:
-- bit: the signal has only the states "1" or "0"
-- boolean: the signal has only the states True or False
-- std_logic: the signal has extended values as "1", "0", "Z", "-"
-- integer: the signal is an integer
-- bit_vector: the signal is a concatenation of bits
-- std_logic_vector: the signal is a concatenation of std_logic signals
-- character: the signal may be any ISO character
ENTITY name IS
PORT(A: MODE TYPE;
B: MODE TYPE;
...
);
END name;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_12.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- retVal = hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
retVal_next <= intrfc2thrd_value;
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
when STATE_12 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- b instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- b instance
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : eth_filter_tb
-- Author : Gideon Zweijtzer (gideon.zweijtzer@gmail.com)
-------------------------------------------------------------------------------
-- Description: Testbench for eth_filter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_filter_tb is
end entity;
architecture testcase of eth_filter_tb is
signal clock : std_logic := '0'; -- 50 MHz reference clock
signal reset : std_logic;
signal io_clock : std_logic := '0'; -- 66 MHz reference clock
signal io_reset : std_logic;
signal rmii_crs_dv : std_logic;
signal rmii_rxd : std_logic_vector(1 downto 0);
signal rmii_tx_en : std_logic;
signal rmii_txd : std_logic_vector(1 downto 0);
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic;
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal ten_meg_mode : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_req_free : t_io_req;
signal io_resp_free : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal io_irq : std_logic;
signal alloc_req : std_logic := '0';
signal alloc_resp : t_alloc_resp;
signal used_req : t_used_req;
signal used_resp : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32 := c_mem_resp_32_init;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_frame_with_crc : t_byte_array := (
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13"
-- , X"7A", X"D5", X"6B", X"B3"
);
procedure io_write_long(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(31 downto 0)) is
begin
io_write(io, to_unsigned(addr+0, 20), data(07 downto 00));
io_write(io, to_unsigned(addr+1, 20), data(15 downto 08));
io_write(io, to_unsigned(addr+2, 20), data(23 downto 16));
io_write(io, to_unsigned(addr+3, 20), data(31 downto 24));
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(7 downto 0)) is
begin
io_write(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(7 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read_word(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(15 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data(7 downto 0));
io_read(io, to_unsigned(addr+1, 20), data(15 downto 8));
end procedure;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
io_clock <= not io_clock after 8 ns;
io_reset <= '1', '0' after 100 ns;
i_rmii: entity work.rmii_transceiver
port map (
clock => clock,
reset => reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode
);
rmii_crs_dv <= rmii_tx_en;
rmii_rxd <= rmii_txd;
test: process
variable io : p_io_bus_bfm_object;
variable i : natural;
begin
eth_tx_data <= X"00";
eth_tx_sof <= '0';
eth_tx_eof <= '0';
eth_tx_valid <= '0';
ten_meg_mode <= '0';
wait until reset = '0';
bind_io_bus_bfm("io", io);
io_write_long(io, 0, X"01200000");
-- insert some free blocks
for x in 1 to 10 loop
io_write(io, 4, std_logic_vector(to_unsigned(x, 8)));
end loop;
-- configure filter
io_write(io, 256, c_frame_with_crc(0));
io_write(io, 257, c_frame_with_crc(1));
io_write(io, 258, c_frame_with_crc(2));
io_write(io, 259, c_frame_with_crc(3));
io_write(io, 260, c_frame_with_crc(4));
io_write(io, 261, c_frame_with_crc(5));
for x in 0 to 61 loop
wait until clock = '1';
i := 0;
L1: loop
wait until clock = '1';
if eth_tx_valid = '0' or eth_tx_ready = '1' then
if eth_tx_eof = '1' then
eth_tx_eof <= '0';
eth_tx_valid <= '0';
eth_tx_data <= X"00";
exit L1;
else
eth_tx_data <= c_frame_with_crc(i);
eth_tx_valid <= '1';
if i = c_frame_with_crc'left then
eth_tx_sof <= '1';
else
eth_tx_sof <= '0';
end if;
if (i+x) = c_frame_with_crc'right then
eth_tx_eof <= '1';
else
eth_tx_eof <= '0';
end if;
i := i + 1;
end if;
end if;
end loop;
if x > 9 then
-- io_write(io, 4, std_logic_vector(to_unsigned(x+16, 8)));
end if;
end loop;
wait;
end process;
i_bfm: entity work.io_bus_bfm
generic map ("io")
port map (
clock => io_clock,
req => io_req,
resp => io_resp
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 2
)
port map (
clock => io_clock,
req => io_req,
resp => io_resp,
reqs(1) => io_req_filt,
reqs(0) => io_req_free,
resps(1) => io_resp_filt,
resps(0) => io_resp_free
);
i_mut: entity work.eth_filter
port map (
clock => io_clock,
reset => io_reset,
io_req => io_req_filt,
io_resp => io_resp_filt,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
mem_req => mem_req,
mem_resp => mem_resp,
eth_clock => clock,
eth_reset => reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid );
i_free: entity work.free_queue
port map (
clock => io_clock,
reset => io_reset,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
io_req => io_req_free,
io_resp => io_resp_free,
io_irq => io_irq
);
process(io_clock)
variable c : integer := 0;
begin
if rising_edge(io_clock) then
if mem_req.request = '1' then
c := c + 1;
end if;
if c = 4 then
mem_resp.rack <= '1';
mem_resp.rack_tag <= mem_req.tag;
c := 0;
else
mem_resp.rack <= '0';
mem_resp.rack_tag <= X"00";
end if;
end if;
end process;
process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable id : std_logic_vector(7 downto 0);
variable data16 : std_logic_vector(15 downto 0);
begin
wait until io_reset = '0';
bind_io_bus_bfm("io", io);
while true loop
if io_irq /= '1' then
wait until io_irq = '1';
end if;
io_read(io, 15, data);
assert data(0) = '1' report "Expected an allocated block to be available";
io_read(io, 8, id);
io_read_word(io, 10, data16);
io_write(io, 15, X"00"); -- pop!
io_read(io, 15, data);
assert data(0) = '0' report "Expected no more allocated blocks to be available";
io_write(io, 4, id); -- re-add
end loop;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:18:21 05/28/2011
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
clk_in : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC
);
end top;
architecture Behavioral of top is
COMPONENT miner
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : IN std_logic_vector(5 downto 0);
data : IN std_logic_vector(95 downto 0);
state : IN STD_LOGIC_VECTOR (255 downto 0);
nonce : IN std_logic_vector(31 downto 0);
hit : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT(
clk : IN std_logic;
rx : IN std_logic;
txdata : IN std_logic_vector(48 downto 0);
txwidth : IN std_logic_vector(5 downto 0);
txstrobe : IN std_logic;
txbusy : OUT std_logic;
tx : OUT std_logic;
rxdata : OUT std_logic_vector(7 downto 0);
rxstrobe : OUT std_logic
);
END COMPONENT;
constant DEPTH : integer := 6;
signal clk : std_logic;
signal clk_dcmin : std_logic;
signal clk_dcmout : std_logic;
signal data : std_logic_vector(95 downto 0);
signal state : std_logic_vector(255 downto 0);
signal nonce : std_logic_vector(31 downto 0);
signal currnonce : std_logic_vector(31 downto 0);
signal load : std_logic_vector(343 downto 0);
signal loadctr : std_logic_vector(5 downto 0);
signal loading : std_logic := '0';
signal hit : std_logic;
signal txdata : std_logic_vector(48 downto 0);
signal txwidth : std_logic_vector(5 downto 0);
signal txstrobe : std_logic;
signal rxdata : std_logic_vector(7 downto 0);
signal rxstrobe : std_logic;
signal step : std_logic_vector(5 downto 0) := "000000";
begin
currnonce <= nonce - 2 * 2 ** DEPTH;
clk_buf : BUFG
port map (I=>clk_dcmout,
O=>clk);
clk_in_buf : IBUFG
port map (I=>clk_in,
O=>clk_dcmin);
dcm : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => TRUE
) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => open, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk_dcmout, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
CLKFB => '0', -- DCM clock feedback
CLKIN => clk_dcmin, -- Clock input (from IBUFG, BUFG or DCM)
RST => '0' -- DCM asynchronous reset input
);
miner0: miner
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
data => data,
state => state,
nonce => nonce,
hit => hit
);
serial: uart
port map (
clk => clk,
tx => tx,
rx => rx,
txdata => txdata,
txwidth => txwidth,
txstrobe => txstrobe,
txbusy => open,
rxdata => rxdata,
rxstrobe => rxstrobe
);
process(clk)
begin
if rising_edge(clk) then
step <= step + 1;
if conv_integer(step) = 2 ** (6 - DEPTH) - 1 then
step <= "000000";
nonce <= nonce + 1;
end if;
txdata <= "-------------------------------------------------";
txwidth <= "------";
txstrobe <= '0';
if rxstrobe = '1' then
if loading = '1' then
if loadctr = "101011" then
state <= load(343 downto 88);
data <= load(87 downto 0) & rxdata;
nonce <= x"00000000";
txdata <= "1111111111111111111111111111111111111111000000010";
txwidth <= "001010";
txstrobe <= '1';
loading <= '0';
else
load(343 downto 8) <= load(335 downto 0);
load(7 downto 0) <= rxdata;
loadctr <= loadctr + 1;
end if;
else
if rxdata = "00000000" then
txdata <= "1111111111111111111111111111111111111111000000000";
txwidth <= "001010";
txstrobe <= '1';
elsif rxdata = "00000001" then
loadctr <= "000000";
loading <= '1';
end if;
end if;
elsif hit = '1' then
txdata <= currnonce(7 downto 0) & "01" & currnonce(15 downto 8) & "01" & currnonce(23 downto 16) & "01" & currnonce(31 downto 24) & "01000000100";
txwidth <= "110010";
txstrobe <= '1';
elsif nonce = x"ffffffff" and step = "000000" then
txdata <= "1111111111111111111111111111111111111111000000110";
txwidth <= "110010";
txstrobe <= '1';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:18:21 05/28/2011
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
clk_in : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC
);
end top;
architecture Behavioral of top is
COMPONENT miner
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : IN std_logic_vector(5 downto 0);
data : IN std_logic_vector(95 downto 0);
state : IN STD_LOGIC_VECTOR (255 downto 0);
nonce : IN std_logic_vector(31 downto 0);
hit : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT(
clk : IN std_logic;
rx : IN std_logic;
txdata : IN std_logic_vector(48 downto 0);
txwidth : IN std_logic_vector(5 downto 0);
txstrobe : IN std_logic;
txbusy : OUT std_logic;
tx : OUT std_logic;
rxdata : OUT std_logic_vector(7 downto 0);
rxstrobe : OUT std_logic
);
END COMPONENT;
constant DEPTH : integer := 6;
signal clk : std_logic;
signal clk_dcmin : std_logic;
signal clk_dcmout : std_logic;
signal data : std_logic_vector(95 downto 0);
signal state : std_logic_vector(255 downto 0);
signal nonce : std_logic_vector(31 downto 0);
signal currnonce : std_logic_vector(31 downto 0);
signal load : std_logic_vector(343 downto 0);
signal loadctr : std_logic_vector(5 downto 0);
signal loading : std_logic := '0';
signal hit : std_logic;
signal txdata : std_logic_vector(48 downto 0);
signal txwidth : std_logic_vector(5 downto 0);
signal txstrobe : std_logic;
signal rxdata : std_logic_vector(7 downto 0);
signal rxstrobe : std_logic;
signal step : std_logic_vector(5 downto 0) := "000000";
begin
currnonce <= nonce - 2 * 2 ** DEPTH;
clk_buf : BUFG
port map (I=>clk_dcmout,
O=>clk);
clk_in_buf : IBUFG
port map (I=>clk_in,
O=>clk_dcmin);
dcm : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => TRUE
) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => open, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk_dcmout, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
CLKFB => '0', -- DCM clock feedback
CLKIN => clk_dcmin, -- Clock input (from IBUFG, BUFG or DCM)
RST => '0' -- DCM asynchronous reset input
);
miner0: miner
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
data => data,
state => state,
nonce => nonce,
hit => hit
);
serial: uart
port map (
clk => clk,
tx => tx,
rx => rx,
txdata => txdata,
txwidth => txwidth,
txstrobe => txstrobe,
txbusy => open,
rxdata => rxdata,
rxstrobe => rxstrobe
);
process(clk)
begin
if rising_edge(clk) then
step <= step + 1;
if conv_integer(step) = 2 ** (6 - DEPTH) - 1 then
step <= "000000";
nonce <= nonce + 1;
end if;
txdata <= "-------------------------------------------------";
txwidth <= "------";
txstrobe <= '0';
if rxstrobe = '1' then
if loading = '1' then
if loadctr = "101011" then
state <= load(343 downto 88);
data <= load(87 downto 0) & rxdata;
nonce <= x"00000000";
txdata <= "1111111111111111111111111111111111111111000000010";
txwidth <= "001010";
txstrobe <= '1';
loading <= '0';
else
load(343 downto 8) <= load(335 downto 0);
load(7 downto 0) <= rxdata;
loadctr <= loadctr + 1;
end if;
else
if rxdata = "00000000" then
txdata <= "1111111111111111111111111111111111111111000000000";
txwidth <= "001010";
txstrobe <= '1';
elsif rxdata = "00000001" then
loadctr <= "000000";
loading <= '1';
end if;
end if;
elsif hit = '1' then
txdata <= currnonce(7 downto 0) & "01" & currnonce(15 downto 8) & "01" & currnonce(23 downto 16) & "01" & currnonce(31 downto 24) & "01000000100";
txwidth <= "110010";
txstrobe <= '1';
elsif nonce = x"ffffffff" and step = "000000" then
txdata <= "1111111111111111111111111111111111111111000000110";
txwidth <= "110010";
txstrobe <= '1';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:18:21 05/28/2011
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
clk_in : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC
);
end top;
architecture Behavioral of top is
COMPONENT miner
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : IN std_logic_vector(5 downto 0);
data : IN std_logic_vector(95 downto 0);
state : IN STD_LOGIC_VECTOR (255 downto 0);
nonce : IN std_logic_vector(31 downto 0);
hit : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT(
clk : IN std_logic;
rx : IN std_logic;
txdata : IN std_logic_vector(48 downto 0);
txwidth : IN std_logic_vector(5 downto 0);
txstrobe : IN std_logic;
txbusy : OUT std_logic;
tx : OUT std_logic;
rxdata : OUT std_logic_vector(7 downto 0);
rxstrobe : OUT std_logic
);
END COMPONENT;
constant DEPTH : integer := 6;
signal clk : std_logic;
signal clk_dcmin : std_logic;
signal clk_dcmout : std_logic;
signal data : std_logic_vector(95 downto 0);
signal state : std_logic_vector(255 downto 0);
signal nonce : std_logic_vector(31 downto 0);
signal currnonce : std_logic_vector(31 downto 0);
signal load : std_logic_vector(343 downto 0);
signal loadctr : std_logic_vector(5 downto 0);
signal loading : std_logic := '0';
signal hit : std_logic;
signal txdata : std_logic_vector(48 downto 0);
signal txwidth : std_logic_vector(5 downto 0);
signal txstrobe : std_logic;
signal rxdata : std_logic_vector(7 downto 0);
signal rxstrobe : std_logic;
signal step : std_logic_vector(5 downto 0) := "000000";
begin
currnonce <= nonce - 2 * 2 ** DEPTH;
clk_buf : BUFG
port map (I=>clk_dcmout,
O=>clk);
clk_in_buf : IBUFG
port map (I=>clk_in,
O=>clk_dcmin);
dcm : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => TRUE
) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => open, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk_dcmout, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
CLKFB => '0', -- DCM clock feedback
CLKIN => clk_dcmin, -- Clock input (from IBUFG, BUFG or DCM)
RST => '0' -- DCM asynchronous reset input
);
miner0: miner
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
data => data,
state => state,
nonce => nonce,
hit => hit
);
serial: uart
port map (
clk => clk,
tx => tx,
rx => rx,
txdata => txdata,
txwidth => txwidth,
txstrobe => txstrobe,
txbusy => open,
rxdata => rxdata,
rxstrobe => rxstrobe
);
process(clk)
begin
if rising_edge(clk) then
step <= step + 1;
if conv_integer(step) = 2 ** (6 - DEPTH) - 1 then
step <= "000000";
nonce <= nonce + 1;
end if;
txdata <= "-------------------------------------------------";
txwidth <= "------";
txstrobe <= '0';
if rxstrobe = '1' then
if loading = '1' then
if loadctr = "101011" then
state <= load(343 downto 88);
data <= load(87 downto 0) & rxdata;
nonce <= x"00000000";
txdata <= "1111111111111111111111111111111111111111000000010";
txwidth <= "001010";
txstrobe <= '1';
loading <= '0';
else
load(343 downto 8) <= load(335 downto 0);
load(7 downto 0) <= rxdata;
loadctr <= loadctr + 1;
end if;
else
if rxdata = "00000000" then
txdata <= "1111111111111111111111111111111111111111000000000";
txwidth <= "001010";
txstrobe <= '1';
elsif rxdata = "00000001" then
loadctr <= "000000";
loading <= '1';
end if;
end if;
elsif hit = '1' then
txdata <= currnonce(7 downto 0) & "01" & currnonce(15 downto 8) & "01" & currnonce(23 downto 16) & "01" & currnonce(31 downto 24) & "01000000100";
txwidth <= "110010";
txstrobe <= '1';
elsif nonce = x"ffffffff" and step = "000000" then
txdata <= "1111111111111111111111111111111111111111000000110";
txwidth <= "110010";
txstrobe <= '1';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:18:21 05/28/2011
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
clk_in : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC
);
end top;
architecture Behavioral of top is
COMPONENT miner
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : IN std_logic_vector(5 downto 0);
data : IN std_logic_vector(95 downto 0);
state : IN STD_LOGIC_VECTOR (255 downto 0);
nonce : IN std_logic_vector(31 downto 0);
hit : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT(
clk : IN std_logic;
rx : IN std_logic;
txdata : IN std_logic_vector(48 downto 0);
txwidth : IN std_logic_vector(5 downto 0);
txstrobe : IN std_logic;
txbusy : OUT std_logic;
tx : OUT std_logic;
rxdata : OUT std_logic_vector(7 downto 0);
rxstrobe : OUT std_logic
);
END COMPONENT;
constant DEPTH : integer := 6;
signal clk : std_logic;
signal clk_dcmin : std_logic;
signal clk_dcmout : std_logic;
signal data : std_logic_vector(95 downto 0);
signal state : std_logic_vector(255 downto 0);
signal nonce : std_logic_vector(31 downto 0);
signal currnonce : std_logic_vector(31 downto 0);
signal load : std_logic_vector(343 downto 0);
signal loadctr : std_logic_vector(5 downto 0);
signal loading : std_logic := '0';
signal hit : std_logic;
signal txdata : std_logic_vector(48 downto 0);
signal txwidth : std_logic_vector(5 downto 0);
signal txstrobe : std_logic;
signal rxdata : std_logic_vector(7 downto 0);
signal rxstrobe : std_logic;
signal step : std_logic_vector(5 downto 0) := "000000";
begin
currnonce <= nonce - 2 * 2 ** DEPTH;
clk_buf : BUFG
port map (I=>clk_dcmout,
O=>clk);
clk_in_buf : IBUFG
port map (I=>clk_in,
O=>clk_dcmin);
dcm : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => TRUE
) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => open, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk_dcmout, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
CLKFB => '0', -- DCM clock feedback
CLKIN => clk_dcmin, -- Clock input (from IBUFG, BUFG or DCM)
RST => '0' -- DCM asynchronous reset input
);
miner0: miner
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
data => data,
state => state,
nonce => nonce,
hit => hit
);
serial: uart
port map (
clk => clk,
tx => tx,
rx => rx,
txdata => txdata,
txwidth => txwidth,
txstrobe => txstrobe,
txbusy => open,
rxdata => rxdata,
rxstrobe => rxstrobe
);
process(clk)
begin
if rising_edge(clk) then
step <= step + 1;
if conv_integer(step) = 2 ** (6 - DEPTH) - 1 then
step <= "000000";
nonce <= nonce + 1;
end if;
txdata <= "-------------------------------------------------";
txwidth <= "------";
txstrobe <= '0';
if rxstrobe = '1' then
if loading = '1' then
if loadctr = "101011" then
state <= load(343 downto 88);
data <= load(87 downto 0) & rxdata;
nonce <= x"00000000";
txdata <= "1111111111111111111111111111111111111111000000010";
txwidth <= "001010";
txstrobe <= '1';
loading <= '0';
else
load(343 downto 8) <= load(335 downto 0);
load(7 downto 0) <= rxdata;
loadctr <= loadctr + 1;
end if;
else
if rxdata = "00000000" then
txdata <= "1111111111111111111111111111111111111111000000000";
txwidth <= "001010";
txstrobe <= '1';
elsif rxdata = "00000001" then
loadctr <= "000000";
loading <= '1';
end if;
end if;
elsif hit = '1' then
txdata <= currnonce(7 downto 0) & "01" & currnonce(15 downto 8) & "01" & currnonce(23 downto 16) & "01" & currnonce(31 downto 24) & "01000000100";
txwidth <= "110010";
txstrobe <= '1';
elsif nonce = x"ffffffff" and step = "000000" then
txdata <= "1111111111111111111111111111111111111111000000110";
txwidth <= "110010";
txstrobe <= '1';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc242.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00242ent IS
END c03s01b02x00p04n01i00242ent;
ARCHITECTURE c03s01b02x00p04n01i00242arch OF c03s01b02x00p04n01i00242ent IS
type a is range (1+1) to 10.0;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00242 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00242arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc242.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00242ent IS
END c03s01b02x00p04n01i00242ent;
ARCHITECTURE c03s01b02x00p04n01i00242arch OF c03s01b02x00p04n01i00242ent IS
type a is range (1+1) to 10.0;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00242 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00242arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc242.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00242ent IS
END c03s01b02x00p04n01i00242ent;
ARCHITECTURE c03s01b02x00p04n01i00242arch OF c03s01b02x00p04n01i00242ent IS
type a is range (1+1) to 10.0;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00242 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00242arch;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Solving_Key_Equation_2
-- Module Name: Tb_Solving_Key_Equation_2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for solving_key_equation_2 circuit.
--
-- Circuit Parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
-- This file is necessary to verify if the output of this circuit is correct.
--
-- dump_sigma_memory_file :
--
-- File that will hold the output of this circuit, polynomial sigma.
--
-- syndrome_memory_file :
--
-- File that holds the syndrome that is needed to compute polynomial sigma.
--
--
-- Dependencies:
--
-- VHDL-93
--
-- solving_key_equation_2 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- ram Rev 1.0
-- ram_double Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_solving_key_equation_2 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- gf_2_m : integer range 1 to 20 := 6;
-- final_degree : integer := 4;
-- size_final_degree : integer := 2;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_qdgoppa_52_28_4_6.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_qdgoppa_52_28_4_6.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 27;
-- size_final_degree : integer := 5;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_goppa_2048_1751_27_11.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_goppa_2048_1751_27_11.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_goppa_2048_1498_50_11.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_goppa_2048_1498_50_11.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 66;
-- size_final_degree : integer := 7;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_goppa_3307_2515_66_12.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_goppa_3307_2515_66_12.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
gf_2_m : integer range 1 to 20 := 12;
final_degree : integer := 32;
size_final_degree : integer := 5;
sigma_memory_file : string := "mceliece\data_tests\sigma_qdgoppa_2528_2144_32_12.dat";
dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_qdgoppa_2528_2144_32_12.dat";
syndrome_memory_file : string := "mceliece\data_tests\syndrome_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_qdgoppa_2816_2048_64_12.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_qdgoppa_2816_2048_64_12.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_qdgoppa_3328_2560_64_12.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_qdgoppa_3328_2560_64_12.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7;
-- sigma_memory_file : string := "mceliece\data_tests\sigma_qdgoppa_7296_5632_128_13.dat";
-- dump_sigma_memory_file : string := "mceliece\data_tests\dump_sigma_qdgoppa_7296_5632_128_13.dat";
-- syndrome_memory_file : string := "mceliece\data_tests\syndrome_qdgoppa_7296_5632_128_13.dat"
);
end tb_solving_key_equation_2;
architecture Behavioral of tb_solving_key_equation_2 is
component solving_key_equation_2
Generic(
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal ready_inv : STD_LOGIC;
signal test_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_inv : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal signal_inv : STD_LOGIC;
signal key_equation_found : STD_LOGIC;
signal test_write_enable_FB : STD_LOGIC;
signal test_write_enable_GC : STD_LOGIC;
signal new_value_inv : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_address_value_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_address_value_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_address_new_value_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_address_new_value_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_value_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_value_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_new_value_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_new_value_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal write_enable_FB : STD_LOGIC;
signal write_enable_GC : STD_LOGIC;
signal true_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_address_value_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal true_address_value_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_error : STD_LOGIC;
signal dump_sigma_memory : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for syndrome_memory : ram_double use entity work.ram_double(file_load);
for test_sigma_memory : ram_double use entity work.ram_double(simple);
for true_sigma_memory : ram use entity work.ram(file_load);
begin
test : solving_key_equation_2
Generic Map(
gf_2_m => gf_2_m,
final_degree => final_degree,
size_final_degree => size_final_degree
)
Port Map(
clk => clk,
rst => rst,
ready_inv => ready_inv,
value_FB => test_value_FB,
value_GC => test_value_GC,
value_inv => value_inv,
signal_inv => signal_inv,
key_equation_found => key_equation_found,
write_enable_FB => test_write_enable_FB,
write_enable_GC => test_write_enable_GC,
new_value_inv => new_value_inv,
new_value_FB => new_value_FB,
new_value_GC => new_value_GC,
address_value_FB => test_address_value_FB,
address_value_GC => test_address_value_GC,
address_new_value_FB => test_address_new_value_FB,
address_new_value_GC => test_address_new_value_GC
);
syndrome_memory : ram_double
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => syndrome_memory_file,
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_FB,
rw_a => '0',
rw_b => test_write_enable_FB,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_FB,
address_b => address_new_value_FB,
rst_value => (others => '0'),
data_out_a => test_value_FB,
data_out_b => open
);
test_sigma_memory : ram_double
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_sigma_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_GC,
rw_a => '0',
rw_b => write_enable_GC,
clk => clk,
rst => rst,
dump => dump_sigma_memory,
address_a => address_value_GC,
address_b => address_new_value_GC,
rst_value => (others => '0'),
data_out_a => test_value_GC,
data_out_b => open
);
true_sigma_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_value_GC,
rst_value => (others => '0'),
data_out => true_value_GC
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => new_value_inv,
flag => signal_inv,
clk => clk,
oflag => ready_inv,
o => value_inv
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
address_value_FB <= true_address_value_FB when key_equation_found = '1' else test_address_value_FB;
address_value_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_value_GC'length) + unsigned(true_address_value_GC)) when key_equation_found = '1' else test_address_value_GC;
address_new_value_FB <= test_address_new_value_FB;
address_new_value_GC <= test_address_new_value_GC;
write_enable_FB <= '0' when key_equation_found = '1' else test_write_enable_FB;
write_enable_GC <= '0' when key_equation_found = '1' else test_write_enable_GC;
process
variable i : integer;
begin
true_address_value_FB <= (others => '0');
true_address_value_GC <= (others => '0');
rst <= '1';
test_error <= '0';
dump_sigma_memory <= '0';
wait for PERIOD*2;
rst <= '0';
wait until key_equation_found = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (final_degree + 1)) loop
true_address_value_FB <= std_logic_vector(to_unsigned(i, true_address_value_FB'Length));
true_address_value_GC <= std_logic_vector(to_unsigned(i, true_address_value_GC'Length));
wait for PERIOD*2;
if (true_value_GC = test_value_GC) then
test_error <= '0';
else
test_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
test_error <= '0';
wait for PERIOD;
i := i + 1;
end loop;
dump_sigma_memory <= '1';
wait for PERIOD;
dump_sigma_memory <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ALUN is
generic(N : natural := 8);
port( a, b : in std_logic_vector(N-1 downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector(N-1 downto 0);
r2 : out std_logic_vector(N-1 downto 0));
end ALUN;
architecture Behavioral of ALUN is
signal s_a, s_b, s_r : unsigned(N-1 downto 0);
signal s_m : unsigned((2*N)-1 downto 0);
begin
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= (s_a + s_b) when "000",
(s_a - s_b) when "001",
s_m(N-1 downto 0) when "010",
(s_a / s_b) when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m((2*N)-1 downto 4)) when (op = "010") else
(others => '0');
r2 <= r;
end Behavioral; |
architecture RTl of FIFO is
component fifo is
end component FIFO;
-- Failures below
component fifo is
end component FIFO;
component fifo is
end component FIFO;
begin
end architecture RTL;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: frmmem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY frmmem IS
PORT
(
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rdclocken : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wrclocken : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END frmmem;
ARCHITECTURE SYN OF frmmem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
BEGIN
q <= sub_wire0(8 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 61440,
numwords_b => 61440,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 16,
widthad_b => 16,
width_a => 9,
width_b => 9,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => wrclock,
clock1 => rdclock,
clocken0 => wrclocken,
clocken1 => rdclocken,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "552960"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "61440"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "61440"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 16 0 INPUT NODEFVAL "rdaddress[15..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken"
-- Retrieval info: USED_PORT: wraddress 0 0 16 0 INPUT NODEFVAL "wraddress[15..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wrclocken 0 0 0 0 INPUT VCC "wrclocken"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 wraddress 0 0 16 0
-- Retrieval info: CONNECT: @address_b 0 0 16 0 rdaddress 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 wrclocken 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_kalman_final is
port
( clock : in std_logic;
Uofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
pofk : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end k_kalman_final;
architecture struct of k_kalman_final is
component kn_kalman_Vactcapdashofkplusone is
port
( clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Pdashofkplusone is
port
( clock : in std_logic;
Pofk : in std_logic_vector(31 downto 0);
Q : in std_logic_vector(31 downto 0);
Pdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Kofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
R : in std_logic_vector(31 downto 0);
Kofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Pofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Vactcapofkplusone is
port
( clock : in std_logic;
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end component;
signal I1 : std_logic_vector (31 downto 0) := "00111101010011001100110011001101";
signal I2 : std_logic_vector (31 downto 0) := "00111100001000111101011100001010";
signal I3 : std_logic_vector (31 downto 0) := "00111000110100011011011100010111";
signal X1,X2,X3 : std_logic_vector (31 downto 0);
begin
M1 : kn_kalman_Vactcapdashofkplusone
port map ( clock => clock,
Vactcapofk => Vactcapofk,
M => I1,
Uofk => Uofk,
Vactcapdashofkplusone => X1 );
M2 : kn_kalman_Pdashofkplusone
port map ( clock => clock,
Pofk => Pofk,
Q => I2,
Pdashofkplusone => X2 );
M3 : kn_kalman_Kofkplusone
port map ( clock => clock,
Pdashofkplusone => X2,
R => I3,
Kofkplusone => X3 );
M4 : kn_kalman_Pofkplusone
port map ( clock => clock,
Pdashofkplusone => X2,
Kofkplusone => X3,
Pofkplusone => Pofkplusone );
M5 : kn_kalman_Vactcapofkplusone
port map ( clock => clock,
Vactcapdashofkplusone => X1,
Vrefofkplusone => Vrefofkplusone,
Kofkplusone => X3,
Vactcapofkplusone => Vactcapofkplusone );
end struct; |
-- Revision history:
-- 2015-08-12 Lukas Jaeger created
-- 2015-08-14 Lukas Jaeger added test cases
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.cpu_pack.all;
entity tb_fsm_pl is
end entity tb_fsm_pl;
architecture behav_tb_fsm of tb_fsm_pl is
component control_pipeline
port(
clk : in std_logic;
rst : in std_logic;
rd_mask : out std_logic_vector(3 downto 0);
wr_mask : out std_logic_vector(3 downto 0);
instr_stall : in std_logic;
data_stall : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
alu_op : out std_logic_vector(5 downto 0);
exc_mux1 : out std_logic_vector(1 downto 0);
exc_mux2 : out std_logic_vector(1 downto 0);
exc_alu_zero : in std_logic_vector(0 downto 0);
memstg_mux : out std_logic;
id_regdest_mux : out std_logic_vector (1 downto 0);
id_regshift_mux : out std_logic_vector (1 downto 0);
id_enable_regs : out std_logic;
in_mux_pc : out std_logic;
stage_control : out std_logic_vector (4 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal instr_in : std_logic_vector (31 downto 0);
signal instr_stall : std_logic;
signal data_stall : std_logic;
signal in_go : std_logic;
signal exc_alu_zero: std_logic_vector(0 downto 0);
signal stage_control : std_logic_vector (4 downto 0);
constant clk_time : time := 10 ns;
begin
dut: control_pipeline port map(
clk => clk,
rst => rst,
instr_in => instr_in,
instr_stall => instr_stall,
data_stall => data_stall,
exc_alu_zero => exc_alu_zero
);
instr_stall <= '0';
data_stall <= '0';
clk_proc : process
begin
clk <= '0';
wait for clk_time / 2;
clk <= '1';
wait for clk_time / 2;
end process;
test_proc : process
begin
instr_in <= x"00000000";
rst <= '1';
wait for clk_time / 2;
rst <= '0';
wait for clk_time / 2;
-- Inserting J-Type-instruction
-- To test:
-- id_regdest_mux : 10
-- id_regshift_mux : 00
-- id_enable_regs : 0
-- exc_mux1 : 10
-- exc_mux2 : 00
-- alu_op : 000100
-- memstg_mux: 0
-- rd_mask: 0000
-- wr_mask: 0000
-- pc_mux: 1
instr_in <= x"0FFFFFFF";
wait for clk_time;
-- Inserting I-Type_instruction (addiu v0, v0, 1)
-- To test:
-- id_regdest_mux: 10
-- id_regshift_mux: 00
-- id_enable_regs: 0
-- exc_mux1: 10
-- exc_mux2: 00
-- alu_op: 000100
-- memstg_mux: 0
-- rd_mask: 0000
-- wr_mask: 0000
-- pc_mux: 0
instr_in <= x"24420001";
wait for clk_time;
-- Inserting LW v0 -32756(gp)
-- To test:
-- id_regdest_mux: 10
-- id_regshift_mux: 00
-- id_enable_regs : 00
-- exc_mux1: 10
-- exc_mux2: 01
-- alu_op: 100000
-- memstg_mux: 0
-- rd_mask : 0000
-- wr_mask : 0000
-- pc_mux : 0
instr_in <= x"8f82800c";
wait for clk_time;
-- Inserting LBU v0, 0(v1)
-- To test:
-- id_regdest_mux: 10
-- id_regshift_mux: 00
-- id_enable_regs: 0
-- exc_mux1: 10
-- exc_mux2: 01
-- alu_op: 100000
-- rd_mask : 0000
-- wr_mask : 0000
-- memstg_mux: 0
-- pc_mux: 0
instr_in <= x"90620000";
wait for clk_time;
-- Inserting SW zero -32756(gp)
-- To test:
-- id_regdest_mux: 10
-- id_regshift_mux: 00
-- id_enable_regs: 1
-- exc_mux1: 10
-- exc_mux2: 01
-- alu_op: 100000
-- memstg_mux: 1
-- in_mux_pc: 0
instr_in <= x"af80800c";
wait for clk_time;
-- Inserting sb, zero 0(v0)
-- To test:
-- id_regdest_mux: 10
-- id_regshift_mux: 00
-- id_enable_regs: 1
-- exc_mux1: 10
-- exc_mux2: 01
-- alu_op: 100000
-- memstg_mux: 1
-- in_mux_pc: 0
instr_in <= x"a0400000";
wait for clk_time;
-- To test:
-- id_regdest_mux: 00
-- id_regshift_mux: 00
-- id_enable_regs: 1
-- exc_mux1: 10
-- exc_mux2: 01
-- alu_op: 100000
-- memstg_mux: 0
-- in_mux_pc: 0
instr_in <= x"00000000";
wait for clk_time;
-- To test:
-- id_regdest_mux: 00
-- id_regshift_mux: 00
-- id_enable_regs: 0
-- exc_mux1: 10
-- exc_mux2: 00
-- alu_op: 000100
-- memstg_mux: 0
-- in_mux_pc: 0
instr_in <= x"00000000";
wait for clk_time;
end process;
end architecture; |
package NameStorePkg is
subtype integer_max is integer;
type NameIDType is record
ID : integer_max ;
end record NameIDType ;
type NameStorePType is protected
impure function Get (ID : integer ; DefaultName : string := "") return string ;
end protected NameStorePType ;
end package NameStorePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body NameStorePkg is
type NameStorePType is protected body
------------------------------------------------------------
impure function Get (ID : integer ; DefaultName : string := "") return string is
------------------------------------------------------------
begin
return DefaultName;
end function Get ;
end protected body NameStorePType ;
shared variable NameStore : NameStorePType ;
------------------------------------------------------------
impure function GetOpt (ID : NameIDType) return string is
------------------------------------------------------------
begin
return NameStore.Get(ID.ID) ;
end function GetOpt ;
end package body NameStorePkg ;
|
-- NEED RESULT: ARCH00383.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00383
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00383(ARCH00383)
-- ENT00383_Test_Bench(ARCH00383_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00383 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00383 ;
--
--
architecture ARCH00383 of ENT00383 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns
when 3,
--
c_boolean_1 after 100 ns
when 4,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_boolean_1 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns
when 3,
--
c_bit_1 after 100 ns
when 4,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_bit_1 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns
when 3,
--
c_severity_level_1 after 100 ns
when 4,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns
when 3,
--
c_character_1 after 100 ns
when 4,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_character_1 after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns
when 3,
--
c_st_enum1_1 after 100 ns
when 4,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns
when 3,
--
c_integer_1 after 100 ns
when 4,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_integer_1 after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns
when 3,
--
c_st_int1_1 after 100 ns
when 4,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns
when 3,
--
c_time_1 after 100 ns
when 4,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_time_1 after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns
when 3,
--
c_st_phys1_1 after 100 ns
when 4,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns
when 3,
--
c_real_1 after 100 ns
when 4,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_real_1 after 40 ns when 6 ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns
when 3,
--
c_st_real1_1 after 100 ns
when 4,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns when 6 ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns
when 3,
--
c_st_rec1_1 after 100 ns
when 4,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns when 6 ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns
when 3,
--
c_st_rec2_1 after 100 ns
when 4,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns when 6 ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns
when 3,
--
c_st_rec3_1 after 100 ns
when 4,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns when 6 ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns
when 3,
--
c_st_arr1_1 after 100 ns
when 4,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns when 6 ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns
when 3,
--
c_st_arr2_1 after 100 ns
when 4,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns when 6 ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns
when 3,
--
c_st_arr3_1 after 100 ns
when 4,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns when 6 ;
--
end ARCH00383 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00383_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00383_Test_Bench ;
--
--
architecture ARCH00383_Test_Bench of ENT00383_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00383 ( ARCH00383 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00383_Test_Bench ;
|
package foo is
group G1: RESOURCE (L1, L2); -- A group of two labels.
group G2: RESOURCE (L3, L4, L5); -- A group of three labels.
group C2Q: PIN2PIN (PROJECT.GLOBALS.CK, Q);
-- Groups may associate named
-- entities in different declarative
-- parts (and regions).
group CONSTRAINT1: DIFF_CYCLES (G1, G3); -- A group of groups.
end;
|
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity decis_levl is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end decis_levl;
architecture augh of decis_levl is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", "00000000000000000000001101110000", "00000000000000000000010010110000", "00000000000000000000010111110000", "00000000000000000000011101001000", "00000000000000000000100010100000", "00000000000000000000101000011000", "00000000000000000000101110010000", "00000000000000000000110100110000", "00000000000000000000111011001000", "00000000000000000001000010010000", "00000000000000000001001001011000", "00000000000000000001010001010000", "00000000000000000001011001010000", "00000000000000000001100010010000", "00000000000000000001101011010000", "00000000000000000001110101100000", "00000000000000000001111111111000", "00000000000000000010001100001000", "00000000000000000010011000011000", "00000000000000000010100111011000", "00000000000000000010110110010000", "00000000000000000011001001100000", "00000000000000000011011100101000", "00000000000000000011110111100000", "00000000000000000100010010011000", "00000000000000000100111111101000", "00000000000000000101101100111000", "00000000000000000111111111111111", "00000000000000000000000000000000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity decis_levl is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end decis_levl;
architecture augh of decis_levl is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", "00000000000000000000001101110000", "00000000000000000000010010110000", "00000000000000000000010111110000", "00000000000000000000011101001000", "00000000000000000000100010100000", "00000000000000000000101000011000", "00000000000000000000101110010000", "00000000000000000000110100110000", "00000000000000000000111011001000", "00000000000000000001000010010000", "00000000000000000001001001011000", "00000000000000000001010001010000", "00000000000000000001011001010000", "00000000000000000001100010010000", "00000000000000000001101011010000", "00000000000000000001110101100000", "00000000000000000001111111111000", "00000000000000000010001100001000", "00000000000000000010011000011000", "00000000000000000010100111011000", "00000000000000000010110110010000", "00000000000000000011001001100000", "00000000000000000011011100101000", "00000000000000000011110111100000", "00000000000000000100010010011000", "00000000000000000100111111101000", "00000000000000000101101100111000", "00000000000000000111111111111111", "00000000000000000000000000000000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity decis_levl is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end decis_levl;
architecture augh of decis_levl is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", "00000000000000000000001101110000", "00000000000000000000010010110000", "00000000000000000000010111110000", "00000000000000000000011101001000", "00000000000000000000100010100000", "00000000000000000000101000011000", "00000000000000000000101110010000", "00000000000000000000110100110000", "00000000000000000000111011001000", "00000000000000000001000010010000", "00000000000000000001001001011000", "00000000000000000001010001010000", "00000000000000000001011001010000", "00000000000000000001100010010000", "00000000000000000001101011010000", "00000000000000000001110101100000", "00000000000000000001111111111000", "00000000000000000010001100001000", "00000000000000000010011000011000", "00000000000000000010100111011000", "00000000000000000010110110010000", "00000000000000000011001001100000", "00000000000000000011011100101000", "00000000000000000011110111100000", "00000000000000000100010010011000", "00000000000000000100111111101000", "00000000000000000101101100111000", "00000000000000000111111111111111", "00000000000000000000000000000000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_dEe_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_dEe_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 to 73=> "00000000", 74 to 91=> "00000001", 92 to 101=> "00000010", 102 to 108=> "00000011",
109 to 113=> "00000100", 114 to 118=> "00000101", 119 to 122=> "00000110", 123 to 125=> "00000111",
126 to 129=> "00001000", 130 to 132=> "00001001", 133 to 134=> "00001010", 135 to 137=> "00001011",
138 to 139=> "00001100", 140 to 141=> "00001101", 142 to 143=> "00001110", 144 to 145=> "00001111",
146 to 147=> "00010000", 148 to 149=> "00010001", 150 => "00010010", 151 to 152=> "00010011",
153 to 154=> "00010100", 155 => "00010101", 156 => "00010110", 157 to 158=> "00010111",
159 => "00011000", 160 => "00011001", 161 to 162=> "00011010", 163 => "00011011",
164 => "00011100", 165 => "00011101", 166 => "00011110", 167 => "00011111",
168 => "00100000", 169 => "00100001", 170 => "00100010", 171 => "00100011",
172 => "00100100", 173 => "00100101", 174 => "00100110", 175 => "00100111",
176 => "00101000", 177 => "00101001", 178 => "00101010", 179 => "00101011",
180 => "00101101", 181 => "00101110", 182 => "00101111", 183 => "00110001",
184 => "00110010", 185 => "00110011", 186 => "00110101", 187 => "00110110",
188 => "00111000", 189 => "00111001", 190 => "00111011", 191 => "00111100",
192 => "00111110", 193 => "00111111", 194 => "01000001", 195 => "01000011",
196 => "01000100", 197 => "01000110", 198 => "01001000", 199 => "01001010",
200 => "01001100", 201 => "01001110", 202 => "01010000", 203 => "01010010",
204 => "01010100", 205 => "01010110", 206 => "01011000", 207 => "01011010",
208 => "01011100", 209 => "01011110", 210 => "01100001", 211 => "01100011",
212 => "01100101", 213 => "01101000", 214 => "01101010", 215 => "01101101",
216 => "01101111", 217 => "01110010", 218 => "01110100", 219 => "01110111",
220 => "01111010", 221 => "01111101", 222 => "10000000", 223 => "10000010",
224 => "10000101", 225 => "10001000", 226 => "10001011", 227 => "10001111",
228 => "10010010", 229 => "10010101", 230 => "10011000", 231 => "10011100",
232 => "10011111", 233 => "10100010", 234 => "10100110", 235 => "10101010",
236 => "10101101", 237 => "10110001", 238 => "10110101", 239 => "10111000",
240 => "10111100", 241 => "11000000", 242 => "11000100", 243 => "11001000",
244 => "11001101", 245 => "11010001", 246 => "11010101", 247 => "11011001",
248 => "11011110", 249 => "11100010", 250 => "11100111", 251 => "11101100",
252 => "11110000", 253 => "11110101", 254 => "11111010", 255 => "11111111" );
signal mem1 : mem_array := (
0 to 73=> "00000000", 74 to 91=> "00000001", 92 to 101=> "00000010", 102 to 108=> "00000011",
109 to 113=> "00000100", 114 to 118=> "00000101", 119 to 122=> "00000110", 123 to 125=> "00000111",
126 to 129=> "00001000", 130 to 132=> "00001001", 133 to 134=> "00001010", 135 to 137=> "00001011",
138 to 139=> "00001100", 140 to 141=> "00001101", 142 to 143=> "00001110", 144 to 145=> "00001111",
146 to 147=> "00010000", 148 to 149=> "00010001", 150 => "00010010", 151 to 152=> "00010011",
153 to 154=> "00010100", 155 => "00010101", 156 => "00010110", 157 to 158=> "00010111",
159 => "00011000", 160 => "00011001", 161 to 162=> "00011010", 163 => "00011011",
164 => "00011100", 165 => "00011101", 166 => "00011110", 167 => "00011111",
168 => "00100000", 169 => "00100001", 170 => "00100010", 171 => "00100011",
172 => "00100100", 173 => "00100101", 174 => "00100110", 175 => "00100111",
176 => "00101000", 177 => "00101001", 178 => "00101010", 179 => "00101011",
180 => "00101101", 181 => "00101110", 182 => "00101111", 183 => "00110001",
184 => "00110010", 185 => "00110011", 186 => "00110101", 187 => "00110110",
188 => "00111000", 189 => "00111001", 190 => "00111011", 191 => "00111100",
192 => "00111110", 193 => "00111111", 194 => "01000001", 195 => "01000011",
196 => "01000100", 197 => "01000110", 198 => "01001000", 199 => "01001010",
200 => "01001100", 201 => "01001110", 202 => "01010000", 203 => "01010010",
204 => "01010100", 205 => "01010110", 206 => "01011000", 207 => "01011010",
208 => "01011100", 209 => "01011110", 210 => "01100001", 211 => "01100011",
212 => "01100101", 213 => "01101000", 214 => "01101010", 215 => "01101101",
216 => "01101111", 217 => "01110010", 218 => "01110100", 219 => "01110111",
220 => "01111010", 221 => "01111101", 222 => "10000000", 223 => "10000010",
224 => "10000101", 225 => "10001000", 226 => "10001011", 227 => "10001111",
228 => "10010010", 229 => "10010101", 230 => "10011000", 231 => "10011100",
232 => "10011111", 233 => "10100010", 234 => "10100110", 235 => "10101010",
236 => "10101101", 237 => "10110001", 238 => "10110101", 239 => "10111000",
240 => "10111100", 241 => "11000000", 242 => "11000100", 243 => "11001000",
244 => "11001101", 245 => "11010001", 246 => "11010101", 247 => "11011001",
248 => "11011110", 249 => "11100010", 250 => "11100111", 251 => "11101100",
252 => "11110000", 253 => "11110101", 254 => "11111010", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_dEe is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_dEe is
component Loop_loop_height_dEe_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_dEe_rom_U : component Loop_loop_height_dEe_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
entity issue187 is
end entity;
architecture a of issue187 is
function expensive_function_returning_false return boolean is
begin
report "This cost much";
return false;
end function;
begin
main : process
begin
assert (not (expensive_function_returning_false or expensive_function_returning_false));
wait;
end process;
end architecture;
|
entity issue187 is
end entity;
architecture a of issue187 is
function expensive_function_returning_false return boolean is
begin
report "This cost much";
return false;
end function;
begin
main : process
begin
assert (not (expensive_function_returning_false or expensive_function_returning_false));
wait;
end process;
end architecture;
|
entity issue187 is
end entity;
architecture a of issue187 is
function expensive_function_returning_false return boolean is
begin
report "This cost much";
return false;
end function;
begin
main : process
begin
assert (not (expensive_function_returning_false or expensive_function_returning_false));
wait;
end process;
end architecture;
|
entity issue187 is
end entity;
architecture a of issue187 is
function expensive_function_returning_false return boolean is
begin
report "This cost much";
return false;
end function;
begin
main : process
begin
assert (not (expensive_function_returning_false or expensive_function_returning_false));
wait;
end process;
end architecture;
|
entity issue187 is
end entity;
architecture a of issue187 is
function expensive_function_returning_false return boolean is
begin
report "This cost much";
return false;
end function;
begin
main : process
begin
assert (not (expensive_function_returning_false or expensive_function_returning_false));
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1998.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i01998ent IS
END c07s02b02x00p07n02i01998ent;
ARCHITECTURE c07s02b02x00p07n02i01998arch OF c07s02b02x00p07n02i01998ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m = 5.5) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i01998"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i01998 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i01998arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1998.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i01998ent IS
END c07s02b02x00p07n02i01998ent;
ARCHITECTURE c07s02b02x00p07n02i01998arch OF c07s02b02x00p07n02i01998ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m = 5.5) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i01998"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i01998 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i01998arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1998.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i01998ent IS
END c07s02b02x00p07n02i01998ent;
ARCHITECTURE c07s02b02x00p07n02i01998arch OF c07s02b02x00p07n02i01998ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m = 5.5) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i01998"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i01998 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i01998arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue May 09 14:50:53 2017
-- Host : DESKTOP-7MUQLTN running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Kiwi/Desktop/Projet_VHDL_-_Paint/04_IP_Xillinx/Clk_Wizard/Clk_Wizard_sim_netlist.vhdl
-- Design : Clk_Wizard
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Clk_Wizard_Clk_Wizard_clk_wiz is
port (
VGA_clock : out STD_LOGIC;
Main_clock : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
Clock_Board : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Clk_Wizard_Clk_Wizard_clk_wiz : entity is "Clk_Wizard_clk_wiz";
end Clk_Wizard_Clk_Wizard_clk_wiz;
architecture STRUCTURE of Clk_Wizard_Clk_Wizard_clk_wiz is
signal Clock_Board_Clk_Wizard : STD_LOGIC;
signal Main_clock_Clk_Wizard : STD_LOGIC;
signal VGA_clock_Clk_Wizard : STD_LOGIC;
signal clkfbout_Clk_Wizard : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => Clock_Board,
O => Clock_Board_Clk_Wizard
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => VGA_clock_Clk_Wizard,
O => VGA_clock
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => Main_clock_Clk_Wizard,
O => Main_clock
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 21.875000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.125000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 11,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 2,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_Clk_Wizard,
CLKFBOUT => clkfbout_Clk_Wizard,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => Clock_Board_Clk_Wizard,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => VGA_clock_Clk_Wizard,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => Main_clock_Clk_Wizard,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Clk_Wizard is
port (
VGA_clock : out STD_LOGIC;
Main_clock : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
Clock_Board : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Clk_Wizard : entity is true;
end Clk_Wizard;
architecture STRUCTURE of Clk_Wizard is
begin
inst: entity work.Clk_Wizard_Clk_Wizard_clk_wiz
port map (
Clock_Board => Clock_Board,
Main_clock => Main_clock,
VGA_clock => VGA_clock,
locked => locked,
resetn => resetn
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1808.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01808ent IS
END c07s01b00x00p07n01i01808ent;
ARCHITECTURE c07s01b00x00p07n01i01808arch OF c07s01b00x00p07n01i01808ent IS
signal POS : integer;
signal P1 : integer := -2;
BEGIN
TESTING: PROCESS
BEGIN
POS <= abs P1 after 20 ns;
wait for 35 ns;
assert NOT(POS = 2)
report "***PASSED TEST: c07s01b00x00p07n01i01808"
severity NOTE;
assert (POS = 2)
report "***FAILED TEST: c07s01b00x00p07n01i01808 - abs Primary test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01808arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1808.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01808ent IS
END c07s01b00x00p07n01i01808ent;
ARCHITECTURE c07s01b00x00p07n01i01808arch OF c07s01b00x00p07n01i01808ent IS
signal POS : integer;
signal P1 : integer := -2;
BEGIN
TESTING: PROCESS
BEGIN
POS <= abs P1 after 20 ns;
wait for 35 ns;
assert NOT(POS = 2)
report "***PASSED TEST: c07s01b00x00p07n01i01808"
severity NOTE;
assert (POS = 2)
report "***FAILED TEST: c07s01b00x00p07n01i01808 - abs Primary test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01808arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1808.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01808ent IS
END c07s01b00x00p07n01i01808ent;
ARCHITECTURE c07s01b00x00p07n01i01808arch OF c07s01b00x00p07n01i01808ent IS
signal POS : integer;
signal P1 : integer := -2;
BEGIN
TESTING: PROCESS
BEGIN
POS <= abs P1 after 20 ns;
wait for 35 ns;
assert NOT(POS = 2)
report "***PASSED TEST: c07s01b00x00p07n01i01808"
severity NOTE;
assert (POS = 2)
report "***FAILED TEST: c07s01b00x00p07n01i01808 - abs Primary test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01808arch;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_increment_decrement_load_rst_n_bits
-- Module Name: Counter_increment_decrement_load_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that can increment or decrements
-- when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1 and reset is 0.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle, when increment_decrement = 0.
--
-- decrement_value :
--
-- The amount will be decremented each cycle, when increment_decrement = 1.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_increment_decrement_load_rst_nbits is
Generic(
size : integer;
increment_value : integer;
decrement_value : integer
);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
increment_decrement : STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_increment_decrement_load_rst_nbits;
architecture Behavioral of counter_increment_decrement_load_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, load, increment_decrement, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
elsif(increment_decrement = '1') then
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
else
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity repro3 is
port (
i : in std_ulogic_vector(1 downto 0);
o : out std_ulogic_vector (3 downto 0)
);
end entity repro3;
architecture behav of repro3 is
function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is
begin
case v is
when "01" =>
null;
when others =>
return "0000";
end case;
return "1111";
end;
begin
o <= func (i);
end architecture behav;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb1.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb1 is
end entity Task4_ent_tb1;
architecture Task4_arch_tb1 of Task4_ent_tb1 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all states of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
-- Test length 5
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb1;
configuration Task4_cfg_tb1 of Task4_ent_tb1 is
for Task4_arch_tb1
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb1;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb1.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb1 is
end entity Task4_ent_tb1;
architecture Task4_arch_tb1 of Task4_ent_tb1 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all states of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
-- Test length 5
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb1;
configuration Task4_cfg_tb1 of Task4_ent_tb1 is
for Task4_arch_tb1
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb1;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiv_atom_pack.all;
package cycloneiv_components is
--
-- cycloneiv_lcell_comb
--
COMPONENT cycloneiv_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_routing_wire
--
COMPONENT cycloneiv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_ff
--
COMPONENT cycloneiv_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- cycloneiv_ram_block
--
COMPONENT cycloneiv_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_mac_mult
--
COMPONENT cycloneiv_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_mac_out
--
COMPONENT cycloneiv_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiv_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_io_ibuf
--
COMPONENT cycloneiv_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- cycloneiv_io_obuf
--
COMPONENT cycloneiv_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiv_ddio_oe
--
COMPONENT cycloneiv_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_ddio_out
--
COMPONENT cycloneiv_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_io_pad
--
COMPONENT cycloneiv_io_pad
GENERIC (
lpm_type : string := "cycloneiv_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- cycloneiv_clkctrl
--
COMPONENT cycloneiv_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiv_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- cycloneiv_pseudo_diff_out
--
COMPONENT cycloneiv_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiv_rublock
--
COMPONENT cycloneiv_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
sim_init_config_is_application : string := "false";
sim_init_watchdog_enabled : string := "false";
operation_mode : string := "active_serial_remote";
lpm_type : string := "cycloneiv_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_termination
--
COMPONENT cycloneiv_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- cycloneiv_jtag
--
COMPONENT cycloneiv_jtag
generic (
lpm_type : string := "cycloneiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneiv_crcblock
--
COMPONENT cycloneiv_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_oscillator
--
COMPONENT cycloneiv_oscillator
generic
(
lpm_type: string := "cycloneiv_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
observableoutputport: out std_logic;
clkout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_controller
--
COMPONENT cycloneiv_controller
generic
(
lpm_type: string := "cycloneiv_controller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_pll
--
COMPONENT cycloneiv_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
feedback_source : integer := 0;
feedback_external_loop_divider : string := "false";
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 1;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiv_pll";
lpm_hint : string := "unused";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
family_name : string := "Cyclone IV GX";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fref : out std_logic;
icdrclk : out std_logic
);
END COMPONENT;
end cycloneiv_components;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end BoothPartProdRed;
architecture Behavioral of BoothPartProdRed is
COMPONENT HAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
END COMPONENT;
COMPONENT FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
COMPONENT Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
END COMPONENT;
SIGNAL tempS1: STD_LOGIC_VECTOR(24 downto 2);
SIGNAL tempC1: STD_LOGIC_VECTOR(23 downto 3);
SIGNAL ctemp1: STD_LOGIC_VECTOR(21 downto 7);
SIGNAL tempS2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempC2: STD_LOGIC_VECTOR(31 downto 11);
SIGNAL ctemp2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempS3: STD_LOGIC_VECTOR(31 downto 3);
SIGNAL tempC3: STD_LOGIC_VECTOR(32 downto 4);
SIGNAL ctemp3: STD_LOGIC_VECTOR(25 downto 12);
begin
result(1 downto 0) <= prod0(1 downto 0);
result(2) <= tempS1(2);
tempS2(9 downto 8) <= prod4(9 downto 8);
tempS1(24 downto 23) <= prod3(24 downto 23);
tempS2(31) <= prod7(31);
result(3) <= tempS3(3);
result(31 downto 4) <= std_logic_vector(unsigned(tempS3(31 downto 4)) + unsigned(tempC3(31 downto 4)));
mainfor: FOR index in 2 to 31 GENERATE
if1_2to3:IF index >= 2 and index <= 3 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_4to5:IF index >= 4 and index <= 5 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
c=>prod2(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_6:IF index = 6 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => '0',
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_7tp19:IF index >= 7 and index <= 19 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_20:IF index = 20 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_21:IF index = 21 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp1(index),
b=>prod2(index),
c=>prod3(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_22:IF index = 22 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod2(index),
b=>prod3(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_10to11:IF index >= 10 and index <= 11 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if1_12to13:IF index >= 12 and index <= 13 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
c=>prod6(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_14:IF index = 14 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => '0',
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_15to26:IF index >= 15 and index <= 26 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_27to28:IF index >= 27 and index <= 28 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_29:IF index = 29 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp2(index),
b=>prod6(index),
c=>prod7(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_30:IF index = 30 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod6(index),
b=>prod7(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if2_3to7:IF index >= 3 and index <= 7 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
if2_8to10:IF index >= 8 and index <= 10 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
c=>tempS2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_11:IF index = 11 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => '0',
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_12to23:IF index >= 12 and index <= 23 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_24:IF index = 24 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => '0',
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_25:IF index = 25 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp3(index),
b=>tempS2(index),
c=>tempC2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_26to31:IF index >= 26 and index <= 31 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS2(index),
b=>tempC2(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
END GENERATE;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end BoothPartProdRed;
architecture Behavioral of BoothPartProdRed is
COMPONENT HAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
END COMPONENT;
COMPONENT FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
COMPONENT Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
END COMPONENT;
SIGNAL tempS1: STD_LOGIC_VECTOR(24 downto 2);
SIGNAL tempC1: STD_LOGIC_VECTOR(23 downto 3);
SIGNAL ctemp1: STD_LOGIC_VECTOR(21 downto 7);
SIGNAL tempS2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempC2: STD_LOGIC_VECTOR(31 downto 11);
SIGNAL ctemp2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempS3: STD_LOGIC_VECTOR(31 downto 3);
SIGNAL tempC3: STD_LOGIC_VECTOR(32 downto 4);
SIGNAL ctemp3: STD_LOGIC_VECTOR(25 downto 12);
begin
result(1 downto 0) <= prod0(1 downto 0);
result(2) <= tempS1(2);
tempS2(9 downto 8) <= prod4(9 downto 8);
tempS1(24 downto 23) <= prod3(24 downto 23);
tempS2(31) <= prod7(31);
result(3) <= tempS3(3);
result(31 downto 4) <= std_logic_vector(unsigned(tempS3(31 downto 4)) + unsigned(tempC3(31 downto 4)));
mainfor: FOR index in 2 to 31 GENERATE
if1_2to3:IF index >= 2 and index <= 3 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_4to5:IF index >= 4 and index <= 5 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
c=>prod2(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_6:IF index = 6 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => '0',
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_7tp19:IF index >= 7 and index <= 19 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_20:IF index = 20 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_21:IF index = 21 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp1(index),
b=>prod2(index),
c=>prod3(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_22:IF index = 22 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod2(index),
b=>prod3(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_10to11:IF index >= 10 and index <= 11 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if1_12to13:IF index >= 12 and index <= 13 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
c=>prod6(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_14:IF index = 14 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => '0',
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_15to26:IF index >= 15 and index <= 26 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_27to28:IF index >= 27 and index <= 28 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_29:IF index = 29 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp2(index),
b=>prod6(index),
c=>prod7(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_30:IF index = 30 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod6(index),
b=>prod7(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if2_3to7:IF index >= 3 and index <= 7 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
if2_8to10:IF index >= 8 and index <= 10 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
c=>tempS2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_11:IF index = 11 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => '0',
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_12to23:IF index >= 12 and index <= 23 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_24:IF index = 24 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => '0',
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_25:IF index = 25 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp3(index),
b=>tempS2(index),
c=>tempC2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_26to31:IF index >= 26 and index <= 31 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS2(index),
b=>tempC2(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
END GENERATE;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end BoothPartProdRed;
architecture Behavioral of BoothPartProdRed is
COMPONENT HAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
END COMPONENT;
COMPONENT FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
COMPONENT Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
END COMPONENT;
SIGNAL tempS1: STD_LOGIC_VECTOR(24 downto 2);
SIGNAL tempC1: STD_LOGIC_VECTOR(23 downto 3);
SIGNAL ctemp1: STD_LOGIC_VECTOR(21 downto 7);
SIGNAL tempS2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempC2: STD_LOGIC_VECTOR(31 downto 11);
SIGNAL ctemp2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempS3: STD_LOGIC_VECTOR(31 downto 3);
SIGNAL tempC3: STD_LOGIC_VECTOR(32 downto 4);
SIGNAL ctemp3: STD_LOGIC_VECTOR(25 downto 12);
begin
result(1 downto 0) <= prod0(1 downto 0);
result(2) <= tempS1(2);
tempS2(9 downto 8) <= prod4(9 downto 8);
tempS1(24 downto 23) <= prod3(24 downto 23);
tempS2(31) <= prod7(31);
result(3) <= tempS3(3);
result(31 downto 4) <= std_logic_vector(unsigned(tempS3(31 downto 4)) + unsigned(tempC3(31 downto 4)));
mainfor: FOR index in 2 to 31 GENERATE
if1_2to3:IF index >= 2 and index <= 3 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_4to5:IF index >= 4 and index <= 5 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
c=>prod2(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_6:IF index = 6 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => '0',
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_7tp19:IF index >= 7 and index <= 19 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_20:IF index = 20 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_21:IF index = 21 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp1(index),
b=>prod2(index),
c=>prod3(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_22:IF index = 22 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod2(index),
b=>prod3(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_10to11:IF index >= 10 and index <= 11 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if1_12to13:IF index >= 12 and index <= 13 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
c=>prod6(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_14:IF index = 14 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => '0',
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_15to26:IF index >= 15 and index <= 26 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_27to28:IF index >= 27 and index <= 28 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_29:IF index = 29 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp2(index),
b=>prod6(index),
c=>prod7(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_30:IF index = 30 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod6(index),
b=>prod7(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if2_3to7:IF index >= 3 and index <= 7 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
if2_8to10:IF index >= 8 and index <= 10 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
c=>tempS2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_11:IF index = 11 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => '0',
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_12to23:IF index >= 12 and index <= 23 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_24:IF index = 24 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => '0',
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_25:IF index = 25 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp3(index),
b=>tempS2(index),
c=>tempC2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_26to31:IF index >= 26 and index <= 31 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS2(index),
b=>tempC2(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
END GENERATE;
end Behavioral; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of vor
--
-- Generated
-- by: wig
-- on: Mon Jun 26 16:38:04 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vor-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: vor-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of vor
--
architecture rtl of vor is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity AluDemoex5 is
port( SW : in std_logic_vector(17 downto 0);
LEDR: out std_logic_vector(7 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0));
end AluDemoex5;
architecture Structural of AluDemoex5 is
signal s, m, i1, i2, i3, i4 : std_logic_vector(3 downto 0);
begin
Alu4: entity work.AluN(Behavioral)
generic map(N => 4)
port map(a => SW(7 downto 4),
b => SW(3 downto 0),
op => SW(17 downto 15),
m => LEDR(7 downto 4),
r2 => s,
r => LEDR(3 downto 0),
m2 => m);
Bin2BCDm: entity work.Bin2BCD(Behavioral)
port map(inBin => m,
outBCD =>i1,
outBCD2=>i2);
Bin2BCDr: entity work.Bin2BCD(Behavioral)
port map(inBin => s,
outBCD => i3,
outBCD2=> i4);
Bin7SecDec: entity work.Bin7SecDec(Behavioral)
port map(binInput => i1,
decOut_n => HEX7(6 downto 0));
Bin7SecDec2: entity work.Bin7SecDec(Behavioral)
port map(binInput => i2,
decOut_n => HEX6(6 downto 0));
Bin7SecDec3: entity work.Bin7SecDec(Behavioral)
port map(binInput => i3,
decOut_n => HEX5(6 downto 0));
Bin7SecDec4: entity work.Bin7SecDec(Behavioral)
port map(binInput => i4,
decOut_n => HEX4(6 downto 0));
end Structural; |
library ieee;
use ieee.std_logic_1164.all;
package repro is
type SPIrecGeneric is record
BIT : positive;
end record;
type SPI_Rec_input is record
SPI_Data_in : std_logic_vector (SPIrecGeneric.BIT-1 downto 0);
end record;
type SPI_Rec_Output is record
SPI_Data_out : std_logic_vector (SPIrecGeneric.BIT-1 downto 0);
end record;
end repro;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY reg_tb IS
END reg_tb;
generic (
DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5
);
ARCHITECTURE reg_arch OF reg_tb IS
SIGNAL: S_clk : std_logic;
SIGNAL: S_wren : std_logic;
SIGNAL: S_radd1 : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
SIGNAL: S_radd2 : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
SIGNAL: S_wadd : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
SIGNAL: S_wdata : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL: S_rdata1 : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL: S_rdata2 : std_logic_vector(DATA_WIDTH -1 downto 0);
COMPONENT reg
port (
clk, wren : in std_logic;
radd1, radd2, wadd : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH -1 downto 0);
rdata1, rdata2 : out std_logic_vector(DATA_WIDTH -1 downto 0)
);
END COMPONENT;
BEGIN
i1 : reg
PORT MAP (
clk => S_clk;
wren => S_wren;
radd1 => S_radd1;
radd2 => S_radd2;
wadd => S_wadd;
wdata => S_wdata;
rdata1 => S_rdata1;
rdata2 => S_rdata2);
Clk_process : PROCESS
BEGIN
S_clk <= '0';
wait for 5 ns;
S_clk <= '1';
wait for 5 ns;
END PROCESS Clk_process;
Wrt_process : PROCESS
BEGIN
S_wren <= '0';
wait for 5 ns;
S_wren <= '1';
wait for 5 ns;
end process Wrt_process;
Stimulus : PROCESS;
BEGIN;
wait for 5 ns;
S_radd1 <=
S_radd2 <=
S_wadd <=
S_wdata <=
wait for 5 ns;
-- case 2
wait for 5 ns;
-- case 3
wait for 5 ns;
-- case 4
wait for 5 ns;
END PROCESS Stimulus;
WAIT;
END PROCESS;
END reg_arch; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionROM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY instructionROM_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE instructionROM_synth_ARCH OF instructionROM_synth IS
COMPONENT instructionROM_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: instructionROM_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionROM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY instructionROM_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE instructionROM_synth_ARCH OF instructionROM_synth IS
COMPONENT instructionROM_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: instructionROM_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:21 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_stub.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_hdmi_0_0 is
Port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end system_zed_hdmi_0_0;
architecture stub of system_zed_hdmi_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_hdmi,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1330.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01330ent IS
port (clock : out bit);
END c08s04b01x00p04n01i01330ent;
ARCHITECTURE c08s04b01x00p04n01i01330arch OF c08s04b01x00p04n01i01330ent IS
BEGIN
TESTING: PROCESS
BEGIN
clock <= '1' after 10 ns,
'0' after 20 ns,
'1' after 30 ns,
'0' after X,
'1' after 70 ns;
wait for 80 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n01i01330 - Time expression must be of predefined type TIME as defined in package STANDARD."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01330arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1330.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01330ent IS
port (clock : out bit);
END c08s04b01x00p04n01i01330ent;
ARCHITECTURE c08s04b01x00p04n01i01330arch OF c08s04b01x00p04n01i01330ent IS
BEGIN
TESTING: PROCESS
BEGIN
clock <= '1' after 10 ns,
'0' after 20 ns,
'1' after 30 ns,
'0' after X,
'1' after 70 ns;
wait for 80 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n01i01330 - Time expression must be of predefined type TIME as defined in package STANDARD."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01330arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1330.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01330ent IS
port (clock : out bit);
END c08s04b01x00p04n01i01330ent;
ARCHITECTURE c08s04b01x00p04n01i01330arch OF c08s04b01x00p04n01i01330ent IS
BEGIN
TESTING: PROCESS
BEGIN
clock <= '1' after 10 ns,
'0' after 20 ns,
'1' after 30 ns,
'0' after X,
'1' after 70 ns;
wait for 80 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n01i01330 - Time expression must be of predefined type TIME as defined in package STANDARD."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01330arch;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- Transaction
WRITE, READ, CHECK, POLL_UNTIL);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--==========================================================================================
--
-- Transaction Info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction type
type t_base_transaction is record
operation : t_operation;
address : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
address => (others => '0'),
data => (others => '0'),
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Compound transaction type
type t_compound_transaction is record
operation : t_operation;
address : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
randomisation : t_randomisation;
num_words : natural;
max_polls : integer;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_COMPOUND_TRANSACTION_SET_DEFAULT : t_compound_transaction := (
operation => NO_OPERATION,
address => (others => '0'),
data => (others => '0'),
randomisation => NA,
num_words => 1,
max_polls => 1,
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
ct : t_compound_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT,
ct => C_COMPOUND_TRANSACTION_SET_DEFAULT
);
-- Global transaction info trigger signal
type t_sbi_transaction_trigger_array is array (natural range <>) of std_logic;
signal global_sbi_vvc_transaction_trigger : t_sbi_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => '0');
-- Type is defined as array to coincide with channel based VVCs
type t_sbi_transaction_group_array is array (natural range <>) of t_transaction_group;
-- Shared transaction info variable
shared variable shared_sbi_vvc_transaction_info : t_sbi_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => C_TRANSACTION_GROUP_DEFAULT);
end package transaction_pkg; |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68d
-- \ \ Application: netgen
-- / / Filename: mbuf_128x72.vhd
-- /___/ /\ Timestamp: Fri Sep 6 17:30:30 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/mbuf_128x72.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/mbuf_128x72.vhd
-- Device : 6vlx240tff1156-1
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/mbuf_128x72.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/mbuf_128x72.vhd
-- # of Entities : 2
-- Design Name : mbuf_128x72
-- Xilinx : /opt/Xilinx/14.6/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity reset_builtin1 is
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end reset_builtin1;
architecture STRUCTURE of reset_builtin1 is
signal wr_rst_reg_2 : STD_LOGIC;
signal wr_rst_reg_GND_25_o_MUX_1_o : STD_LOGIC;
signal wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_RD_RST_I : STD_LOGIC_VECTOR ( 0 downto 0 );
signal NlwRenamedSig_OI_n0013 : STD_LOGIC_VECTOR ( 5 downto 5 );
begin
WR_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
WR_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
INT_RST_I(1) <= NlwRenamedSig_OI_n0013(5);
INT_RST_I(0) <= NlwRenamedSig_OI_n0013(5);
XST_GND : GND
port map (
G => NlwRenamedSig_OI_n0013(5)
);
power_on_wr_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(1),
Q => power_on_wr_rst(0)
);
power_on_wr_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(2),
Q => power_on_wr_rst(1)
);
power_on_wr_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(3),
Q => power_on_wr_rst(2)
);
power_on_wr_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(4),
Q => power_on_wr_rst(3)
);
power_on_wr_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(5),
Q => power_on_wr_rst(4)
);
power_on_wr_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => NlwRenamedSig_OI_n0013(5),
Q => power_on_wr_rst(5)
);
wr_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_GND_25_o_MUX_1_o,
PRE => RST,
Q => wr_rst_reg_2
);
wr_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(1),
Q => wr_rst_fb(0)
);
wr_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(2),
Q => wr_rst_fb(1)
);
wr_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(3),
Q => wr_rst_fb(2)
);
wr_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(4),
Q => wr_rst_fb(3)
);
wr_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_2,
Q => wr_rst_fb(4)
);
RD_RST_I_0_1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wr_rst_reg_2,
I1 => power_on_wr_rst(0),
O => NlwRenamedSignal_RD_RST_I(0)
);
Mmux_wr_rst_reg_GND_25_o_MUX_1_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => wr_rst_fb(0),
I1 => wr_rst_reg_2,
O => wr_rst_reg_GND_25_o_MUX_1_o
);
end STRUCTURE;
-- synthesis translate_on
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity mbuf_128x72 is
port (
clk : in STD_LOGIC := 'X';
rst : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 71 downto 0 );
dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
);
end mbuf_128x72;
architecture STRUCTURE of mbuf_128x72 is
component reset_builtin1
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19 : STD_LOGIC;
signal NlwRenamedSig_OI_empty : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
empty <= NlwRenamedSig_OI_empty;
prog_full <= U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt : reset_builtin1
port map (
CLK => clk,
WR_CLK => N1,
RD_CLK => N1,
INT_CLK => N1,
RST => rst,
WR_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED,
WR_RST_I(0) => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RD_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED,
RD_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED,
INT_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED,
INT_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
generic map(
ALMOST_EMPTY_OFFSET => X"0002",
ALMOST_FULL_OFFSET => X"0180",
DATA_WIDTH => 72,
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => TRUE,
FIFO_MODE => "FIFO36_72",
FIRST_WORD_FALL_THROUGH => FALSE,
INIT => X"000000000000000000",
SIM_DEVICE => "VIRTEX6",
SRVAL => X"000000000000000000"
)
port map (
ALMOSTEMPTY =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
,
ALMOSTFULL => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
EMPTY => NlwRenamedSig_OI_empty,
FULL => full,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
RDCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
RDERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
REGCE => N1,
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RSTREG => N1,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
WRCLK => clk,
WREN => wr_en,
WRERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
DI(63) => din(67),
DI(62) => din(66),
DI(61) => din(65),
DI(60) => din(64),
DI(59) => din(63),
DI(58) => din(62),
DI(57) => din(61),
DI(56) => din(60),
DI(55) => din(59),
DI(54) => din(58),
DI(53) => din(57),
DI(52) => din(56),
DI(51) => din(55),
DI(50) => din(54),
DI(49) => din(53),
DI(48) => din(52),
DI(47) => din(51),
DI(46) => din(50),
DI(45) => din(49),
DI(44) => din(48),
DI(43) => din(47),
DI(42) => din(46),
DI(41) => din(45),
DI(40) => din(44),
DI(39) => din(43),
DI(38) => din(42),
DI(37) => din(41),
DI(36) => din(40),
DI(35) => din(39),
DI(34) => din(38),
DI(33) => din(37),
DI(32) => din(36),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => din(71),
DIP(6) => din(70),
DIP(5) => din(69),
DIP(4) => din(68),
DIP(3) => din(35),
DIP(2) => din(34),
DIP(1) => din(33),
DIP(0) => din(32),
DO(63) => dout(67),
DO(62) => dout(66),
DO(61) => dout(65),
DO(60) => dout(64),
DO(59) => dout(63),
DO(58) => dout(62),
DO(57) => dout(61),
DO(56) => dout(60),
DO(55) => dout(59),
DO(54) => dout(58),
DO(53) => dout(57),
DO(52) => dout(56),
DO(51) => dout(55),
DO(50) => dout(54),
DO(49) => dout(53),
DO(48) => dout(52),
DO(47) => dout(51),
DO(46) => dout(50),
DO(45) => dout(49),
DO(44) => dout(48),
DO(43) => dout(47),
DO(42) => dout(46),
DO(41) => dout(45),
DO(40) => dout(44),
DO(39) => dout(43),
DO(38) => dout(42),
DO(37) => dout(41),
DO(36) => dout(40),
DO(35) => dout(39),
DO(34) => dout(38),
DO(33) => dout(37),
DO(32) => dout(36),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) => dout(71),
DOP(6) => dout(70),
DOP(5) => dout(69),
DOP(4) => dout(68),
DOP(3) => dout(35),
DOP(2) => dout(34),
DOP(1) => dout(33),
DOP(0) => dout(32),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
,
RDCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
,
RDCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
,
RDCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
,
RDCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
,
RDCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
,
RDCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
,
RDCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
,
RDCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
,
RDCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
,
RDCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
,
RDCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
,
RDCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
,
RDCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
,
WRCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
,
WRCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
,
WRCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
,
WRCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
,
WRCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
,
WRCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
,
WRCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
,
WRCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
,
WRCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
,
WRCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
,
WRCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
,
WRCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
,
WRCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_empty,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
);
end STRUCTURE;
-- synthesis translate_on
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:44:52 10/01/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/OmegaTopTB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: OmegaTop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
library work;
use work.Constants.ALL;
ENTITY OmegaTopTB IS
END OmegaTopTB;
ARCHITECTURE behavior OF OmegaTopTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OmegaTop
PORT(
CLK : IN std_logic;
RX : IN std_logic;
TX : OUT std_logic;
LEDS : out std_logic_vector(7 downto 0);
SRAM_addr : out std_logic_vector(20 downto 0);
SRAM_OE : out std_logic;
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
SRAM_data : inout std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RX : std_logic := '0';
--Outputs
signal TX : std_logic;
signal LEDS : std_logic_vector(7 downto 0);
signal SRAM_addr : std_logic_vector(20 downto 0);
signal SRAM_OE : std_logic;
signal SRAM_CE : std_logic;
signal SRAM_WE : std_logic;
signal SRAM_data : std_logic_vector(7 downto 0);
signal memory : MemoryArray := (others => (others => '0'));
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OmegaTop PORT MAP (
CLK => CLK,
RX => RX,
TX => TX,
LEDS => LEDS,
SRAM_addr => SRAM_addr,
SRAM_OE => SRAM_OE,
SRAM_CE => SRAM_CE,
SRAM_WE => SRAM_WE,
SRAM_data => SRAM_data
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
read_proc: process(SRAM_oe,SRAM_addr)
begin
if SRAM_oe = '1' then
sram_data <= (others => 'Z');
else
sram_data <= memory(to_integer(unsigned(SRAM_ADDR)));
end if;
end process read_proc;
write_proc: process(SRAM_we,SRAM_addr)
begin
if SRAM_we = '0' then
memory(to_integer(unsigned(SRAM_ADDR))) <= sram_data;
end if;
end process write_proc;
-- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for CLK_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
END;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
ENA <= DO_READ OR DO_WRITE ;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
|
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