content stringlengths 1 1.04M ⌀ |
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----------------------------------------------------------------------
-- mySerTxd.vhd
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- My simple fixed speed UART serial transmitter.
--
----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
----------------------------------------------------------------------
entity mySerTxd is
generic (
baud : positive := 115_200;
freq : positive := 50_000_000);
port (
i_clk : in std_logic;
i_rst_n : in std_logic;
i_str : in std_logic;
i_dat : in std_logic_vector(7 downto 0);
o_bsy : out std_logic;
o_txd : out std_logic );
end mySerTxd;
----------------------------------------------------------------------
architecture rtl of mySerTxd is
constant c_bd_div : integer := ((freq / baud)-2);
constant c_bd_div_width : integer := integer(log2(real(c_bd_div))) + 1;
signal bd_cur, bd_nxt : unsigned(c_bd_div_width downto 0);
signal s_dat, s_bsy : std_logic_vector(10 downto 0);
signal s_tck : std_logic;
begin
process(i_clk) -- clock divider
begin
if (i_clk'event and i_clk = '1') then
if (bd_nxt(bd_nxt'length-1) = '1') then
bd_nxt <= to_unsigned(c_bd_div,bd_cur'length);
else
bd_nxt <= bd_nxt -1;
end if;
end if;
end process;
s_tck <= bd_nxt(bd_nxt'length-1);
process(i_clk,i_rst_n) -- transmitter
begin
if (i_rst_n='0') then
s_dat <= (others => '1');
s_bsy <= (others => '0');
elsif (i_clk'event and i_clk = '1') then
s_dat <= s_dat;
s_bsy <= s_bsy;
if (s_bsy(0) = '0') then
if (i_str = '1') then
s_dat <= '1' & i_dat & "01";
s_bsy <= (others => '1');
end if;
else
if (s_tck = '1') then
s_dat <= '1' & s_dat(s_dat'length-1 downto 1);
s_bsy <= '0' & s_bsy(s_bsy'length-1 downto 1);
end if;
end if;
end if;
end process;
o_bsy <= s_tck;
o_txd <= s_dat(0);
end rtl;
----------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity test2 is
generic(
MEMORY_SIZE : natural := 32;
RAM_INIT_FILE : string := "firmware.hex"
);
port (addr : std_logic_vector (1 downto 0);
data : out std_logic_vector (63 downto 0));
end entity test2;
architecture behaviour of test2 is
type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
impure function init_ram(name : STRING) return ram_t is
file ram_file : text open read_mode is name;
variable ram_line : line;
variable temp_word : std_logic_vector(63 downto 0);
variable temp_ram : ram_t := (others => (others => '0'));
begin
for i in 0 to (MEMORY_SIZE/8)-1 loop
exit when endfile(ram_file);
readline(ram_file, ram_line);
report "read: " & ram_line.all;
hread(ram_line, temp_word);
temp_ram(i) := temp_word;
end loop;
return temp_ram;
end function;
signal memory : ram_t := init_ram(RAM_INIT_FILE);
begin
data <= memory (to_integer (unsigned (addr)));
end architecture behaviour;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file resultRam.vhd when simulating
-- the core, resultRam. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY resultRam IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END resultRam;
ARCHITECTURE resultRam_a OF resultRam IS
-- synthesis translate_off
COMPONENT wrapped_resultRam
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_resultRam USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 9,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 512,
c_read_depth_b => 512,
c_read_width_a => 72,
c_read_width_b => 72,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 512,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 72,
c_write_width_b => 72,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_resultRam
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END resultRam_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file resultRam.vhd when simulating
-- the core, resultRam. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY resultRam IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END resultRam;
ARCHITECTURE resultRam_a OF resultRam IS
-- synthesis translate_off
COMPONENT wrapped_resultRam
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_resultRam USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 9,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 512,
c_read_depth_b => 512,
c_read_width_a => 72,
c_read_width_b => 72,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 512,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 72,
c_write_width_b => 72,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_resultRam
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END resultRam_a;
|
--! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Altera
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamSplx is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWordsA,
numwords_b => gNumberOfWordsB,
widthad_a => logDualis(gNumberOfWordsA),
widthad_b => logDualis(gNumberOfWordsB),
width_a => gWordWidthA,
width_b => gWordWidthB,
width_byteena_a => gByteenableWidthA,
width_byteena_b => gByteenableWidthA
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
address_b => iAddress_B,
q_b => oReaddata_B
);
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Entity: jtag_client
-- Date:2016-11-08
-- Author: Gideon
--
-- Description: Client for Virtual JTAG module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity jtag_client is
port (
avm_clock : in std_logic;
avm_reset : in std_logic;
avm_read : out std_logic;
avm_write : out std_logic;
avm_byteenable : out std_logic_vector(3 downto 0);
avm_address : out std_logic_vector(31 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_readdata : in std_logic_vector(31 downto 0);
avm_readdatavalid : in std_logic;
avm_waitrequest : in std_logic;
clock_1 : in std_logic;
clock_2 : in std_logic;
sample_vector : in std_logic_vector(47 downto 0);
write_vector : out std_logic_vector(7 downto 0) );
end entity;
architecture arch of jtag_client is
component virtual_jtag is
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(3 downto 0); -- ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component virtual_jtag;
constant c_rom : std_logic_vector(31 downto 0) := X"DEAD1541";
signal shiftreg_sample : std_logic_vector(sample_vector'range);
signal shiftreg_write : std_logic_vector(write_vector'range);
signal shiftreg_debug : std_logic_vector(24 downto 0);
signal shiftreg_clock : std_logic_vector(7 downto 0);
signal debug_bits : std_logic_vector(4 downto 0);
signal clock_1_shift : std_logic_vector(7 downto 0) := X"00";
signal clock_2_shift : std_logic_vector(7 downto 0) := X"00";
signal bypass_reg : std_logic;
signal bit_count : unsigned(4 downto 0) := (others => '0');
signal tdi : std_logic; -- tdi
signal tdo : std_logic := 'X'; -- tdo
signal ir_in : std_logic_vector(3 downto 0); -- ir_in
signal ir_out : std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
signal virtual_state_cdr : std_logic; -- virtual_state_cdr
signal virtual_state_sdr : std_logic; -- virtual_state_sdr
signal virtual_state_e1dr : std_logic; -- virtual_state_e1dr
signal virtual_state_pdr : std_logic; -- virtual_state_pdr
signal virtual_state_e2dr : std_logic; -- virtual_state_e2dr
signal virtual_state_udr : std_logic; -- virtual_state_udr
signal virtual_state_cir : std_logic; -- virtual_state_cir
signal virtual_state_uir : std_logic; -- virtual_state_uir
signal tck : std_logic; -- clk
signal write_fifo_full : std_logic;
signal write_fifo_put : std_logic := '0';
signal write_fifo_din : std_logic_vector(11 downto 0);
signal read_fifo_get : std_logic;
signal shiftreg_fifo : std_logic_vector(15 downto 0);
signal read_fifo_count : unsigned(7 downto 0);
signal read_fifo_data : std_logic_vector(7 downto 0);
signal cmd_count : unsigned(7 downto 0) := X"00";
signal last_command : std_logic_vector(11 downto 0);
-- signals that live in the avm clock domain
type t_state is (idle, do_write, do_read, do_read2, do_read3);
signal state : t_state;
signal incrementing : std_logic;
signal byte_count : integer range 0 to 3;
signal read_count : unsigned(7 downto 0);
signal avm_read_reg : std_logic_vector(31 downto 0) := (others => '0');
signal write_enabled : std_logic;
signal write_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_be : std_logic_vector(3 downto 0) := (others => '0');
signal address : unsigned(31 downto 0) := (others => '0');
signal avm_rfifo_put : std_logic;
signal avm_rfifo_full : std_logic;
signal avm_wfifo_get : std_logic;
signal avm_wfifo_valid : std_logic;
signal avm_read_i : std_logic;
signal avm_write_i : std_logic;
signal avm_wfifo_dout : std_logic_vector(11 downto 0);
signal avm_wfifo_count : unsigned(4 downto 0);
signal avm_exec_count : unsigned(2 downto 0) := "000";
signal avm_clock_count : unsigned(2 downto 0) := "000";
begin
i_vj: virtual_jtag
port map (
tdi => tdi,
tdo => tdo,
ir_in => ir_in,
ir_out => ir_out,
virtual_state_cdr => virtual_state_cdr,
virtual_state_sdr => virtual_state_sdr,
virtual_state_e1dr => virtual_state_e1dr,
virtual_state_pdr => virtual_state_pdr,
virtual_state_e2dr => virtual_state_e2dr,
virtual_state_udr => virtual_state_udr,
virtual_state_cir => virtual_state_cir,
virtual_state_uir => virtual_state_uir,
tck => tck
);
process(tck)
begin
if rising_edge(tck) then
read_fifo_get <= '0';
write_fifo_put <= '0';
if write_fifo_put = '1' then
last_command <= write_fifo_din;
end if;
if virtual_state_sdr = '1' then
bypass_reg <= tdi;
shiftreg_sample <= tdi & shiftreg_sample(shiftreg_sample'high downto 1);
shiftreg_write <= tdi & shiftreg_write(shiftreg_write'high downto 1);
shiftreg_debug <= tdi & shiftreg_debug(shiftreg_debug'high downto 1);
shiftreg_clock <= tdi & shiftreg_clock(shiftreg_clock'high downto 1);
bit_count <= bit_count + 1;
if ir_in = X"4" then
if bit_count(2 downto 0) = "111" then
shiftreg_fifo <= X"00" & read_fifo_data;
read_fifo_get <= not tdi;
else
shiftreg_fifo <= '0' & shiftreg_fifo(shiftreg_fifo'high downto 1);
end if;
elsif ir_in = X"5" then
shiftreg_fifo <= tdi & shiftreg_fifo(shiftreg_fifo'high downto 1);
if bit_count(3 downto 0) = "1111" then
write_fifo_put <= '1';
cmd_count <= cmd_count + 1;
end if;
elsif ir_in = X"6" then
shiftreg_fifo <= tdi & shiftreg_fifo(shiftreg_fifo'high downto 1);
if bit_count(2 downto 0) = "111" then
write_fifo_put <= '1';
cmd_count <= cmd_count + 1;
end if;
end if;
end if;
if virtual_state_cdr = '1' then
shiftreg_write <= (others => '0');
shiftreg_sample <= sample_vector;
bit_count <= (others => '0');
shiftreg_fifo <= X"00" & std_logic_vector(read_fifo_count);
shiftreg_debug <= debug_bits & last_command & std_logic_vector(cmd_count);
if ir_in = X"8" then
shiftreg_clock <= clock_1_shift;
end if;
if ir_in = X"9" then
shiftreg_clock <= clock_2_shift;
end if;
end if;
if virtual_state_udr = '1' then
case ir_in is
when X"2" =>
write_vector <= shiftreg_write;
when others =>
null;
end case;
end if;
end if;
end process;
process(clock_1)
begin
if rising_edge(clock_1) then
clock_1_shift <= clock_1_shift(6 downto 0) & not clock_1_shift(7);
end if;
end process;
process(clock_2)
begin
if rising_edge(clock_2) then
clock_2_shift <= clock_2_shift(6 downto 0) & not clock_2_shift(7);
end if;
end process;
process(ir_in, bit_count, shiftreg_sample, shiftreg_write, bypass_reg, shiftreg_fifo, shiftreg_debug, shiftreg_clock)
begin
case ir_in is
when X"0" =>
tdo <= c_rom(to_integer(bit_count));
when X"1" =>
tdo <= shiftreg_sample(0);
when X"2" =>
tdo <= shiftreg_write(0);
when X"3" =>
tdo <= shiftreg_debug(0);
when X"4" =>
tdo <= shiftreg_fifo(0);
when X"8" | X"9" =>
tdo <= shiftreg_clock(0);
when others =>
tdo <= bypass_reg;
end case;
end process;
-- Avalon JTAG commands
-- E000 => write data (byte is data)
-- x0010 => Start Write Non Incrementing (only upper bit of byte used)
-- x0011 => Start Write incrementing (only upper bit of byte used)
-- x010 => Do Read Non-Incrementing (byte is length)
-- x011 => Do Read incrementing (byte is length)
-- x1xx => Set address (bytes is address data) xx = index of address byte
--
write_fifo_din <= ("1000" & shiftreg_fifo(15 downto 8)) when ir_in = X"6" else
(shiftreg_fifo(11 downto 0));
i_write_fifo: entity work.async_fifo_ft
generic map(
g_data_width => 12,
g_depth_bits => 4
)
port map (
wr_clock => tck,
wr_reset => '0',
wr_en => write_fifo_put,
wr_din => write_fifo_din,
wr_full => write_fifo_full,
rd_clock => avm_clock,
rd_reset => avm_reset,
rd_next => avm_wfifo_get,
rd_dout => avm_wfifo_dout,
rd_valid => avm_wfifo_valid,
rd_count => avm_wfifo_count
);
i_read_fifo: entity work.async_fifo_ft
generic map(
g_data_width => 8,
g_depth_bits => 7 )
port map(
wr_clock => avm_clock,
wr_reset => avm_reset,
wr_en => avm_rfifo_put,
wr_din => avm_read_reg(7 downto 0),
wr_full => avm_rfifo_full,
rd_clock => tck,
rd_reset => '0',
rd_next => read_fifo_get,
rd_dout => read_fifo_data,
rd_valid => open,
rd_count => read_fifo_count
);
process(avm_clock)
variable v_cmd : std_logic_vector(2 downto 0);
begin
if rising_edge(avm_clock) then
avm_clock_count <= avm_clock_count + 1;
case state is
when idle =>
avm_rfifo_put <= '0';
if avm_wfifo_valid = '1' then -- command?
avm_exec_count <= avm_exec_count + 1;
v_cmd := avm_wfifo_dout(10 downto 8);
case v_cmd is
when "000" =>
if write_enabled = '1' then
write_be(3) <= avm_wfifo_dout(11);
write_data(31 downto 24) <= avm_wfifo_dout(7 downto 0);
write_be(2 downto 0) <= write_be(3 downto 1);
write_data(23 downto 00) <= write_data(31 downto 8);
if byte_count = 3 then
avm_write_i <= '1';
state <= do_write;
byte_count <= 0;
else
byte_count <= byte_count + 1;
end if;
end if;
when "001" =>
byte_count <= 0;
write_enabled <= '1';
incrementing <= avm_wfifo_dout(7);
when "010" | "011" =>
write_enabled <= '0';
read_count <= unsigned(avm_wfifo_dout(7 downto 0));
state <= do_read;
incrementing <= v_cmd(0);
when "100" =>
write_enabled <= '0';
address(7 downto 0) <= unsigned(avm_wfifo_dout(7 downto 0));
when "101" =>
write_enabled <= '0';
address(15 downto 8) <= unsigned(avm_wfifo_dout(7 downto 0));
when "110" =>
write_enabled <= '0';
address(23 downto 16) <= unsigned(avm_wfifo_dout(7 downto 0));
when "111" =>
write_enabled <= '0';
address(31 downto 24) <= unsigned(avm_wfifo_dout(7 downto 0));
when others =>
null;
end case;
end if;
when do_write =>
if avm_waitrequest = '0' then
avm_write_i <= '0';
state <= idle;
if incrementing = '1' then
address(31 downto 2) <= address(31 downto 2) + 1;
end if;
end if;
when do_read =>
write_be <= "1111";
avm_read_i <= '1';
state <= do_read2;
when do_read2 =>
if avm_waitrequest = '0' then
avm_read_i <= '0';
end if;
if avm_readdatavalid = '1' then
avm_read_reg <= avm_readdata;
byte_count <= 0;
avm_rfifo_put <= '1';
state <= do_read3;
end if;
when do_read3 =>
if avm_rfifo_full = '0' then
if byte_count = 3 then
byte_count <= 0;
avm_rfifo_put <= '0';
read_count <= read_count - 1;
if read_count = 0 then
state <= idle;
else
state <= do_read;
if incrementing = '1' then
address(31 downto 2) <= address(31 downto 2) + 1;
end if;
end if;
else
byte_count <= byte_count + 1;
avm_read_reg(23 downto 0) <= avm_read_reg(31 downto 8);
end if;
end if;
when others =>
null;
end case;
if avm_reset = '1' then
state <= idle;
incrementing <= '0';
byte_count <= 0;
read_count <= (others => '0');
write_enabled <= '0';
write_be <= "0000";
avm_read_i <= '0';
avm_write_i <= '0';
avm_rfifo_put <= '0';
avm_exec_count <= "000";
end if;
end if;
end process;
with state select debug_bits(2 downto 0) <=
"000" when idle,
"001" when do_write,
"010" when do_read,
"011" when do_read2,
"100" when do_read3,
"111" when others;
debug_bits(3) <= avm_read_i;
debug_bits(4) <= avm_write_i;
avm_read <= avm_read_i;
avm_write <= avm_write_i;
avm_wfifo_get <= '1' when avm_wfifo_valid = '1' and state = idle else '0';
avm_address <= std_logic_vector(address(31 downto 2) & "00");
avm_byteenable <= write_be;
avm_writedata <= write_data;
end arch;
|
--------------------------------------------------------------------------------
-- Entity: jtag_client
-- Date:2016-11-08
-- Author: Gideon
--
-- Description: Client for Virtual JTAG module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity jtag_client is
port (
avm_clock : in std_logic;
avm_reset : in std_logic;
avm_read : out std_logic;
avm_write : out std_logic;
avm_byteenable : out std_logic_vector(3 downto 0);
avm_address : out std_logic_vector(31 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_readdata : in std_logic_vector(31 downto 0);
avm_readdatavalid : in std_logic;
avm_waitrequest : in std_logic;
clock_1 : in std_logic;
clock_2 : in std_logic;
sample_vector : in std_logic_vector(47 downto 0);
write_vector : out std_logic_vector(7 downto 0) );
end entity;
architecture arch of jtag_client is
component virtual_jtag is
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(3 downto 0); -- ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component virtual_jtag;
constant c_rom : std_logic_vector(31 downto 0) := X"DEAD1541";
signal shiftreg_sample : std_logic_vector(sample_vector'range);
signal shiftreg_write : std_logic_vector(write_vector'range);
signal shiftreg_debug : std_logic_vector(24 downto 0);
signal shiftreg_clock : std_logic_vector(7 downto 0);
signal debug_bits : std_logic_vector(4 downto 0);
signal clock_1_shift : std_logic_vector(7 downto 0) := X"00";
signal clock_2_shift : std_logic_vector(7 downto 0) := X"00";
signal bypass_reg : std_logic;
signal bit_count : unsigned(4 downto 0) := (others => '0');
signal tdi : std_logic; -- tdi
signal tdo : std_logic := 'X'; -- tdo
signal ir_in : std_logic_vector(3 downto 0); -- ir_in
signal ir_out : std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
signal virtual_state_cdr : std_logic; -- virtual_state_cdr
signal virtual_state_sdr : std_logic; -- virtual_state_sdr
signal virtual_state_e1dr : std_logic; -- virtual_state_e1dr
signal virtual_state_pdr : std_logic; -- virtual_state_pdr
signal virtual_state_e2dr : std_logic; -- virtual_state_e2dr
signal virtual_state_udr : std_logic; -- virtual_state_udr
signal virtual_state_cir : std_logic; -- virtual_state_cir
signal virtual_state_uir : std_logic; -- virtual_state_uir
signal tck : std_logic; -- clk
signal write_fifo_full : std_logic;
signal write_fifo_put : std_logic := '0';
signal write_fifo_din : std_logic_vector(11 downto 0);
signal read_fifo_get : std_logic;
signal shiftreg_fifo : std_logic_vector(15 downto 0);
signal read_fifo_count : unsigned(7 downto 0);
signal read_fifo_data : std_logic_vector(7 downto 0);
signal cmd_count : unsigned(7 downto 0) := X"00";
signal last_command : std_logic_vector(11 downto 0);
-- signals that live in the avm clock domain
type t_state is (idle, do_write, do_read, do_read2, do_read3);
signal state : t_state;
signal incrementing : std_logic;
signal byte_count : integer range 0 to 3;
signal read_count : unsigned(7 downto 0);
signal avm_read_reg : std_logic_vector(31 downto 0) := (others => '0');
signal write_enabled : std_logic;
signal write_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_be : std_logic_vector(3 downto 0) := (others => '0');
signal address : unsigned(31 downto 0) := (others => '0');
signal avm_rfifo_put : std_logic;
signal avm_rfifo_full : std_logic;
signal avm_wfifo_get : std_logic;
signal avm_wfifo_valid : std_logic;
signal avm_read_i : std_logic;
signal avm_write_i : std_logic;
signal avm_wfifo_dout : std_logic_vector(11 downto 0);
signal avm_wfifo_count : unsigned(4 downto 0);
signal avm_exec_count : unsigned(2 downto 0) := "000";
signal avm_clock_count : unsigned(2 downto 0) := "000";
begin
i_vj: virtual_jtag
port map (
tdi => tdi,
tdo => tdo,
ir_in => ir_in,
ir_out => ir_out,
virtual_state_cdr => virtual_state_cdr,
virtual_state_sdr => virtual_state_sdr,
virtual_state_e1dr => virtual_state_e1dr,
virtual_state_pdr => virtual_state_pdr,
virtual_state_e2dr => virtual_state_e2dr,
virtual_state_udr => virtual_state_udr,
virtual_state_cir => virtual_state_cir,
virtual_state_uir => virtual_state_uir,
tck => tck
);
process(tck)
begin
if rising_edge(tck) then
read_fifo_get <= '0';
write_fifo_put <= '0';
if write_fifo_put = '1' then
last_command <= write_fifo_din;
end if;
if virtual_state_sdr = '1' then
bypass_reg <= tdi;
shiftreg_sample <= tdi & shiftreg_sample(shiftreg_sample'high downto 1);
shiftreg_write <= tdi & shiftreg_write(shiftreg_write'high downto 1);
shiftreg_debug <= tdi & shiftreg_debug(shiftreg_debug'high downto 1);
shiftreg_clock <= tdi & shiftreg_clock(shiftreg_clock'high downto 1);
bit_count <= bit_count + 1;
if ir_in = X"4" then
if bit_count(2 downto 0) = "111" then
shiftreg_fifo <= X"00" & read_fifo_data;
read_fifo_get <= not tdi;
else
shiftreg_fifo <= '0' & shiftreg_fifo(shiftreg_fifo'high downto 1);
end if;
elsif ir_in = X"5" then
shiftreg_fifo <= tdi & shiftreg_fifo(shiftreg_fifo'high downto 1);
if bit_count(3 downto 0) = "1111" then
write_fifo_put <= '1';
cmd_count <= cmd_count + 1;
end if;
elsif ir_in = X"6" then
shiftreg_fifo <= tdi & shiftreg_fifo(shiftreg_fifo'high downto 1);
if bit_count(2 downto 0) = "111" then
write_fifo_put <= '1';
cmd_count <= cmd_count + 1;
end if;
end if;
end if;
if virtual_state_cdr = '1' then
shiftreg_write <= (others => '0');
shiftreg_sample <= sample_vector;
bit_count <= (others => '0');
shiftreg_fifo <= X"00" & std_logic_vector(read_fifo_count);
shiftreg_debug <= debug_bits & last_command & std_logic_vector(cmd_count);
if ir_in = X"8" then
shiftreg_clock <= clock_1_shift;
end if;
if ir_in = X"9" then
shiftreg_clock <= clock_2_shift;
end if;
end if;
if virtual_state_udr = '1' then
case ir_in is
when X"2" =>
write_vector <= shiftreg_write;
when others =>
null;
end case;
end if;
end if;
end process;
process(clock_1)
begin
if rising_edge(clock_1) then
clock_1_shift <= clock_1_shift(6 downto 0) & not clock_1_shift(7);
end if;
end process;
process(clock_2)
begin
if rising_edge(clock_2) then
clock_2_shift <= clock_2_shift(6 downto 0) & not clock_2_shift(7);
end if;
end process;
process(ir_in, bit_count, shiftreg_sample, shiftreg_write, bypass_reg, shiftreg_fifo, shiftreg_debug, shiftreg_clock)
begin
case ir_in is
when X"0" =>
tdo <= c_rom(to_integer(bit_count));
when X"1" =>
tdo <= shiftreg_sample(0);
when X"2" =>
tdo <= shiftreg_write(0);
when X"3" =>
tdo <= shiftreg_debug(0);
when X"4" =>
tdo <= shiftreg_fifo(0);
when X"8" | X"9" =>
tdo <= shiftreg_clock(0);
when others =>
tdo <= bypass_reg;
end case;
end process;
-- Avalon JTAG commands
-- E000 => write data (byte is data)
-- x0010 => Start Write Non Incrementing (only upper bit of byte used)
-- x0011 => Start Write incrementing (only upper bit of byte used)
-- x010 => Do Read Non-Incrementing (byte is length)
-- x011 => Do Read incrementing (byte is length)
-- x1xx => Set address (bytes is address data) xx = index of address byte
--
write_fifo_din <= ("1000" & shiftreg_fifo(15 downto 8)) when ir_in = X"6" else
(shiftreg_fifo(11 downto 0));
i_write_fifo: entity work.async_fifo_ft
generic map(
g_data_width => 12,
g_depth_bits => 4
)
port map (
wr_clock => tck,
wr_reset => '0',
wr_en => write_fifo_put,
wr_din => write_fifo_din,
wr_full => write_fifo_full,
rd_clock => avm_clock,
rd_reset => avm_reset,
rd_next => avm_wfifo_get,
rd_dout => avm_wfifo_dout,
rd_valid => avm_wfifo_valid,
rd_count => avm_wfifo_count
);
i_read_fifo: entity work.async_fifo_ft
generic map(
g_data_width => 8,
g_depth_bits => 7 )
port map(
wr_clock => avm_clock,
wr_reset => avm_reset,
wr_en => avm_rfifo_put,
wr_din => avm_read_reg(7 downto 0),
wr_full => avm_rfifo_full,
rd_clock => tck,
rd_reset => '0',
rd_next => read_fifo_get,
rd_dout => read_fifo_data,
rd_valid => open,
rd_count => read_fifo_count
);
process(avm_clock)
variable v_cmd : std_logic_vector(2 downto 0);
begin
if rising_edge(avm_clock) then
avm_clock_count <= avm_clock_count + 1;
case state is
when idle =>
avm_rfifo_put <= '0';
if avm_wfifo_valid = '1' then -- command?
avm_exec_count <= avm_exec_count + 1;
v_cmd := avm_wfifo_dout(10 downto 8);
case v_cmd is
when "000" =>
if write_enabled = '1' then
write_be(3) <= avm_wfifo_dout(11);
write_data(31 downto 24) <= avm_wfifo_dout(7 downto 0);
write_be(2 downto 0) <= write_be(3 downto 1);
write_data(23 downto 00) <= write_data(31 downto 8);
if byte_count = 3 then
avm_write_i <= '1';
state <= do_write;
byte_count <= 0;
else
byte_count <= byte_count + 1;
end if;
end if;
when "001" =>
byte_count <= 0;
write_enabled <= '1';
incrementing <= avm_wfifo_dout(7);
when "010" | "011" =>
write_enabled <= '0';
read_count <= unsigned(avm_wfifo_dout(7 downto 0));
state <= do_read;
incrementing <= v_cmd(0);
when "100" =>
write_enabled <= '0';
address(7 downto 0) <= unsigned(avm_wfifo_dout(7 downto 0));
when "101" =>
write_enabled <= '0';
address(15 downto 8) <= unsigned(avm_wfifo_dout(7 downto 0));
when "110" =>
write_enabled <= '0';
address(23 downto 16) <= unsigned(avm_wfifo_dout(7 downto 0));
when "111" =>
write_enabled <= '0';
address(31 downto 24) <= unsigned(avm_wfifo_dout(7 downto 0));
when others =>
null;
end case;
end if;
when do_write =>
if avm_waitrequest = '0' then
avm_write_i <= '0';
state <= idle;
if incrementing = '1' then
address(31 downto 2) <= address(31 downto 2) + 1;
end if;
end if;
when do_read =>
write_be <= "1111";
avm_read_i <= '1';
state <= do_read2;
when do_read2 =>
if avm_waitrequest = '0' then
avm_read_i <= '0';
end if;
if avm_readdatavalid = '1' then
avm_read_reg <= avm_readdata;
byte_count <= 0;
avm_rfifo_put <= '1';
state <= do_read3;
end if;
when do_read3 =>
if avm_rfifo_full = '0' then
if byte_count = 3 then
byte_count <= 0;
avm_rfifo_put <= '0';
read_count <= read_count - 1;
if read_count = 0 then
state <= idle;
else
state <= do_read;
if incrementing = '1' then
address(31 downto 2) <= address(31 downto 2) + 1;
end if;
end if;
else
byte_count <= byte_count + 1;
avm_read_reg(23 downto 0) <= avm_read_reg(31 downto 8);
end if;
end if;
when others =>
null;
end case;
if avm_reset = '1' then
state <= idle;
incrementing <= '0';
byte_count <= 0;
read_count <= (others => '0');
write_enabled <= '0';
write_be <= "0000";
avm_read_i <= '0';
avm_write_i <= '0';
avm_rfifo_put <= '0';
avm_exec_count <= "000";
end if;
end if;
end process;
with state select debug_bits(2 downto 0) <=
"000" when idle,
"001" when do_write,
"010" when do_read,
"011" when do_read2,
"100" when do_read3,
"111" when others;
debug_bits(3) <= avm_read_i;
debug_bits(4) <= avm_write_i;
avm_read <= avm_read_i;
avm_write <= avm_write_i;
avm_wfifo_get <= '1' when avm_wfifo_valid = '1' and state = idle else '0';
avm_address <= std_logic_vector(address(31 downto 2) & "00");
avm_byteenable <= write_be;
avm_writedata <= write_data;
end arch;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-e.vhd,v 1.2 2005/07/19 07:13:15 wig Exp $
-- $Date: 2005/07/19 07:13:15 $
-- $Log: ios_e-e.vhd,v $
-- Revision 1.2 2005/07/19 07:13:15 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ios_e
--
entity ios_e is
-- Generics:
-- No Generated Generics for Entity ios_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end ios_e;
--
-- End of Generated Entity ios_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
entity ucecho is
port(
FXCLK : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd_prev : std_logic := '1';
signal wr : std_logic := '1';
signal wr_prev : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
begin
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(FXCLK)
begin
if FXCLK' event and FXCLK = '1' then
if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd_prev <= rd;
wr_prev <= wr;
end if;
end process dpUCECHO;
end RTL;
|
--
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
architecture Behavioral of vga_clk_div is
signal tmp_clkf : std_logic;
begin
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = 1) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
clkout <= tmp_clkf;
end process my_div_fast;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Functions Package File
-- Project :
-------------------------------------------------------------------------------
-- File : functions.vhd
-- Author : Lucas Groposo
-- Company :
-- Created : 2015-04-25
-- Last update : 2015-04-25
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-25 1.0 groposo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package functions_pkg is
function log2ceil (
L : positive)
return natural;
function srlInteger (
arg : integer;
s : natural)
return integer;
end package functions_pkg;
package body functions_pkg is
function log2ceil (L : positive) return natural is
variable i, bitCount : natural;
begin
i := L-1;
bitCount := 0;
while (i > 0) loop
bitCount := bitCount + 1;
i := srlInteger(i, 1);
end loop;
return bitCount;
end log2ceil;
function srlInteger(arg : integer; s : natural) return integer is
begin
return to_integer(SHIFT_RIGHT(to_UNSIGNED(ARG, 32), s));
end srlInteger;
end package body functions_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1612.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01612ent IS
END c08s11b00x00p04n01i01612ent;
ARCHITECTURE c08s11b00x00p04n01i01612arch OF c08s11b00x00p04n01i01612ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when "Tt";
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01612 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01612arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1612.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01612ent IS
END c08s11b00x00p04n01i01612ent;
ARCHITECTURE c08s11b00x00p04n01i01612arch OF c08s11b00x00p04n01i01612ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when "Tt";
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01612 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01612arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1612.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01612ent IS
END c08s11b00x00p04n01i01612ent;
ARCHITECTURE c08s11b00x00p04n01i01612arch OF c08s11b00x00p04n01i01612ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when "Tt";
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01612 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01612arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_data_pkg.all;
use work.cpu_l1mem_data_pkg.all;
entity cpu_l1mem_data is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_data_ctrl_in : out cpu_mmu_data_ctrl_in_type;
cpu_mmu_data_dp_in : out cpu_mmu_data_dp_in_type;
cpu_mmu_data_ctrl_out : in cpu_mmu_data_ctrl_out_type;
cpu_mmu_data_dp_out : in cpu_mmu_data_dp_out_type;
cpu_l1mem_data_ctrl_in : in cpu_l1mem_data_ctrl_in_type;
cpu_l1mem_data_dp_in : in cpu_l1mem_data_dp_in_type;
cpu_l1mem_data_ctrl_out : out cpu_l1mem_data_ctrl_out_type;
cpu_l1mem_data_dp_out : out cpu_l1mem_data_dp_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_master_dp_out : out sys_master_dp_out_type;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
sys_slave_dp_out : in sys_slave_dp_out_type
);
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ml506_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 21;
COUNT_CYCLES : boolean := false;
CLK_FREQ : positive := 100000000;
CLK_MUL : positive := 20;
CLK_DIV : positive := 11;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clkx : in std_logic;
rstx : in std_logic;
rx : in std_logic;
tx : out std_logic;
leds : out std_logic_vector(0 to 7)
);
end ml506_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of ml506_queens_uart is
-- Global Control
signal clk : std_logic;
signal rst : std_logic;
-- Solver Status
signal snap : std_logic_vector(3 downto 0);
signal avail : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clk_u : std_logic; -- Unbuffered Synthesized Clock
signal rst_s : std_logic_vector(1 downto 0) := (others => '0');
begin
DCM0 : DCM_BASE
generic map (
CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "HIGH",
DFS_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE -- Delay until DCM LOCK
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_u,
CLKFX180 => open,
LOCKED => open,
CLKFB => '0',
CLKIN => clkx,
RST => '0'
);
clk_buf : BUFG
port map (
I => clk_u,
O => clk
);
-- Reset Synchronization
process(clk)
begin
if rising_edge(clk) then
rst_s <= (not rstx) & rst_s(rst_s'left downto 1);
end if;
end process;
rst <= rst_s(0);
end block blkGlobal;
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk,
rst => rst,
rx => rx,
tx => tx,
snap => snap,
avail => avail
);
----------------------------------------------------------------------------
-- Basic Status Output
leds <= snap & std_logic_vector(to_unsigned((SOLVERS mod 7)+1, 3)) & avail;
end rtl;
|
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
if a = b then
sig3 <= sig4;
sig4 <= sig5;
if c = d then
sig6 <= sig7;
sig7 <= sig8;
end if;
end if;
case address is
when 0 =>
sig5 <= sig6;
sig6 <= sig7;
sig8 <= '0' when b = '1';
end case;
end process;
-- Violations below
process
begin
sig1 <= sig2;
sig2 <= sig3;
if a = b then
sig3 <= sig4;
sig4 <= sig5;
if c = d then
sig6 <= sig7;
sig7 <= sig8;
end if;
end if;
case address is
when 0 =>
sig5 <= sig6;
sig6 <= sig7;
sig8 <= '0' when b = '1';
end case;
end process;
end architecture RTL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END delayLineBRAM_exdes;
ARCHITECTURE xilinx OF delayLineBRAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT delayLineBRAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : delayLineBRAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END delayLineBRAM_exdes;
ARCHITECTURE xilinx OF delayLineBRAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT delayLineBRAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : delayLineBRAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D10_C2 is
port(
clk : in STD_LOGIC;
y : out STD_LOGIC
);
end D10_C2;
architecture D10_C2 of D10_C2 is
begin
process(clk)
begin
if(clk='1') then y<='1';
else y<='0';
end if;
end process;
end D10_C2;
--clk=0.5hz |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity post_norm_addsub is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
fract_28_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
sign_i : in std_logic;
fpu_op_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end post_norm_addsub;
architecture rtl of post_norm_addsub is
signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_fract_28_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_sign_i : std_logic;
signal s_fpu_op_i : std_logic;
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o : std_logic;
signal s_overflow : std_logic;
signal s_zeros, s_shr1, s_shl1 : std_logic_vector(5 downto 0);
signal s_shr2, s_carry : std_logic;
signal s_exp10: std_logic_vector(9 downto 0);
signal s_expo9_1, s_expo9_2, s_expo9_3: std_logic_vector(EXP_WIDTH downto 0);
signal s_fracto28_1, s_fracto28_2, s_fracto28_rnd : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_roundup : std_logic;
signal s_sticky : std_logic;
signal s_zero_fract : std_logic;
signal s_lost : std_logic;
signal s_infa, s_infb : std_logic;
signal s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign : std_logic;
begin
-- Input Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_opb_i <= opb_i;
s_fract_28_i <= fract_28_i;
s_exp_i <= exp_i;
s_sign_i <= sign_i;
s_fpu_op_i <= fpu_op_i;
s_rmode_i <= rmode_i;
-- end if;
--end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
end if;
end process;
--*** Stage 1 ****
-- figure out the output exponent and howmuch the fraction has to be shiftd right/left
s_carry <= s_fract_28_i(27);
s_zeros <= count_l_zeros(s_fract_28_i(26 downto 0)) when s_fract_28_i(27)='0' else "000000";
s_exp10 <= ("00"&s_exp_i) + ("000000000"&s_carry) - ("0000"&s_zeros); -- negative flag & large flag & exp
process(clk_i)
begin
if rising_edge(clk_i) then
if s_exp10(9)='1' or s_exp10="0000000000" then
s_shr1 <= (others =>'0');
if or_reduce(s_exp_i)/='0' then
s_shl1 <= s_exp_i(5 downto 0) - "000001";
else
s_shl1 <= "000000";
end if;
s_expo9_1 <= "000000001";
elsif s_exp10(8)='1' then
s_shr1 <= (others =>'0');
s_shl1 <= (others =>'0');
s_expo9_1 <= "011111111";
else
s_shr1 <= ("00000"&s_carry);
s_shl1 <= s_zeros;
s_expo9_1 <= s_exp10(8 downto 0);
end if;
end if;
end process;
---
-- *** Stage 2 ***
-- Shifting the fraction and rounding
process(clk_i)
begin
if rising_edge(clk_i) then
if s_shr1 /= "000000" then
s_fracto28_1 <= shr(s_fract_28_i, s_shr1);
else
s_fracto28_1 <= shl(s_fract_28_i, s_shl1);
end if;
end if;
end process;
s_expo9_2 <= s_expo9_1 - "000000001" when s_fracto28_1(27 downto 26)="00" else s_expo9_1;
-- round
s_sticky <='1' when s_fracto28_1(0)='1' or (s_fract_28_i(0) and s_fract_28_i(27))='1' else '0'; --check last bit, before and after right-shift
s_roundup <= s_fracto28_1(2) and ((s_fracto28_1(1) or s_sticky)or s_fracto28_1(3)) when s_rmode_i="00" else -- round to nearset even
(s_fracto28_1(2) or s_fracto28_1(1) or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
(s_fracto28_1(2) or s_fracto28_1(1) or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
'0'; -- round to zero(truncate = no rounding)
s_fracto28_rnd <= s_fracto28_1 + "0000000000000000000000001000" when s_roundup='1' else s_fracto28_1;
-- ***Stage 3***
-- right-shift after rounding (if necessary)
s_shr2 <= s_fracto28_rnd(27);
s_expo9_3 <= s_expo9_2 + "000000001" when s_shr2='1' and s_expo9_2 /= "011111111" else s_expo9_2;
s_fracto28_2 <= ("0"&s_fracto28_rnd(27 downto 1)) when s_shr2='1' else s_fracto28_rnd;
-----
s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
s_nan_in <= '1' when s_nan_a='1' or s_nan_b='1' else '0';
s_nan_op <= '1' when (s_infa and s_infb)='1' and (s_opa_i(31) xor (s_fpu_op_i xor s_opb_i(31)) )='1' else '0'; -- inf-inf=Nan
s_nan_sign <= s_sign_i when (s_nan_a and s_nan_b)='1' else
s_opa_i(31) when s_nan_a='1' else
s_opb_i(31);
-- check if result is inexact;
s_lost <= (s_shr1(0) and s_fract_28_i(0)) or (s_shr2 and s_fracto28_rnd(0)) or or_reduce(s_fracto28_2(2 downto 0));
s_ine_o <= '1' when (s_lost or s_overflow)='1' and (s_infa or s_infb)='0' else '0';
s_overflow <='1' when s_expo9_3="011111111" and (s_infa or s_infb)='0' else '0';
s_zero_fract <= '1' when s_zeros=27 and s_fract_28_i(27)='0' else '0'; -- '1' if fraction result is zero
process(s_sign_i, s_expo9_3, s_fracto28_2, s_nan_in, s_nan_op, s_nan_sign, s_infa, s_infb, s_overflow, s_zero_fract)
begin
if (s_nan_in or s_nan_op)='1' then
s_output_o <= s_nan_sign & QNAN;
elsif (s_infa or s_infb)='1' or s_overflow='1' then
s_output_o <= s_sign_i & INF;
elsif s_zero_fract='1' then
s_output_o <= s_sign_i & ZERO_VECTOR;
else
s_output_o <= s_sign_i & s_expo9_3(7 downto 0) & s_fracto28_2(25 downto 3);
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library heat_core_v1_00_a;
use heat_core_v1_00_a.user_logic;
entity heat_core is
generic
(
C_NUM_LUTS : integer := 1000;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5"
);
port
(
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity heat_core;
architecture IMP of heat_core is
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR,
ZERO_ADDR_PAD & USER_SLV_HIGHADDR
);
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG)
);
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
USER_LOGIC_I : entity heat_core_v1_00_a.user_logic
generic map
(
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_NUM_LUTS => C_NUM_LUTS
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd_display is
Port ( clk : in std_logic;
masterReset : in std_logic;
byte_in : in STD_LOGIC_VECTOR(7 downto 0);
bcd_val : out STD_LOGIC_VECTOR(11 downto 0)
);
end bcd_display;
architecture Behavioral of bcd_display is begin
process ( masterReset, clk, byte_in )
variable byte_src : std_logic_vector (4 downto 0) ;
variable bcd_out : std_logic_vector (11 downto 0) ;
begin
if(masterReset = '1') then
byte_src := (others => '0');
bcd_out := (others => '0');
bcd_val <= (others => '0');
elsif(clk'event and clk='1') then
bcd_out := (others => '0');
bcd_out(2 downto 0) := byte_in(7 downto 5);
byte_src := byte_in(4 downto 0);
for i in byte_src'range loop
if bcd_out(3 downto 0) > "0100" then
bcd_out(3 downto 0) := bcd_out(3 downto 0) + "0011";
end if ;
if bcd_out(7 downto 4) > "0100" then
bcd_out(7 downto 4) := bcd_out(7 downto 4) + "0011";
end if ;
-- No roll over for hundred digit
bcd_out := bcd_out(10 downto 0) & byte_src(byte_src'left) ;
byte_src := byte_src(byte_src'left - 1 downto byte_src'right) & '0' ;
end loop ;
bcd_val <= bcd_out + '1';
end if;
end process ;
end Behavioral;
--Reference: http://stackoverflow.com/questions/23871792/convert-8bit-binary-number-to-bcd-in-vhdl |
-- frank Vanbever 13/03/2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
--! Adder to calculate adresses for jumps
-------------------------------------------------------------------------------
entity jump_adder is
port(
-- input vectors
--! Current value of the PC
instruction : in std_logic_vector(31 downto 0);
--! Amount by which the current PC should be shifted
jmp_offset : in std_logic_vector(31 downto 0);
-- output vectors
--! New value for the program counter
jmp_adress : out std_logic_vector(31 downto 0)
);
end jump_adder;
-------------------------------------------------------------------------------
--! The architecture of this component is trivial, it adds 2 values together.
-------------------------------------------------------------------------------
architecture behavioral of jump_adder is
signal jmp_offset_shifted : std_logic_vector(31 downto 0);
begin
jmp_offset_shifted(31 downto 2) <= jmp_offset(29 downto 0);
jmp_offset_shifted(1 downto 0) <= (others => '0');
jmp_adress <= instruction + jmp_offset_shifted;
end behavioral;
|
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
process (IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val)
begin
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
|
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
process (IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val)
begin
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 47328)
`protect data_block
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|
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library open16750;
use open16750.UART;
use work.Constants.ALL;
entity PortController is
port (
CLK : in std_logic;
CLK16x : in std_logic;
XMit : in Word;
Recv : out Word;
SerialIn : in std_logic;
SerialOut : out std_logic;
instruction : in Word;
CPUReady : in std_logic;
CPUSending: in std_logic;
PortReady: out std_logic;
PortSending: out std_logic;
Done: out std_logic);
end PortController;
architecture Behavioral of PortController is
component UART is
generic (
word_length : integer range 5 to 8 := 8;
stop_bits : integer range 1 to 2 := 1;
has_parity : boolean := false;
parity_is_even : boolean := false;
baud_divisor : integer range 1 to 65535 := 1);
port (
clk : in std_logic;
rst : in std_logic;
-- This clock should run at 16 times the baud rate.
clk_16x : in std_logic;
serial_out : out std_logic;
serial_in : in std_logic;
din : in std_logic_vector(7 downto 0);
xmit_buffer_ready : out std_logic;
xmit_enable : in std_logic;
was_read : in std_logic;
recv_data_ready : out std_logic;
dout : out std_logic_vector(7 downto 0));
end component UART;
signal recv_s : Word := (others => '0');
signal portReady_s : std_logic := '0';
signal portSending_s : std_logic := '0';
signal done_s : std_logic := '0';
signal rst_s : std_logic := '1';
-- This clock should run at 16 times the baud rate.
signal din_s : std_logic_vector(7 downto 0) := (others => '0');
signal xmit_buffer_ready_s : std_logic;
signal xmit_enable_s : std_logic := '0';
signal was_read_s : std_logic := '0';
signal recv_data_ready_s : std_logic;
signal dout_s : std_logic_vector(7 downto 0);
begin
recv <= recv_s;
portReady <= portReady_s;
portSending <= portSending_s;
done <= done_s;
UART1 : UART generic map (
baud_divisor => 25
) port map (
clk => clk,
rst => rst_s,
clk_16x => CLK16x,
serial_in => serialIn,
serial_out => serialOut,
din => din_s,
xmit_buffer_ready => xmit_buffer_ready_s,
xmit_enable => xmit_enable_s,
was_read => was_read_s,
recv_data_ready => recv_data_ready_s,
dout => dout_s
);
process (clk) begin
if rising_edge(clk) then
if rst_s = '1' then
rst_s <= '0';
end if;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if GetOpcode(instruction) = OpcodePort and
(GetOperator(instruction) = LoadByteSigned or
GetOperator(instruction) = LoadHalfWordSigned or
GetOperator(instruction) = LoadByteUnsigned or
GetOperator(instruction) = LoadHalfWordUnsigned or
GetOperator(instruction) = LoadWord) and
getRegisterReferenceB(instruction) = "00001" then
if portSending_s = '0' then
portReady_s <= recv_data_ready_s;
if recv_data_ready_s = '1' and CPUReady = '1' then
portSending_s <= '1';
recv_s <= "000000000000000000000000" & dout_s;
was_read_s <= '1';
end if;
elsif portSending_s = '1' then
portSending_s <= '0';
portReady_s <= '0';
was_read_s <= '0';
recv_s <= (others => '0');
end if;
elsif GetOpcode(instruction) = OpcodePort and
(GetOperator(instruction) = StoreByte or
GetOperator(instruction) = StoreHalfWord or
GetOperator(instruction) = StoreWord) and
getRegisterReferenceB(instruction) = "00001" then
if done_s = '0' then
if CPUReady = '1' and xmit_buffer_ready_s = '1' then
din_s <= Xmit(7 downto 0);
done_s <= '1';
xmit_enable_s <= '1';
end if;
elsif done_s = '1' then
din_s <= (others => '0');
done_s <= '0';
xmit_enable_s <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: rxcver.vhd
--
-- Purpose: Main UART receiver logic module. Receives
-- incoming serial data and present parallel
-- byte of data to system. Includes rxrdy control
-- signals for handshaking of system bus. Includes
-- control flags for parity, overrun data, and
-- framing errors.
--
-- Created: VHDL code generated by Visual HDL 8-15-01
--
-- Revision 2.00 (Ning Chen): avoid latch
--
-- *******************************************************************
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
-- use work.pkg_util.all;
entity rxcver is
port (
mclkx16 : in STD_LOGIC;
read : in STD_LOGIC;
sin : in STD_LOGIC;
reset : in STD_LOGIC;
rxrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC;
rxdata : out STD_LOGIC_VECTOR(7 downto 0 )
);
end rxcver;
architecture behavior of rxcver is
-- Internal control signals.
signal rxcnt : STD_LOGIC_VECTOR(3 downto 0 ); -- Count of clock cycles
signal rx1 : STD_LOGIC; -- Delayed version signals
signal read1 : STD_LOGIC;
signal read2 : STD_LOGIC;
signal idle1 : STD_LOGIC;
signal hunt : STD_LOGIC;
-- Receive shift register bits
signal rhr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive hold register
signal rsr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive shift register
signal rxparity : STD_LOGIC; -- Received parity bit
signal paritygen : STD_LOGIC; -- Parity generated from received data
signal rxstop : STD_LOGIC; -- Received data stop bit
-- Receive clock and control signals.
signal rxclk : STD_LOGIC; -- Receive data shift clock
signal idle : STD_LOGIC; -- idle = 1 when receiver is idle
signal rxdatardy : STD_LOGIC; -- rsdatardy = 1 when data is ready to be read
begin
-- Idle signal enables rxclk generation - idle = 0 when not shifting data
-- idle = 1 when low "rxstop" bit = rsr[0]
process (rxclk, reset)
begin
if (reset) = '1' then
idle <= '1';
elsif (rxclk'event and rxclk = '1' ) then
idle <= not(idle) and not(rsr(0));
end if ;
end process ;
-- Synchronizing rxclk to the centerpoint of low leading startbit
process (mclkx16)
begin
if (mclkx16'event and mclkx16 = '1' ) then
-- A start bit is eight clock times with sin=0 after a falling edge of sin
if (reset) = '1' then
hunt <= '0';
else
-- Look for falling edge of sin
if (idle) = '1' and (sin = '0' ) and (rx1) = '1' then
hunt <= '1';
else
-- Stop when shifting in data, or a 1 is found on sin
if (idle = '0' ) or (sin) = '1' then
hunt <= '0';
end if ;
end if;
end if ;
if (idle = '0' ) or (hunt) = '1' then
-- Count clocks when not idle, or looking for start bit
rxcnt <= ext(ext(rxcnt,32) + 1,abs(3-0)+1);
else
-- Hold rxcnt = 1, when idle and waiting for falling edge of sin
rxcnt <= "0001";
end if ;
rx1 <= sin; -- Looking for falling edge detect on sin
rxclk <= rxcnt(3); -- rxclk = mclkx16 / 16
end if;
end process ;
-- When not idle, sample data at the sin input and create parity
process (rxclk, reset)
begin
if (reset) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
elsif (rxclk'event and rxclk = '1' ) then
if (idle) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
else
-- Right shift sin shift register
rsr <= std_logic_vector(SHR(unsigned(rsr) ,
unsigned'("00000000000000000000000000000001")));
rsr(7) <= rxparity; -- Load rsr[7] with rxparity
rxparity <= rxstop; -- Load rxparity with rxstop
rxstop <= sin; -- Load rxstop with sin
paritygen <= paritygen xor rxstop; -- Generate running parity
end if ;
end if ;
end process ;
-- Generate status & error flags
process (mclkx16, reset)
begin
if (reset) = '1' then
rhr <= "00000000";
rxdatardy <= '0';
overrun <= '0';
parity_error <= '0';
framing_error <= '0';
idle1 <= '1';
read2 <= '1';
read1 <= '1';
elsif (mclkx16'event and mclkx16 = '1' ) then
-- Look for rising edge of idle and update output registers
if (idle) = '1' and (idle1 = '0' ) then
if (rxdatardy) = '1' then
overrun <= '1'; -- Overrun error, if previous data
-- still in holding register
else
overrun <= '0'; -- No overrun error, since holding register is empty
rhr <= rsr; -- Update holding register with contens of shift register
parity_error <= paritygen; -- paritygen = 1, if parity error
framing_error <= not(rxstop); -- framing_error, if stop bit is not 1
rxdatardy <= '1'; -- Data is ready for reading flag
end if ;
end if ;
-- Clear error and data registers when data is read
if (read2 = '0' ) and (read1) = '1' then
rxdatardy <= '0';
parity_error <= '0';
framing_error <= '0';
overrun <= '0';
end if ;
idle1 <= idle; -- Edge detect on idle signal
read2 <= read1; -- 2 cycle delayed version of read - edge detection
read1 <= read; -- 1 cycle delayed version of read - edge detection
end if ;
end process ;
rxrdy <= rxdatardy; -- Receive data ready output signal
process (read, rhr)
begin
if not((read) = '1' ) then
rxdata <= rhr;
else
rxdata <= rhr;
end if ;
end process ;
-- Latch data output when read goes low
end ;
|
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: rxcver.vhd
--
-- Purpose: Main UART receiver logic module. Receives
-- incoming serial data and present parallel
-- byte of data to system. Includes rxrdy control
-- signals for handshaking of system bus. Includes
-- control flags for parity, overrun data, and
-- framing errors.
--
-- Created: VHDL code generated by Visual HDL 8-15-01
--
-- Revision 2.00 (Ning Chen): avoid latch
--
-- *******************************************************************
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
-- use work.pkg_util.all;
entity rxcver is
port (
mclkx16 : in STD_LOGIC;
read : in STD_LOGIC;
sin : in STD_LOGIC;
reset : in STD_LOGIC;
rxrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC;
rxdata : out STD_LOGIC_VECTOR(7 downto 0 )
);
end rxcver;
architecture behavior of rxcver is
-- Internal control signals.
signal rxcnt : STD_LOGIC_VECTOR(3 downto 0 ); -- Count of clock cycles
signal rx1 : STD_LOGIC; -- Delayed version signals
signal read1 : STD_LOGIC;
signal read2 : STD_LOGIC;
signal idle1 : STD_LOGIC;
signal hunt : STD_LOGIC;
-- Receive shift register bits
signal rhr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive hold register
signal rsr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive shift register
signal rxparity : STD_LOGIC; -- Received parity bit
signal paritygen : STD_LOGIC; -- Parity generated from received data
signal rxstop : STD_LOGIC; -- Received data stop bit
-- Receive clock and control signals.
signal rxclk : STD_LOGIC; -- Receive data shift clock
signal idle : STD_LOGIC; -- idle = 1 when receiver is idle
signal rxdatardy : STD_LOGIC; -- rsdatardy = 1 when data is ready to be read
begin
-- Idle signal enables rxclk generation - idle = 0 when not shifting data
-- idle = 1 when low "rxstop" bit = rsr[0]
process (rxclk, reset)
begin
if (reset) = '1' then
idle <= '1';
elsif (rxclk'event and rxclk = '1' ) then
idle <= not(idle) and not(rsr(0));
end if ;
end process ;
-- Synchronizing rxclk to the centerpoint of low leading startbit
process (mclkx16)
begin
if (mclkx16'event and mclkx16 = '1' ) then
-- A start bit is eight clock times with sin=0 after a falling edge of sin
if (reset) = '1' then
hunt <= '0';
else
-- Look for falling edge of sin
if (idle) = '1' and (sin = '0' ) and (rx1) = '1' then
hunt <= '1';
else
-- Stop when shifting in data, or a 1 is found on sin
if (idle = '0' ) or (sin) = '1' then
hunt <= '0';
end if ;
end if;
end if ;
if (idle = '0' ) or (hunt) = '1' then
-- Count clocks when not idle, or looking for start bit
rxcnt <= ext(ext(rxcnt,32) + 1,abs(3-0)+1);
else
-- Hold rxcnt = 1, when idle and waiting for falling edge of sin
rxcnt <= "0001";
end if ;
rx1 <= sin; -- Looking for falling edge detect on sin
rxclk <= rxcnt(3); -- rxclk = mclkx16 / 16
end if;
end process ;
-- When not idle, sample data at the sin input and create parity
process (rxclk, reset)
begin
if (reset) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
elsif (rxclk'event and rxclk = '1' ) then
if (idle) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
else
-- Right shift sin shift register
rsr <= std_logic_vector(SHR(unsigned(rsr) ,
unsigned'("00000000000000000000000000000001")));
rsr(7) <= rxparity; -- Load rsr[7] with rxparity
rxparity <= rxstop; -- Load rxparity with rxstop
rxstop <= sin; -- Load rxstop with sin
paritygen <= paritygen xor rxstop; -- Generate running parity
end if ;
end if ;
end process ;
-- Generate status & error flags
process (mclkx16, reset)
begin
if (reset) = '1' then
rhr <= "00000000";
rxdatardy <= '0';
overrun <= '0';
parity_error <= '0';
framing_error <= '0';
idle1 <= '1';
read2 <= '1';
read1 <= '1';
elsif (mclkx16'event and mclkx16 = '1' ) then
-- Look for rising edge of idle and update output registers
if (idle) = '1' and (idle1 = '0' ) then
if (rxdatardy) = '1' then
overrun <= '1'; -- Overrun error, if previous data
-- still in holding register
else
overrun <= '0'; -- No overrun error, since holding register is empty
rhr <= rsr; -- Update holding register with contens of shift register
parity_error <= paritygen; -- paritygen = 1, if parity error
framing_error <= not(rxstop); -- framing_error, if stop bit is not 1
rxdatardy <= '1'; -- Data is ready for reading flag
end if ;
end if ;
-- Clear error and data registers when data is read
if (read2 = '0' ) and (read1) = '1' then
rxdatardy <= '0';
parity_error <= '0';
framing_error <= '0';
overrun <= '0';
end if ;
idle1 <= idle; -- Edge detect on idle signal
read2 <= read1; -- 2 cycle delayed version of read - edge detection
read1 <= read; -- 1 cycle delayed version of read - edge detection
end if ;
end process ;
rxrdy <= rxdatardy; -- Receive data ready output signal
process (read, rhr)
begin
if not((read) = '1' ) then
rxdata <= rhr;
else
rxdata <= rhr;
end if ;
end process ;
-- Latch data output when read goes low
end ;
|
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: rxcver.vhd
--
-- Purpose: Main UART receiver logic module. Receives
-- incoming serial data and present parallel
-- byte of data to system. Includes rxrdy control
-- signals for handshaking of system bus. Includes
-- control flags for parity, overrun data, and
-- framing errors.
--
-- Created: VHDL code generated by Visual HDL 8-15-01
--
-- Revision 2.00 (Ning Chen): avoid latch
--
-- *******************************************************************
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
-- use work.pkg_util.all;
entity rxcver is
port (
mclkx16 : in STD_LOGIC;
read : in STD_LOGIC;
sin : in STD_LOGIC;
reset : in STD_LOGIC;
rxrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC;
rxdata : out STD_LOGIC_VECTOR(7 downto 0 )
);
end rxcver;
architecture behavior of rxcver is
-- Internal control signals.
signal rxcnt : STD_LOGIC_VECTOR(3 downto 0 ); -- Count of clock cycles
signal rx1 : STD_LOGIC; -- Delayed version signals
signal read1 : STD_LOGIC;
signal read2 : STD_LOGIC;
signal idle1 : STD_LOGIC;
signal hunt : STD_LOGIC;
-- Receive shift register bits
signal rhr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive hold register
signal rsr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive shift register
signal rxparity : STD_LOGIC; -- Received parity bit
signal paritygen : STD_LOGIC; -- Parity generated from received data
signal rxstop : STD_LOGIC; -- Received data stop bit
-- Receive clock and control signals.
signal rxclk : STD_LOGIC; -- Receive data shift clock
signal idle : STD_LOGIC; -- idle = 1 when receiver is idle
signal rxdatardy : STD_LOGIC; -- rsdatardy = 1 when data is ready to be read
begin
-- Idle signal enables rxclk generation - idle = 0 when not shifting data
-- idle = 1 when low "rxstop" bit = rsr[0]
process (rxclk, reset)
begin
if (reset) = '1' then
idle <= '1';
elsif (rxclk'event and rxclk = '1' ) then
idle <= not(idle) and not(rsr(0));
end if ;
end process ;
-- Synchronizing rxclk to the centerpoint of low leading startbit
process (mclkx16)
begin
if (mclkx16'event and mclkx16 = '1' ) then
-- A start bit is eight clock times with sin=0 after a falling edge of sin
if (reset) = '1' then
hunt <= '0';
else
-- Look for falling edge of sin
if (idle) = '1' and (sin = '0' ) and (rx1) = '1' then
hunt <= '1';
else
-- Stop when shifting in data, or a 1 is found on sin
if (idle = '0' ) or (sin) = '1' then
hunt <= '0';
end if ;
end if;
end if ;
if (idle = '0' ) or (hunt) = '1' then
-- Count clocks when not idle, or looking for start bit
rxcnt <= ext(ext(rxcnt,32) + 1,abs(3-0)+1);
else
-- Hold rxcnt = 1, when idle and waiting for falling edge of sin
rxcnt <= "0001";
end if ;
rx1 <= sin; -- Looking for falling edge detect on sin
rxclk <= rxcnt(3); -- rxclk = mclkx16 / 16
end if;
end process ;
-- When not idle, sample data at the sin input and create parity
process (rxclk, reset)
begin
if (reset) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
elsif (rxclk'event and rxclk = '1' ) then
if (idle) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
else
-- Right shift sin shift register
rsr <= std_logic_vector(SHR(unsigned(rsr) ,
unsigned'("00000000000000000000000000000001")));
rsr(7) <= rxparity; -- Load rsr[7] with rxparity
rxparity <= rxstop; -- Load rxparity with rxstop
rxstop <= sin; -- Load rxstop with sin
paritygen <= paritygen xor rxstop; -- Generate running parity
end if ;
end if ;
end process ;
-- Generate status & error flags
process (mclkx16, reset)
begin
if (reset) = '1' then
rhr <= "00000000";
rxdatardy <= '0';
overrun <= '0';
parity_error <= '0';
framing_error <= '0';
idle1 <= '1';
read2 <= '1';
read1 <= '1';
elsif (mclkx16'event and mclkx16 = '1' ) then
-- Look for rising edge of idle and update output registers
if (idle) = '1' and (idle1 = '0' ) then
if (rxdatardy) = '1' then
overrun <= '1'; -- Overrun error, if previous data
-- still in holding register
else
overrun <= '0'; -- No overrun error, since holding register is empty
rhr <= rsr; -- Update holding register with contens of shift register
parity_error <= paritygen; -- paritygen = 1, if parity error
framing_error <= not(rxstop); -- framing_error, if stop bit is not 1
rxdatardy <= '1'; -- Data is ready for reading flag
end if ;
end if ;
-- Clear error and data registers when data is read
if (read2 = '0' ) and (read1) = '1' then
rxdatardy <= '0';
parity_error <= '0';
framing_error <= '0';
overrun <= '0';
end if ;
idle1 <= idle; -- Edge detect on idle signal
read2 <= read1; -- 2 cycle delayed version of read - edge detection
read1 <= read; -- 1 cycle delayed version of read - edge detection
end if ;
end process ;
rxrdy <= rxdatardy; -- Receive data ready output signal
process (read, rhr)
begin
if not((read) = '1' ) then
rxdata <= rhr;
else
rxdata <= rhr;
end if ;
end process ;
-- Latch data output when read goes low
end ;
|
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: rxcver.vhd
--
-- Purpose: Main UART receiver logic module. Receives
-- incoming serial data and present parallel
-- byte of data to system. Includes rxrdy control
-- signals for handshaking of system bus. Includes
-- control flags for parity, overrun data, and
-- framing errors.
--
-- Created: VHDL code generated by Visual HDL 8-15-01
--
-- Revision 2.00 (Ning Chen): avoid latch
--
-- *******************************************************************
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
-- use work.pkg_util.all;
entity rxcver is
port (
mclkx16 : in STD_LOGIC;
read : in STD_LOGIC;
sin : in STD_LOGIC;
reset : in STD_LOGIC;
rxrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC;
rxdata : out STD_LOGIC_VECTOR(7 downto 0 )
);
end rxcver;
architecture behavior of rxcver is
-- Internal control signals.
signal rxcnt : STD_LOGIC_VECTOR(3 downto 0 ); -- Count of clock cycles
signal rx1 : STD_LOGIC; -- Delayed version signals
signal read1 : STD_LOGIC;
signal read2 : STD_LOGIC;
signal idle1 : STD_LOGIC;
signal hunt : STD_LOGIC;
-- Receive shift register bits
signal rhr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive hold register
signal rsr : STD_LOGIC_VECTOR(7 downto 0 ); -- Receive shift register
signal rxparity : STD_LOGIC; -- Received parity bit
signal paritygen : STD_LOGIC; -- Parity generated from received data
signal rxstop : STD_LOGIC; -- Received data stop bit
-- Receive clock and control signals.
signal rxclk : STD_LOGIC; -- Receive data shift clock
signal idle : STD_LOGIC; -- idle = 1 when receiver is idle
signal rxdatardy : STD_LOGIC; -- rsdatardy = 1 when data is ready to be read
begin
-- Idle signal enables rxclk generation - idle = 0 when not shifting data
-- idle = 1 when low "rxstop" bit = rsr[0]
process (rxclk, reset)
begin
if (reset) = '1' then
idle <= '1';
elsif (rxclk'event and rxclk = '1' ) then
idle <= not(idle) and not(rsr(0));
end if ;
end process ;
-- Synchronizing rxclk to the centerpoint of low leading startbit
process (mclkx16)
begin
if (mclkx16'event and mclkx16 = '1' ) then
-- A start bit is eight clock times with sin=0 after a falling edge of sin
if (reset) = '1' then
hunt <= '0';
else
-- Look for falling edge of sin
if (idle) = '1' and (sin = '0' ) and (rx1) = '1' then
hunt <= '1';
else
-- Stop when shifting in data, or a 1 is found on sin
if (idle = '0' ) or (sin) = '1' then
hunt <= '0';
end if ;
end if;
end if ;
if (idle = '0' ) or (hunt) = '1' then
-- Count clocks when not idle, or looking for start bit
rxcnt <= ext(ext(rxcnt,32) + 1,abs(3-0)+1);
else
-- Hold rxcnt = 1, when idle and waiting for falling edge of sin
rxcnt <= "0001";
end if ;
rx1 <= sin; -- Looking for falling edge detect on sin
rxclk <= rxcnt(3); -- rxclk = mclkx16 / 16
end if;
end process ;
-- When not idle, sample data at the sin input and create parity
process (rxclk, reset)
begin
if (reset) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
elsif (rxclk'event and rxclk = '1' ) then
if (idle) = '1' then
rsr <= "11111111"; -- Initialize shift register
rxparity <= '1'; -- Set to 1 -> for data shifting
paritygen <= '1'; -- Set to 1 -> odd parity mode
rxstop <= '0'; -- Controls idle = 1, when rsr[0] gets rxstop bit
else
-- Right shift sin shift register
rsr <= std_logic_vector(SHR(unsigned(rsr) ,
unsigned'("00000000000000000000000000000001")));
rsr(7) <= rxparity; -- Load rsr[7] with rxparity
rxparity <= rxstop; -- Load rxparity with rxstop
rxstop <= sin; -- Load rxstop with sin
paritygen <= paritygen xor rxstop; -- Generate running parity
end if ;
end if ;
end process ;
-- Generate status & error flags
process (mclkx16, reset)
begin
if (reset) = '1' then
rhr <= "00000000";
rxdatardy <= '0';
overrun <= '0';
parity_error <= '0';
framing_error <= '0';
idle1 <= '1';
read2 <= '1';
read1 <= '1';
elsif (mclkx16'event and mclkx16 = '1' ) then
-- Look for rising edge of idle and update output registers
if (idle) = '1' and (idle1 = '0' ) then
if (rxdatardy) = '1' then
overrun <= '1'; -- Overrun error, if previous data
-- still in holding register
else
overrun <= '0'; -- No overrun error, since holding register is empty
rhr <= rsr; -- Update holding register with contens of shift register
parity_error <= paritygen; -- paritygen = 1, if parity error
framing_error <= not(rxstop); -- framing_error, if stop bit is not 1
rxdatardy <= '1'; -- Data is ready for reading flag
end if ;
end if ;
-- Clear error and data registers when data is read
if (read2 = '0' ) and (read1) = '1' then
rxdatardy <= '0';
parity_error <= '0';
framing_error <= '0';
overrun <= '0';
end if ;
idle1 <= idle; -- Edge detect on idle signal
read2 <= read1; -- 2 cycle delayed version of read - edge detection
read1 <= read; -- 1 cycle delayed version of read - edge detection
end if ;
end process ;
rxrdy <= rxdatardy; -- Receive data ready output signal
process (read, rhr)
begin
if not((read) = '1' ) then
rxdata <= rhr;
else
rxdata <= rhr;
end if ;
end process ;
-- Latch data output when read goes low
end ;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k1_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k1_k4_e-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_k1_k4_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_k1_k4_rtl_conf / inst_k1_k4_e
--
configuration inst_k1_k4_rtl_conf of inst_k1_k4_e is
for rtl
-- Generated Configuration
end for;
end inst_k1_k4_rtl_conf;
--
-- End of Generated Configuration inst_k1_k4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Apr 14 18:32:23 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top bd_proc_sys_reset_1_0 -prefix
-- bd_proc_sys_reset_1_0_ bd_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : bd_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_cdc_sync;
architecture STRUCTURE of bd_proc_sys_reset_1_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_proc_sys_reset_1_0_cdc_sync_0 : entity is "cdc_sync";
end bd_proc_sys_reset_1_0_cdc_sync_0;
architecture STRUCTURE of bd_proc_sys_reset_1_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_upcnt_n;
architecture STRUCTURE of bd_proc_sys_reset_1_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_lpf;
architecture STRUCTURE of bd_proc_sys_reset_1_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.bd_proc_sys_reset_1_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.bd_proc_sys_reset_1_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_sequence_psr;
architecture STRUCTURE of bd_proc_sys_reset_1_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.bd_proc_sys_reset_1_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_proc_sys_reset_1_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
end bd_proc_sys_reset_1_0_proc_sys_reset;
architecture STRUCTURE of bd_proc_sys_reset_1_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.bd_proc_sys_reset_1_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.bd_proc_sys_reset_1_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bd_proc_sys_reset_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bd_proc_sys_reset_1_0 : entity is "bd_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bd_proc_sys_reset_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bd_proc_sys_reset_1_0 : entity is "proc_sys_reset,Vivado 2016.4";
end bd_proc_sys_reset_1_0;
architecture STRUCTURE of bd_proc_sys_reset_1_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.bd_proc_sys_reset_1_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:47 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_stub.vhdl
-- Design : bg_pole
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_pole is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_pole;
architecture stub of bg_pole is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[6:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:47 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_stub.vhdl
-- Design : bg_pole
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_pole is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_pole;
architecture stub of bg_pole is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[6:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Module Name: scrambler_reset_inserter - Behavioral
--
-- Description: Replaces one in 512 Blank Start (BS) symbols with
-- a Scrambler Reset (SR).
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email (hamster@snap.net.nz)?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-10-13 | Optimize out 72 registers :-)
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0) := (others => '0')
);
end entity;
architecture arch of scrambler_reset_inserter is
signal bs_count : unsigned(8 downto 0) := (others => '0'); -- Cycles from 0 to 511
signal substitue_next : std_logic := '0';
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
begin
process(in_data,bs_count,substitue_next)
begin
out_data <= in_data;
if in_data(8 downto 0) = BS then
if substitue_next = '1' then
out_data( 8 downto 0) <= SR;
out_data(26 downto 18) <= SR;
out_data(44 downto 36) <= SR;
out_data(62 downto 54) <= SR;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
------------------------------------------------
-- Subsitute every 512nd Blank start (BS) symbol
-- with a Scrambler Reset (SR) symbol.
------------------------------------------------
if in_data(8 downto 0) = BS then
if bs_count = 0 then
substitue_next <= '1';
else
substitue_next <= '0';
end if;
bs_count <= bs_count + 1;
end if;
end if;
end process;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNGQ56ZS4N is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "1";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNGQ56ZS4N is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNGQ56ZS4N is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "1";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNGQ56ZS4N is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNGQ56ZS4N is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "1";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNGQ56ZS4N is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNGQ56ZS4N is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "1";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNGQ56ZS4N is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- First-in, first-out buffer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fifo is
generic (
-- FIFO depth
depth_g : positive := 32;
-- Data bit width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Write port
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
done_o : out std_ulogic;
full_o : out std_ulogic;
-- Read port
rd_en_i : in std_ulogic;
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
empty_o : out std_ulogic);
end entity fifo;
architecture rtl of fifo is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
type mem_t is array (0 to depth_g - 1) of std_ulogic_vector(data_i'range);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal mem : mem_t;
signal wr_addr : unsigned(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
signal rd_addr : unsigned(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
signal data : std_ulogic_vector(data_o'range);
signal data_en : std_ulogic;
signal done : std_ulogic;
signal op : std_ulogic;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal full : std_ulogic;
signal empty : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data;
data_en_o <= data_en;
done_o <= done;
full_o <= full;
empty_o <= empty;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
wr_addr <= to_unsigned(0, wr_addr'length);
rd_addr <= to_unsigned(0, rd_addr'length);
data <= (others => '0');
data_en <= '0';
done <= '0';
op <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
data_en <= '0';
done <= '0';
if rst_syn_i = '1' then
reset;
else
if wr_en_i = '1' and full = '0' then
mem(to_integer(wr_addr)) <= data_i;
done <= '1';
op <= '1';
if to_integer(wr_addr) < depth_g - 1 then
wr_addr <= wr_addr + 1;
else
wr_addr <= to_unsigned(0, wr_addr'length);
end if;
elsif wr_en_i = '0' and rd_en_i = '1' and empty = '0' then
data <= mem(to_integer(rd_addr));
data_en <= '1';
op <= '0';
if to_integer(rd_addr) < depth_g -1 then
rd_addr <= rd_addr + 1;
else
rd_addr <= to_unsigned(0, rd_addr'length);
end if;
end if;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
comb : process (wr_addr, rd_addr, op) is
begin -- process comb
-- Defaults
empty <= '0';
full <= '0';
if wr_addr = rd_addr then
if op = '1' then
full <= '1';
else
empty <= '1';
end if;
end if;
end process comb;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CpuWrapper is
generic (
CImplDebugger : boolean := false;
CImplCpu65c02 : boolean := false
);
port (
clk_main : in std_logic;
clk_avr : in std_logic;
cpu_clken : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
RST_n : in std_logic;
PRST_n : in std_logic;
SO : in std_logic;
RDY : in std_logic;
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
R_W_n : out std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
avr_RxD : in std_logic;
avr_TxD : out std_logic
);
end CpuWrapper;
architecture BEHAVIORAL of CpuWrapper is
signal cpu_clken1 : std_logic;
signal Addr_us : unsigned(15 downto 0);
signal Dout_us : unsigned(7 downto 0);
signal Din_us : unsigned(7 downto 0);
begin
process(clk_main)
begin
if rising_edge(clk_main) then
cpu_clken1 <= cpu_clken;
end if;
end process;
---------------------------------------------------------------------
-- 6502/65C02 CPU (using ICET65 Debugger)
---------------------------------------------------------------------
debugger_nmos: if CImplDebugger and not CImplCpu65c02 generate
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => true,
UseAlanDCore => false,
num_comparators => 8,
filename => "avr_progmem_ice6502.data"
)
port map (
clock_avr => clk_avr,
busmon_clk => clk_main,
busmon_clken => cpu_clken1,
cpu_clk => clk_main,
cpu_clken => cpu_clken,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n,
Din => Din,
Dout => Dout,
SO_n => SO,
Res_n => RST_n,
Rdy => RDY,
trig => "00",
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => '0',
sw_reset_avr => not PRST_n
);
end generate;
debugger_cmos: if CImplDebugger and CImplCpu65c02 generate
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => false,
UseAlanDCore => true,
num_comparators => 8,
filename => "avr_progmem_ice65c02.data"
)
port map (
clock_avr => clk_avr,
busmon_clk => clk_main,
busmon_clken => cpu_clken1,
cpu_clk => clk_main,
cpu_clken => cpu_clken,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n,
Din => Din,
Dout => Dout,
SO_n => SO,
Res_n => RST_n,
Rdy => RDY,
trig => "00",
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => '0',
sw_reset_avr => not PRST_n
);
end generate;
---------------------------------------------------------------------
-- 6502 CPU (using T65 core)
---------------------------------------------------------------------
not_debugger_nmos: if not CImplDebugger and not CImplCpu65c02 generate
cpu : entity work.T65 port map (
Mode => "00",
Abort_n => '1',
SO_n => SO,
Res_n => RST_n,
Enable => cpu_clken,
Clk => clk_main,
Rdy => RDY,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
R_W_n => R_W_n,
Sync => Sync,
A(23 downto 16) => open,
A(15 downto 0) => Addr(15 downto 0),
DI(7 downto 0) => Din(7 downto 0),
DO(7 downto 0) => Dout(7 downto 0)
);
avr_TxD <= '1';
end generate;
---------------------------------------------------------------------
-- 65C02 CPU (using AlanD core)
---------------------------------------------------------------------
-- TODO: Need to add RDY
not_debugger_cmos: if not CImplDebugger and CImplCpu65c02 generate
inst_r65c02: entity work.r65c02 port map (
reset => RST_n,
clk => clk_main,
enable => cpu_clken,
nmi_n => NMI_n,
irq_n => IRQ_n,
di => Din_us,
do => Dout_us,
addr => Addr_us,
nwe => R_W_n,
sync => Sync
);
Din_us <= unsigned(Din);
Dout <= std_logic_vector(Dout_us);
Addr <= std_logic_vector(Addr_us);
avr_TxD <= '1';
end generate;
end BEHAVIORAL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity observation is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- CHANGE 1 OF 7
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
-- END CHANGE
);
end observation;
architecture Behavioral of observation is
component uf_extract_observation is
Port(
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input data address
input_data_address : in std_logic_vector(0 to 31);
input_data_needed : out std_logic;
-- get word data
word_data_en : in std_logic;
word_address : out std_logic_vector(0 to 31);
word_data : in std_logic_vector(0 to 31);
word_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
constant C_MB_EXIT : std_logic_vector(0 to 31) := X"00000003";
-- states
type state_t is (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_CALCULATE_REMAINING_OBSERVATIONS_6,
STATE_CALCULATE_REMAINING_OBSERVATIONS_7,
STATE_CALCULATE_REMAINING_OBSERVATIONS_8,
STATE_CALCULATE_REMAINING_OBSERVATIONS_9,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_READ_NEXT_PARTICLE,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_INPUT_DATA,
STATE_CACHE_HIT,
STATE_CACHE_MISS,
STATE_CACHE_MISS_2,
STATE_LOAD_WORD,
STATE_LOAD_WORD_2,
STATE_WRITE_WORD_BACK,
STATE_WRITE_WORD_ACK,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_EXIT
); -- 51 states = 0x00 - 0x32
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F",
X"20",
X"21",
X"22",
X"23",
X"24",
X"25",
X"26",
X"27",
X"28",
X"29",
X"2A",
X"2B",
X"2C",
X"2D",
X"2E",
X"2F",
X"30",
X"31",
X"32",
X"33"
);
constant decode : decode_t := (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_CALCULATE_REMAINING_OBSERVATIONS_6,
STATE_CALCULATE_REMAINING_OBSERVATIONS_7,
STATE_CALCULATE_REMAINING_OBSERVATIONS_8,
STATE_CALCULATE_REMAINING_OBSERVATIONS_9,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_READ_NEXT_PARTICLE,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_INPUT_DATA,
STATE_CACHE_HIT,
STATE_CACHE_MISS,
STATE_CACHE_MISS_2,
STATE_LOAD_WORD,
STATE_LOAD_WORD_2,
STATE_WRITE_WORD_BACK,
STATE_WRITE_WORD_ACK,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_EXIT
);
-- current state
signal state : state_t := STATE_CHECK;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- := "00010000000000000000000000000000";
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--local RAM cache addresses
signal local_ram_cache_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := "00000000000000000001111110000000";
signal local_ram_cache_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := "011111100000";
signal cache_min : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal cache_max : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- lin/pointer to memory word, where the input address is stored
signal input_data_link_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of observations
signal remaining_observations : integer := 2;
-- number of needed bursts
signal number_of_bursts : integer := 3;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 3;
-- length of last burst
signal length_of_last_burst : integer := 7;
-- size of a particle
signal particle_size : integer := 32;
-- number of particles
signal N : integer := 20;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal cache_offset : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 2;
-- current particle data
signal particle_data : integer := 0;
-- parameter address
signal parameter_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter size
signal parameter_size : integer := 0;
-- parameter loaded
signal parameter_loaded : std_logic := '0';
-- parameters acknowledged by user process
signal parameter_loaded_ack : std_logic; -- := '0';
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- new particle loaded
signal new_particle : std_logic := '0';
-- new particle loaded - ackowledgement
signal new_particle_ack : std_logic := '1';
-- input data address
signal input_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- input data needed signal
signal input_data_needed : std_logic := '0';
-- word data enable
signal word_data_en : std_logic := '0';
-- word data address
signal word_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- word address
signal word_address : std_logic_vector(0 to 31) := (others => '0');
-- word_ack
signal word_data_ack : std_logic := '0';
-- if the observation is extracted, this signal is set to '1'
signal finished : std_logic := '1';
--current address
signal current_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrExtractObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this observation thread
signal o_RAMAddrObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEExtractObservation : std_logic := '0';
-- for switch 2: Write enable, observation
signal o_RAMWEObservation : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataExtractObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, observation
signal o_RAMDataObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_extract_observation
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrExtractObservation,
o_RAMData=>o_RAMDataExtractObservation, i_RAMData=>i_RAMData,
o_RAMWE=>o_RAMWEExtractObservation, o_RAMClk=>o_RAMClk,
parameter_loaded=>parameter_loaded, parameter_loaded_ack=>parameter_loaded_ack,
new_particle=>new_particle, new_particle_ack=>new_particle_ack,
input_data_address=>input_data_address, input_data_needed=>input_data_needed,
word_data_en=>word_data_en, word_address=>word_address,
word_data=>word_data, word_data_ack=>word_data_ack,
init=>init, enable=>enable, finished=>finished);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrExtractObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrExtractObservation(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrObservation(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEExtractObservation when enable = '1' else o_RAMWEObservation;
-- switch 3: output ram data
o_RAMData <= o_RAMDataExtractObservation when enable = '1' else o_RAMDataObservation;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
--
-- 1) read data from information struct
--
-- 2) receive message m
--
-- 3) set current address for input data
--
-- 4) load current particle (into local ram, starting address (others=>'0'))
--
-- 5) start user process for observation extraction
--
-- 6) wait for finished signal of user process
--
-- 7) write observation into main memory (from local ram, starting address (others=>'0'))
--
-- 8) if more particle need to be processed
-- go to step 4
-- else
-- go to step 9
--
-- 9) send message m
--
-- 9*) send measurement
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable parameter_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable preempted : boolean;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"0B0B0B0B");
resume_state_enc := (others => '0');
done := false;
success := false;
preempted := false;
state <= STATE_CHECK;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case (state) is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
-- preempted
preempted := true;
state <= decode(to_integer(unsigned(resume_state_enc)));
else
-- unpreempted
state <= STATE_INIT;
end if;
end if;
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
local_ram_cache_address <= "00000000000000000001111110000000";
local_ram_cache_address_if <= "011111100000";
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
new_particle <= '0';
parameter_loaded <= '0';
-- CHANGE CHANGE CHANGE
state <= STATE_READ_PARTICLE_ADDRESS;
--state <= STATE_WAIT_FOR_MESSAGE;
-- END OF CHANGE CHANGE CHANGE
-- CHANGE 2 OF 7
--state <= STATE_NEEDED_BURSTS;
-- END CHANGE
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ INFORMATION_STRUCT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
state <= STATE_LENGTH_LAST_BURST;
when STATE_LENGTH_LAST_BURST =>
--! calculate number of reads (1 of 2)
length_of_last_burst <= observation_size mod 128;
state <= STATE_LENGTH_LAST_BURST_2;
when STATE_LENGTH_LAST_BURST_2 =>
--! calculate number of reads (2 of 2)
length_of_last_burst <= length_of_last_burst / 8;
state <= STATE_READ_OBSERVATION_ARRAY_ADDRESS;
-- CHANGE 3 OF 7
--state <= STATE_WAIT_FOR_MESSAGE;
-- END CHANGE
when STATE_READ_OBSERVATION_ARRAY_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_INPUT_DATA_LINK_ADDRESS;
end if;
when STATE_READ_INPUT_DATA_LINK_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+24, input_data_link_address);
if done then
--state <= STATE_WAIT_FOR_MESSAGE;
state <= STATE_READ_PARAMETER_SIZE;
end if;
when STATE_READ_PARAMETER_SIZE =>
--! read parameter size
reconos_read (done, o_osif, i_osif, information_struct+28, parameter_size_var);
if done then
parameter_size <= TO_INTEGER(SIGNED(parameter_size_var));
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, information_struct+32, parameter_address);
if done then
state <= STATE_COPY_PARAMETER;
local_ram_address_if <= local_ram_start_address_if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ PARAMETERS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_COPY_PARAMETER =>
--! read parameter size
o_RAMWEObservation <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= STATE_COPY_PARAMETER_2;
else
state <= STATE_COPY_PARAMETER_ACK;
parameter_loaded <= '1';
enable <= '1';
init <= '0';
end if;
when STATE_COPY_PARAMETER_2 =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, parameter_address, ram_data);
if done then
state <= STATE_COPY_PARAMETER_3;
end if;
when STATE_COPY_PARAMETER_3 =>
--! read parameter size
parameter_address <= parameter_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= STATE_COPY_PARAMETER;
when STATE_COPY_PARAMETER_ACK =>
--! read parameter size
if (parameter_loaded_ack = '1') then
enable <= '0';
init <= '1';
parameter_loaded <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
if preempted then
preempted := false;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 2: WAIT FOR MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done then
if success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
enable <= '0';
init <= '1';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
parameter_loaded <= '0';
if preempted then
state <= STATE_INIT;
else
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
else
state <= STATE_EXIT;
end if;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
temp <= 0;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
--temp <= message2 * block_size; -- timing error for virtex 4 ("18 setup errors")
if (message2 > 0) then
temp <= temp + block_size;
message2 <= message2 - 1;
else
-- temp = (message-1) * block_size
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_6;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_6 =>
--! calculates particle array address and number of particles to sample
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_7;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_7 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_8;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_8 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_9;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_9 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
end if;
state <= STATE_READ_INPUT_DATA_ADDRESS;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: READ CURRENT INPUT DATA ADDRESS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_INPUT_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, input_data_link_address, input_data_address);
if done then
state <= STATE_READ_NEXT_PARTICLE;
end if;
-- CHANGE 5 of 7
-- input data address: 0x20000000
--input_data_address <= "00100000000000000000000000000000";
-- the particle array address: 0x10000000
--particle_array_address <= "00010000000000000000000000000000";
-- the observation array address: 0x11000000
--observation_array_address <= "00010001000000000000000000000000";
--state <= STATE_READ_NEXT_PARTICLE;
-- END CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: WRITE PARTICLE INTO CURRENT RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_NEXT_PARTICLE =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
-- CHANGE CHANGE CHANGE
reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, particle_array_address);
if done then
particle_array_address <= particle_array_address + particle_size;
-- CHANGE CHANGE CHANGE
state <= STATE_START_EXTRACT_OBSERVATION;
--state <= STATE_WRITE_OBSERVATION;
-- END OF CHANGE CHANGE CHANGE
end if;
-- END OF CHANGE CHANGE CHANGE
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: START OBSERVATION EXTRACTION
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_START_EXTRACT_OBSERVATION =>
--! start the user process
init <= '0';
enable <= '1';
new_particle <= '1';
state <= STATE_START_EXTRACT_OBSERVATION_WAIT;
when STATE_START_EXTRACT_OBSERVATION_WAIT =>
--! user process needs to start the execution
-- CHANGE CHANGE CHANGE
if new_particle_ack = '1' then
new_particle <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- END OF CHANGE CHANGE CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: WAIT FOR OBSERVATION EXTRACTION TO FINISH / ANSWER DATA CALLS INBETWEEN
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_EXTRACT_OBSERVATION =>
--! check if observation is finished, or it input data is needed (from cache)
if finished = '1' then
-- observation finished
enable <= '0';
init <= '1';
new_particle <= '0';
state <= STATE_WRITE_OBSERVATION;
elsif input_data_needed = '1' then
state <= STATE_GET_INPUT_DATA;
end if;
when STATE_GET_INPUT_DATA =>
--! get input data at word_address (and write it into word_data)
enable <= '0';
cache_offset <= 0;
if (cache_min <= word_address) and (word_address < cache_max) then
-- cache hit
state <= STATE_CACHE_HIT;
--current_address <= cache_min;
current_address <= word_address - cache_min;
else
-- cache miss
state <= STATE_CACHE_MISS;
end if;
when STATE_CACHE_HIT =>
--! calculate the correct position in the local ram
cache_offset <= TO_INTEGER(UNSIGNED(current_address)) / 4;
state <= STATE_LOAD_WORD;
when STATE_CACHE_MISS =>
--! check if word address is double aligned
if (word_address(29) = '0') then
-- word address is double-word aligned (needed for read bursts)
cache_min <= word_address;
cache_max <= word_address + 128;
cache_offset <= 0;
else
-- word address is NOT double-word aligned => cache_min has to be adjusted
cache_min <= word_address - 4;
cache_max <= word_address + 124;
cache_offset <= 1;
end if;
state <= STATE_CACHE_MISS_2;
when STATE_CACHE_MISS_2 =>
--! reads 128 byte input burst into local ram cache
reconos_read_burst(done, o_osif, i_osif, local_ram_cache_address, cache_min);
if done then
state <= STATE_LOAD_WORD;
end if;
when STATE_LOAD_WORD =>
--! load word data
o_RAMAddrObservation <= local_ram_cache_address_if + cache_offset;
state <= STATE_LOAD_WORD_2;
when STATE_LOAD_WORD_2 =>
--! load word data (wait one cycle)
-- state <= STATE_LOAD_WORD_3;
--
--
-- when STATE_LOAD_WORD_3 =>
-- --! load word data (get word)
-- word_data <= i_RAMData;
state <= STATE_WRITE_WORD_BACK;
when STATE_WRITE_WORD_BACK =>
--! activate user process and transfer the word
enable <= '1';
word_data_en <= '1';
word_data <= i_RAMData;
state <= STATE_WRITE_WORD_ACK;
when STATE_WRITE_WORD_ACK =>
--! wait for acknowledgement
if word_data_ack = '1' then
word_data_en <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 7: WRITE OBSERVATION TO MAIN MEMORY
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WRITE_OBSERVATION =>
--! write observation (init)
number_of_bursts <= number_of_bursts_remember;
local_ram_address <= local_ram_start_address;
--write_histo_en <= '1';
state <= STATE_WRITE_OBSERVATION_2;
when STATE_WRITE_OBSERVATION_2 =>
--! write observation (check burst number)
if number_of_bursts > 0 then
-- more full bursts needed
state <= STATE_WRITE_OBSERVATION_3;
number_of_bursts <= number_of_bursts - 1;
elsif length_of_last_burst > 0 then
-- last burst needed (not full)
temp4 <= length_of_last_burst * 8;
state <= STATE_WRITE_OBSERVATION_4;
else
-- no last burst needed (which is not full)
state <= STATE_MORE_PARTICLES;
end if;
when STATE_WRITE_OBSERVATION_3 =>
--! write observation (write bursts)
reconos_write_burst(done, o_osif, i_osif, local_ram_address, observation_array_address);
if done then
observation_array_address <= observation_array_address + 128;
local_ram_address <= local_ram_address + 128;
state <= STATE_WRITE_OBSERVATION_2;
end if;
when STATE_WRITE_OBSERVATION_4 =>
--! write observation (write last burst)
reconos_write_burst_l(done, o_osif, i_osif, local_ram_address, observation_array_address, length_of_last_burst);
if done then
state <= STATE_MORE_PARTICLES;
observation_array_address <= observation_array_address + temp4;
local_ram_address <= local_ram_address + temp4;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: MORE PARTICLES?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_MORE_PARTICLES =>
--! check if more particles need an observation
remaining_observations <= remaining_observations - 1;
state <= STATE_MORE_PARTICLES_2;
when STATE_MORE_PARTICLES_2 =>
--! check if more particles need an observation
if (remaining_observations > 0) then
state <= STATE_READ_NEXT_PARTICLE;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: SEND MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
state <= STATE_SEND_MEASUREMENT_1;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9*: SEND MEASURMENT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
reconos_mbox_tryget(done, success, o_osif, i_osif, C_MB_EXIT, message_var);
if done then
if success then
state <= STATE_EXIT;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
-- state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
--reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
--if (done and success) then
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- file numeric_std_tb1.vhd is a simulation testbench for
-- IEEE 1076.3 numeric_std package.
-- This is the first in a series of testbenches.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ieee10 is
generic (
quiet : boolean := false); -- make the simulation quiet
end entity ieee10;
architecture t1 of ieee10 is
begin
process
-- required A15_38
variable res4,sgn4: signed(3 downto 0);
variable sgn6: signed(5 downto 0);
variable res8: signed(7 downto 0);
variable sgn10,res10:signed(9 downto 0);
variable ures4,uns4: unsigned(1 to 4);
variable uns6: unsigned(2 to 7);
variable uns8: unsigned(0 to 7);
variable uns10,ures10:unsigned(1 to 10);
begin
-- Id: A.21, A.23, and A.24
for i in 0 to 1023 loop
uns10:=to_unsigned(i,10);
for j in 1 to 15 loop
uns4:=to_unsigned(j,4);
ures10:=uns10/uns4;
assert to_integer(ures10)=i/j report "A.21 fails"
severity FAILURE;
ures10:=uns10/j;
assert to_integer(ures10)=i/j report "A.23 fails"
severity FAILURE;
ures10:=i/("000000"&uns4);
assert to_integer(ures10)=i/j report "A.24 fails"
severity FAILURE;
end loop;
end loop;
if now < 2 ns then
wait for 1 ns;
else
wait;
end if;
end process;
end architecture t1;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
use work.axilite_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the AXILITE VVC
--===============================================================================================
constant C_VVC_NAME : string := "AXILITE_VVC";
signal AXILITE_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is AXILITE_VVCT;
alias t_bfm_config is t_axilite_bfm_config;
type t_executor_result is record
cmd_idx : natural; -- from UVVM handshake mechanism
data : std_logic_vector(127 downto 0);
value_is_new : boolean; -- turn true/false for put/fetch
fetch_is_accepted : boolean;
end record;
type t_executor_result_array is array (natural range <>) of t_executor_result;
-- Type found in UVVM-Util types_pkg
constant C_AXILITE_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_axilite_bfm_config; -- Configuration for AXI4-Lite BFM. See quick reference for AXI4-Lite BFM
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
parent_msg_id_panel : t_msg_id_panel; -- UVVM: temporary fix for HVVC, remove in v3.0
force_single_pending_transaction : boolean; -- Waits until the previous transaction is completed before starting the next one
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_AXILITE_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_AXILITE_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_AXILITE_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
force_single_pending_transaction => false
);
type t_vvc_status is record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'),
msg => (others => ' ')
);
shared variable shared_axilite_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_AXILITE_VVC_CONFIG_DEFAULT);
shared variable shared_axilite_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_axilite_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
-- Scoreboard
package axilite_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0),
element_match => std_match,
to_string_element => to_string);
use axilite_sb_pkg.all;
shared variable AXILITE_VVC_SB : axilite_sb_pkg.t_generic_sb;
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure axilite_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data_routing : in t_data_routing;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure axilite_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure axilite_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure set_arw_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure set_w_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure set_b_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure set_r_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record
);
procedure reset_arw_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record
);
procedure reset_w_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group
);
procedure reset_b_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group
);
procedure reset_r_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group
);
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME);
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_axilite_sb(
constant data : in std_logic_vector
) return std_logic_vector;
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX)
& ", " & to_string(byte_enable, BIN, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_normalised_byte_ena : std_logic_vector(shared_vvc_cmd.byte_enable'length-1 downto 0) :=
normalize_and_check(byte_enable, shared_vvc_cmd.byte_enable, ALLOW_WIDER_NARROWER, "byte_enable", "shared_vvc_cmd.byte_enable", proc_call & " called with to wide byte_enable. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.byte_enable := v_normalised_byte_ena;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure axilite_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data_routing : in t_data_routing;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", msg);
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure axilite_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
axilite_read(VVCT, vvc_instance_idx, addr, NA, msg, scope, parent_msg_id_panel);
end procedure;
procedure axilite_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is
begin
case vvc_cmd.operation is
when WRITE =>
vvc_transaction_info_group.bt_wr.operation := vvc_cmd.operation;
vvc_transaction_info_group.bt_wr.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.bt_wr.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.bt_wr.transaction_status := IN_PROGRESS;
when READ | CHECK =>
vvc_transaction_info_group.bt_rd.operation := vvc_cmd.operation;
vvc_transaction_info_group.bt_rd.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.bt_rd.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.bt_rd.transaction_status := IN_PROGRESS;
when others =>
alert(TB_ERROR, "VVC operation not recognized");
end case;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
wait for 0 ns;
end procedure set_global_vvc_transaction_info;
procedure set_arw_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
begin
case vvc_cmd.operation is
when WRITE =>
vvc_transaction_info_group.st_aw.operation := vvc_cmd.operation;
vvc_transaction_info_group.st_aw.arwaddr := vvc_cmd.addr;
vvc_transaction_info_group.st_aw.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.st_aw.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.st_aw.transaction_status := IN_PROGRESS;
when READ | CHECK =>
vvc_transaction_info_group.st_ar.operation := vvc_cmd.operation;
vvc_transaction_info_group.st_ar.arwaddr := vvc_cmd.addr;
vvc_transaction_info_group.st_ar.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.st_ar.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.st_ar.transaction_status := IN_PROGRESS;
when others =>
alert(TB_ERROR, "VVC operation not recognized");
end case;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
wait for 0 ns;
end procedure set_arw_vvc_transaction_info;
procedure set_w_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
begin
vvc_transaction_info_group.st_w.operation := vvc_cmd.operation;
vvc_transaction_info_group.st_w.wdata := vvc_cmd.data;
vvc_transaction_info_group.st_w.wstrb := vvc_cmd.byte_enable;
vvc_transaction_info_group.st_w.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.st_w.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.st_w.transaction_status := IN_PROGRESS;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
wait for 0 ns;
end procedure set_w_vvc_transaction_info;
procedure set_b_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
begin
vvc_transaction_info_group.st_b.operation := vvc_cmd.operation;
vvc_transaction_info_group.st_b.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.st_b.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.st_b.transaction_status := IN_PROGRESS;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
wait for 0 ns;
end procedure set_b_vvc_transaction_info;
procedure set_r_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
begin
vvc_transaction_info_group.st_r.operation := vvc_cmd.operation;
vvc_transaction_info_group.st_r.rdata := vvc_cmd.data;
vvc_transaction_info_group.st_r.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.st_r.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.st_r.transaction_status := IN_PROGRESS;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
wait for 0 ns;
end procedure set_r_vvc_transaction_info;
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record) is
begin
case vvc_cmd.operation is
when WRITE =>
if vvc_cmd.cmd_idx = vvc_transaction_info_group.bt_wr.vvc_meta.cmd_idx then
vvc_transaction_info_group.bt_wr := C_BASE_TRANSACTION_SET_DEFAULT;
end if;
when READ | CHECK =>
if vvc_cmd.cmd_idx = vvc_transaction_info_group.bt_rd.vvc_meta.cmd_idx then
vvc_transaction_info_group.bt_rd := C_BASE_TRANSACTION_SET_DEFAULT;
end if;
when others =>
null;
end case;
wait for 0 ns;
end procedure reset_vvc_transaction_info;
procedure reset_arw_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record
) is
begin
case vvc_cmd.operation is
when WRITE =>
vvc_transaction_info_group.st_aw := C_ARW_TRANSACTION_DEFAULT;
when READ | CHECK =>
vvc_transaction_info_group.st_ar := C_ARW_TRANSACTION_DEFAULT;
when others =>
null;
end case;
wait for 0 ns;
end procedure reset_arw_vvc_transaction_info;
procedure reset_w_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group
) is
begin
vvc_transaction_info_group.st_w := C_W_TRANSACTION_DEFAULT;
end procedure reset_w_vvc_transaction_info;
procedure reset_b_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group
) is
begin
vvc_transaction_info_group.st_b := C_B_TRANSACTION_DEFAULT;
end procedure reset_b_vvc_transaction_info;
procedure reset_r_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group
) is
begin
vvc_transaction_info_group.st_r := C_R_TRANSACTION_DEFAULT;
end procedure reset_r_vvc_transaction_info;
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME) is
variable v_activity : t_activity := activity;
begin
-- Update vvc_status after a command has finished (during same delta cycle the activity register is updated)
if activity = INACTIVE then
vvc_status.previous_cmd_idx := last_cmd_idx_executed;
vvc_status.current_cmd_idx := 0;
end if;
if v_activity = INACTIVE and not(command_queue_is_empty) then
v_activity := ACTIVE;
end if;
shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register,
activity => v_activity,
last_cmd_idx_executed => last_cmd_idx_executed);
if global_trigger_vvc_activity_register /= 'L' then
wait until global_trigger_vvc_activity_register = 'L';
end if;
gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER);
end procedure;
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_axilite_sb(
constant data : in std_logic_vector
) return std_logic_vector is
begin
return pad_sb_slv(data, C_VVC_CMD_DATA_MAX_LENGTH);
end function pad_axilite_sb;
end package body vvc_methods_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc218.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00218ent IS
END c03s01b01x00p06n03i00218ent;
ARCHITECTURE c03s01b01x00p06n03i00218arch OF c03s01b01x00p06n03i00218ent IS
subtype BTRUE is BOOLEAN range TRUE to TRUE;
type ENUM1 is (ZERO, ONE, TWO, THREE);
type ENUM2 is (TRUE, FALSE);
type ENUM3 is ('1', '0');
type ENUM4 is ('Z', 'Y', 'X');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((ENUM1'POS(ZERO) = 0)
and (ENUM1'POS(ONE) = 1)
and (ENUM1'POS(TWO) = 2)
and (ENUM1'POS(THREE) = 3)
and (ENUM2'POS(TRUE) = 0)
and (ENUM2'POS(FALSE) = 1)
and (ENUM3'POS('1') = 0)
and (ENUM3'POS('0') = 1)
and (ENUM4'POS('Z') = 0)
and (ENUM4'POS('Y') = 1)
and (ENUM4'POS('X') = 2) )
report "***PASSED TEST: c03s01b01x00p06n03i00218"
severity NOTE;
assert ( (ENUM1'POS(ZERO) = 0)
and (ENUM1'POS(ONE) = 1)
and (ENUM1'POS(TWO) = 2)
and (ENUM1'POS(THREE) = 3)
and (ENUM2'POS(TRUE) = 0)
and (ENUM2'POS(FALSE) = 1)
and (ENUM3'POS('1') = 0)
and (ENUM3'POS('0') = 1)
and (ENUM4'POS('Z') = 0)
and (ENUM4'POS('Y') = 1)
and (ENUM4'POS('X') = 2))
report "***FAILED TEST: c03s01b01x00p06n03i00218 - The position value of the nth listed enumeration literal is n-1."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00218arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc218.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00218ent IS
END c03s01b01x00p06n03i00218ent;
ARCHITECTURE c03s01b01x00p06n03i00218arch OF c03s01b01x00p06n03i00218ent IS
subtype BTRUE is BOOLEAN range TRUE to TRUE;
type ENUM1 is (ZERO, ONE, TWO, THREE);
type ENUM2 is (TRUE, FALSE);
type ENUM3 is ('1', '0');
type ENUM4 is ('Z', 'Y', 'X');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((ENUM1'POS(ZERO) = 0)
and (ENUM1'POS(ONE) = 1)
and (ENUM1'POS(TWO) = 2)
and (ENUM1'POS(THREE) = 3)
and (ENUM2'POS(TRUE) = 0)
and (ENUM2'POS(FALSE) = 1)
and (ENUM3'POS('1') = 0)
and (ENUM3'POS('0') = 1)
and (ENUM4'POS('Z') = 0)
and (ENUM4'POS('Y') = 1)
and (ENUM4'POS('X') = 2) )
report "***PASSED TEST: c03s01b01x00p06n03i00218"
severity NOTE;
assert ( (ENUM1'POS(ZERO) = 0)
and (ENUM1'POS(ONE) = 1)
and (ENUM1'POS(TWO) = 2)
and (ENUM1'POS(THREE) = 3)
and (ENUM2'POS(TRUE) = 0)
and (ENUM2'POS(FALSE) = 1)
and (ENUM3'POS('1') = 0)
and (ENUM3'POS('0') = 1)
and (ENUM4'POS('Z') = 0)
and (ENUM4'POS('Y') = 1)
and (ENUM4'POS('X') = 2))
report "***FAILED TEST: c03s01b01x00p06n03i00218 - The position value of the nth listed enumeration literal is n-1."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00218arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc218.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00218ent IS
END c03s01b01x00p06n03i00218ent;
ARCHITECTURE c03s01b01x00p06n03i00218arch OF c03s01b01x00p06n03i00218ent IS
subtype BTRUE is BOOLEAN range TRUE to TRUE;
type ENUM1 is (ZERO, ONE, TWO, THREE);
type ENUM2 is (TRUE, FALSE);
type ENUM3 is ('1', '0');
type ENUM4 is ('Z', 'Y', 'X');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((ENUM1'POS(ZERO) = 0)
and (ENUM1'POS(ONE) = 1)
and (ENUM1'POS(TWO) = 2)
and (ENUM1'POS(THREE) = 3)
and (ENUM2'POS(TRUE) = 0)
and (ENUM2'POS(FALSE) = 1)
and (ENUM3'POS('1') = 0)
and (ENUM3'POS('0') = 1)
and (ENUM4'POS('Z') = 0)
and (ENUM4'POS('Y') = 1)
and (ENUM4'POS('X') = 2) )
report "***PASSED TEST: c03s01b01x00p06n03i00218"
severity NOTE;
assert ( (ENUM1'POS(ZERO) = 0)
and (ENUM1'POS(ONE) = 1)
and (ENUM1'POS(TWO) = 2)
and (ENUM1'POS(THREE) = 3)
and (ENUM2'POS(TRUE) = 0)
and (ENUM2'POS(FALSE) = 1)
and (ENUM3'POS('1') = 0)
and (ENUM3'POS('0') = 1)
and (ENUM4'POS('Z') = 0)
and (ENUM4'POS('Y') = 1)
and (ENUM4'POS('X') = 2))
report "***FAILED TEST: c03s01b01x00p06n03i00218 - The position value of the nth listed enumeration literal is n-1."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00218arch;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15936)
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|
-- Tweakable constants
library ieee;
use ieee.std_logic_1164.all;
use work.utils.all;
package constants is
constant clk_period : time := 1 sec / 50_000_000;
-- todo this constant is useless. Remove it.
constant spi_word_length : integer := 8;
-----------------------------------------------------------------------------
--sine wave generator configuration
-- The higher this number, the more concurrent midi notes can be played
constant num_sines : integer := 10;
-----------------------------------------------------------------------------
-- Always ensure that the maximum number of brams is used.
--each The lx9 FPGA has 64 brams.
constant device_brams : integer := 50;
-- The number of brams used for the SPI tx buffer. The higher this number,
-- the more protection against the pi hiccoughing and failing to read data
-- from the FPGA.
constant spi_tx_ram_brams : integer := 4;
-- brams for holding sine lookup data. The higher this number, the more
-- accurate the sine lookup process is
constant sine_lut_brams : integer := 2;
-- Allocate all remaining block rams to the receive buffer from the pi. The
-- higher this number, the more music can be played.
constant midi_file_rx_brams : integer := device_brams - spi_tx_ram_brams - sine_lut_brams;
-- each spartan 6 RAMB8BWER is 1024 bits long
constant device_bram_depth : integer := 1024;
constant spi_tx_ram_depth : integer := spi_tx_ram_brams * device_bram_depth;
constant sine_lut_bram_depth : integer := sine_lut_brams * device_bram_depth;
constant midi_file_rx_bram_depth : integer := midi_file_rx_brams * device_bram_depth;
-------------------------------------------------------------------------------
-- The max number of words (each word is currently 2 bytes) that SPI transmitter will send
-- in a frame. Must be less than (256/word size)
constant spi_tx_max_block_size : integer := 100;
-----------------------------------------------------------------------------
-- midi constants
-- The maximum number of tracks in a midi file that may be simulataneously decoded.
constant max_num_tracks : integer := 5;
-----------------------------------------------------------------------------
-- Midi track constants.
-- Record some constant data as defined in the midi format.
-- The midi spec expects MThd to be the first four bytes of a midi file.
constant mthd : std_logic_vector(31 downto 0) := to_slv("MThd");
constant mtrk : std_logic_vector(31 downto 0) := to_slv("MTrk");
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types.all;
entity alu_tb is
end;
architecture rtl of alu_tb is
component alu is
port( op : in alu_op_t;
i0 : in reg_t;
i1 : in reg_t;
q : out reg_t;
flags_in : in reg_t;
flags_out : out reg_t);
end component;
signal clk : std_logic;
signal op : alu_op_t;
signal input : std_logic_vector(16 downto 0) := (others => '0');
signal i0 : reg_t := (others => '0');
signal i1 : reg_t := (others => '0');
signal q : reg_t := (others => '0');
signal flags_in : reg_t := (others => '0');
signal flags_out : reg_t := (others => '0');
begin
alu0: alu
port map (op, i0, i1, q, flags_in, flags_out);
clkgen:
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
gen_data:
process(clk)
begin
if rising_edge(clk) then
op <= alu_op_or;
input <= std_logic_vector( unsigned(input) + 1);
end if;
end process;
i0 <= input( 7 downto 0);
i1 <= input(15 downto 8);
flags_in(CARRY_BIT) <= input(16);
end rtl;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- This file is part of top_alphanumeric
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity image_controler is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
r : out STD_LOGIC_VECTOR (5 downto 0);
g : out STD_LOGIC_VECTOR (5 downto 0);
b : out STD_LOGIC_VECTOR (5 downto 0);
x : in STD_LOGIC_VECTOR (9 downto 0);
y : in STD_LOGIC_VECTOR (8 downto 0);
enable_in : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
write_enable : in std_logic;
write_addr : in std_logic_vector(12 downto 0);
char_code : in std_logic_vector(7 downto 0);
color_code : in std_logic_vector(9 downto 0);
enable_out : out std_logic;
hsync_out : out std_logic;
vsync_out : out std_logic);
end image_controler;
architecture Behavioral of image_controler is
------------ Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component ram
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(12 downto 0);
dina: IN std_logic_VECTOR(17 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(12 downto 0);
doutb: OUT std_logic_VECTOR(17 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of ram: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
component character_rom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box of character_rom: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component color_rom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(17 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box of color_rom: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- Signals needed to write in memory
signal ram_write_enable : std_logic_vector(0 downto 0);
signal ram_data_in : std_logic_vector(17 downto 0);
-- Signals needed to read from ram
signal ram_read_addr : std_logic_vector(12 downto 0) := (others => '0');
signal ram_data_out : std_logic_vector(17 downto 0);
-- SIgnals to read from character rom
signal read_char_addr : std_logic_vector(10 downto 0);
signal read_char_data : std_logic_vector(7 downto 0);
-- SIgnals to read from character rom
signal read_color_addr : std_logic_vector(9 downto 0);
signal read_color_data : std_logic_vector(17 downto 0);
-- Signal defining column
signal column : std_logic_vector(6 downto 0) := (others => '0');
signal line : std_logic_vector(5 downto 0) := (others => '0');
signal pixel_state : std_logic ;
signal x_delayed : std_logic_vector(2 downto 0) ;
-- Constant defining the delay introduced by the image controler
constant controler_delay : natural := 2;
begin
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
my_ram : ram
port map (
clka => clk,
wea => ram_write_enable,
addra => write_addr,
dina => ram_data_in,
clkb => clk,
addrb => ram_read_addr,
doutb => ram_data_out);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
my_character_rom : character_rom
port map (
clka => clk,
addra => read_char_addr,
douta => read_char_data);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
my_color_rom : color_rom
port map (
clka => clk,
addra => read_color_addr,
douta => read_color_data);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- Block to introduce delays need to have control signals
-- synchronous with colour signals
hsync_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => hsync_in,
output => hsync_out);
vsync_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => vsync_in,
output => vsync_out);
enable_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => enable_in,
output => enable_out);
x_delayer : entity work.delay_register
generic map(
width => 3,
delay => controler_delay)
port map(
clk => clk,
rst => rst,
input => x(2 downto 0), -- input
output => x_delayed); -- output
-- Process controling adress of read port
--TO DELETE process(clk,rst)
--TO DELETE begin
--TO DELETE if rst = '1' then
--TO DELETE read_addr <= (others => '0');
--TO DELETE elsif rising_edge(clk) and enable_in = '1' and x(2 downto 0) = "111" and y(2 downto 0) = "111" then
--TO DELETE if unsigned(read_addr) /= 4799 then
--TO DELETE read_addr <= std_logic_vector(unsigned(read_addr) + 1);
--TO DELETE else
--TO DELETE read_addr <= (others => '0');
--TO DELETE end if;
--TO DELETE end if;
--TO DELETE end process;
-- Extracting coordinate from pixel in term of character array
column <= x(9 downto 3);
line <= y(8 downto 3);
-- Rebulding corresponding memory addr
ram_read_addr <= line & column;
-- Getting char and color code
read_color_addr <= ram_data_out(17 downto 8);
read_char_addr <= ram_data_out(7 downto 0) & y(2 downto 0);
-- with x(2 downto 0) select
with x_delayed select
pixel_state <= read_char_data(7) when "000",
read_char_data(6) when "001",
read_char_data(5) when "010",
read_char_data(4) when "011",
read_char_data(3) when "100",
read_char_data(2) when "101",
read_char_data(1) when "110",
read_char_data(0) when "111",
'0' when others;
-- Getting color value and pixel value
r <= read_color_data(17 downto 12) when pixel_state = '1' else (others => '0');
g <= read_color_data(11 downto 6) when pixel_state = '1' else (others => '0');
b <= read_color_data(5 downto 0) when pixel_state = '1' else (others => '0');
ram_write_enable <= (others => write_enable);
ram_data_in <= color_code & char_code;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
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