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----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file asyn_fifo_distrib_64.vhd when simulating
-- the core, asyn_fifo_distrib_64. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY asyn_fifo_distrib_64 IS
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
almost_full: OUT std_logic;
almost_empty: OUT std_logic;
wr_count: OUT std_logic_VECTOR(3 downto 0);
rd_count: OUT std_logic_VECTOR(3 downto 0));
END asyn_fifo_distrib_64;
ARCHITECTURE asyn_fifo_distrib_64_a OF asyn_fifo_distrib_64 IS
component wrapped_asyn_fifo_distrib_64
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
almost_full: OUT std_logic;
almost_empty: OUT std_logic;
wr_count: OUT std_logic_VECTOR(3 downto 0);
rd_count: OUT std_logic_VECTOR(3 downto 0));
end component;
-- Configuration specification
for all : wrapped_asyn_fifo_distrib_64 use entity XilinxCoreLib.async_fifo_v3_0(behavioral)
generic map(
c_wr_count_width => 4,
c_has_rd_err => 0,
c_data_width => 16,
c_has_almost_full => 1,
c_rd_err_low => 0,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_fifo_depth => 63,
c_rd_count_width => 4,
c_has_wr_err => 0,
c_has_almost_empty => 1,
c_rd_ack_low => 0,
c_has_wr_count => 1,
c_use_blockmem => 0,
c_has_rd_ack => 0,
c_has_rd_count => 1,
c_wr_err_low => 0,
c_enable_rlocs => 0);
BEGIN
U0 : wrapped_asyn_fifo_distrib_64
port map (
din => din,
wr_en => wr_en,
wr_clk => wr_clk,
rd_en => rd_en,
rd_clk => rd_clk,
ainit => ainit,
dout => dout,
full => full,
empty => empty,
almost_full => almost_full,
almost_empty => almost_empty,
wr_count => wr_count,
rd_count => rd_count);
END asyn_fifo_distrib_64_a;
-- synopsys translate_on
|
-- $Id: byte2word.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: byte2word - syn
-- Description: 2 byte -> 1 word stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.0.1 now numeric_std clean
-- 2011-07-30 400 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end byte2word;
architecture syn of byte2word is
type state_type is (
s_idle,
s_vall,
s_valw
);
type regs_type is record
datl : slv8; -- lsb data
dath : slv8; -- msb data
state : state_type; -- state
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),
(others=>'0'),
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable iodd : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ival := '0';
ibusy := '0';
iodd := '0';
case r.state is
when s_idle =>
if ENA = '1' then
n.datl := DI;
n.state := s_vall;
end if;
when s_vall =>
iodd := '1';
if ENA = '1' then
n.dath := DI;
n.state := s_valw;
end if;
when s_valw =>
ival := '1';
if HOLD = '0' then
if ENA = '1' then
n.datl := DI;
n.state := s_vall;
else
n.state := s_idle;
end if;
else
ibusy := '1';
end if;
when others => null;
end case;
N_REGS <= n;
DO <= r.dath & r.datl;
VAL <= ival;
BUSY <= ibusy;
ODD <= iodd;
end process proc_next;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
package stream is
constant SYNC_RESET : boolean:=true;
subtype valid_t is std_logic;
subtype ready_t is std_logic;
function state_log2(x : positive) return integer;
pure function ceil_log2(x : positive) return integer;
function get(str : valid_t) return std_logic;
function b2std(x:boolean) return std_logic;
end package;
package body stream is
function b2std(x:boolean) return std_logic is
begin
if x then return '1';
else return '0';
end if;
end function;
function get(str : valid_t) return std_logic is
begin
return std_logic(str);
end get;
function state_log2(x : positive) return integer is
variable r : integer;
begin
if x=1 then
r := 1;
else
r := ceil_log2(x);
end if;
return r;
end state_log2;
pure function ceil_log(x : positive; b : positive) return integer is
begin
for r in 0 to 30 loop
if (x <=b**r) then
return r;
end if;
end loop;
return -1;
end ceil_log;
pure function ceil_log2(x : positive) return integer is
begin
return ceil_log(x,2);
end ceil_log2;
end package body stream;
library ieee;
use ieee.std_logic_1164.all;
use work.stream.all;
use ieee.numeric_std.all;
entity tdm_counter is
generic
(
TDM : positive := 1
);
port
(reset : in std_logic;
clock : in std_logic;
clock_en : in std_logic;
valid : in valid_t;
ready : in ready_t;
counter : out std_logic_vector(state_log2(TDM)-1 downto 0)
);
end tdm_counter;
architecture rtl of tdm_counter is
-- just declaring the counter here works
--signal counter_u: unsigned(ceil_log2(TDM)-1 downto 0);
begin -- rtl
U_SIMPLE: if TDM = 1 generate
counter <= (others=>'0');
end generate U_SIMPLE;
U_COMPLEX: if TDM /= 1 generate
signal enable_i : std_logic;
signal counter_u: unsigned(ceil_log2(TDM)-1 downto 0);
begin
process(reset,clock)
-- also expanding do_reset and removing the procedure works
procedure do_reset is
begin
counter_u <= to_unsigned(0, counter_u'length);
end procedure;
begin
if not(SYNC_RESET) and reset='1' then
do_reset;
elsif rising_edge(clock) then
if SYNC_RESET and reset='1' then
do_reset;
elsif clock_en='1' then
if get(valid)='1' and get(ready)='1' then
if enable_i='1' then
counter_u <= to_unsigned(0, counter_u'length);
else
counter_u <= counter_u+1;
end if;
end if;
end if;
end if;
end process;
counter <= std_logic_vector(counter_u);
enable_i <= b2std(counter_u = TDM-1) and get(valid) and get(ready);
end generate U_COMPLEX;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
package stream is
constant SYNC_RESET : boolean:=true;
subtype valid_t is std_logic;
subtype ready_t is std_logic;
function state_log2(x : positive) return integer;
pure function ceil_log2(x : positive) return integer;
function get(str : valid_t) return std_logic;
function b2std(x:boolean) return std_logic;
end package;
package body stream is
function b2std(x:boolean) return std_logic is
begin
if x then return '1';
else return '0';
end if;
end function;
function get(str : valid_t) return std_logic is
begin
return std_logic(str);
end get;
function state_log2(x : positive) return integer is
variable r : integer;
begin
if x=1 then
r := 1;
else
r := ceil_log2(x);
end if;
return r;
end state_log2;
pure function ceil_log(x : positive; b : positive) return integer is
begin
for r in 0 to 30 loop
if (x <=b**r) then
return r;
end if;
end loop;
return -1;
end ceil_log;
pure function ceil_log2(x : positive) return integer is
begin
return ceil_log(x,2);
end ceil_log2;
end package body stream;
library ieee;
use ieee.std_logic_1164.all;
use work.stream.all;
use ieee.numeric_std.all;
entity tdm_counter is
generic
(
TDM : positive := 1
);
port
(reset : in std_logic;
clock : in std_logic;
clock_en : in std_logic;
valid : in valid_t;
ready : in ready_t;
counter : out std_logic_vector(state_log2(TDM)-1 downto 0)
);
end tdm_counter;
architecture rtl of tdm_counter is
-- just declaring the counter here works
--signal counter_u: unsigned(ceil_log2(TDM)-1 downto 0);
begin -- rtl
U_SIMPLE: if TDM = 1 generate
counter <= (others=>'0');
end generate U_SIMPLE;
U_COMPLEX: if TDM /= 1 generate
signal enable_i : std_logic;
signal counter_u: unsigned(ceil_log2(TDM)-1 downto 0);
begin
process(reset,clock)
-- also expanding do_reset and removing the procedure works
procedure do_reset is
begin
counter_u <= to_unsigned(0, counter_u'length);
end procedure;
begin
if not(SYNC_RESET) and reset='1' then
do_reset;
elsif rising_edge(clock) then
if SYNC_RESET and reset='1' then
do_reset;
elsif clock_en='1' then
if get(valid)='1' and get(ready)='1' then
if enable_i='1' then
counter_u <= to_unsigned(0, counter_u'length);
else
counter_u <= counter_u+1;
end if;
end if;
end if;
end if;
end process;
counter <= std_logic_vector(counter_u);
enable_i <= b2std(counter_u = TDM-1) and get(valid) and get(ready);
end generate U_COMPLEX;
end rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:prog_rom:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_prog_rom_0_0 IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END RAT_prog_rom_0_0;
ARCHITECTURE RAT_prog_rom_0_0_arch OF RAT_prog_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT prog_rom IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END COMPONENT prog_rom;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : prog_rom
PORT MAP (
ADDRESS => ADDRESS,
INSTRUCTION => INSTRUCTION,
CLK => CLK
);
END RAT_prog_rom_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:prog_rom:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_prog_rom_0_0 IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END RAT_prog_rom_0_0;
ARCHITECTURE RAT_prog_rom_0_0_arch OF RAT_prog_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT prog_rom IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END COMPONENT prog_rom;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : prog_rom
PORT MAP (
ADDRESS => ADDRESS,
INSTRUCTION => INSTRUCTION,
CLK => CLK
);
END RAT_prog_rom_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
attribute sync_set_reset of resetn : signal is "true";
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
--attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to 7 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i), ahbsi.testen);
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0');
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
|
library IEEE ;
use IEEE.STD_LOGIC_1164.all ;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.HelperFunctions.all;
use work.HelperFunctions_Unsigned.all;
use work.HelperFunctions_Signed.all;
entity BurstAddressGen is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--input burst data
base_address_in : in STD_LOGIC_VECTOR(31 downto 0);
burst_size_in : in STD_LOGIC_VECTOR(31 downto 0);
burst_valid_in : in STD_LOGIC;
--burst_address_read_out : out STD_LOGIC;
burst_stall_out : out STD_LOGIC;
--output addresses
address_valid_out : out STD_LOGIC;
address_out : out STD_LOGIC_VECTOR(31 downto 0);
address_stall_in : in STD_LOGIC
);
end BurstAddressGen;
architecture Behavioral of BurstAddressGen is
--used when reading from an external BRAM
--type BRAM_STATE_TYPE is (S_EMPTY, S_READY, S_READ, S_STALL);
--signal bram_state : BRAM_STATE_TYPE;
--signal micro_valid_in : STD_LOGIC;
--signal micro_data_in : STD_LOGIC_VECTOR(63 downto 0);
--signal micro_full_out : STD_LOGIC;
signal base_value : STD_LOGIC_VECTOR(31 downto 0);
signal burst_value : STD_LOGIC_VECTOR(31 downto 0);
signal micro_read_enable_in : STD_LOGIC;
signal micro_empty_out : STD_LOGIC;
component MicroFifo is
generic (
ADDRESS_WIDTH : POSITIVE;
DATA_WIDTH : POSITIVE;
ALMOST_FULL_COUNT : NATURAL;
ALMOST_EMPTY_COUNT : NATURAL
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
valid_in : in STD_LOGIC;
full_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
read_enable_in : in STD_LOGIC;
empty_out : out STD_LOGIC
);
end component;
--type state_STATE_TYPE is (S_READY, S_READ, S_PROCESSING) ;
type state_STATE_TYPE is (S_READY, S_READ, S_PROCESSING, S_PROCESSING_LAST) ;
signal state : state_STATE_TYPE ;
signal cur_address : STD_LOGIC_VECTOR(31 downto 0);
signal end_address : STD_LOGIC_VECTOR(31 downto 0);
begin
--used when reading from an external BRAM
--process(clk, rst)
--begin
-- if( rst = '1' ) then
-- burst_address_read_out <= '0';
-- micro_valid_in <= '0';
-- micro_data_in <= (others=>'0');
-- bram_state <= S_EMPTY;
-- elsif( clk'event and clk = '1' ) then
-- burst_address_read_out <= '0';
-- micro_valid_in <= '0';
-- case bram_state is
-- when S_EMPTY =>
-- if( burst_valid_in = '1' and micro_full_out = '0' ) then
-- burst_address_read_out <= '1';
-- bram_state <= S_READY;
-- end if;
-- when S_READY =>
-- burst_address_read_out <= '1';
-- bram_state <= S_READ;
-- when S_READ =>
-- --read
-- micro_valid_in <= '1';
-- micro_data_in(31 downto 0) <= base_address_in;
-- micro_data_in(63 downto 32) <= burst_size_in;
-- if( burst_valid_in = '1' and micro_full_out = '0' ) then
-- burst_address_read_out <= '1';
-- elsif( micro_full_out = '1' ) then
-- bram_state <= S_STALL;
-- else
-- bram_state <= S_EMPTY;
-- end if;
-- when S_STALL =>
-- --read
-- micro_valid_in <= '1';
-- micro_data_in(31 downto 0) <= base_address_in;
-- micro_data_in(63 downto 32) <= burst_size_in;
-- bram_state <= S_EMPTY;
-- end case;
-- end if;
--end process;
micro : MicroFifo
generic map(
ADDRESS_WIDTH => 4,
DATA_WIDTH => 64,
ALMOST_FULL_COUNT => 3,
ALMOST_EMPTY_COUNT => 0
)
port map(
clk => clk,
rst => rst,
data_in(31 downto 0) => base_address_in,
data_in(63 downto 32) => burst_size_in,
valid_in => burst_valid_in,
full_out => burst_stall_out,
--used when reading from an external BRAM
-- data_in => micro_data_in,
-- valid_in => micro_valid_in,
-- full_out => micro_full_out,
data_out(31 downto 0) => base_value,
data_out(63 downto 32) => burst_value,
read_enable_in => micro_read_enable_in,
empty_out => micro_empty_out
);
--process(clk, rst)
--begin
-- if( rst = '1' ) then
-- address_valid_out <= '0';
-- address_out <= (others=>'0');
-- cur_address <= (others=>'0');
-- end_address <= (others=>'0');
-- micro_read_enable_in <= '0';
-- state <= S_READY;
-- elsif( clk'event and clk = '1' ) then
-- address_valid_out <= '0';
-- micro_read_enable_in <= '0';
-- case state is
-- when S_READY =>
-- if( micro_empty_out = '0' ) then
-- state <= S_READ;
-- micro_read_enable_in <= '1';
-- end if;
-- when S_READ =>
-- state <= S_PROCESSING;
-- --micro_read_enable_in <= '1';
-- cur_address <= base_value;
-- end_address <=
-- ROCCCSUB(
-- ROCCCADD(
-- base_value,
-- burst_value,
-- 32),
-- "00000000000000000000000000000001",
-- 32);
-- when S_PROCESSING =>
-- if( address_stall_in = '0' ) then
-- address_valid_out <= '1';
-- address_out <= cur_address;
-- if( ROCCC_UGTE(cur_address, end_address, 32) ) then
-- state <= S_READY;
-- if( micro_empty_out = '0' ) then
-- state <= S_READ;
-- micro_read_enable_in <= '1';
-- end if;
-- end if;
-- --else
-- cur_address <=
-- ROCCCADD(
-- cur_address,
-- "00000000000000000000000000000001",
-- 32);
-- --end if;
-- end if;
-- end case;
-- end if;
--end process;
process(clk, rst)
begin
if( rst = '1' ) then
address_valid_out <= '0';
address_out <= (others=>'0');
cur_address <= (others=>'0');
end_address <= (others=>'0');
micro_read_enable_in <= '0';
state <= S_READY;
elsif( clk'event and clk = '1' ) then
address_valid_out <= '0';
micro_read_enable_in <= '0';
case state is
when S_READY =>
if( micro_empty_out = '0' ) then
state <= S_READ;
micro_read_enable_in <= '1';
end if;
when S_READ =>
state <= S_PROCESSING;
--micro_read_enable_in <= '1';
cur_address <= base_value;
end_address <=
ROCCCSUB(
ROCCCADD(
base_value,
burst_value,
32),
"00000000000000000000000000000001",
32);
when S_PROCESSING =>
if( address_stall_in = '0' ) then
address_valid_out <= '1';
address_out <= cur_address;
if( cur_address = end_address ) then
state <= S_READY;
if( micro_empty_out = '0' ) then
state <= S_READ;
micro_read_enable_in <= '1';
end if;
elsif( ROCCCADD(cur_address,"00000000000000000000000000000001",32) = end_address ) then
state <= S_PROCESSING;
if( micro_empty_out = '0' ) then
state <= S_PROCESSING_LAST;
micro_read_enable_in <= '1';
end if;
end if;
cur_address <=
ROCCCADD(
cur_address,
"00000000000000000000000000000001",
32);
end if;
when S_PROCESSING_LAST =>
if( address_stall_in = '0' ) then
address_valid_out <= '1';
address_out <= cur_address;
state <= S_PROCESSING;
cur_address <= base_value;
end_address <=
ROCCCSUB(
ROCCCADD(
base_value,
burst_value,
32),
"00000000000000000000000000000001",
32);
end if;
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity strings_test is
end strings_test;
architecture rtl of strings_test is
type T_TYPE is (TYPE_1, TYPE_2, TYPE_3);
function str_low(str : string) return integer is
begin
assert str'low = 1 severity failure;
return str'low;
end function;
constant string1 : string := "TYPE_1";
constant string2 : T_TYPE := TYPE_1;
begin
assert false report "str_low of type'image : i =" & integer'image(str_low(T_TYPE'image(string2))) severity note;
assert false report "tic low of type'image : i =" & integer'image(T_TYPE'image(string2)'low) severity note;
assert false report "tic low of string : i =" & integer'image(string1'low) severity note;
assert false report "str_low of string : i =" & integer'image(str_low(string1)) severity note;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
end record;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0');
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1)
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkahb2x : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
entity ClockManager is
Port ( clock : in std_logic;
reset : in std_logic;
ce_param : out std_logic);
end ClockManager;
architecture Behavioral of ClockManager is
signal cpt : integer := 0;
begin
process (clock, reset)
begin
if (reset = '1') then
cpt<=0;
elsif (rising_edge(clock)) then
if (cpt< PARAM_DELAY) then
cpt<= cpt + 1;
ce_param<='0';
else
cpt<=0;
ce_param<='1';
end if;
end if;
end process;
end Behavioral; |
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:20:49 09/25/2012
-- Design Name:
-- Module Name: vetor_de_debounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
entity debounce is
Port ( clock : in std_logic;
entrada : in STD_LOGIC;
entrada_tmp1_o : out STD_LOGIC;
entrada_tmp2_o : out STD_LOGIC;
contagem_o : out std_logic_vector(19 downto 0);
saida_DB : out STD_LOGIC);
end debounce;
architecture Behavioral of debounce is
constant atraso : integer := 500000; -- alterado p/ 500 p/ simular. Valor p/ sintese ingual a 500000
signal contagem : integer := 0;
signal entrada_tmp1, entrada_tmp2 : std_logic:='0';
signal saida_tmp : std_logic;
begin
contar: process (entrada, clock, entrada_tmp1)
begin
if entrada /= entrada_tmp1 then
contagem <= 0;
entrada_tmp1 <= entrada;
elsif clock'event and clock = '1' then
entrada_tmp1 <= entrada;
entrada_tmp2 <= entrada_tmp1;
contagem <= contagem +1;
else
contagem <= contagem;
end if;
end process;
avaliar: process (clock, entrada_tmp1, entrada_tmp2, contagem)
begin
if clock'event and clock='1' then
if contagem >= atraso and entrada_tmp1 = entrada_tmp2 then
saida_tmp <= entrada;
else
saida_tmp <= saida_tmp;
end if;
else
saida_tmp <= saida_tmp;
end if;
end process;
saida_DB <= saida_tmp;
contagem_o <= conv_std_logic_vector(contagem, 20);
entrada_tmp1_o <= entrada_tmp1;
entrada_tmp2_o <= entrada_tmp2;
end Behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pma_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0)
);
end pma_rnd;
architecture behaviour of pma_rnd is
constant s0: std_logic_vector(4 downto 0) := "11101";
constant s1: std_logic_vector(4 downto 0) := "00010";
constant s21: std_logic_vector(4 downto 0) := "11011";
constant s2: std_logic_vector(4 downto 0) := "11110";
constant s3: std_logic_vector(4 downto 0) := "11111";
constant s4: std_logic_vector(4 downto 0) := "10001";
constant s6: std_logic_vector(4 downto 0) := "10110";
constant s7: std_logic_vector(4 downto 0) := "01011";
constant s5: std_logic_vector(4 downto 0) := "01111";
constant s10: std_logic_vector(4 downto 0) := "00001";
constant s8: std_logic_vector(4 downto 0) := "10000";
constant s9: std_logic_vector(4 downto 0) := "11010";
constant s11: std_logic_vector(4 downto 0) := "11000";
constant s12: std_logic_vector(4 downto 0) := "01000";
constant s13: std_logic_vector(4 downto 0) := "00100";
constant s14: std_logic_vector(4 downto 0) := "01001";
constant s22: std_logic_vector(4 downto 0) := "00110";
constant s30: std_logic_vector(4 downto 0) := "11100";
constant s23: std_logic_vector(4 downto 0) := "00011";
constant s25: std_logic_vector(4 downto 0) := "10111";
constant s24: std_logic_vector(4 downto 0) := "10011";
constant s26: std_logic_vector(4 downto 0) := "10010";
constant s27: std_logic_vector(4 downto 0) := "00111";
constant s28: std_logic_vector(4 downto 0) := "01100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--------";
case current_state is
when s0 =>
if std_match(input, "----1---") then next_state <= s1; output <= "00000000";
elsif std_match(input, "1---01--") then next_state <= s21; output <= "00000000";
end if;
when s1 =>
if std_match(input, "---0---1") then next_state <= s2; output <= "00001000";
elsif std_match(input, "---0--1-") then next_state <= s2; output <= "00001000";
elsif std_match(input, "1--1----") then next_state <= s3; output <= "00001000";
end if;
when s2 =>
if std_match(input, "1--1----") then next_state <= s3; output <= "00000100";
end if;
when s3 =>
if std_match(input, "1--1----") then next_state <= s4; output <= "10000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "10000000";
end if;
when s4 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "01000000";
end if;
when s5 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "11000000";
end if;
when s6 =>
if std_match(input, "1-----01") then next_state <= s0; output <= "00100000";
elsif std_match(input, "1-----1-") then next_state <= s10; output <= "00100000";
end if;
when s7 =>
if std_match(input, "-1--1---") then next_state <= s8; output <= "11101010";
elsif std_match(input, "-1--0--1") then next_state <= s6; output <= "11101010";
elsif std_match(input, "-1--0-1-") then next_state <= s6; output <= "11101010";
end if;
when s8 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01110000";
elsif std_match(input, "---0---1") then next_state <= s9; output <= "01110000";
elsif std_match(input, "---0--1-") then next_state <= s9; output <= "01110000";
end if;
when s9 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11100100";
end if;
when s10 =>
if std_match(input, "1--10--0") then next_state <= s11; output <= "10101100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10101100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10101100";
end if;
when s11 =>
if std_match(input, "-11-0--0") then next_state <= s12; output <= "11111101";
elsif std_match(input, "11-----1") then next_state <= s0; output <= "11111101";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "11111101";
end if;
when s12 =>
if std_match(input, "---00--0") then next_state <= s13; output <= "10111100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10111100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10111100";
end if;
when s13 =>
if std_match(input, "1-------") then next_state <= s14; output <= "11111100";
end if;
when s14 =>
if std_match(input, "1---0--0") then next_state <= s10; output <= "01100000";
elsif std_match(input, "1------1") then next_state <= s0; output <= "01100000";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "01100000";
end if;
when s21 =>
if std_match(input, "1---0-00") then next_state <= s22; output <= "00011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "00011100";
end if;
when s22 =>
if std_match(input, "1---0100") then next_state <= s23; output <= "10011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "10011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "10011100";
end if;
when s23 =>
if std_match(input, "1---0100") then next_state <= s24; output <= "01011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "01011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01011100";
end if;
when s24 =>
if std_match(input, "1---0000") then next_state <= s25; output <= "11011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11011100";
end if;
when s25 =>
if std_match(input, "---10-00") then next_state <= s26; output <= "01111100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111100";
end if;
when s26 =>
if std_match(input, "011---00") then next_state <= s27; output <= "01111101";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111101";
end if;
when s27 =>
if std_match(input, "0--00-00") then next_state <= s28; output <= "11101100";
elsif std_match(input, "1--00-00") then next_state <= s0; output <= "11101100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11101100";
end if;
when s28 =>
if std_match(input, "1-------") then next_state <= s0; output <= "10111000";
end if;
when s30 =>
if std_match(input, "1-------") then next_state <= s0; output <= "00110000";
end if;
when others => next_state <= "-----"; output <= "--------";
end case;
end process;
end behaviour;
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_mod
-- File: can_mod.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: OpenCores CAN MAC with FIFO RAM
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library opencores;
use opencores.cancomp.all;
library grlib;
use grlib.stdlib.all;
entity can_mod is
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic;
testen : in std_logic
);
attribute sync_set_reset of reset : signal is "true";
end;
architecture rtl of can_mod is
type reg_type is record
waddr : std_logic_vector(5 downto 0);
ready : std_ulogic;
end record;
-- // port connections for Ram
--//64x8
signal q_dp_64x8 : std_logic_vector(7 downto 0);
signal data_64x8 : std_logic_vector(7 downto 0);
signal ldata_64x8 : std_logic_vector(7 downto 0);
signal wren_64x8 : std_logic;
signal lwren_64x8 : std_logic;
signal rden_64x8 : std_logic;
signal wraddress_64x8 : std_logic_vector(5 downto 0);
signal lwraddress_64x8 : std_logic_vector(5 downto 0);
signal rdaddress_64x8 : std_logic_vector(5 downto 0);
--//64x4
signal q_dp_64x4 : std_logic_vector(3 downto 0);
signal lq_dp_64x4 : std_logic_vector(4 downto 0);
signal data_64x4 : std_logic_vector(3 downto 0);
signal ldata_64x4 : std_logic_vector(4 downto 0);
signal wren_64x4x1 : std_logic;
signal lwren_64x4x1 : std_logic;
signal wraddress_64x4x1 : std_logic_vector(5 downto 0);
signal lwraddress_64x4x1 : std_logic_vector(5 downto 0);
signal rdaddress_64x4x1 : std_logic_vector(5 downto 0);
--//64x1
signal q_dp_64x1 : std_logic_vector(0 downto 0);
signal data_64x1 : std_logic_vector(0 downto 0);
signal ldata_64x1 : std_logic_vector(0 downto 0);
signal vcc, gnd : std_ulogic;
signal testin : std_logic_vector(3 downto 0);
signal r, rin : reg_type;
begin
ramclear : if syncrst = 2 generate
comb : process(r, reset, wren_64x8, data_64x8, wraddress_64x8,
data_64x4, wren_64x4x1, wraddress_64x4x1, data_64x1)
variable v : reg_type;
begin
v := r;
if r.ready = '0' then
v.waddr := r.waddr + 1;
if (r.waddr(5) and not v.waddr(5)) = '1' then v.ready := '1'; end if;
lwren_64x8 <= '1'; ldata_64x8 <= (others => '0');
lwraddress_64x8 <= r.waddr;
ldata_64x4 <= (others => '0'); lwren_64x4x1 <= '1';
lwraddress_64x4x1 <= r.waddr;
ldata_64x1 <= "0";
else
lwren_64x8 <= wren_64x8; ldata_64x8 <= data_64x8;
lwraddress_64x8 <= wraddress_64x8;
ldata_64x4 <= data_64x1 & data_64x4; lwren_64x4x1 <= wren_64x4x1;
lwraddress_64x4x1 <= wraddress_64x4x1;
ldata_64x1 <= data_64x1;
end if;
if reset = '1' then
v.ready := '0'; v.waddr := (others => '0');
end if;
rin <= v;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end generate;
noramclear : if syncrst /= 2 generate
lwren_64x8 <= wren_64x8; ldata_64x8 <= data_64x8;
lwraddress_64x8 <= wraddress_64x8;
ldata_64x4 <= data_64x1 & data_64x4; lwren_64x4x1 <= wren_64x4x1;
lwraddress_64x4x1 <= wraddress_64x4x1;
ldata_64x1 <= data_64x1;
end generate;
gnd <= '0'; vcc <= '1';
testin <= testen & "000";
async : if syncrst = 0 generate
can : can_top port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
sync : if syncrst /= 0 generate
can : can_top_sync port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
noft : if (ft = 0) or (memtech = 0) generate
fifo : syncram_2p generic map(memtech,6,8,0)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => lwraddress_64x8,
datain => ldata_64x8, write => lwren_64x8, dataout => q_dp_64x8,
testin => testin);
info_fifo : syncram_2p generic map(memtech,6,5,0)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => lwraddress_64x4x1, datain => ldata_64x4,
write => lwren_64x4x1, dataout => lq_dp_64x4, renable =>vcc,
testin => testin);
end generate;
ften : if not((ft = 0) or (memtech = 0)) generate
fifo : syncram_2pft generic map(memtech,6,8,0,0,2)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => lwraddress_64x8,
datain => ldata_64x8, write => lwren_64x8, dataout => q_dp_64x8,
testin => testin);
info_fifo : syncram_2pft generic map(memtech,6,5,0,0,2)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => lwraddress_64x4x1, datain => ldata_64x4,
write => lwren_64x4x1, dataout => lq_dp_64x4, renable =>vcc,
testin => testin);
end generate;
q_dp_64x4 <= lq_dp_64x4(3 downto 0);
q_dp_64x1 <= lq_dp_64x4(4 downto 4);
-- overrun_fifo : syncram_2p generic map(0,6,1,0)
-- port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
-- waddress => lwraddress_64x4x1, datain => ldata_64x1,
-- write => lwren_64x4x1, dataout => q_dp_64x1, renable => vcc,
-- testin => testin);
end;
|
-- $Id: tb_tst_sram_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_arty
-- Description: Configuration for tb_tst_sram_arty for tb_arty_dram
--
-- Dependencies: sys_tst_sram_arty
--
-- To test: sys_tst_sram_arty
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_sram_arty of tb_arty_dram is
for sim
for all : arty_dram_aif
use entity work.sys_tst_sram_arty;
end for;
end for;
end tb_tst_sram_arty;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
sysace_clk_in : in std_ulogic; -- System ACE clock
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr2_ck : out std_logic_vector(1 downto 0);
ddr2_ck_n : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic_vector(1 downto 0);
ddr2_cs_n : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(1 downto 0);
ddr2_we_n : out std_ulogic; -- ddr write enable
ddr2_ras_n : out std_ulogic; -- ddr ras
ddr2_cas_n : out std_ulogic; -- ddr cas
ddr2_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr2_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_dqs_n : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_a : out std_logic_vector (13 downto 0); -- ddr address
ddr2_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr2_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- txd2 : out std_ulogic; -- UART2 tx data
-- rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
-- D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML501,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr2_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr2_a(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr2_ba(1 downto 0), ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n, ddr2_we_n => ddr2_we_n,
ddr2_cs_n => ddr2_cs_n(CS_NUM-1 downto 0), ddr2_odt => ddr2_odt(0 downto 0),
ddr2_cke => ddr2_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr2_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr2_dqs(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr2_dqs_n(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr2_ck((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr2_ck_n((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
ddr2_a(13) <= '0';
ddr2_odt(1) <= '0';
ddr2_cs_n(1) <= '0';
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#E00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock,
clkml, clkml, ahbsi, ahbso(0),
ddr2_ck, ddr2_ck_n, ddr_clk_fb, ddr_clk_fb, ddr2_cke, ddr2_cs_n,
ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs, ddr2_dqs_n, ddr2_a, ddr2_ba, ddr2_dq, ddr2_odt);
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML501),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu Jun 01 11:35:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_sim_netlist.vhdl
-- Design : system_vga_overlay_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0_vga_overlay is
port (
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 20 downto 0 );
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_overlay_0_0_vga_overlay : entity is "vga_overlay";
end system_vga_overlay_0_0_vga_overlay;
architecture STRUCTURE of system_vga_overlay_0_0_vga_overlay is
signal b_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal b_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal rgb0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb00_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb01_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rgb[11]_i_2_n_0\ : STD_LOGIC;
signal \rgb[11]_i_3_n_0\ : STD_LOGIC;
signal \rgb[11]_i_4_n_0\ : STD_LOGIC;
signal \rgb[11]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_2_n_0\ : STD_LOGIC;
signal \rgb[19]_i_3_n_0\ : STD_LOGIC;
signal \rgb[19]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_2_n_0\ : STD_LOGIC;
signal \rgb[3]_i_3_n_0\ : STD_LOGIC;
signal \rgb[3]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\b_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(0),
Q => b_0(0),
R => '0'
);
\b_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(1),
Q => b_0(1),
R => '0'
);
\b_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(2),
Q => b_0(2),
R => '0'
);
\b_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(3),
Q => b_0(3),
R => '0'
);
\b_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(4),
Q => b_0(4),
R => '0'
);
\b_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(5),
Q => b_0(5),
R => '0'
);
\b_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(6),
Q => b_0(6),
R => '0'
);
\b_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(0),
Q => b_1(0),
R => '0'
);
\b_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(1),
Q => b_1(1),
R => '0'
);
\b_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(2),
Q => b_1(2),
R => '0'
);
\b_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(3),
Q => b_1(3),
R => '0'
);
\b_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(4),
Q => b_1(4),
R => '0'
);
\b_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(5),
Q => b_1(5),
R => '0'
);
\b_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(6),
Q => b_1(6),
R => '0'
);
\g_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(7),
Q => g_0(0),
R => '0'
);
\g_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(8),
Q => g_0(1),
R => '0'
);
\g_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(9),
Q => g_0(2),
R => '0'
);
\g_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(10),
Q => g_0(3),
R => '0'
);
\g_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(11),
Q => g_0(4),
R => '0'
);
\g_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(12),
Q => g_0(5),
R => '0'
);
\g_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(13),
Q => g_0(6),
R => '0'
);
\g_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(7),
Q => g_1(0),
R => '0'
);
\g_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(8),
Q => g_1(1),
R => '0'
);
\g_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(9),
Q => g_1(2),
R => '0'
);
\g_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(10),
Q => g_1(3),
R => '0'
);
\g_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(11),
Q => g_1(4),
R => '0'
);
\g_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(12),
Q => g_1(5),
R => '0'
);
\g_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(13),
Q => g_1(6),
R => '0'
);
\r_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(14),
Q => r_0(0),
R => '0'
);
\r_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(15),
Q => r_0(1),
R => '0'
);
\r_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(16),
Q => r_0(2),
R => '0'
);
\r_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(17),
Q => r_0(3),
R => '0'
);
\r_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(18),
Q => r_0(4),
R => '0'
);
\r_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(19),
Q => r_0(5),
R => '0'
);
\r_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(20),
Q => r_0(6),
R => '0'
);
\r_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(14),
Q => r_1(0),
R => '0'
);
\r_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(15),
Q => r_1(1),
R => '0'
);
\r_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(16),
Q => r_1(2),
R => '0'
);
\r_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(17),
Q => r_1(3),
R => '0'
);
\r_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(18),
Q => r_1(4),
R => '0'
);
\r_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(19),
Q => r_1(5),
R => '0'
);
\r_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(20),
Q => r_1(6),
R => '0'
);
\rgb[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(3),
I1 => g_1(3),
O => \rgb[11]_i_2_n_0\
);
\rgb[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(2),
I1 => g_1(2),
O => \rgb[11]_i_3_n_0\
);
\rgb[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(1),
I1 => g_1(1),
O => \rgb[11]_i_4_n_0\
);
\rgb[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(0),
I1 => g_1(0),
O => \rgb[11]_i_5_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(6),
I1 => g_1(6),
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(5),
I1 => g_1(5),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(4),
I1 => g_1(4),
O => \rgb[15]_i_4_n_0\
);
\rgb[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(3),
I1 => r_1(3),
O => \rgb[19]_i_2_n_0\
);
\rgb[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(2),
I1 => r_1(2),
O => \rgb[19]_i_3_n_0\
);
\rgb[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(1),
I1 => r_1(1),
O => \rgb[19]_i_4_n_0\
);
\rgb[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(0),
I1 => r_1(0),
O => \rgb[19]_i_5_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(6),
I1 => r_1(6),
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(5),
I1 => r_1(5),
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(4),
I1 => r_1(4),
O => \rgb[23]_i_4_n_0\
);
\rgb[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(3),
I1 => b_1(3),
O => \rgb[3]_i_2_n_0\
);
\rgb[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(2),
I1 => b_1(2),
O => \rgb[3]_i_3_n_0\
);
\rgb[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(1),
I1 => b_1(1),
O => \rgb[3]_i_4_n_0\
);
\rgb[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(0),
I1 => b_1(0),
O => \rgb[3]_i_5_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(6),
I1 => b_1(6),
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(5),
I1 => b_1(5),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(4),
I1 => b_1(4),
O => \rgb[7]_i_4_n_0\
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[11]_i_1_n_0\,
CO(2) => \rgb_reg[11]_i_1_n_1\,
CO(1) => \rgb_reg[11]_i_1_n_2\,
CO(0) => \rgb_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => g_0(3 downto 0),
O(3 downto 0) => rgb00_out(3 downto 0),
S(3) => \rgb[11]_i_2_n_0\,
S(2) => \rgb[11]_i_3_n_0\,
S(1) => \rgb[11]_i_4_n_0\,
S(0) => \rgb[11]_i_5_n_0\
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[11]_i_1_n_0\,
CO(3) => rgb00_out(7),
CO(2) => \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[15]_i_1_n_2\,
CO(0) => \rgb_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => g_0(6 downto 4),
O(3) => \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb00_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[15]_i_2_n_0\,
S(1) => \rgb[15]_i_3_n_0\,
S(0) => \rgb[15]_i_4_n_0\
);
\rgb_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(0),
Q => rgb(16),
R => '0'
);
\rgb_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(1),
Q => rgb(17),
R => '0'
);
\rgb_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(2),
Q => rgb(18),
R => '0'
);
\rgb_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(3),
Q => rgb(19),
R => '0'
);
\rgb_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[19]_i_1_n_0\,
CO(2) => \rgb_reg[19]_i_1_n_1\,
CO(1) => \rgb_reg[19]_i_1_n_2\,
CO(0) => \rgb_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => r_0(3 downto 0),
O(3 downto 0) => rgb01_out(3 downto 0),
S(3) => \rgb[19]_i_2_n_0\,
S(2) => \rgb[19]_i_3_n_0\,
S(1) => \rgb[19]_i_4_n_0\,
S(0) => \rgb[19]_i_5_n_0\
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(4),
Q => rgb(20),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(5),
Q => rgb(21),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(6),
Q => rgb(22),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(7),
Q => rgb(23),
R => '0'
);
\rgb_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[19]_i_1_n_0\,
CO(3) => rgb01_out(7),
CO(2) => \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[23]_i_1_n_2\,
CO(0) => \rgb_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => r_0(6 downto 4),
O(3) => \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb01_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[23]_i_2_n_0\,
S(1) => \rgb[23]_i_3_n_0\,
S(0) => \rgb[23]_i_4_n_0\
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[3]_i_1_n_0\,
CO(2) => \rgb_reg[3]_i_1_n_1\,
CO(1) => \rgb_reg[3]_i_1_n_2\,
CO(0) => \rgb_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => b_0(3 downto 0),
O(3 downto 0) => rgb0(3 downto 0),
S(3) => \rgb[3]_i_2_n_0\,
S(2) => \rgb[3]_i_3_n_0\,
S(1) => \rgb[3]_i_4_n_0\,
S(0) => \rgb[3]_i_5_n_0\
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[3]_i_1_n_0\,
CO(3) => rgb0(7),
CO(2) => \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[7]_i_1_n_2\,
CO(0) => \rgb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => b_0(6 downto 4),
O(3) => \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb0(6 downto 4),
S(3) => '1',
S(2) => \rgb[7]_i_2_n_0\,
S(1) => \rgb[7]_i_3_n_0\,
S(0) => \rgb[7]_i_4_n_0\
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_overlay_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_overlay_0_0 : entity is "system_vga_overlay_0_0,vga_overlay,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_overlay_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_overlay_0_0 : entity is "vga_overlay,Vivado 2016.4";
end system_vga_overlay_0_0;
architecture STRUCTURE of system_vga_overlay_0_0 is
begin
U0: entity work.system_vga_overlay_0_0_vga_overlay
port map (
clk => clk,
rgb(23 downto 0) => rgb(23 downto 0),
rgb_0(20 downto 14) => rgb_0(23 downto 17),
rgb_0(13 downto 7) => rgb_0(15 downto 9),
rgb_0(6 downto 0) => rgb_0(7 downto 1),
rgb_1(20 downto 14) => rgb_1(23 downto 17),
rgb_1(13 downto 7) => rgb_1(15 downto 9),
rgb_1(6 downto 0) => rgb_1(7 downto 1)
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:13:04 11/28/2012
-- Design Name:
-- Module Name: AluControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AluControl is port (funct: in std_logic_vector(5 downto 0);
AluOp:in std_logic_vector(2 downto 0);
--AluOp(1) es 1
AluCtr: out std_logic_vector(1 downto 0));
end AluControl;
architecture Behavioral of AluControl is
begin
process(AluOp, funct)
begin-- tipo R
AluCtr<="00";
if AluOp = "010" then
if funct= "100000" then --suma
AluCtr<="10";
elsif funct= "100010" then --resta
AluCtr<="11";
elsif funct= "100100" then --and
AluCtr<="00";
elsif funct= "100101" then --or
AluCtr<="01";
end if;
-- beq,bne,bgt,blt,subi
elsif AluOp = "001" then --resta
AluCtr<="11";
-- lw, sw, addi
elsif AluOp = "000" then --suma
AluCtr<="10";
-- andi
elsif AluOp = "100" then
AluCtr<="00";
-- ori
elsif AluOp = "101" then
AluCtr<="01";
else
AluCtr<="10";
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:13:04 11/28/2012
-- Design Name:
-- Module Name: AluControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AluControl is port (funct: in std_logic_vector(5 downto 0);
AluOp:in std_logic_vector(2 downto 0);
--AluOp(1) es 1
AluCtr: out std_logic_vector(1 downto 0));
end AluControl;
architecture Behavioral of AluControl is
begin
process(AluOp, funct)
begin-- tipo R
AluCtr<="00";
if AluOp = "010" then
if funct= "100000" then --suma
AluCtr<="10";
elsif funct= "100010" then --resta
AluCtr<="11";
elsif funct= "100100" then --and
AluCtr<="00";
elsif funct= "100101" then --or
AluCtr<="01";
end if;
-- beq,bne,bgt,blt,subi
elsif AluOp = "001" then --resta
AluCtr<="11";
-- lw, sw, addi
elsif AluOp = "000" then --suma
AluCtr<="10";
-- andi
elsif AluOp = "100" then
AluCtr<="00";
-- ori
elsif AluOp = "101" then
AluCtr<="01";
else
AluCtr<="10";
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use pack_sum_medio.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eTopSumMedio is
port(
entrada1_tsm: in std_logic;
entrada2_tsm: in std_logic;
resultado_tsm: out std_logic;
acarreo_tsm: out std_logic);
end;
-- Arquitectura
architecture aTopSumMedio of eTopSumMedio is
begin
U1: eAnd port map(
entrada1_and => entrada1_tsm,
entrada2_and => entrada2_tsm,
salida_and => acarreo_tsm);
U2: eXor port map(
entrada1_xor => entrada1_tsm,
entrada2_xor => entrada2_tsm,
salida_xor => resultado_tsm);
end aTopSumMedio;
|
entity func18 is
end entity;
architecture test of func18 is
function get_array(n : in integer) return bit_vector is
-- The state struct for this function cannot be allocated on the stack
variable result : bit_vector(3 downto 0);
function get_xor return bit_vector is
begin
case n is
when 1 => return X"1";
when 2 => return X"2";
when others => return X"f";
end case;
end function;
begin
result := result xor get_xor;
return result;
end function;
begin
p1: process is
variable n : integer := 1;
begin
wait for 1 ns;
assert get_array(n) = X"1";
wait;
end process;
end architecture;
|
-- $Id: serport_xontx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx_tb - sim
-- Description: serial port: xon/xoff logic tx path (SIM only!)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serport_xontx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib_tb.all;
entity serport_xontx_tb is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx_tb;
architecture sim of serport_xontx_tb is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end sim;
|
-- NEED RESULT: ENT00209: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00209: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00209
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00209(ARCH00209)
-- ENT00209_Test_Bench(ARCH00209_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00209 is
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00209 ;
--
--
architecture ARCH00209 of ENT00209 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_rec3.f1 <= transport
c_st_rec3_2.f1 ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ;
wait until s_st_rec3.f2 =
c_st_rec3_2.f2 ;
Test_Report (
"ENT00209",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f2 =
c_st_rec3_2.f2 )) ;
--
when 1
=>
s_st_rec3.f1 <= transport
c_st_rec3_1.f1 ;
s_st_rec3.f3 <= transport
c_st_rec3_2.f3 after 10 ns ;
wait until s_st_rec3.f3 =
c_st_rec3_2.f3 ;
Test_Report (
"ENT00209",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f3 =
c_st_rec3_2.f3 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00209 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00209_Test_Bench is
end ENT00209_Test_Bench ;
--
--
architecture ARCH00209_Test_Bench of ENT00209_Test_Bench is
begin
L1:
block
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00209 ( ARCH00209 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00209_Test_Bench ;
|
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_MUX_2to1 is
end TB_MUX_2to1;
architecture Behavioral of TB_MUX_2to1 is
component MUX_2to1 is
Port (
SEL : in STD_LOGIC; -- 2 bits
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal SEL : STD_LOGIC;
signal IN_1,IN_2 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal OUTPUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 2 TO 1 MUX
MUX1: MUX_2to1 port map(
SEL => SEL,
IN_1 => IN_1,
IN_2 => IN_2,
output => output
);
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
--Set up the four inputs
IN_1 <= x"111111";
IN_2 <= x"222222";
--Test the Select for each input
SEL <= '0'; wait for 2*period;
SEL <= '1'; wait for 2*period;
end process;
end Behavioral;
|
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|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:36:40 05/24/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trigger.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: trigger
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.types.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_trigger IS
END test_trigger;
ARCHITECTURE behavior OF test_trigger IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT trigger
PORT(
nrst : IN std_logic;
clk108 : IN std_logic;
trigger_btn : IN std_logic;
trigger_event : IN TRIGGER_EVENT_T;
red_enable : IN std_logic;
green_enable : IN std_logic;
blue_enable : IN std_logic;
continue_after_reading : IN std_logic;
red_input : IN std_logic;
green_input : IN std_logic;
blue_input : IN std_logic;
overflow_indicator : IN std_logic;
red_output : OUT std_logic;
green_output : OUT std_logic;
blue_output : OUT std_logic;
is_reading_active : OUT std_logic
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk108 : std_logic := '0';
signal trigger_btn : std_logic := '0';
signal trigger_event : TRIGGER_EVENT_T := BUTTON_TRIGGER_T;
signal red_enable : std_logic := '0';
signal green_enable : std_logic := '0';
signal blue_enable : std_logic := '0';
signal continue_after_reading : std_logic := '0';
signal red_input : std_logic := '0';
signal green_input : std_logic := '0';
signal blue_input : std_logic := '0';
signal overflow_indicator : std_logic := '0';
--Outputs
signal red_output : std_logic;
signal green_output : std_logic;
signal blue_output : std_logic;
signal is_reading_active : std_logic;
-- Clock period definitions
constant clk108_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: trigger PORT MAP (
nrst => nrst,
clk108 => clk108,
trigger_btn => trigger_btn,
trigger_event => trigger_event,
red_enable => red_enable,
green_enable => green_enable,
blue_enable => blue_enable,
continue_after_reading => continue_after_reading,
red_input => red_input,
green_input => green_input,
blue_input => blue_input,
overflow_indicator => overflow_indicator,
red_output => red_output,
green_output => green_output,
blue_output => blue_output,
is_reading_active => is_reading_active
);
-- Clock process definitions
clk108_process :process
begin
clk108 <= '0';
wait for clk108_period/2;
clk108 <= '1';
wait for clk108_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for 100 ns;
nrst <= '1';
wait for clk108_period;
wait for clk108_period * 10;
trigger_btn <= '1';
wait for clk108_period;
trigger_btn <= '0';
assert is_reading_active = '1' report "Reading should be active";
red_enable <= '1';
green_enable <= '0';
blue_enable <= '1';
red_input <= '1';
green_input <= '1';
blue_input <= '0';
wait for clk108_period;
assert red_output = '1' report "Red should be active";
assert green_output = '0' report "Green should not be active";
assert blue_output = '0' report "Blue should not be active";
wait for clk108_period;
red_input <= '0';
green_input <= '0';
blue_input <= '0';
wait for clk108_period * 10;
continue_after_reading <= '0';
overflow_indicator <= '1';
wait for clk108_period;
assert is_reading_active = '0' report "Reading should not be active; issued an overflow";
overflow_indicator <= '0';
wait for clk108_period * 10;
trigger_event <= GREEN_TRIGGER_T;
green_input <= '1';
wait for clk108_period;
green_input <= '0';
wait for clk108_period;
assert is_reading_active = '1' report "Reading should be active; trigger on rising edge at green";
wait for clk108_period * 10;
trigger_btn <= '1';
wait for clk108_period;
trigger_btn <= '0';
assert is_reading_active = '0' report "Reading should not be active; stopped it with button";
wait;
end process;
END;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter9.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter9 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END lpm_counter9;
ARCHITECTURE SYN OF lpm_counter9 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(23 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 24
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (3 downto 0);
result : out STD_LOGIC_VECTOR (31 downto 0);
flags : out STD_LOGIC_VECTOR (3 downto 0));
end ALU;
architecture Behavioral of ALU is
component FPMultiply is
port( A_in : in std_logic_vector(31 downto 0);
B_in : in std_logic_vector(31 downto 0);
R : out std_logic_vector(31 downto 0));
end component;
signal output, normal_output : std_logic_vector(32 downto 0);
signal fixed_output : std_logic_vector(31 downto 0);
begin
main: process(A, B, sel, fixed_output, normal_output, output) is
begin
--Set flags to 0 as default
flags <= "0000";
--This actually performs the operation chosen by the select lines
--The reason the output variable is 33 bits wide is to accomodate for
--the carry bit, and it also helps a lot with shifting operations. By
--the way, I did try the built-in shift operations, but without much
--luck.
case sel is
when "0000" => --add
normal_output <= ('0' & A(31 downto 0)) + ('0' & B(31 downto 0));
when "0001" => --sub
normal_output <= ('0' & A(31 downto 0)) - ('0' & B(31 downto 0));
when "0010" => --and
normal_output <= '0' & (A and B);
when "0011" => --or
normal_output <= '0' & (A or B);
when "0100" => --xor
normal_output <= '0' & (A xor B);
when "0101" => --cp
normal_output <= ('0' & A);
when "0110" => --sll
normal_output <= (A(31 downto 0) & '0');
when "0111" => --srl
normal_output <= ("00" & A(31 downto 1));
when "1000" => --rol
normal_output <= (A(0) & A(0) & A(31 downto 1));
when "1001" => --ror
normal_output <= (A(30) & A(30 downto 0) & A(31));
when others =>
normal_output <= ('0' & A);
end case;
if sel(3 downto 1) = "101" then
output <= '0' & fixed_output;
else
output <= normal_output;
end if;
--This if statement generates the flags
if (A > B) then --Greater than
flags(1) <= '1';
elsif (A = B) then --Equal to
flags(2) <= '1';
elsif (A < B) then --Less than
flags(3) <= '1';
end if;
flags(0) <= output(32); --Carry flag (33rd bit)
result <= output(31 downto 0);
end process;
fpmul : FPMultiply
port map(
A_in => A,
B_in => B,
R => fixed_output
);
end Behavioral;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package package8bita00 is
component xora00
port (Ax: in std_logic;
Bx: in std_logic;
Yx: out std_logic);
end component;
component topfaa00
port (A00: in std_logic;
B00: in std_logic;
C00: in std_logic;
C01: out std_logic;
S00: out std_logic);
end component;
component xnora00
port (Anx: in std_logic;
Bnx: in std_logic;
Ynx: out std_logic);
end component;
component anda00
port (Aa: in std_logic;
Ba: in std_logic;
Ya: out std_logic);
end component;
end package8bita00;
|
architecture RTL of FIFO is
attribute coordinate OF comp_1:component is (0.0, 17.5);
ATTRIBUTE COORDINATE OF comp_1:component IS (0.0, 17.5);
begin
end architecture RTL;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Dummy Cache Replacement Algorithm for Direct-Mapped Caches
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_l1mem_inst_cache_replace_none_pkg.all;
entity cpu_l1mem_inst_cache_replace_none is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_l1mem_inst_cache_replace_none_ctrl_in : in cpu_l1mem_inst_cache_replace_none_ctrl_in_type;
cpu_l1mem_inst_cache_replace_none_dp_in : in cpu_l1mem_inst_cache_replace_none_dp_in_type;
cpu_l1mem_inst_cache_replace_none_dp_out : out cpu_l1mem_inst_cache_replace_none_dp_out_type
);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:21:09 09/09/2015
-- Design Name:
-- Module Name: BinGray - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional CommDatos:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity BinGray is
Port ( Code : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
Display : out STD_LOGIC_VECTOR (3 downto 0));
end BinGray;
architecture Behavioral of BinGray is
--Las señales embebidas se declaran aqui !!!!!!!!!!!!!!
signal Gray : STD_LOGIC_VECTOR (3 downto 0);
signal Bin : STD_LOGIC_VECTOR (3 downto 0);
signal Dato : STD_LOGIC_VECTOR (3 downto 0);
begin
-- Definicion de BinToGray
-- Binary to Gray conversion using Loops
Gray(3) <= Code(3);
for_loop:
for i in 2 downto 0 generate
begin
Gray(i) <= Code(i+1) xor Code(i);
end generate;
-- Definicion de GrayToBin
-- Gray to Bin conversion using Loops
Bin(3) <= Code(3);
for_loop1:
for i in 2 downto 0 generate
begin
Bin(i) <= Bin(i+1) xor Code(i);
end generate;
-- Definicion del multiplexor
Dato <= Gray when Sel = '0' else
Bin;
-- Definicion del Decodificador Bin a 7 Segmentos
-- utilizando una declaracion concurrente.
decoder: process(Dato)
begin --.gfedcba
if Dato = x"0" then Seg <= "11000000";
elsif Dato = x"1" then Seg <= "11111001";
elsif Dato = x"2" then Seg <= "10100100";
elsif Dato = x"3" then Seg <= "10110000";
elsif Dato = x"4" then Seg <= "10011001";
elsif Dato = x"5" then Seg <= "10010010";
elsif Dato = x"6" then Seg <= "10000010";
elsif Dato = x"7" then Seg <= "11111000";
elsif Dato = x"8" then Seg <= "10000000";
elsif Dato = x"9" then Seg <= "10010000";
elsif Dato = x"A" then Seg <= "10001000";
elsif Dato = x"B" then Seg <= "10000011";
elsif Dato = x"C" then Seg <= "11000110";
elsif Dato = x"D" then Seg <= "10100001";
elsif Dato = x"E" then Seg <= "10000110";
else Seg <= "10001110";
end if;
end process decoder;
-- Select Display
Display <= "1110";
end Behavioral;
|
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`protect end_protected
|
-------------------------------------------------------------------------------
--! @file onewire_discover.vhd
--! @author Johannes Walter <johannes@greenshire.io>
--! @copyright LGPL v2.1
--! @brief Perform a search algorithm to discover devices on the bus.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
use work.onewire_idtemp_pkg.all;
--! @brief Entity declaration of onewire_discover
entity onewire_discover is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Internal signals
--! @{
--! Start search algorithm
discover_i : in std_ulogic;
--! Discovered device ID
id_o : out std_ulogic_vector(63 downto 0);
--! Discovered device ID enable
id_en_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! @}
--! @name Bus interface signals
--! @{
--! Send a bus reset command
bus_rst_o : out std_ulogic;
--! Send data bit
bit_send_o : out std_ulogic;
--! The data bit to be sent
bit_o : out std_ulogic;
--! Receive data bit
bit_recv_o : out std_ulogic;
--! The received data bit
bit_i : in std_ulogic;
--! The received data bit enable
bit_en_i : in std_ulogic;
--! Done flag
bit_done_i : in std_ulogic);
--! @}
end entity onewire_discover;
--! RTL implementation of onewire_discover
architecture rtl of onewire_discover is
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
constant lfsr_len_c : natural := lfsr_length(cmd_search_c'length);
subtype lfsr_t is std_ulogic_vector(lfsr_len_c - 1 downto 0);
constant lfsr_seed_c : lfsr_t := lfsr_seed(lfsr_len_c);
constant lfsr_max_c : lfsr_t := lfsr_shift(lfsr_seed_c, cmd_search_c'length - 1);
type state_t is (IDLE, RESET_DONE, SEARCH_COMMAND, READ_ID_BIT,
READ_CMP_ID_BIT, COMPARE, CHECK);
type reg_t is record
state : state_t;
lfsr : lfsr_t;
done : std_ulogic;
id : std_ulogic_vector(id_o'high + 1 downto id_o'low + 1);
id_en : std_ulogic;
cmd : std_ulogic_vector(7 downto 0);
bus_rst : std_ulogic;
bit_send : std_ulogic;
bit_recv : std_ulogic;
crc_reset : std_ulogic;
id_bit : std_ulogic;
cmp_id_bit : std_ulogic;
search : std_ulogic;
id_bit_number : unsigned(6 downto 0);
marker : unsigned(6 downto 0);
last_discrepancy : unsigned(6 downto 0);
end record;
constant init_c : reg_t := (
state => IDLE,
lfsr => lfsr_seed_c,
done => '0',
id => (others => '0'),
id_en => '0',
cmd => cmd_search_c,
bus_rst => '0',
bit_send => '0',
bit_recv => '0',
crc_reset => '0',
id_bit => '0',
cmp_id_bit => '0',
search => '0',
id_bit_number => to_unsigned(1, 7),
marker => to_unsigned(0, 7),
last_discrepancy => to_unsigned(0, 7));
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal nxt_reg : reg_t;
signal crc_valid : std_ulogic;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
id_o <= reg.id;
id_en_o <= reg.id_en;
done_o <= reg.done;
bus_rst_o <= reg.bus_rst;
bit_send_o <= reg.bit_send;
bit_recv_o <= reg.bit_recv;
bit_o <= reg.search;
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
crc_inst : entity work.onewire_crc
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
reset_i => reg.crc_reset,
data_i => reg.search,
data_en_i => reg.bit_send,
valid_o => crc_valid);
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= nxt_reg;
end if;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, discover_i, bit_i, bit_en_i, bit_done_i, crc_valid) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.done <= init_c.done;
nxt_reg.id_en <= init_c.id_en;
nxt_reg.bus_rst <= init_c.bus_rst;
nxt_reg.bit_send <= init_c.bit_send;
nxt_reg.bit_recv <= init_c.bit_recv;
nxt_reg.crc_reset <= init_c.crc_reset;
case reg.state is
when IDLE =>
if discover_i = '1' then
nxt_reg.bus_rst <= '1';
nxt_reg.state <= RESET_DONE;
end if;
when RESET_DONE =>
if bit_done_i = '1' then
if bit_i = '1' then
nxt_reg <= init_c;
nxt_reg.done <= '1';
else
nxt_reg.bit_send <= '1';
nxt_reg.search <= reg.cmd(reg.cmd'low);
nxt_reg.cmd <= '0' & reg.cmd(reg.cmd'high downto reg.cmd'low + 1);
nxt_reg.state <= SEARCH_COMMAND;
end if;
end if;
when SEARCH_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = lfsr_max_c then
nxt_reg.bit_recv <= '1';
nxt_reg.crc_reset <= '1';
nxt_reg.state <= READ_ID_BIT;
else
nxt_reg.bit_send <= '1';
nxt_reg.search <= reg.cmd(reg.cmd'low);
nxt_reg.cmd <= '0' & reg.cmd(reg.cmd'high downto reg.cmd'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when READ_ID_BIT =>
if bit_en_i = '1' then
nxt_reg.id_bit <= bit_i;
nxt_reg.bit_recv <= '1';
nxt_reg.state <= READ_CMP_ID_BIT;
end if;
when READ_CMP_ID_BIT =>
if bit_en_i = '1' then
nxt_reg.cmp_id_bit <= bit_i;
nxt_reg.state <= COMPARE;
end if;
when COMPARE =>
nxt_reg.state <= CHECK;
nxt_reg.bit_send <= '1';
if reg.id_bit = '1' and reg.cmp_id_bit = '1' then
nxt_reg <= init_c;
nxt_reg.done <= '1';
elsif reg.id_bit = '0' and reg.cmp_id_bit = '0' then
if reg.id_bit_number = reg.last_discrepancy then
nxt_reg.id(to_integer(reg.id_bit_number)) <= '1';
nxt_reg.search <= '1';
elsif reg.id_bit_number > reg.last_discrepancy then
nxt_reg.id(to_integer(reg.id_bit_number)) <= '0';
nxt_reg.search <= '0';
nxt_reg.marker <= reg.id_bit_number;
else
nxt_reg.search <= reg.id(to_integer(reg.id_bit_number));
if reg.id(to_integer(reg.id_bit_number)) = '0' then
nxt_reg.marker <= reg.id_bit_number;
end if;
end if;
else
nxt_reg.id(to_integer(reg.id_bit_number)) <= reg.id_bit;
nxt_reg.search <= reg.id_bit;
end if;
when CHECK =>
if bit_done_i = '1' then
if to_integer(reg.id_bit_number) < reg.id'length then
nxt_reg.id_bit_number <= reg.id_bit_number + 1;
nxt_reg.bit_recv <= '1';
nxt_reg.state <= READ_ID_BIT;
else
if to_integer(reg.marker) = 0 then
nxt_reg <= init_c;
nxt_reg.done <= '1';
else
nxt_reg <= init_c;
nxt_reg.last_discrepancy <= reg.marker;
nxt_reg.bus_rst <= '1';
nxt_reg.state <= RESET_DONE;
end if;
if crc_valid = '0' then
nxt_reg.id <= (others => '1');
else
nxt_reg.id <= reg.id;
end if;
nxt_reg.id_en <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14a is
end entity inline_14a;
----------------------------------------------------------------
architecture test of inline_14a is
-- code from book:
type array3 is array (10 downto 1) of real tolerance "default";
quantity a3 : array3;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14a is
end entity inline_14a;
----------------------------------------------------------------
architecture test of inline_14a is
-- code from book:
type array3 is array (10 downto 1) of real tolerance "default";
quantity a3 : array3;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14a is
end entity inline_14a;
----------------------------------------------------------------
architecture test of inline_14a is
-- code from book:
type array3 is array (10 downto 1) of real tolerance "default";
quantity a3 : array3;
-- end of code from book
begin
end architecture test;
|
--!
--! @file: exercise5_2.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity dual_edge_ff is
--generic declarations
port (
d: in std_logic;
clk: in std_logic;
q: out std_logic);
end entity dual_edge_ff;
--------------------------------------
architecture circuit of dual_edge_ff is
signal p: std_logic;
signal r: std_logic;
signal q_p: std_logic;
signal q_r: std_logic;
begin
-- positive edge flip flop
p <= d when clk = '0' else p;
q_p <= p when clk = '1' else q_p;
-- negative edge flip flop
r <= d when clk = '1' else r;
q_r <= r when clk = '0' else q_r;
-- multiplexer for output
q <= q_p when clk = '1' else q_r;
end architecture circuit;
--------------------------------------
-- according to the example 7.6 of book
architecture circuit1 of dual_edge_ff is
signal q1: std_logic;
signal q2: std_logic;
begin
q1 <= d when clk = '1' else q1;
q2 <= d when clk = '0' else q2;
q <= q1 when clk = '0' else q2;
end architecture circuit;
--------------------------------------
|
-------------------------------------------------------------------------------
-- Title : IGMP Assembler
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_assembler.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-03-15
-- Platform : Virtex 4/5/6
-------------------------------------------------------------------------------
--
--* @brief Assemble the IGMP Packet
--
--! @details: This module creates the IGMP packet for the join, report, and leave.
--! All values are prestored in constants and used as needed.
--!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity igmp_assembler is
generic (
gen_dataWidth : integer := 8
);
port (
dataClk : in std_logic;
reset : in std_logic;
-- packet constuctor information signals
srcMAC : in std_logic_vector(47 downto 0);
destMAC : in std_logic_vector(47 downto 0);
vlanEn : in std_logic;
vlanId : in std_logic_vector(11 downto 0);
srcIP : in std_logic_vector(31 downto 0);
destIP : in std_logic_vector(31 downto 0);
-- control signals
join : in std_logic;
leave : in std_logic;
tx_ready_n : in std_logic;
messageSent : out std_logic;
tx_sof : out std_logic;
tx_eof : out std_logic;
tx_vld : out std_logic;
tx_data : out std_logic_vector(7 downto 0)
);
end igmp_assembler;
architecture rtl of igmp_assembler is
type ipv4Header is array(9 downto 0) of std_logic_vector(7 downto 0);
constant headerValues : ipv4Header := (X"45", X"00", X"00", X"1C", X"00", X"00", X"40", X"00", X"01", X"02");
constant c_vlanType : std_logic_vector(15 downto 0) := X"8100";
constant c_packetType : std_logic_vector(15 downto 0) := X"0800";
signal assembly_state : std_logic_vector(3 downto 0) := (others => '0');
signal byteCount : integer range 0 to 9 := 0;
signal done : std_logic := '0';
signal ipv4_layer_checksum_join, ipv4_layer_checksum_leave : std_logic_vector(15 downto 0) := (others => '0');
signal igmp_layer_checksum_join, igmp_layer_checksum_leave : std_logic_vector(15 downto 0) := (others => '0');
signal join_r, join_r2, leave_r, leave_r2, join_hold, leave_hold, rsp_hold : std_logic := '0';
signal igmpType : std_logic_vector(7 downto 0) := (others => '0');
signal ipv4Checksum : std_logic_vector(15 downto 0) := (others => '0');
signal igmpChecksum : std_logic_vector(15 downto 0) := (others => '0');
signal ipv4Address : std_logic_vector(31 downto 0) := (others => '0');
signal groupaddress : std_logic_vector(31 downto 0) := (others => '0');
-- 2 1 0
signal currentState : std_logic_vector(2 downto 0) := (others => '0');
signal startChecksum : std_logic := '0';
-- bit 2 join
-- bit 1 leave
signal srcMAC_r : std_logic_vector(47 downto 0);
signal destMAC_r : std_logic_vector(47 downto 0);
signal vlanEn_r : std_logic;
signal vlanId_r : std_logic_vector(11 downto 0);
signal srcIP_r : std_logic_vector(31 downto 0);
signal destIP_r : std_logic_vector(31 downto 0);
signal tx_ready_n_r : std_logic;
begin
register_and_hold_join_rsp_leave : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
--rsp_r <= '0';
--rsp_r2 <= '0';
join_r <= '0';
leave_r <= '0';
join_r2 <= '0';
leave_r2 <= '0';
else
join_r <= join;
leave_r <= leave;
join_r2 <= join_r;
leave_r2 <= leave_r;
srcMAC_r <= srcMAC;
destMAC_r <= destMAC;
vlanEn_r <= vlanEn;
vlanId_r <= vlanId;
srcIP_r <= srcIP;
destIP_r <= destIP;
tx_ready_n_r <= tx_ready_n;
end if;
end if;
end process;
new_one : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
-- tx_ready_n <= '0';
tx_data <= (others => '0');
tx_eof <= '0';
tx_sof <= '0';
tx_vld <= '0';
assembly_state <= (others => '0');
igmpType <= (others => '0');
byteCount <= 0;
ipv4Checksum <= (others => '0');
igmpChecksum <= (others => '0');
groupAddress <= (others => '0');
ipv4Address <= (others => '0');
currentState <= "000";
messageSent <= '0';
startChecksum <= '0';
else
if(tx_ready_n_r = '0')then
messageSent <= '0';
case assembly_state is
when "0001" =>
startChecksum <= '0';
if(done = '1')then
if(currentState = "100" or currentState = "001")then
ipv4Checksum <= ipv4_layer_checksum_join;
igmpChecksum <= igmp_layer_checksum_join;
ipv4Address <= destIP_r;
groupAddress <= destIP_r;
assembly_state <= "0010";
igmpType <= X"16";
byteCount <= 6;
elsif(currentState = "010")then
ipv4Checksum <= ipv4_layer_checksum_leave;
igmpChecksum <= igmp_layer_checksum_leave;
ipv4Address <= X"E0000002";
groupAddress <= destIP_r;
assembly_state <= "0010";
igmpType <= X"17";
byteCount <= 6;
else
ipv4Checksum <= (others => '0');
igmpChecksum <= (others => '0');
assembly_state <= (others => '0');
igmpType <= (others => '0');
byteCount <= 0;
end if;
end if;
when "0010" =>
assembly_state <= "0010";
if(byteCount = 6)then
tx_sof <= '1';
tx_data <= destMAC_r(47 downto 40);
byteCount <= byteCount - 1;
elsif(byteCount > 1)then
tx_sof <= '0';
tx_data <= destMAC_r((8*byteCount)-1 downto 8*(byteCount - 1));
byteCount <= byteCount - 1;
elsif(byteCount = 1)then
tx_data <= destMAC_r(7 downto 0);
assembly_state <= "0011";
byteCount <= 6;
end if;
tx_vld <= '1';
when "0011" =>
assembly_state <= "0011";
if(byteCount = 6)then
tx_data <= srcMAC_r(47 downto 40);
byteCount <= byteCount - 1;
elsif(byteCount > 1)then
tx_sof <= '0';
tx_data <= srcMAC_r((8*byteCount)-1 downto 8*(byteCount - 1));
byteCount <= byteCount - 1;
elsif(byteCount = 1)then
tx_data <= srcMAC_r(7 downto 0);
if(vlanEn_r = '1')then
assembly_state <= "0100";
byteCount <= 3;
else
assembly_state <= "0101";
byteCount <= 2;
end if;
-- else
-- assembly_state <= "000000010";
end if;
tx_vld <= '1';
when "0100" =>
assembly_state <= "0100";
tx_vld <= '1';
if(byteCount = 3)then
tx_data <= c_vlanType(15 downto 8);
byteCount <= byteCount - 1;
elsif(byteCount = 2)then
tx_data <= c_vlanType(7 downto 0);
byteCount <= byteCount - 1;
elsif(byteCount = 1)then
tx_data <= "0000" & vlanId_r(11 downto 8);
byteCount <= byteCount - 1;
elsif(byteCount = 0)then
tx_data <= vlanId_r(7 downto 0);
byteCount <= 2;
assembly_state <= "0101";
end if;
when "0101" =>
assembly_state <= "0101";
tx_vld <= '1';
if(byteCount = 2)then
tx_data <= c_packetType(15 downto 8);
byteCount <= byteCount - 1;
else
tx_data <= c_packetType(7 downto 0);
assembly_state <= "0110";
byteCount <= 9;
end if;
when "0110" =>
if(byteCount = 0)then
assembly_state <= "0111";
byteCount <= 1;
else
byteCount <= byteCount - 1;
end if;
tx_data <= headerValues(byteCount);
tx_vld <= '1';
when "0111" =>
if(byteCount = 0)then
assembly_state <= "1000";
byteCount <= 3;
else
byteCount <= byteCount-1;
assembly_state <= "0111";
end if;
tx_data <= ipv4Checksum(((byteCount+1)*8)-1 downto byteCount*8);
tx_vld <= '1';
when "1000" =>
if(byteCount = 0)then
assembly_state <= "1001";
byteCount <= 3;
else
assembly_state <= "1000";
byteCount <= byteCount - 1;
end if;
tx_vld <= '1';
tx_data <= srcIP_r(((byteCount+1)*8)-1 downto byteCount*8);
when "1001" =>
if(byteCount = 0)then
assembly_state <= "1100";
byteCount <= 1;
else
assembly_state <= "1001";
byteCount <= byteCount - 1;
end if;
tx_data <= ipv4Address((byteCount+1)*8-1 downto byteCount*8);
tx_vld <= '1';
when "1100" =>
byteCount <= 1;
assembly_state <= "1101";
tx_data <= igmpType;
tx_vld <= '1';
when "1101" =>
tx_data <= X"00";
tx_vld <= '1';
assembly_state <= "1110";
when "1110" =>
if(byteCount = 0)then
byteCount <= 3;
assembly_state <= "1111";
else
byteCount <= byteCount - 1;
assembly_state <= "1110";
end if;
tx_data <= igmpChecksum(8*(byteCount+1)-1 downto byteCount*8);
tx_vld <= '1';
when "1111" =>
if(byteCount = 0)then
byteCount <= 0;
messageSent <= '1';
assembly_state <= "0000"; --(others => '0');
currentState <= "000";
tx_eof <= '1';
else
byteCount <= byteCount - 1;
assembly_state <= "1111";
end if;
tx_data <= groupAddress(8*(byteCount+1)-1 downto byteCount*8);
tx_vld <= '1';
when "0000" =>
tx_eof <= '0';
tx_vld <= '0';
if((join_r = '1' and join_r2 = '0') or (leave_r = '1' and leave_r2 = '0'))then
currentState <= join_r & leave_r & '0';
assembly_state <= "0001";
else
assembly_state <= "0000";
end if;
if(join_r = '1')then
startChecksum <= '1';
else
startChecksum <= '0';
end if;
when others =>
end case;
else
tx_vld <= '0';
tx_sof <= '0';
tx_eof <= '0';
end if;
-- tx_sof <= '0';
-- tx_eof <= '0';
-- tx_vld <= '0';
end if;
end if;
end process;
create_checksum : entity work.checksum
port map (
dataClk => dataClk,
reset => reset,
start_checksum => startChecksum,
multicast_ip => destIP,
source_ip => srcIP,
checksum_done => done,
ipv4_layer_checksum_j => ipv4_layer_checksum_join,
ipv4_layer_checksum_l => ipv4_layer_checksum_leave,
igmp_layer_checksum_j => igmp_layer_checksum_join,
igmp_layer_checksum_l => igmp_layer_checksum_leave
);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY segseven IS
PORT (SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END segseven;
ARCHITECTURE Behavior OF segseven IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= (SW(3) AND SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND SW(1) AND SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(3) AND NOT SW(2));
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= (NOT SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(2) AND NOT SW(1) AND SW (0)) OR
(NOT SW(3) AND NOT SW(2));
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= (SW(2) AND NOT SW(1) AND SW(0)) OR
(NOT SW(3) AND NOT SW(2)) OR
(NOT SW(3) AND NOT SW(1));
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= (NOT SW(3) AND NOT SW(0)) OR
(SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND SW(1) AND SW(0)) OR
(NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1));
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= (NOT SW(3) AND NOT SW(1)) OR
(NOT SW(2) AND SW(1)) OR
(NOT SW(0));
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= (SW(3) AND SW(2) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(2)) OR
(SW(2) AND NOT SW(1)) OR
(NOT SW(1) AND NOT SW(0));
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= (SW(3) AND SW(2) AND SW(1)) OR
(NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(3) AND NOT SW(2));
END Behavior; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY segseven IS
PORT (SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END segseven;
ARCHITECTURE Behavior OF segseven IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= (SW(3) AND SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND SW(1) AND SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(3) AND NOT SW(2));
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= (NOT SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(2) AND NOT SW(1) AND SW (0)) OR
(NOT SW(3) AND NOT SW(2));
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= (SW(2) AND NOT SW(1) AND SW(0)) OR
(NOT SW(3) AND NOT SW(2)) OR
(NOT SW(3) AND NOT SW(1));
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= (NOT SW(3) AND NOT SW(0)) OR
(SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND SW(1) AND SW(0)) OR
(NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1));
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= (NOT SW(3) AND NOT SW(1)) OR
(NOT SW(2) AND SW(1)) OR
(NOT SW(0));
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= (SW(3) AND SW(2) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(2)) OR
(SW(2) AND NOT SW(1)) OR
(NOT SW(1) AND NOT SW(0));
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= (SW(3) AND SW(2) AND SW(1)) OR
(NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(3) AND NOT SW(2));
END Behavior; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cos is
end entity tb_cos;
----------------------------------------------------------------
architecture test_series of tb_cos is
signal theta, result : real := 0.0;
begin
dut : entity work.cos(series)
port map ( theta => theta, result => result );
stimulus : process is
constant pi : real := 3.1415927;
begin
wait for 10 ns;
theta <= pi / 6.0; wait for 10 ns;
theta <= pi / 4.0; wait for 10 ns;
theta <= pi / 3.0; wait for 10 ns;
theta <= pi / 2.0; wait for 10 ns;
wait;
end process stimulus;
end architecture test_series;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cos is
end entity tb_cos;
----------------------------------------------------------------
architecture test_series of tb_cos is
signal theta, result : real := 0.0;
begin
dut : entity work.cos(series)
port map ( theta => theta, result => result );
stimulus : process is
constant pi : real := 3.1415927;
begin
wait for 10 ns;
theta <= pi / 6.0; wait for 10 ns;
theta <= pi / 4.0; wait for 10 ns;
theta <= pi / 3.0; wait for 10 ns;
theta <= pi / 2.0; wait for 10 ns;
wait;
end process stimulus;
end architecture test_series;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cos is
end entity tb_cos;
----------------------------------------------------------------
architecture test_series of tb_cos is
signal theta, result : real := 0.0;
begin
dut : entity work.cos(series)
port map ( theta => theta, result => result );
stimulus : process is
constant pi : real := 3.1415927;
begin
wait for 10 ns;
theta <= pi / 6.0; wait for 10 ns;
theta <= pi / 4.0; wait for 10 ns;
theta <= pi / 3.0; wait for 10 ns;
theta <= pi / 2.0; wait for 10 ns;
wait;
end process stimulus;
end architecture test_series;
|
-----------------------------------------------------------------------------
-- Module for 50Mhz clock-generating on a Spartan 3 for hwpulse
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clocking is
Port (
clk_in : in std_logic;
rst : in std_logic;
clk1x : out std_logic;
clk_div : out std_logic;
lock : out std_logic
);
end clocking;
architecture clocking_arch of clocking is
signal gnd, clk_div_w, clk0_w, clkdv_w, clk1x_w:std_logic;
signal lock_s:std_logic:='1';
begin
lock <= lock_s;
gnd <= '0';
clk_div <= clk_div_w;
clk1x <= clk1x_w;
DCM_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any Integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an Integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => clk0_w, -- 0 degree DCM_SP CLK ouptput
CLK180 => open, -- 180 degree DCM_SP CLK output
CLK270 => open, -- 270 degree DCM_SP CLK output
CLK2X => open, -- 2X DCM_SP CLK output
CLK2X180 => open, -- 2X, 180 degree DCM_SP CLK out
CLK90 => open, -- 90 degree DCM_SP CLK output
CLKDV => clkdv_w, -- Divided DCM_SP CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM_SP CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => lock_s, -- DCM_SP LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM_SP status bits output
CLKFB => clk1x_w, -- DCM_SP clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM_SP)
PSCLK => gnd, -- Dynamic phase adjust clock input
PSEN => gnd, -- Dynamic phase adjust enable input
PSINCDEC => gnd, -- Dynamic phase adjust increment/decrement
RST => rst -- DCM_SP asynchronous reset input
);
u0_bufg: bufg
port map (
i => clk0_w,
o => clk1x_w
);
u1_bufg: bufg
port map (
i => clkdv_w,
o => clk_div_w
);
end clocking_arch;
|
package pack is
signal x, y : integer := 0;
procedure inc(signal s : out integer);
end package;
package body pack is
procedure inc(signal s : out integer) is
begin
s <= x + 1;
end procedure;
procedure bar(signal s : in integer) is
begin
end procedure;
procedure foo is
begin
bar(x);
end procedure;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
end entity;
architecture test of sub is
begin
process is
begin
report x'path_name;
report x'instance_name;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity signal11 is
end entity;
use work.pack.all;
architecture test of signal11 is
begin
process is
begin
assert x = 0;
inc(x);
wait for 1 ns;
assert x = 1;
wait for 1 ns;
assert y = 2;
wait;
end process;
y <= x + 1;
sub_i: entity work.sub;
end architecture;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:21)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_asap_entity;
ARCHITECTURE arf_asap_description OF arf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
WHEN "00000010" =>
register1 := register4 + register1;
register2 := register2 + register8;
register3 := register6 + register3;
register4 := register7 + register5;
WHEN "00000011" =>
register1 := register1 + 10;
register3 := register3 + 12;
WHEN "00000100" =>
register5 := register1 * 14;
register1 := register1 * 16;
register6 := register3 * 18;
register3 := register3 * 20;
WHEN "00000101" =>
register5 := register6 + register5;
register1 := register3 + register1;
WHEN "00000110" =>
register3 := register5 * 22;
register5 := register5 * 24;
register6 := register1 * 26;
register1 := register1 * 28;
WHEN "00000111" =>
register3 := register3 + register6;
register1 := register5 + register1;
WHEN "00001000" =>
output1 <= register4 + register3;
output2 <= register2 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_asap_description; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := ahbsi.hwdata(31 downto 24);
when "01" => v.hwdata := ahbsi.hwdata(23 downto 16);
when "10" => v.hwdata := ahbsi.hwdata(15 downto 8);
when others => v.hwdata := ahbsi.hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= dataout & dataout & dataout & dataout;
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to ncores-1 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i));
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0'); irqo(i) <= '1';
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := ahbsi.hwdata(31 downto 24);
when "01" => v.hwdata := ahbsi.hwdata(23 downto 16);
when "10" => v.hwdata := ahbsi.hwdata(15 downto 8);
when others => v.hwdata := ahbsi.hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= dataout & dataout & dataout & dataout;
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to ncores-1 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i));
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0'); irqo(i) <= '1';
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
-- Company: vienna university of technology
-- Engineer: mario faschang
-- Create Date: 11:12:56 19/01/2010
-- Module Name: tb_ClkGen
-- Project Name: i2c master controller
-- Description: * testbench for the variable Clock-Generator
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
ENTITY tb_ClkDiv IS
END tb_ClkDiv;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where an overlapping slices of next signal are set conditionally
--
ENTITY AssignToASliceOfReg2b IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg2b IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_11downto8 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_15downto12 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_3downto0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_7downto4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto12 & r_next_11downto8 & r_next_7downto4 & r_next_3downto0;
assig_process_r_next_11downto8: PROCESS(data_in_addr, data_in_data, data_in_mask, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "1" THEN
IF data_in_mask = X"FF" THEN
r_next_11downto8 <= data_in_data(3 DOWNTO 0);
r_next_15downto12 <= data_in_data(7 DOWNTO 4);
ELSIF data_in_mask = X"0F" THEN
r_next_15downto12 <= data_in_data(3 DOWNTO 0);
r_next_11downto8 <= r(11 DOWNTO 8);
ELSE
r_next_11downto8 <= r(11 DOWNTO 8);
r_next_15downto12 <= r(15 DOWNTO 12);
END IF;
ELSE
r_next_11downto8 <= r(11 DOWNTO 8);
r_next_15downto12 <= r(15 DOWNTO 12);
END IF;
END PROCESS;
assig_process_r_next_3downto0: PROCESS(data_in_addr, data_in_data, data_in_mask, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "0" THEN
IF data_in_mask = X"FF" THEN
r_next_3downto0 <= data_in_data(3 DOWNTO 0);
r_next_7downto4 <= data_in_data(7 DOWNTO 4);
ELSIF data_in_mask = X"0F" THEN
r_next_7downto4 <= data_in_data(3 DOWNTO 0);
r_next_3downto0 <= r(3 DOWNTO 0);
ELSE
r_next_3downto0 <= r(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
END IF;
ELSE
r_next_3downto0 <= r(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
END IF;
END PROCESS;
END ARCHITECTURE;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY system_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_processing_system7_0_100M_0;
ARCHITECTURE system_rst_processing_system7_0_100M_0_arch OF system_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_processing_system7_0_100M_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity srg4 is
Port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end srg4;
architecture Behavioral of srg4 is
signal reg: STD_LOGIC_VECTOR(3 downto 0);
begin
process (CLK, reset)
begin
if RESET='1' then --asynchronous RESET active High
reg <= "0000";
elsif CLK'event and CLK='1' then
REG <= DIN & REG( 3 downto 1 );
end if;
end process;
DOUT <= REG(0);
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_LOGIC is
generic (N: integer := 8);
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic);
end entity FIFO_LOGIC;
architecture RTL of FIFO_LOGIC is
signal WPTR, RPTR: std_logic_vector(N-1 downto 0);
signal LASTOP: std_logic;
begin
SYNC: process (CLK) begin
if (CLK'event and CLK = '1') then
if (INIT = '1') then -- initialization --
WPTR <= (others => '0');
RPTR <= (others => '0');
LASTOP <= '0';
elsif (POP = '1' and empty = '0') then -- pop --
RPTR <= RPTR + 1;
LASTOP <= '0';
elsif (PUSH = '1' and FULL = '0') then -- push --
WPTR <= WPTR + 1;
LASTOP <= '1';
end if; -- otherwise all Fs hold their value --
end if;
end process SYNC;
COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY)
begin
-- full and empty flags --
if (RPTR = WPTR) then
if (LASTOP = '1') then
FULL <= '1';
empty <= '0';
else
FULL <= '0';
empty <= '1';
end if;
else
FULL <= '0';
empty <= '0';
end if;
-- address, write enable and nopush/nopop logic --
if (POP = '0' and PUSH = '0') then -- no operation --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '0';
NOPOP <= '0';
elsif (POP = '0' and PUSH = '1') then -- push only --
ADD <= WPTR;
NOPOP <= '0';
if (FULL = '0') then -- valid write condition --
WE <= '1';
NOPUSH <= '0';
else -- no write condition --
WE <= '0';
NOPUSH <= '1';
end if;
elsif (POP = '1' and PUSH = '0') then -- pop only --
ADD <= RPTR;
NOPUSH <= '0';
WE <= '0';
if (empty = '0') then
-- valid read condition --
NOPOP <= '0';
else
NOPOP <= '1'; -- no red condition --
end if;
else -- push and pop at same time \u2013
if (empty = '0') then -- valid pop --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '1';
NOPOP <= '0';
else
ADD <= wptr;
WE <= '1';
NOPUSH <= '0';
NOPOP <= '1';
end if;
end if;
end process COMB;
end architecture RTL; |
-------------------------------------------------------------------------------------
-- FILE NAME :
-- AUTHOR : Luis
-- COMPANY :
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- SPI controller for the Texas Instruments AMC7823 analog monitoring and control circuit
--
-- 1-bit R/W, 15-bit Address field, 16-bit Data
-- Clocked in MSB first (R/W), and LSB (D0) last
-- Serial data is clocked in on the rising edge of SCK
--
----------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";--x"0005400";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"--x"00073FF"
);
port (
rst : in std_logic;
clk : in std_logic; --serial clock
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
-- Spi interface
trig_n_cs : out std_logic;
trig_sclk : out std_logic;
trig_sdo : out std_logic;
trig_clksel0 : in std_logic
);
end amc7823_ctrl;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioural of amc7823_ctrl is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0001FFF";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0001FFF";
attribute keep : string;
type sh_states is (idle, instruct, data_wait, data_io, data_valid, update, update_instruct, update_data_io);
constant TOTAL_BITS : natural := 32;
constant ADDR_BITS : natural := 15;
constant DATA_BITS : natural := 16;
constant WR_BIT : std_logic := '0'; -- 0 means write
constant RD_BIT : std_logic := '1'; -- 1 means read
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal sh_state : sh_states;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal sclk_prebuf : std_logic;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal trig_sdi : std_logic;
signal trig_sdi_in : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(ADDR_BITS-1 downto 0); --IMPORTANT
signal data_reg : std_logic_vector(DATA_BITS-1 downto 0); -- IMPORTANT
signal shifting : std_logic;
signal shift_reg : std_logic_vector(TOTAL_BITS-1 downto 0); -- IMPORTANT
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_write_val : std_logic;
signal data_read : std_logic_vector(DATA_BITS-1 downto 0);
signal sh_counter : integer;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal ncs_trig : std_logic;
signal busy : std_logic;
--signal ncs_int_w : std_logic;
signal out_mailbox_data_sig : std_logic_vector(31 downto 0);
--------------------------------------------------------------------------------
--debug signals
--------------------------------------------------------------------------------
signal probe0 : std_logic_vector(127 downto 0);
--attribute keep of trig_clksel0 : signal is "true";
--attribute keep of inst_val : signal is "true";
--attribute keep of inst_rw : signal is "true";
--attribute keep of inst_reg : signal is "true";
--attribute keep of data_reg : signal is "true";
signal out_cmd_t :std_logic_vector(63 downto 0);
signal out_cmd_val_t :std_logic;
attribute keep of data_read_val : signal is "true";
attribute keep of data_read : signal is "true";
attribute keep of out_cmd_t : signal is "true";
attribute keep of out_cmd_val_t : signal is "true";
--*****************************************************************************************************
begin
--*****************************************************************************************************
--ila_inst0: entity work.ila_0
--PORT MAP (
-- clk => clk_cmd,
-- probe0 => probe0
--);
--
--
--probe0(63 downto 0) <= out_cmd_t;
--probe0(64) <= out_cmd_val_t;
--probe0(72 downto 65) <= data_read;
--probe0(73) <= data_read_val;
--probe0(127 downto 74) <= (others=>'0');
--probe0(0) <= '1';
--probe0(1) <= inst_val;
--probe0(2) <= inst_rw;
--probe0(15 downto 3) <= inst_reg(12 downto 0);
--probe0(23 downto 16) <= data_reg(7 downto 0);
--probe0(24) <= data_read_val;
----probe0(19 downto 12) <= data_read(7 downto 0);
--probe0(127 downto 25) <= (others=>'0');
--probe0(23 downto 0) <= shift_reg(23 downto 0);
--probe0(24) <= inst_reg_val;
--probe0(25) <= shifting;
--probe0(26) <= read_n_write;
--probe0(27) <= clk;
--probe0(28) <= ncs_int;
--probe0(29) <= trig_sdi_in;
--
--probe0(30) <= inst_val;
--probe0(31) <= inst_rw;
--probe0(44 downto 32) <= inst_reg(12 downto 0);
--probe0(52 downto 45) <= data_reg(7 downto 0);
--probe0(53) <= sdo_0;
--probe0(54) <= data_read_val;
--probe0(62 downto 55) <= data_read;
--probe0(127 downto 63) <= (others=>'0');
--
-- -- Intruction pulse
-- pulse2pulse_inst1120 : pulse2pulse
-- port map
-- (
-- rst => rst,
-- in_clk => serial_clk, --LM clk
-- out_clk => clk_cmd,
-- pulsein => shift_reg(shift_reg'length - 1),
-- pulseout => sdo_0,
-- inbusy => open
-- );
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 25MHz)
----------------------------------------------------------------------------------------------------
--process (clk)
-- -- Divide by 2^4 = 16, CLKmax = 16 x 25MHz = 400MHz
-- variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
--begin
-- if (rising_edge(clk)) then
-- clk_div := clk_div + '1';
-- -- The slave samples the data on the rising edge of SCLK.
-- -- therefore we make sure the external clock is slightly
-- -- after the internal clock.
-- sclk_ext <= clk_div(clk_div'length-1);
-- sclk_prebuf <= sclk_ext;
-- end if;
--end process;
--bufg_sclk : bufg
--port map (
-- i => sclk_prebuf,
-- o => serial_clk
--);
serial_clk <= clk;
sclk_ext <= serial_clk;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc408_stellar_cmd_inst : entity work.fmc408_stellar_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd, --LM clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_out_reg => out_mailbox_data_sig,
mbx_out_val => open,
mbx_in_reg => (others=>'0'),
mbx_in_val => '0'
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd) --LM clk
begin
if (rst = '1') then
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
--data_read <= (others=> '0');
elsif (rising_edge(clk_cmd)) then -- LM clk
if (in_reg_addr <= ADDR_MAX_RD) then --(in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
-- read from serial if when address is within device range
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 32-DATA_BITS) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= WR_BIT; -- write
inst_reg <= out_reg_addr(ADDR_BITS-1 downto 0);
data_reg <= out_reg(DATA_BITS-1 downto 0);
-- Read instruction, only when address is within LMK04828 range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= RD_BIT; -- read
inst_reg <= in_reg_addr(ADDR_BITS-1 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
sh_state <= idle;
sh_counter <= 0;
read_n_write <= '0';
--ncs_int_r <= '1';
--ncs_int_w <= '1';
ncs_int <= '1';
shifting <= '0';
elsif (rising_edge(serial_clk)) then
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1') then
shifting <= '1';
read_n_write <= inst_rw; -- 0 = write, 1 = read
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid; -- read
else
sh_state <= data_wait; -- write
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid => -- read
sh_state <= idle;
when data_wait => -- write
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle) else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (inst_reg_val = '1' and read_n_write = '0') then -- write
shift_reg <= inst_rw & inst_reg & data_reg;
elsif (inst_reg_val = '1' and read_n_write = '1') then -- read
shift_reg <= inst_rw & inst_reg & data_reg;
end if;
if (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length-2 downto 0) & trig_sdi_in;
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(DATA_BITS-1 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map (
rst => rst,
in_clk => serial_clk,
out_clk => clk_cmd, -- LM clk
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map (
rst => rst,
in_clk => clk_cmd, --LM clk
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
trig_sdi_in <= trig_clksel0;
end if;
end process;
--------------------------------------------------------------------------------
-- Outputs
--------------------------------------------------------------------------------
--spi_io_t <= '1' when (sh_state = data_io and read_n_write = '1') else '0'; -- 0 = output, 1 = input
trig_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);--shift_reg(shift_reg'length - 1) when ncs_int = '0' else 'Z';
trig_n_cs <= ncs_int;
trig_sclk <= not sclk_ext when ncs_int = '0' else '0';
-- ncs_trig <= ncs_int when read_n_write = '0' else ncs_int_w;
--------------------------------------------------------------------------------
-- Output buffer
--------------------------------------------------------------------------------
--iobuf_trig : iobuf
--port map (
-- I => data_write_val,
-- O => trig_sdi,
-- IO => trig_sdo,
-- T => ncs_trig
--);
--********************************************************************************
end Behavioural;
--********************************************************************************
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc455.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00455ent IS
END c03s02b01x01p19n01i00455ent;
ARCHITECTURE c03s02b01x01p19n01i00455arch OF c03s02b01x01p19n01i00455ent IS
subtype word is bit_vector(0 to 15);
constant C77 : word := (others => '0');
function complex_scalar(s : word) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return word is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : word;
signal S2 : word;
signal S3 : word := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00455"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00455 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00455arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc455.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00455ent IS
END c03s02b01x01p19n01i00455ent;
ARCHITECTURE c03s02b01x01p19n01i00455arch OF c03s02b01x01p19n01i00455ent IS
subtype word is bit_vector(0 to 15);
constant C77 : word := (others => '0');
function complex_scalar(s : word) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return word is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : word;
signal S2 : word;
signal S3 : word := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00455"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00455 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00455arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc455.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00455ent IS
END c03s02b01x01p19n01i00455ent;
ARCHITECTURE c03s02b01x01p19n01i00455arch OF c03s02b01x01p19n01i00455ent IS
subtype word is bit_vector(0 to 15);
constant C77 : word := (others => '0');
function complex_scalar(s : word) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return word is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : word;
signal S2 : word;
signal S3 : word := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00455"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00455 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00455arch;
|
architecture rtl of fifo is
begin
end architecture rtl;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s208_jed is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s208_jed;
architecture behaviour of s208_jed is
constant s11111111: std_logic_vector(4 downto 0) := "11001";
constant s00000000: std_logic_vector(4 downto 0) := "00011";
constant s00010000: std_logic_vector(4 downto 0) := "00111";
constant s00100000: std_logic_vector(4 downto 0) := "01011";
constant s00110000: std_logic_vector(4 downto 0) := "01111";
constant s01000000: std_logic_vector(4 downto 0) := "10011";
constant s01010000: std_logic_vector(4 downto 0) := "10010";
constant s01100000: std_logic_vector(4 downto 0) := "01001";
constant s01110000: std_logic_vector(4 downto 0) := "00110";
constant s10000000: std_logic_vector(4 downto 0) := "00000";
constant s10010000: std_logic_vector(4 downto 0) := "11011";
constant s10100000: std_logic_vector(4 downto 0) := "00010";
constant s10110000: std_logic_vector(4 downto 0) := "01010";
constant s11000000: std_logic_vector(4 downto 0) := "00101";
constant s11010000: std_logic_vector(4 downto 0) := "10111";
constant s11100000: std_logic_vector(4 downto 0) := "10001";
constant s11110000: std_logic_vector(4 downto 0) := "00100";
constant s00000001: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s11111111 =>
if std_match(input, "0--------01") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------01") then next_state <= s00000000; output <= "11";
elsif std_match(input, "0--------11") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------11") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------10") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------00") then next_state <= s00000000; output <= "10";
elsif std_match(input, "0---------0") then next_state <= s00000000; output <= "10";
end if;
when s00000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10--------0") then next_state <= s00010000; output <= "00";
end if;
when s00010000 =>
if std_match(input, "10-------00") then next_state <= s00100000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s00100000; output <= "01";
elsif std_match(input, "10-------1-") then next_state <= s00100000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
end if;
when s00100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s00110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s00110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s00110000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s00110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s01000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01000000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s01000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-----1--0") then next_state <= s01010000; output <= "01";
elsif std_match(input, "10-----0--0") then next_state <= s01010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01010000; output <= "01";
end if;
when s01010000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s01100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01100000; output <= "01";
end if;
when s01100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1-0") then next_state <= s01110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s01110000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01110000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s01110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s10000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10----0---0") then next_state <= s10010000; output <= "00";
elsif std_match(input, "10----1---0") then next_state <= s10010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s10010000; output <= "01";
elsif std_match(input, "11----1---0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11----0---0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s10010000 =>
if std_match(input, "10--------1") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10100000; output <= "00";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s10100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s10110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s10110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s10110000; output <= "01";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when s10110000 =>
if std_match(input, "10--------1") then next_state <= s11000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11000000; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s11000000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s11000000 =>
if std_match(input, "10-----0--0") then next_state <= s11010000; output <= "00";
elsif std_match(input, "10-----1--0") then next_state <= s11010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s11010000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s11010000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s11100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s11100000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01--------1") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s11100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10------1--") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-1") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s11110000; output <= "00";
end if;
when s11110000 =>
if std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------01") then next_state <= s00000001; output <= "00";
elsif std_match(input, "-0-------00") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------11") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------11") then next_state <= s00000001; output <= "00";
elsif std_match(input, "00-------10") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s00000001; output <= "01";
end if;
when s00000001 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10---1----0") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10---0----0") then next_state <= s00010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "11---0----0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11---1----0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
entity PIPO4_tb is
end PIPO4_tb;
architecture tb of PIPO4_tb is
component PIPO4
port (Rin : in STD_LOGIC_VECTOR (3 downto 0);
CLK, preset, clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal Rin: std_logic_vector(3 downto 0);
signal CLK,Preset,Clear : std_logic := '1';
signal Rout: std_logic_vector(3 downto 0);
begin
mapping: PIPO4 port map(Rin,CLK,Preset,Clear,Rout);
process
begin
Rin(3) <= '0'; wait for 16 ps;
Rin(3) <= '1'; wait for 16 ps;
end process;
process
begin
Rin(2) <= '0'; wait for 8 ps;
Rin(2) <= '1'; wait for 8 ps;
end process;
process
begin
Rin(1) <= '0'; wait for 4 ps;
Rin(1) <= '1'; wait for 4 ps;
end process;
process
begin
Rin(0) <= '0'; wait for 2 ps;
Rin(0) <= '1'; wait for 2 ps;
end process;
process
begin
CLK <= '0'; wait for 1 ps;
CLK <= '1'; wait for 1 ps;
end process;
end tb;
configuration cfg_tb of PIPO4_tb is
for tb
end for;
end cfg_tb; |
--**********************************************************************************************
-- Timers/Counters Block Peripheral for the AVR Core
-- Version 1.37? (Special version for the JTAG OCD)
-- Modified 11.06.2004
-- Synchronizer for EXT1/EXT2 inputs was added
-- Designed by Ruslan Lepetenok
-- Note : Only T/C0 and T/C2 are implemented
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end Timer_Counter;
architecture RTL of Timer_Counter is
-- Copies of the external signals
signal OC0_PWM0_Int : std_logic;
signal OC2_PWM2_Int : std_logic;
-- Registers
signal TCCR0 : std_logic_vector(7 downto 0);
signal TCCR1A : std_logic_vector(7 downto 0);
signal TCCR1B : std_logic_vector(7 downto 0);
signal TCCR2 : std_logic_vector(7 downto 0);
signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0)
signal TIMSK : std_logic_vector(7 downto 0);
signal TIFR : std_logic_vector(7 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal TCNT2 : std_logic_vector(7 downto 0);
signal OCR0 : std_logic_vector(7 downto 0);
signal OCR2 : std_logic_vector(7 downto 0);
signal TCNT1H : std_logic_vector(7 downto 0);
signal TCNT1L : std_logic_vector(7 downto 0);
signal OCR1AH : std_logic_vector(7 downto 0);
signal OCR1AL : std_logic_vector(7 downto 0);
signal OCR1BH : std_logic_vector(7 downto 0);
signal OCR1BL : std_logic_vector(7 downto 0);
signal ICR1AH : std_logic_vector(7 downto 0);
signal ICR1AL : std_logic_vector(7 downto 0);
-- TCCR0 Bits
alias CS00 : std_logic is TCCR0(0);
alias CS01 : std_logic is TCCR0(1);
alias CS02 : std_logic is TCCR0(2);
alias CTC0 : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0 : std_logic is TCCR0(6);
-- TCCR1A Bits
alias PWM10 : std_logic is TCCR1A(0);
alias PWM11 : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);
-- TCCR1B Bits
alias CS10 : std_logic is TCCR1A(0);
alias CS11 : std_logic is TCCR1A(1);
alias CS12 : std_logic is TCCR1A(2);
alias CTC1 : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);
-- TCCR2 Bits
alias CS20 : std_logic is TCCR2(0);
alias CS21 : std_logic is TCCR2(1);
alias CS22 : std_logic is TCCR2(2);
alias CTC2 : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2 : std_logic is TCCR2(6);
-- ASSR bits
alias TCR0UB : std_logic is ASSR(0);
alias OCR0UB : std_logic is ASSR(1);
alias TCN0UB : std_logic is ASSR(2);
alias AS0 : std_logic is ASSR(3);
-- TIMSK bits
alias TOIE0 : std_logic is TIMSK(0);
alias OCIE0 : std_logic is TIMSK(1);
alias TOIE1 : std_logic is TIMSK(2);
alias OCIE1B : std_logic is TIMSK(3);
alias OCIE1A : std_logic is TIMSK(4);
alias TICIE1 : std_logic is TIMSK(5);
alias TOIE2 : std_logic is TIMSK(6);
alias OCIE2 : std_logic is TIMSK(7);
-- TIFR bits
alias TOV0 : std_logic is TIFR(0);
alias OCF0 : std_logic is TIFR(1);
alias TOV1 : std_logic is TIFR(2);
alias OCF1B : std_logic is TIFR(3);
alias OCF1A : std_logic is TIFR(4);
alias ICF1 : std_logic is TIFR(5);
alias TOV2 : std_logic is TIFR(6);
alias OCF2 : std_logic is TIFR(7);
-- Prescaler1 signals
signal CK8 : std_logic;
signal CK64 : std_logic;
signal CK256 : std_logic;
signal CK1024 : std_logic;
signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit)
signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only)
signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only)
signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only)
-- Risign/falling edge detectors
signal EXT1Latched : std_logic;
signal EXT2Latched : std_logic;
-- Prescalers outputs
signal TCNT0_En : std_logic; -- Output of the prescaler 0
signal TCNT1_En : std_logic; -- Output of the prescaler 1
signal TCNT2_En : std_logic; -- Output of the prescaler 1
-- Prescaler0 signals
signal PCK08 : std_logic;
signal PCK032 : std_logic;
signal PCK064 : std_logic;
signal PCK0128 : std_logic;
signal PCK0256 : std_logic;
signal PCK01024 : std_logic;
signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit)
-- Synchronizer signals
signal EXT1SA : std_logic;
signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1
signal EXT2SA : std_logic;
signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1
-- Temporary registers
signal OCR0_Tmp : std_logic_vector(OCR0'range);
signal OCR2_Tmp : std_logic_vector(OCR2'range);
-- Counters control(Inc/Dec)
signal Cnt0Dir : std_logic;
signal Cnt2Dir : std_logic;
--
signal TCNT0WrFl : std_logic;
signal TCNT0CmpBl : std_logic;
signal TCNT2WrFl : std_logic;
signal TCNT2CmpBl : std_logic;
begin
-- Synchronizers
SyncDFFs:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
EXT1SA <= '0';
EXT1SB <= '0';
EXT2SA <= '0';
EXT2SB <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
EXT1SA <= EXT1;
EXT1SB <= EXT1SA;
EXT2SA <= EXT2;
EXT2SB <= EXT2SA;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------------------
-- Prescalers
-- -------------------------------------------------------------------------------------------
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Pre1Cnt <= (others => '0');
CK8 <= '0';
CK64 <= '0';
CK256 <= '0';
CK1024 <= '0';
EXT1RE <= '0';
EXT1FE <= '0';
EXT2RE <= '0';
EXT2FE <= '0';
EXT1Latched <= '0';
EXT2Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
Pre1Cnt <= Pre1Cnt+1;
CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched);
EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched);
EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched);
EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched);
EXT1Latched <= EXT1SB;
EXT2Latched <= EXT2SB;
end if;
end if;
end process;
TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001"
(CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010"
(CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011"
(CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100"
(CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101"
(EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110"
(EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111"
TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001"
(CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010"
(CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011"
(CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100"
(CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101"
(EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110"
(EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111"
Prescaler_0_Cnt:process(cp2,ireset)
begin
if(ireset='0') then -- Reset
Pre0Cnt <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
Pre0Cnt <= Pre0Cnt+1;
end if;
end if;
end process;
Prescaler_0:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PCK08 <= '0';
PCK032 <= '0';
PCK064 <= '0';
PCK0128 <= '0';
PCK0256 <= '0';
PCK01024 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2)));
PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4)));
PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5)));
PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6)));
PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7)));
PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9)));
end if;
end if;
end process;
TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001"
(PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010"
(PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011"
(PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100"
(PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101"
(PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110"
(PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111"
-- -------------------------------------------------------------------------------------------
-- End of prescalers
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 0
-- -------------------------------------------------------------------------------------------
TimerCounter0Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0
TCNT0 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM0 is
when '0' => -- Non-PWM mode
if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match
TCNT0 <= (others => '0');
elsif(TCNT0_En='1') then
TCNT0 <= TCNT0 + 1; -- Increment TCNT0
end if;
when '1' => -- PWM mode
if(TCNT0_En='1') then
case Cnt0Dir is
when '0' => -- Counts up
if(TCNT0=x"FF") then
TCNT0<=x"FE";
else
TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT0=x"00") then
TCNT0 <= x"01";
else
TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt0DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt0Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
if (PWM0='1') then
case Cnt0Dir is
when '0' =>
if(TCNT0=x"FF") then
Cnt0Dir <= '1';
end if;
when '1' =>
if(TCNT0=x"00") then
Cnt0Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt0OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
case PWM0 is
when '0' => -- Non PWM Mode
if(TCNT0=OCR0 and TCNT0CmpBl='0') then
if(COM01='0' and COM00='1') then -- Toggle
OC0_PWM0_Int <= not OC0_PWM0_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR0(5 downto 4) is -- -> COM01&COM00
when "10" => -- Non-inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '0'; -- Clear
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '1'; -- Set
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '0'; -- Clear
else -- Down-counting
OC0_PWM0_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '1'; -- Set
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '0'; -- Clear
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '1'; -- Set
else -- Down-counting
OC0_PWM0_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC0_PWM0 <= OC0_PWM0_Int;
TCnt0_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV0 <= '0';
OCF0 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV0 <= dbus_in(0); -- !!!
end if;
else
case TOV0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (PWM0='0') then -- Non PWM Mode
if (TCNT0=x"FF") then
TOV0 <= '1';
end if;
else -- PWM Mode
if(TCNT0=x"00") then
TOV0 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag
TOV0 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF0 <= dbus_in(1); -- !!!
end if;
else
case OCF0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (TCNT0=OCR0 and TCNT0CmpBl='0') then
OCF0 <= '1';
end if;
end if;
when '1' =>
if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF0 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR0(7) <= '0';
TCCR0_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR0(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR0_Address and iowe='1') then
TCCR0(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR0_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM0 is
when '0' => -- Non-PWM mode
if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR0 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register
OCR0 <= OCR0_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR0_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus
OCR0_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT0WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT0WrFl is
when '0' =>
if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus
TCNT0WrFl <= '1';
end if;
when '1' =>
if(TCNT0_En='0') then
TCNT0WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF0 and Toggling) disabled for TCNT0
TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 2
-- -------------------------------------------------------------------------------------------
TimerCounter2Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2
TCNT2 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM2 is
when '0' => -- Non-PWM mode
if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match
TCNT2 <= (others => '0');
elsif(TCNT2_En='1') then
TCNT2 <= TCNT2 + 1; -- Increment TCNT2
end if;
when '1' => -- PWM mode
if(TCNT2_En='1') then
case Cnt2Dir is
when '0' => -- Counts up
if(TCNT2=x"FF") then
TCNT2 <= x"FE";
else
TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT2=x"00") then
TCNT2 <= x"01";
else
TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt2DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt2Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
if (PWM2='1') then
case Cnt2Dir is
when '0' =>
if(TCNT2=x"FF") then
Cnt2Dir <= '1';
end if;
when '1' =>
if(TCNT2=x"00") then
Cnt2Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt2OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC2_PWM2_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
case PWM2 is
when '0' => -- Non PWM Mode
if(TCNT2=OCR2 and TCNT2CmpBl='0') then
if(COM21='0' and COM20='1') then -- Toggle
OC2_PWM2_Int <= not OC2_PWM2_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR2(5 downto 4) is -- -> COM21&COM20
when "10" => -- Non-inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '0'; -- Clear
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '1'; -- Set
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '0'; -- Clear
else -- Down-counting
OC2_PWM2_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '1'; -- Set
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '0'; -- Clear
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '1'; -- Set
else -- Down-counting
OC2_PWM2_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC2_PWM2 <= OC2_PWM2_Int;
TCnt2_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV2 <= '0';
OCF2 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV2 <= dbus_in(6); -- !!!
end if;
else
case TOV2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (PWM2='0') then -- Non PWM Mode
if (TCNT2=x"FF") then
TOV2 <= '1';
end if;
else -- PWM Mode
if(TCNT2=x"00") then
TOV2 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag
TOV2 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF2 <= dbus_in(7); -- !!!
end if;
else
case OCF2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (TCNT2=OCR2 and TCNT2CmpBl='0') then
OCF2 <= '1';
end if;
end if;
when '1' =>
if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF2 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR2(7) <= '0';
TCCR2_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR2(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR2_Address and iowe='1') then
TCCR2(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR2_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM2 is
when '0' => -- Non-PWM mode
if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR2 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register
OCR2 <= OCR2_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR2_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus
OCR2_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT2WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT2WrFl is
when '0' =>
if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus
TCNT2WrFl <= '1';
end if;
when '1' =>
if(TCNT2_En='0') then
TCNT2WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF2 and Toggling) disabled for TCNT2
TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
TIMSK_Bits:process(cp2,ireset)
begin
if (ireset='0') then
TIMSK <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock Enable
if (adr=TIMSK_Address and iowe='1') then
TIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Interrupt flags of Timer/Counter0
TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0
TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0
-- Interrupt flags of Timer/Counter0
TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2
TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2
-- Unused interrupt requests(for T/C1)
TC1OvfIRQ <= TOV1 and TOIE1;
TC1CmpAIRQ <= OCF1A and OCIE1A;
TC1CmpBIRQ <= OCF1B and OCIE1B;
TC1ICIRQ <= ICF1 and TICIE1;
-- Unused TIFR flags(for T/C1)
TOV1 <= '0';
OCF1A <= '0';
OCF1B <= '0';
ICF1 <= '0';
-- -------------------------------------------------------------------------------------------
-- End of common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Bus interface
-- -------------------------------------------------------------------------------------------
out_en <= '1' when ((adr=TCCR0_Address or
adr=TCCR1A_Address or
adr=TCCR1B_Address or
adr=TCCR2_Address or
adr=ASSR_Address or
adr=TIMSK_Address or
adr=TIFR_Address or
adr=TCNT0_Address or
adr=TCNT2_Address or
adr=OCR0_Address or
adr=OCR2_Address or
adr=TCNT1H_Address or
adr=TCNT1L_Address or
adr=OCR1AH_Address or
adr=OCR1AL_Address or
adr=OCR1BH_Address or
adr=OCR1BL_Address or
adr=ICR1AH_Address or
adr=ICR1AL_Address) and iore='1') else '0';
-- Output multilexer
--Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial
--begin
-- case adr is
-- when TCCR0_Address => dbus_out <= TCCR0;
-- when OCR0_Address =>
-- if (PWM0='0') then
-- dbus_out <= OCR0;
-- else
-- dbus_out <= OCR0_Tmp;
-- end if;
-- when TCNT0_Address => dbus_out <= TCNT0;
-- when TCCR2_Address => dbus_out <= TCCR2;
-- when OCR2_Address =>
-- if (PWM2='0') then
-- dbus_out <= OCR2;
-- else
-- dbus_out <= OCR2_Tmp;
-- end if;
-- when TCNT2_Address => dbus_out <= TCNT2;
-- when TIFR_Address => dbus_out <= TIFR;
-- when TIMSK_Address => dbus_out <= TIMSK;
-- when others => dbus_out <= (others => '0');
-- end case;
--end process;
PWM0bit <= PWM0;
PWM10bit <= PWM10;
PWM11bit <= PWM11;
PWM2bit <= PWM2;
-- Synopsys version
dbus_out <= TCCR0 when (adr=TCCR0_Address) else
OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0
OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0
TCNT0 when (adr=TCNT0_Address) else
TCCR2 when (adr=TCCR2_Address) else
OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2
OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2
TCNT2 when (adr=TCNT2_Address) else
TIFR when (adr=TIFR_Address) else
TIMSK when (adr=TIMSK_Address) else
(others => '0');
-- -------------------------------------------------------------------------------------------
-- End of bus interface
-- -------------------------------------------------------------------------------------------
end RTL;
|
--**********************************************************************************************
-- Timers/Counters Block Peripheral for the AVR Core
-- Version 1.37? (Special version for the JTAG OCD)
-- Modified 11.06.2004
-- Synchronizer for EXT1/EXT2 inputs was added
-- Designed by Ruslan Lepetenok
-- Note : Only T/C0 and T/C2 are implemented
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end Timer_Counter;
architecture RTL of Timer_Counter is
-- Copies of the external signals
signal OC0_PWM0_Int : std_logic;
signal OC2_PWM2_Int : std_logic;
-- Registers
signal TCCR0 : std_logic_vector(7 downto 0);
signal TCCR1A : std_logic_vector(7 downto 0);
signal TCCR1B : std_logic_vector(7 downto 0);
signal TCCR2 : std_logic_vector(7 downto 0);
signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0)
signal TIMSK : std_logic_vector(7 downto 0);
signal TIFR : std_logic_vector(7 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal TCNT2 : std_logic_vector(7 downto 0);
signal OCR0 : std_logic_vector(7 downto 0);
signal OCR2 : std_logic_vector(7 downto 0);
signal TCNT1H : std_logic_vector(7 downto 0);
signal TCNT1L : std_logic_vector(7 downto 0);
signal OCR1AH : std_logic_vector(7 downto 0);
signal OCR1AL : std_logic_vector(7 downto 0);
signal OCR1BH : std_logic_vector(7 downto 0);
signal OCR1BL : std_logic_vector(7 downto 0);
signal ICR1AH : std_logic_vector(7 downto 0);
signal ICR1AL : std_logic_vector(7 downto 0);
-- TCCR0 Bits
alias CS00 : std_logic is TCCR0(0);
alias CS01 : std_logic is TCCR0(1);
alias CS02 : std_logic is TCCR0(2);
alias CTC0 : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0 : std_logic is TCCR0(6);
-- TCCR1A Bits
alias PWM10 : std_logic is TCCR1A(0);
alias PWM11 : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);
-- TCCR1B Bits
alias CS10 : std_logic is TCCR1A(0);
alias CS11 : std_logic is TCCR1A(1);
alias CS12 : std_logic is TCCR1A(2);
alias CTC1 : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);
-- TCCR2 Bits
alias CS20 : std_logic is TCCR2(0);
alias CS21 : std_logic is TCCR2(1);
alias CS22 : std_logic is TCCR2(2);
alias CTC2 : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2 : std_logic is TCCR2(6);
-- ASSR bits
alias TCR0UB : std_logic is ASSR(0);
alias OCR0UB : std_logic is ASSR(1);
alias TCN0UB : std_logic is ASSR(2);
alias AS0 : std_logic is ASSR(3);
-- TIMSK bits
alias TOIE0 : std_logic is TIMSK(0);
alias OCIE0 : std_logic is TIMSK(1);
alias TOIE1 : std_logic is TIMSK(2);
alias OCIE1B : std_logic is TIMSK(3);
alias OCIE1A : std_logic is TIMSK(4);
alias TICIE1 : std_logic is TIMSK(5);
alias TOIE2 : std_logic is TIMSK(6);
alias OCIE2 : std_logic is TIMSK(7);
-- TIFR bits
alias TOV0 : std_logic is TIFR(0);
alias OCF0 : std_logic is TIFR(1);
alias TOV1 : std_logic is TIFR(2);
alias OCF1B : std_logic is TIFR(3);
alias OCF1A : std_logic is TIFR(4);
alias ICF1 : std_logic is TIFR(5);
alias TOV2 : std_logic is TIFR(6);
alias OCF2 : std_logic is TIFR(7);
-- Prescaler1 signals
signal CK8 : std_logic;
signal CK64 : std_logic;
signal CK256 : std_logic;
signal CK1024 : std_logic;
signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit)
signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only)
signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only)
signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only)
-- Risign/falling edge detectors
signal EXT1Latched : std_logic;
signal EXT2Latched : std_logic;
-- Prescalers outputs
signal TCNT0_En : std_logic; -- Output of the prescaler 0
signal TCNT1_En : std_logic; -- Output of the prescaler 1
signal TCNT2_En : std_logic; -- Output of the prescaler 1
-- Prescaler0 signals
signal PCK08 : std_logic;
signal PCK032 : std_logic;
signal PCK064 : std_logic;
signal PCK0128 : std_logic;
signal PCK0256 : std_logic;
signal PCK01024 : std_logic;
signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit)
-- Synchronizer signals
signal EXT1SA : std_logic;
signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1
signal EXT2SA : std_logic;
signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1
-- Temporary registers
signal OCR0_Tmp : std_logic_vector(OCR0'range);
signal OCR2_Tmp : std_logic_vector(OCR2'range);
-- Counters control(Inc/Dec)
signal Cnt0Dir : std_logic;
signal Cnt2Dir : std_logic;
--
signal TCNT0WrFl : std_logic;
signal TCNT0CmpBl : std_logic;
signal TCNT2WrFl : std_logic;
signal TCNT2CmpBl : std_logic;
begin
-- Synchronizers
SyncDFFs:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
EXT1SA <= '0';
EXT1SB <= '0';
EXT2SA <= '0';
EXT2SB <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
EXT1SA <= EXT1;
EXT1SB <= EXT1SA;
EXT2SA <= EXT2;
EXT2SB <= EXT2SA;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------------------
-- Prescalers
-- -------------------------------------------------------------------------------------------
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Pre1Cnt <= (others => '0');
CK8 <= '0';
CK64 <= '0';
CK256 <= '0';
CK1024 <= '0';
EXT1RE <= '0';
EXT1FE <= '0';
EXT2RE <= '0';
EXT2FE <= '0';
EXT1Latched <= '0';
EXT2Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
Pre1Cnt <= Pre1Cnt+1;
CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched);
EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched);
EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched);
EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched);
EXT1Latched <= EXT1SB;
EXT2Latched <= EXT2SB;
end if;
end if;
end process;
TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001"
(CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010"
(CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011"
(CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100"
(CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101"
(EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110"
(EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111"
TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001"
(CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010"
(CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011"
(CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100"
(CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101"
(EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110"
(EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111"
Prescaler_0_Cnt:process(cp2,ireset)
begin
if(ireset='0') then -- Reset
Pre0Cnt <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
Pre0Cnt <= Pre0Cnt+1;
end if;
end if;
end process;
Prescaler_0:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PCK08 <= '0';
PCK032 <= '0';
PCK064 <= '0';
PCK0128 <= '0';
PCK0256 <= '0';
PCK01024 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2)));
PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4)));
PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5)));
PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6)));
PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7)));
PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9)));
end if;
end if;
end process;
TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001"
(PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010"
(PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011"
(PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100"
(PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101"
(PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110"
(PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111"
-- -------------------------------------------------------------------------------------------
-- End of prescalers
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 0
-- -------------------------------------------------------------------------------------------
TimerCounter0Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0
TCNT0 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM0 is
when '0' => -- Non-PWM mode
if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match
TCNT0 <= (others => '0');
elsif(TCNT0_En='1') then
TCNT0 <= TCNT0 + 1; -- Increment TCNT0
end if;
when '1' => -- PWM mode
if(TCNT0_En='1') then
case Cnt0Dir is
when '0' => -- Counts up
if(TCNT0=x"FF") then
TCNT0<=x"FE";
else
TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT0=x"00") then
TCNT0 <= x"01";
else
TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt0DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt0Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
if (PWM0='1') then
case Cnt0Dir is
when '0' =>
if(TCNT0=x"FF") then
Cnt0Dir <= '1';
end if;
when '1' =>
if(TCNT0=x"00") then
Cnt0Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt0OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
case PWM0 is
when '0' => -- Non PWM Mode
if(TCNT0=OCR0 and TCNT0CmpBl='0') then
if(COM01='0' and COM00='1') then -- Toggle
OC0_PWM0_Int <= not OC0_PWM0_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR0(5 downto 4) is -- -> COM01&COM00
when "10" => -- Non-inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '0'; -- Clear
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '1'; -- Set
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '0'; -- Clear
else -- Down-counting
OC0_PWM0_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '1'; -- Set
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '0'; -- Clear
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '1'; -- Set
else -- Down-counting
OC0_PWM0_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC0_PWM0 <= OC0_PWM0_Int;
TCnt0_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV0 <= '0';
OCF0 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV0 <= dbus_in(0); -- !!!
end if;
else
case TOV0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (PWM0='0') then -- Non PWM Mode
if (TCNT0=x"FF") then
TOV0 <= '1';
end if;
else -- PWM Mode
if(TCNT0=x"00") then
TOV0 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag
TOV0 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF0 <= dbus_in(1); -- !!!
end if;
else
case OCF0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (TCNT0=OCR0 and TCNT0CmpBl='0') then
OCF0 <= '1';
end if;
end if;
when '1' =>
if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF0 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR0(7) <= '0';
TCCR0_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR0(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR0_Address and iowe='1') then
TCCR0(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR0_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM0 is
when '0' => -- Non-PWM mode
if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR0 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register
OCR0 <= OCR0_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR0_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus
OCR0_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT0WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT0WrFl is
when '0' =>
if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus
TCNT0WrFl <= '1';
end if;
when '1' =>
if(TCNT0_En='0') then
TCNT0WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF0 and Toggling) disabled for TCNT0
TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 2
-- -------------------------------------------------------------------------------------------
TimerCounter2Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2
TCNT2 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM2 is
when '0' => -- Non-PWM mode
if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match
TCNT2 <= (others => '0');
elsif(TCNT2_En='1') then
TCNT2 <= TCNT2 + 1; -- Increment TCNT2
end if;
when '1' => -- PWM mode
if(TCNT2_En='1') then
case Cnt2Dir is
when '0' => -- Counts up
if(TCNT2=x"FF") then
TCNT2 <= x"FE";
else
TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT2=x"00") then
TCNT2 <= x"01";
else
TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt2DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt2Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
if (PWM2='1') then
case Cnt2Dir is
when '0' =>
if(TCNT2=x"FF") then
Cnt2Dir <= '1';
end if;
when '1' =>
if(TCNT2=x"00") then
Cnt2Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt2OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC2_PWM2_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
case PWM2 is
when '0' => -- Non PWM Mode
if(TCNT2=OCR2 and TCNT2CmpBl='0') then
if(COM21='0' and COM20='1') then -- Toggle
OC2_PWM2_Int <= not OC2_PWM2_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR2(5 downto 4) is -- -> COM21&COM20
when "10" => -- Non-inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '0'; -- Clear
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '1'; -- Set
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '0'; -- Clear
else -- Down-counting
OC2_PWM2_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '1'; -- Set
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '0'; -- Clear
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '1'; -- Set
else -- Down-counting
OC2_PWM2_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC2_PWM2 <= OC2_PWM2_Int;
TCnt2_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV2 <= '0';
OCF2 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV2 <= dbus_in(6); -- !!!
end if;
else
case TOV2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (PWM2='0') then -- Non PWM Mode
if (TCNT2=x"FF") then
TOV2 <= '1';
end if;
else -- PWM Mode
if(TCNT2=x"00") then
TOV2 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag
TOV2 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF2 <= dbus_in(7); -- !!!
end if;
else
case OCF2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (TCNT2=OCR2 and TCNT2CmpBl='0') then
OCF2 <= '1';
end if;
end if;
when '1' =>
if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF2 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR2(7) <= '0';
TCCR2_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR2(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR2_Address and iowe='1') then
TCCR2(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR2_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM2 is
when '0' => -- Non-PWM mode
if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR2 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register
OCR2 <= OCR2_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR2_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus
OCR2_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT2WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT2WrFl is
when '0' =>
if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus
TCNT2WrFl <= '1';
end if;
when '1' =>
if(TCNT2_En='0') then
TCNT2WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF2 and Toggling) disabled for TCNT2
TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
TIMSK_Bits:process(cp2,ireset)
begin
if (ireset='0') then
TIMSK <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock Enable
if (adr=TIMSK_Address and iowe='1') then
TIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Interrupt flags of Timer/Counter0
TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0
TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0
-- Interrupt flags of Timer/Counter0
TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2
TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2
-- Unused interrupt requests(for T/C1)
TC1OvfIRQ <= TOV1 and TOIE1;
TC1CmpAIRQ <= OCF1A and OCIE1A;
TC1CmpBIRQ <= OCF1B and OCIE1B;
TC1ICIRQ <= ICF1 and TICIE1;
-- Unused TIFR flags(for T/C1)
TOV1 <= '0';
OCF1A <= '0';
OCF1B <= '0';
ICF1 <= '0';
-- -------------------------------------------------------------------------------------------
-- End of common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Bus interface
-- -------------------------------------------------------------------------------------------
out_en <= '1' when ((adr=TCCR0_Address or
adr=TCCR1A_Address or
adr=TCCR1B_Address or
adr=TCCR2_Address or
adr=ASSR_Address or
adr=TIMSK_Address or
adr=TIFR_Address or
adr=TCNT0_Address or
adr=TCNT2_Address or
adr=OCR0_Address or
adr=OCR2_Address or
adr=TCNT1H_Address or
adr=TCNT1L_Address or
adr=OCR1AH_Address or
adr=OCR1AL_Address or
adr=OCR1BH_Address or
adr=OCR1BL_Address or
adr=ICR1AH_Address or
adr=ICR1AL_Address) and iore='1') else '0';
-- Output multilexer
--Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial
--begin
-- case adr is
-- when TCCR0_Address => dbus_out <= TCCR0;
-- when OCR0_Address =>
-- if (PWM0='0') then
-- dbus_out <= OCR0;
-- else
-- dbus_out <= OCR0_Tmp;
-- end if;
-- when TCNT0_Address => dbus_out <= TCNT0;
-- when TCCR2_Address => dbus_out <= TCCR2;
-- when OCR2_Address =>
-- if (PWM2='0') then
-- dbus_out <= OCR2;
-- else
-- dbus_out <= OCR2_Tmp;
-- end if;
-- when TCNT2_Address => dbus_out <= TCNT2;
-- when TIFR_Address => dbus_out <= TIFR;
-- when TIMSK_Address => dbus_out <= TIMSK;
-- when others => dbus_out <= (others => '0');
-- end case;
--end process;
PWM0bit <= PWM0;
PWM10bit <= PWM10;
PWM11bit <= PWM11;
PWM2bit <= PWM2;
-- Synopsys version
dbus_out <= TCCR0 when (adr=TCCR0_Address) else
OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0
OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0
TCNT0 when (adr=TCNT0_Address) else
TCCR2 when (adr=TCCR2_Address) else
OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2
OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2
TCNT2 when (adr=TCNT2_Address) else
TIFR when (adr=TIFR_Address) else
TIMSK when (adr=TIMSK_Address) else
(others => '0');
-- -------------------------------------------------------------------------------------------
-- End of bus interface
-- -------------------------------------------------------------------------------------------
end RTL;
|
--**********************************************************************************************
-- Timers/Counters Block Peripheral for the AVR Core
-- Version 1.37? (Special version for the JTAG OCD)
-- Modified 11.06.2004
-- Synchronizer for EXT1/EXT2 inputs was added
-- Designed by Ruslan Lepetenok
-- Note : Only T/C0 and T/C2 are implemented
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end Timer_Counter;
architecture RTL of Timer_Counter is
-- Copies of the external signals
signal OC0_PWM0_Int : std_logic;
signal OC2_PWM2_Int : std_logic;
-- Registers
signal TCCR0 : std_logic_vector(7 downto 0);
signal TCCR1A : std_logic_vector(7 downto 0);
signal TCCR1B : std_logic_vector(7 downto 0);
signal TCCR2 : std_logic_vector(7 downto 0);
signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0)
signal TIMSK : std_logic_vector(7 downto 0);
signal TIFR : std_logic_vector(7 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal TCNT2 : std_logic_vector(7 downto 0);
signal OCR0 : std_logic_vector(7 downto 0);
signal OCR2 : std_logic_vector(7 downto 0);
signal TCNT1H : std_logic_vector(7 downto 0);
signal TCNT1L : std_logic_vector(7 downto 0);
signal OCR1AH : std_logic_vector(7 downto 0);
signal OCR1AL : std_logic_vector(7 downto 0);
signal OCR1BH : std_logic_vector(7 downto 0);
signal OCR1BL : std_logic_vector(7 downto 0);
signal ICR1AH : std_logic_vector(7 downto 0);
signal ICR1AL : std_logic_vector(7 downto 0);
-- TCCR0 Bits
alias CS00 : std_logic is TCCR0(0);
alias CS01 : std_logic is TCCR0(1);
alias CS02 : std_logic is TCCR0(2);
alias CTC0 : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0 : std_logic is TCCR0(6);
-- TCCR1A Bits
alias PWM10 : std_logic is TCCR1A(0);
alias PWM11 : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);
-- TCCR1B Bits
alias CS10 : std_logic is TCCR1A(0);
alias CS11 : std_logic is TCCR1A(1);
alias CS12 : std_logic is TCCR1A(2);
alias CTC1 : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);
-- TCCR2 Bits
alias CS20 : std_logic is TCCR2(0);
alias CS21 : std_logic is TCCR2(1);
alias CS22 : std_logic is TCCR2(2);
alias CTC2 : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2 : std_logic is TCCR2(6);
-- ASSR bits
alias TCR0UB : std_logic is ASSR(0);
alias OCR0UB : std_logic is ASSR(1);
alias TCN0UB : std_logic is ASSR(2);
alias AS0 : std_logic is ASSR(3);
-- TIMSK bits
alias TOIE0 : std_logic is TIMSK(0);
alias OCIE0 : std_logic is TIMSK(1);
alias TOIE1 : std_logic is TIMSK(2);
alias OCIE1B : std_logic is TIMSK(3);
alias OCIE1A : std_logic is TIMSK(4);
alias TICIE1 : std_logic is TIMSK(5);
alias TOIE2 : std_logic is TIMSK(6);
alias OCIE2 : std_logic is TIMSK(7);
-- TIFR bits
alias TOV0 : std_logic is TIFR(0);
alias OCF0 : std_logic is TIFR(1);
alias TOV1 : std_logic is TIFR(2);
alias OCF1B : std_logic is TIFR(3);
alias OCF1A : std_logic is TIFR(4);
alias ICF1 : std_logic is TIFR(5);
alias TOV2 : std_logic is TIFR(6);
alias OCF2 : std_logic is TIFR(7);
-- Prescaler1 signals
signal CK8 : std_logic;
signal CK64 : std_logic;
signal CK256 : std_logic;
signal CK1024 : std_logic;
signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit)
signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only)
signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only)
signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only)
-- Risign/falling edge detectors
signal EXT1Latched : std_logic;
signal EXT2Latched : std_logic;
-- Prescalers outputs
signal TCNT0_En : std_logic; -- Output of the prescaler 0
signal TCNT1_En : std_logic; -- Output of the prescaler 1
signal TCNT2_En : std_logic; -- Output of the prescaler 1
-- Prescaler0 signals
signal PCK08 : std_logic;
signal PCK032 : std_logic;
signal PCK064 : std_logic;
signal PCK0128 : std_logic;
signal PCK0256 : std_logic;
signal PCK01024 : std_logic;
signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit)
-- Synchronizer signals
signal EXT1SA : std_logic;
signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1
signal EXT2SA : std_logic;
signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1
-- Temporary registers
signal OCR0_Tmp : std_logic_vector(OCR0'range);
signal OCR2_Tmp : std_logic_vector(OCR2'range);
-- Counters control(Inc/Dec)
signal Cnt0Dir : std_logic;
signal Cnt2Dir : std_logic;
--
signal TCNT0WrFl : std_logic;
signal TCNT0CmpBl : std_logic;
signal TCNT2WrFl : std_logic;
signal TCNT2CmpBl : std_logic;
begin
-- Synchronizers
SyncDFFs:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
EXT1SA <= '0';
EXT1SB <= '0';
EXT2SA <= '0';
EXT2SB <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
EXT1SA <= EXT1;
EXT1SB <= EXT1SA;
EXT2SA <= EXT2;
EXT2SB <= EXT2SA;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------------------
-- Prescalers
-- -------------------------------------------------------------------------------------------
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Pre1Cnt <= (others => '0');
CK8 <= '0';
CK64 <= '0';
CK256 <= '0';
CK1024 <= '0';
EXT1RE <= '0';
EXT1FE <= '0';
EXT2RE <= '0';
EXT2FE <= '0';
EXT1Latched <= '0';
EXT2Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
Pre1Cnt <= Pre1Cnt+1;
CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched);
EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched);
EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched);
EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched);
EXT1Latched <= EXT1SB;
EXT2Latched <= EXT2SB;
end if;
end if;
end process;
TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001"
(CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010"
(CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011"
(CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100"
(CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101"
(EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110"
(EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111"
TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001"
(CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010"
(CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011"
(CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100"
(CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101"
(EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110"
(EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111"
Prescaler_0_Cnt:process(cp2,ireset)
begin
if(ireset='0') then -- Reset
Pre0Cnt <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
Pre0Cnt <= Pre0Cnt+1;
end if;
end if;
end process;
Prescaler_0:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PCK08 <= '0';
PCK032 <= '0';
PCK064 <= '0';
PCK0128 <= '0';
PCK0256 <= '0';
PCK01024 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2)));
PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4)));
PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5)));
PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6)));
PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7)));
PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9)));
end if;
end if;
end process;
TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001"
(PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010"
(PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011"
(PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100"
(PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101"
(PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110"
(PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111"
-- -------------------------------------------------------------------------------------------
-- End of prescalers
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 0
-- -------------------------------------------------------------------------------------------
TimerCounter0Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0
TCNT0 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM0 is
when '0' => -- Non-PWM mode
if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match
TCNT0 <= (others => '0');
elsif(TCNT0_En='1') then
TCNT0 <= TCNT0 + 1; -- Increment TCNT0
end if;
when '1' => -- PWM mode
if(TCNT0_En='1') then
case Cnt0Dir is
when '0' => -- Counts up
if(TCNT0=x"FF") then
TCNT0<=x"FE";
else
TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT0=x"00") then
TCNT0 <= x"01";
else
TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt0DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt0Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
if (PWM0='1') then
case Cnt0Dir is
when '0' =>
if(TCNT0=x"FF") then
Cnt0Dir <= '1';
end if;
when '1' =>
if(TCNT0=x"00") then
Cnt0Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt0OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
case PWM0 is
when '0' => -- Non PWM Mode
if(TCNT0=OCR0 and TCNT0CmpBl='0') then
if(COM01='0' and COM00='1') then -- Toggle
OC0_PWM0_Int <= not OC0_PWM0_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR0(5 downto 4) is -- -> COM01&COM00
when "10" => -- Non-inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '0'; -- Clear
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '1'; -- Set
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '0'; -- Clear
else -- Down-counting
OC0_PWM0_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '1'; -- Set
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '0'; -- Clear
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '1'; -- Set
else -- Down-counting
OC0_PWM0_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC0_PWM0 <= OC0_PWM0_Int;
TCnt0_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV0 <= '0';
OCF0 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV0 <= dbus_in(0); -- !!!
end if;
else
case TOV0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (PWM0='0') then -- Non PWM Mode
if (TCNT0=x"FF") then
TOV0 <= '1';
end if;
else -- PWM Mode
if(TCNT0=x"00") then
TOV0 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag
TOV0 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF0 <= dbus_in(1); -- !!!
end if;
else
case OCF0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (TCNT0=OCR0 and TCNT0CmpBl='0') then
OCF0 <= '1';
end if;
end if;
when '1' =>
if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF0 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR0(7) <= '0';
TCCR0_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR0(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR0_Address and iowe='1') then
TCCR0(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR0_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM0 is
when '0' => -- Non-PWM mode
if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR0 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register
OCR0 <= OCR0_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR0_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus
OCR0_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT0WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT0WrFl is
when '0' =>
if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus
TCNT0WrFl <= '1';
end if;
when '1' =>
if(TCNT0_En='0') then
TCNT0WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF0 and Toggling) disabled for TCNT0
TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 2
-- -------------------------------------------------------------------------------------------
TimerCounter2Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2
TCNT2 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM2 is
when '0' => -- Non-PWM mode
if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match
TCNT2 <= (others => '0');
elsif(TCNT2_En='1') then
TCNT2 <= TCNT2 + 1; -- Increment TCNT2
end if;
when '1' => -- PWM mode
if(TCNT2_En='1') then
case Cnt2Dir is
when '0' => -- Counts up
if(TCNT2=x"FF") then
TCNT2 <= x"FE";
else
TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT2=x"00") then
TCNT2 <= x"01";
else
TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt2DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt2Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
if (PWM2='1') then
case Cnt2Dir is
when '0' =>
if(TCNT2=x"FF") then
Cnt2Dir <= '1';
end if;
when '1' =>
if(TCNT2=x"00") then
Cnt2Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt2OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC2_PWM2_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
case PWM2 is
when '0' => -- Non PWM Mode
if(TCNT2=OCR2 and TCNT2CmpBl='0') then
if(COM21='0' and COM20='1') then -- Toggle
OC2_PWM2_Int <= not OC2_PWM2_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR2(5 downto 4) is -- -> COM21&COM20
when "10" => -- Non-inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '0'; -- Clear
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '1'; -- Set
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '0'; -- Clear
else -- Down-counting
OC2_PWM2_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '1'; -- Set
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '0'; -- Clear
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '1'; -- Set
else -- Down-counting
OC2_PWM2_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC2_PWM2 <= OC2_PWM2_Int;
TCnt2_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV2 <= '0';
OCF2 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV2 <= dbus_in(6); -- !!!
end if;
else
case TOV2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (PWM2='0') then -- Non PWM Mode
if (TCNT2=x"FF") then
TOV2 <= '1';
end if;
else -- PWM Mode
if(TCNT2=x"00") then
TOV2 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag
TOV2 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF2 <= dbus_in(7); -- !!!
end if;
else
case OCF2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (TCNT2=OCR2 and TCNT2CmpBl='0') then
OCF2 <= '1';
end if;
end if;
when '1' =>
if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF2 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR2(7) <= '0';
TCCR2_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR2(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR2_Address and iowe='1') then
TCCR2(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR2_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM2 is
when '0' => -- Non-PWM mode
if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR2 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register
OCR2 <= OCR2_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR2_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus
OCR2_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT2WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT2WrFl is
when '0' =>
if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus
TCNT2WrFl <= '1';
end if;
when '1' =>
if(TCNT2_En='0') then
TCNT2WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF2 and Toggling) disabled for TCNT2
TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
TIMSK_Bits:process(cp2,ireset)
begin
if (ireset='0') then
TIMSK <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock Enable
if (adr=TIMSK_Address and iowe='1') then
TIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Interrupt flags of Timer/Counter0
TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0
TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0
-- Interrupt flags of Timer/Counter0
TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2
TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2
-- Unused interrupt requests(for T/C1)
TC1OvfIRQ <= TOV1 and TOIE1;
TC1CmpAIRQ <= OCF1A and OCIE1A;
TC1CmpBIRQ <= OCF1B and OCIE1B;
TC1ICIRQ <= ICF1 and TICIE1;
-- Unused TIFR flags(for T/C1)
TOV1 <= '0';
OCF1A <= '0';
OCF1B <= '0';
ICF1 <= '0';
-- -------------------------------------------------------------------------------------------
-- End of common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Bus interface
-- -------------------------------------------------------------------------------------------
out_en <= '1' when ((adr=TCCR0_Address or
adr=TCCR1A_Address or
adr=TCCR1B_Address or
adr=TCCR2_Address or
adr=ASSR_Address or
adr=TIMSK_Address or
adr=TIFR_Address or
adr=TCNT0_Address or
adr=TCNT2_Address or
adr=OCR0_Address or
adr=OCR2_Address or
adr=TCNT1H_Address or
adr=TCNT1L_Address or
adr=OCR1AH_Address or
adr=OCR1AL_Address or
adr=OCR1BH_Address or
adr=OCR1BL_Address or
adr=ICR1AH_Address or
adr=ICR1AL_Address) and iore='1') else '0';
-- Output multilexer
--Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial
--begin
-- case adr is
-- when TCCR0_Address => dbus_out <= TCCR0;
-- when OCR0_Address =>
-- if (PWM0='0') then
-- dbus_out <= OCR0;
-- else
-- dbus_out <= OCR0_Tmp;
-- end if;
-- when TCNT0_Address => dbus_out <= TCNT0;
-- when TCCR2_Address => dbus_out <= TCCR2;
-- when OCR2_Address =>
-- if (PWM2='0') then
-- dbus_out <= OCR2;
-- else
-- dbus_out <= OCR2_Tmp;
-- end if;
-- when TCNT2_Address => dbus_out <= TCNT2;
-- when TIFR_Address => dbus_out <= TIFR;
-- when TIMSK_Address => dbus_out <= TIMSK;
-- when others => dbus_out <= (others => '0');
-- end case;
--end process;
PWM0bit <= PWM0;
PWM10bit <= PWM10;
PWM11bit <= PWM11;
PWM2bit <= PWM2;
-- Synopsys version
dbus_out <= TCCR0 when (adr=TCCR0_Address) else
OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0
OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0
TCNT0 when (adr=TCNT0_Address) else
TCCR2 when (adr=TCCR2_Address) else
OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2
OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2
TCNT2 when (adr=TCNT2_Address) else
TIFR when (adr=TIFR_Address) else
TIMSK when (adr=TIMSK_Address) else
(others => '0');
-- -------------------------------------------------------------------------------------------
-- End of bus interface
-- -------------------------------------------------------------------------------------------
end RTL;
|
--**********************************************************************************************
-- Timers/Counters Block Peripheral for the AVR Core
-- Version 1.37? (Special version for the JTAG OCD)
-- Modified 11.06.2004
-- Synchronizer for EXT1/EXT2 inputs was added
-- Designed by Ruslan Lepetenok
-- Note : Only T/C0 and T/C2 are implemented
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end Timer_Counter;
architecture RTL of Timer_Counter is
-- Copies of the external signals
signal OC0_PWM0_Int : std_logic;
signal OC2_PWM2_Int : std_logic;
-- Registers
signal TCCR0 : std_logic_vector(7 downto 0);
signal TCCR1A : std_logic_vector(7 downto 0);
signal TCCR1B : std_logic_vector(7 downto 0);
signal TCCR2 : std_logic_vector(7 downto 0);
signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0)
signal TIMSK : std_logic_vector(7 downto 0);
signal TIFR : std_logic_vector(7 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal TCNT2 : std_logic_vector(7 downto 0);
signal OCR0 : std_logic_vector(7 downto 0);
signal OCR2 : std_logic_vector(7 downto 0);
signal TCNT1H : std_logic_vector(7 downto 0);
signal TCNT1L : std_logic_vector(7 downto 0);
signal OCR1AH : std_logic_vector(7 downto 0);
signal OCR1AL : std_logic_vector(7 downto 0);
signal OCR1BH : std_logic_vector(7 downto 0);
signal OCR1BL : std_logic_vector(7 downto 0);
signal ICR1AH : std_logic_vector(7 downto 0);
signal ICR1AL : std_logic_vector(7 downto 0);
-- TCCR0 Bits
alias CS00 : std_logic is TCCR0(0);
alias CS01 : std_logic is TCCR0(1);
alias CS02 : std_logic is TCCR0(2);
alias CTC0 : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0 : std_logic is TCCR0(6);
-- TCCR1A Bits
alias PWM10 : std_logic is TCCR1A(0);
alias PWM11 : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);
-- TCCR1B Bits
alias CS10 : std_logic is TCCR1A(0);
alias CS11 : std_logic is TCCR1A(1);
alias CS12 : std_logic is TCCR1A(2);
alias CTC1 : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);
-- TCCR2 Bits
alias CS20 : std_logic is TCCR2(0);
alias CS21 : std_logic is TCCR2(1);
alias CS22 : std_logic is TCCR2(2);
alias CTC2 : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2 : std_logic is TCCR2(6);
-- ASSR bits
alias TCR0UB : std_logic is ASSR(0);
alias OCR0UB : std_logic is ASSR(1);
alias TCN0UB : std_logic is ASSR(2);
alias AS0 : std_logic is ASSR(3);
-- TIMSK bits
alias TOIE0 : std_logic is TIMSK(0);
alias OCIE0 : std_logic is TIMSK(1);
alias TOIE1 : std_logic is TIMSK(2);
alias OCIE1B : std_logic is TIMSK(3);
alias OCIE1A : std_logic is TIMSK(4);
alias TICIE1 : std_logic is TIMSK(5);
alias TOIE2 : std_logic is TIMSK(6);
alias OCIE2 : std_logic is TIMSK(7);
-- TIFR bits
alias TOV0 : std_logic is TIFR(0);
alias OCF0 : std_logic is TIFR(1);
alias TOV1 : std_logic is TIFR(2);
alias OCF1B : std_logic is TIFR(3);
alias OCF1A : std_logic is TIFR(4);
alias ICF1 : std_logic is TIFR(5);
alias TOV2 : std_logic is TIFR(6);
alias OCF2 : std_logic is TIFR(7);
-- Prescaler1 signals
signal CK8 : std_logic;
signal CK64 : std_logic;
signal CK256 : std_logic;
signal CK1024 : std_logic;
signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit)
signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only)
signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only)
signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only)
-- Risign/falling edge detectors
signal EXT1Latched : std_logic;
signal EXT2Latched : std_logic;
-- Prescalers outputs
signal TCNT0_En : std_logic; -- Output of the prescaler 0
signal TCNT1_En : std_logic; -- Output of the prescaler 1
signal TCNT2_En : std_logic; -- Output of the prescaler 1
-- Prescaler0 signals
signal PCK08 : std_logic;
signal PCK032 : std_logic;
signal PCK064 : std_logic;
signal PCK0128 : std_logic;
signal PCK0256 : std_logic;
signal PCK01024 : std_logic;
signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit)
-- Synchronizer signals
signal EXT1SA : std_logic;
signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1
signal EXT2SA : std_logic;
signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1
-- Temporary registers
signal OCR0_Tmp : std_logic_vector(OCR0'range);
signal OCR2_Tmp : std_logic_vector(OCR2'range);
-- Counters control(Inc/Dec)
signal Cnt0Dir : std_logic;
signal Cnt2Dir : std_logic;
--
signal TCNT0WrFl : std_logic;
signal TCNT0CmpBl : std_logic;
signal TCNT2WrFl : std_logic;
signal TCNT2CmpBl : std_logic;
begin
-- Synchronizers
SyncDFFs:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
EXT1SA <= '0';
EXT1SB <= '0';
EXT2SA <= '0';
EXT2SB <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
EXT1SA <= EXT1;
EXT1SB <= EXT1SA;
EXT2SA <= EXT2;
EXT2SB <= EXT2SA;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------------------
-- Prescalers
-- -------------------------------------------------------------------------------------------
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Pre1Cnt <= (others => '0');
CK8 <= '0';
CK64 <= '0';
CK256 <= '0';
CK1024 <= '0';
EXT1RE <= '0';
EXT1FE <= '0';
EXT2RE <= '0';
EXT2FE <= '0';
EXT1Latched <= '0';
EXT2Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
Pre1Cnt <= Pre1Cnt+1;
CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched);
EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched);
EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched);
EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched);
EXT1Latched <= EXT1SB;
EXT2Latched <= EXT2SB;
end if;
end if;
end process;
TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001"
(CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010"
(CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011"
(CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100"
(CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101"
(EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110"
(EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111"
TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001"
(CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010"
(CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011"
(CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100"
(CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101"
(EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110"
(EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111"
Prescaler_0_Cnt:process(cp2,ireset)
begin
if(ireset='0') then -- Reset
Pre0Cnt <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
Pre0Cnt <= Pre0Cnt+1;
end if;
end if;
end process;
Prescaler_0:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PCK08 <= '0';
PCK032 <= '0';
PCK064 <= '0';
PCK0128 <= '0';
PCK0256 <= '0';
PCK01024 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2)));
PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4)));
PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5)));
PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6)));
PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7)));
PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9)));
end if;
end if;
end process;
TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001"
(PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010"
(PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011"
(PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100"
(PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101"
(PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110"
(PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111"
-- -------------------------------------------------------------------------------------------
-- End of prescalers
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 0
-- -------------------------------------------------------------------------------------------
TimerCounter0Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0
TCNT0 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM0 is
when '0' => -- Non-PWM mode
if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match
TCNT0 <= (others => '0');
elsif(TCNT0_En='1') then
TCNT0 <= TCNT0 + 1; -- Increment TCNT0
end if;
when '1' => -- PWM mode
if(TCNT0_En='1') then
case Cnt0Dir is
when '0' => -- Counts up
if(TCNT0=x"FF") then
TCNT0<=x"FE";
else
TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT0=x"00") then
TCNT0 <= x"01";
else
TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt0DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt0Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
if (PWM0='1') then
case Cnt0Dir is
when '0' =>
if(TCNT0=x"FF") then
Cnt0Dir <= '1';
end if;
when '1' =>
if(TCNT0=x"00") then
Cnt0Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt0OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
case PWM0 is
when '0' => -- Non PWM Mode
if(TCNT0=OCR0 and TCNT0CmpBl='0') then
if(COM01='0' and COM00='1') then -- Toggle
OC0_PWM0_Int <= not OC0_PWM0_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR0(5 downto 4) is -- -> COM01&COM00
when "10" => -- Non-inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '0'; -- Clear
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '1'; -- Set
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '0'; -- Clear
else -- Down-counting
OC0_PWM0_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '1'; -- Set
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '0'; -- Clear
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '1'; -- Set
else -- Down-counting
OC0_PWM0_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC0_PWM0 <= OC0_PWM0_Int;
TCnt0_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV0 <= '0';
OCF0 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV0 <= dbus_in(0); -- !!!
end if;
else
case TOV0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (PWM0='0') then -- Non PWM Mode
if (TCNT0=x"FF") then
TOV0 <= '1';
end if;
else -- PWM Mode
if(TCNT0=x"00") then
TOV0 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag
TOV0 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF0 <= dbus_in(1); -- !!!
end if;
else
case OCF0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (TCNT0=OCR0 and TCNT0CmpBl='0') then
OCF0 <= '1';
end if;
end if;
when '1' =>
if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF0 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR0(7) <= '0';
TCCR0_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR0(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR0_Address and iowe='1') then
TCCR0(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR0_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM0 is
when '0' => -- Non-PWM mode
if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR0 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register
OCR0 <= OCR0_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR0_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus
OCR0_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT0WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT0WrFl is
when '0' =>
if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus
TCNT0WrFl <= '1';
end if;
when '1' =>
if(TCNT0_En='0') then
TCNT0WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF0 and Toggling) disabled for TCNT0
TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 2
-- -------------------------------------------------------------------------------------------
TimerCounter2Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2
TCNT2 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM2 is
when '0' => -- Non-PWM mode
if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match
TCNT2 <= (others => '0');
elsif(TCNT2_En='1') then
TCNT2 <= TCNT2 + 1; -- Increment TCNT2
end if;
when '1' => -- PWM mode
if(TCNT2_En='1') then
case Cnt2Dir is
when '0' => -- Counts up
if(TCNT2=x"FF") then
TCNT2 <= x"FE";
else
TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT2=x"00") then
TCNT2 <= x"01";
else
TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt2DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt2Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
if (PWM2='1') then
case Cnt2Dir is
when '0' =>
if(TCNT2=x"FF") then
Cnt2Dir <= '1';
end if;
when '1' =>
if(TCNT2=x"00") then
Cnt2Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt2OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC2_PWM2_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
case PWM2 is
when '0' => -- Non PWM Mode
if(TCNT2=OCR2 and TCNT2CmpBl='0') then
if(COM21='0' and COM20='1') then -- Toggle
OC2_PWM2_Int <= not OC2_PWM2_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR2(5 downto 4) is -- -> COM21&COM20
when "10" => -- Non-inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '0'; -- Clear
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '1'; -- Set
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '0'; -- Clear
else -- Down-counting
OC2_PWM2_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '1'; -- Set
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '0'; -- Clear
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '1'; -- Set
else -- Down-counting
OC2_PWM2_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC2_PWM2 <= OC2_PWM2_Int;
TCnt2_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV2 <= '0';
OCF2 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV2 <= dbus_in(6); -- !!!
end if;
else
case TOV2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (PWM2='0') then -- Non PWM Mode
if (TCNT2=x"FF") then
TOV2 <= '1';
end if;
else -- PWM Mode
if(TCNT2=x"00") then
TOV2 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag
TOV2 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF2 <= dbus_in(7); -- !!!
end if;
else
case OCF2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (TCNT2=OCR2 and TCNT2CmpBl='0') then
OCF2 <= '1';
end if;
end if;
when '1' =>
if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF2 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR2(7) <= '0';
TCCR2_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR2(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR2_Address and iowe='1') then
TCCR2(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR2_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM2 is
when '0' => -- Non-PWM mode
if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR2 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register
OCR2 <= OCR2_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR2_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus
OCR2_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT2WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT2WrFl is
when '0' =>
if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus
TCNT2WrFl <= '1';
end if;
when '1' =>
if(TCNT2_En='0') then
TCNT2WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF2 and Toggling) disabled for TCNT2
TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
TIMSK_Bits:process(cp2,ireset)
begin
if (ireset='0') then
TIMSK <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock Enable
if (adr=TIMSK_Address and iowe='1') then
TIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Interrupt flags of Timer/Counter0
TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0
TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0
-- Interrupt flags of Timer/Counter0
TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2
TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2
-- Unused interrupt requests(for T/C1)
TC1OvfIRQ <= TOV1 and TOIE1;
TC1CmpAIRQ <= OCF1A and OCIE1A;
TC1CmpBIRQ <= OCF1B and OCIE1B;
TC1ICIRQ <= ICF1 and TICIE1;
-- Unused TIFR flags(for T/C1)
TOV1 <= '0';
OCF1A <= '0';
OCF1B <= '0';
ICF1 <= '0';
-- -------------------------------------------------------------------------------------------
-- End of common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Bus interface
-- -------------------------------------------------------------------------------------------
out_en <= '1' when ((adr=TCCR0_Address or
adr=TCCR1A_Address or
adr=TCCR1B_Address or
adr=TCCR2_Address or
adr=ASSR_Address or
adr=TIMSK_Address or
adr=TIFR_Address or
adr=TCNT0_Address or
adr=TCNT2_Address or
adr=OCR0_Address or
adr=OCR2_Address or
adr=TCNT1H_Address or
adr=TCNT1L_Address or
adr=OCR1AH_Address or
adr=OCR1AL_Address or
adr=OCR1BH_Address or
adr=OCR1BL_Address or
adr=ICR1AH_Address or
adr=ICR1AL_Address) and iore='1') else '0';
-- Output multilexer
--Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial
--begin
-- case adr is
-- when TCCR0_Address => dbus_out <= TCCR0;
-- when OCR0_Address =>
-- if (PWM0='0') then
-- dbus_out <= OCR0;
-- else
-- dbus_out <= OCR0_Tmp;
-- end if;
-- when TCNT0_Address => dbus_out <= TCNT0;
-- when TCCR2_Address => dbus_out <= TCCR2;
-- when OCR2_Address =>
-- if (PWM2='0') then
-- dbus_out <= OCR2;
-- else
-- dbus_out <= OCR2_Tmp;
-- end if;
-- when TCNT2_Address => dbus_out <= TCNT2;
-- when TIFR_Address => dbus_out <= TIFR;
-- when TIMSK_Address => dbus_out <= TIMSK;
-- when others => dbus_out <= (others => '0');
-- end case;
--end process;
PWM0bit <= PWM0;
PWM10bit <= PWM10;
PWM11bit <= PWM11;
PWM2bit <= PWM2;
-- Synopsys version
dbus_out <= TCCR0 when (adr=TCCR0_Address) else
OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0
OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0
TCNT0 when (adr=TCNT0_Address) else
TCCR2 when (adr=TCCR2_Address) else
OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2
OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2
TCNT2 when (adr=TCNT2_Address) else
TIFR when (adr=TIFR_Address) else
TIMSK when (adr=TIMSK_Address) else
(others => '0');
-- -------------------------------------------------------------------------------------------
-- End of bus interface
-- -------------------------------------------------------------------------------------------
end RTL;
|
-- This package defines constants relating to the WCI interface
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; use ocpi.ocp;
package wci is
TYPE control_op_t IS (INITIALIZE_e,
START_e,
STOP_e,
RELEASE_e,
BEFORE_QUERY_e,
AFTER_CONFIG_e,
TEST_e,
NO_OP_e);
subtype control_op_mask_t is std_logic_vector(control_op_t'pos(no_op_e) downto 0);
--subtype control_op_t is unsigned(2 downto 0); -- natural range 0 to 7;
--constant INITIALIZE_e : control_op_t := to_unsigned(0,3);
--constant START_e : control_op_t := to_unsigned(1,3);
--constant STOP_e : control_op_t := to_unsigned(2,3);
--constant RELEASE_e : control_op_t := to_unsigned(3,3);
--constant BEFORE_QUERY_e : control_op_t := to_unsigned(4,3);
--constant AFTER_CONFIG_e : control_op_t := to_unsigned(5,3);
--constant TEST_e : control_op_t := to_unsigned(6,3);
--constant NO_OP_e : control_op_t := to_unsigned(7,3);
--subtype control_op_mask_t is std_logic_vector(to_integer(NO_OP_e) downto 0);
type worker_t is record
decode_width : natural;
allowed_ops : control_op_mask_t;
end record worker_t;
type property_t is record
data_width, -- data width of datum in bits, but 32 for strings
offset, -- offset in property space in bytes
bytes_1, -- total bytes in this property minus 1
string_length, -- bytes (excluding null) for string values
nitems -- nitems array
: natural; -- with of a single item
writable, readable, volatile, parameter : boolean;
end record property_t;
-- Address Space Selection
CONSTANT CONFIG : std_logic := '1';
CONSTANT CONTROL : std_logic := '0';
-- Worker State
-- These are not normative to the WCI interface, but are useful for bookkeepping
-- Note we track the state where we have accepted a control operation but
-- have not yet responded to it.
--TYPE State_t IS (EXISTS_e, -- 0
-- INITIALIZED_e, -- 1
-- OPERATING_e, -- 2
-- SUSPENDED_e, -- 3
-- UNUSABLE_e); -- 4
subtype State_t is natural range 0 to 4;
constant EXISTS_e : State_t := 0;
constant INITIALIZED_e : State_t := 1;
constant OPERATING_e : State_t := 2;
constant SUSPENDED_e : State_t := 3;
constant UNUSABLE_e : State_t := 4;
type control_op_masks_t is array (natural range <>) of control_op_mask_t;
-- constant masks for what control op is allowed in each state
constant next_ops : control_op_masks_t :=
("00000010", -- EXISTS_e
"10010100", -- INITIALIZED_e
"01111000", -- OPERATING_e
"01110100", -- SUSPENDED_e
"00000000" -- UNUSABLE_e: nothing to do but reset
);
--SUBTYPE State_t IS std_logic_vector(2 DOWNTO 0);
--CONSTANT EXISTS : State_t := "000";
--CONSTANT INITIALIZED : State_t := "001";
--CONSTANT OPERATING : State_t := "010";
--CONSTANT SUSPENDED : State_t := "011";
--CONSTANT UNUSABLE : State_t := "100";
---- Worker Control Operations
--SUBTYPE ControlOp_t IS std_logic_vector(2 DOWNTO 0);
--CONSTANT INITIALIZE : ControlOp_t := "000";
--CONSTANT START : ControlOp_t := "001";
--CONSTANT STOP : ControlOp_t := "010";
--CONSTANT RELEASE : ControlOp_t := "011";
--CONSTANT TEST : ControlOp_t := "100";
--CONSTANT BEFORE_QUERY : ControlOp_t := "101";
--CONSTANT AFTER_CONFIG : ControlOp_t := "110";
--CONSTANT RESERVED : ControlOp_t := "111";
type in_t is record
Clk : std_logic;
MAddr : std_logic_vector(31 downto 0);
MAddrSpace : std_logic_vector(0 downto 0);
MByteEn : std_logic_vector(3 downto 0);
MCmd : ocp.MCmd_t;
MData : std_logic_vector(31 downto 0);
MFlag : std_logic_vector(1 downto 0);
MReset_n : std_logic;
end record in_t;
type out_t is record
SData : std_logic_vector(31 downto 0);
SFlag : std_logic_vector(1 downto 0);
SResp : ocp.SResp_t;
SThreadBusy : std_logic_vector(0 downto 0);
end record out_t;
-- This is the type of access to the property, or none
type Access_t IS (None_e, Error_e, Read_e, Write_e, Control_e);
-- Return the currently decoded access
function decode_access(input : in_t) return Access_t;
-- Return the byte offset from the byte enables
--subtype byte_offset_t is unsigned(1 downto 0);
-- function be2offset(input: in_t) return byte_offset_t;
-- pull the value from the data bus, shifted and sized
function get_value(input : in_t; boffset : unsigned; width : natural) return std_logic_vector;
function to_control_op(bits : std_logic_vector(2 downto 0)) return control_op_t;
function resize(bits : std_logic_vector; n : natural) return std_logic_vector;
subtype hword_t is std_logic_vector(15 downto 0);
subtype byte_t is std_logic_vector(7 downto 0);
type properties_t is array (natural range <>) of property_t;
type data_a_t is array (natural range <>) of word_t;
type offset_a_t is array (natural range <>) of unsigned(31 downto 0);
type boolean_array_t is array (natural range <>) of boolean;
function data_out_top (property : property_t) return natural;
-- the wci convenience IP that makes it simple to implement a WCI interface
component decoder
generic(worker : worker_t; properties : properties_t);
port(
ocp_in : in in_t;
done : in bool_t := btrue;
resp : out ocp.SResp_t;
write_enables : out bool_array_t(properties'range);
read_enables : out bool_array_t(properties'range);
offsets : out offset_a_t(properties'range);
indices : out offset_a_t(properties'range);
hi32 : out bool_t;
nbytes_1 : out byte_offset_t;
data_outputs : out data_a_t(properties'range);
control_op : out control_op_t;
state : out state_t;
is_operating : out bool_t; -- just a convenience for state = operating_e
abort_control_op : out bool_t;
is_big_endian : out bool_t -- for runtime dynamic endian
);
end Component;
component readback
generic(properties : properties_t);
port(
read_enables : in bool_array_t(properties'range);
data_inputs : in data_a_t(properties'range);
data_output : out std_logic_vector(31 downto 0)
);
end component readback;
end package wci;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2048.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02048ent IS
END c07s02b04x00p01n01i02048ent;
ARCHITECTURE c07s02b04x00p01n01i02048arch OF c07s02b04x00p01n01i02048ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := "goodbye" + "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02048 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02048arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2048.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02048ent IS
END c07s02b04x00p01n01i02048ent;
ARCHITECTURE c07s02b04x00p01n01i02048arch OF c07s02b04x00p01n01i02048ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := "goodbye" + "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02048 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02048arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2048.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02048ent IS
END c07s02b04x00p01n01i02048ent;
ARCHITECTURE c07s02b04x00p01n01i02048arch OF c07s02b04x00p01n01i02048ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := "goodbye" + "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02048 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02048arch;
|
--
-- escci.vhd (based on megaram.vhd from MSX OCM project)
-- Mega-ROM emulation, ASC8K/16K/SCC+(8Mbits)
-- Revision 1.00
--
-- Copyright (c) 2006 Kazuhiro Tsujikawa (ESE Artists' factory)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- modified by t.hara
--
-- 2016/09 modified by Fabio Belavenuto <belavenuto@gmail.com>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity escci is
port(
clock_i : in std_logic;
clock_en_i : in std_logic;
reset_i : in std_logic;
--
addr_i : in std_logic_vector(15 downto 0);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
cs_i : in std_logic;
rd_i : in std_logic;
wr_i : in std_logic;
--
ram_addr_o : out std_logic_vector(19 downto 0); -- 1MB
ram_data_i : in std_logic_vector( 7 downto 0);
ram_ce_o : out std_logic;
ram_oe_o : out std_logic;
ram_we_o : out std_logic;
--
map_type_i : in std_logic_vector( 1 downto 0); -- "-0" : SCC+, "01" : ASC8K, "11" : ASC16K
--
wave_o : out signed(14 downto 0)
);
end entity;
architecture Behavior of escci is
signal cs_s : std_logic;
signal SccSel_s : std_logic_vector( 1 downto 0);
signal Dec1FFE : std_logic;
signal DecSccA : std_logic;
signal DecSccB : std_logic;
signal cs_dly_s : std_logic;
signal wav_copy_s : std_logic;
signal wav_cs_s : std_logic;
signal wav_addr_s : std_logic_vector( 7 downto 0);
signal WavDbi : std_logic_vector( 7 downto 0);
signal SccBank0 : std_logic_vector( 7 downto 0);
signal SccBank1 : std_logic_vector( 7 downto 0);
signal SccBank2 : std_logic_vector( 7 downto 0);
signal SccBank3 : std_logic_vector( 7 downto 0);
signal SccModeA : std_logic_vector( 7 downto 0); -- regs on 7FFE-7FFF
signal SccModeB : std_logic_vector( 7 downto 0); -- regs on BFFE-BFFF
begin
----------------------------------------------------------------
-- Connect components
----------------------------------------------------------------
SccWave : entity work.scc_wave
port map(
clock_i => clock_i,
clock_en_i => clock_en_i,
reset_i => reset_i,
cs_i => wav_cs_s,
wr_i => wr_i,
addr_i => wav_addr_s,
data_i => data_i,
data_o => WavDbi,
wave_o => wave_o
);
-- Select only in read ou write cycle
cs_s <= cs_i and (rd_i or wr_i);
----------------------------------------------------------------
-- SCC access decoder
----------------------------------------------------------------
process (reset_i, clock_i)
variable flag_v : std_logic;
begin
if reset_i = '1' then
flag_v := '0';
wav_copy_s <= '0';
elsif rising_edge(clock_i) then
-- SCC wave memory copy (ch.D > ch.E)
wav_copy_s <= '0';
if wav_cs_s = '1' and cs_dly_s = '0' then
if wr_i = '1' and addr_i(7 downto 5) = "011" and DecSccA = '1' and flag_v = '0' then -- 9860-987F
flag_v := '1';
else
flag_v := '0';
end if;
elsif flag_v = '1' then
wav_copy_s <= '1';
flag_v := '0';
end if;
cs_dly_s <= cs_s;
end if;
end process;
-- RAM request
ram_ce_o <= cs_s when SccSel_s = "01" else '0';
ram_oe_o <= rd_i;
ram_we_o <= wr_i;
ram_addr_o <= SccBank0(6 downto 0) & addr_i(12 downto 0) when addr_i(14 downto 13) = "10" else
SccBank1(6 downto 0) & addr_i(12 downto 0) when addr_i(14 downto 13) = "11" else
SccBank2(6 downto 0) & addr_i(12 downto 0) when addr_i(14 downto 13) = "00" else
SccBank3(6 downto 0) & addr_i(12 downto 0);
-- Mapped I/O port access on 9800-98FFh / B800-B8FFh ... Wave memory
wav_cs_s <= '1' when cs_s = '1' and cs_dly_s = '0' and SccSel_s(1) = '1' else
'1' when wav_copy_s = '1' and SccSel_s(1) = '1' else
'0';
-- exchange B8A0-B8BF <> 9880-989F (wave_ch.E) / B8C0-B8DF <> 98E0-98FF (mode register)
wav_addr_s <= "100" & addr_i(4 downto 0) when wav_copy_s = '1' else -- access B88x (copy wave to ch.E)
addr_i(7 downto 0) xor X"20" when addr_i(13) = '0' and addr_i(7) = '1' else -- 988x -> B8Ax and 98Ex -> B8Cx
addr_i(7 downto 0);
-- SCC data bus control
data_o <= ram_data_i when SccSel_s = "01" else
WavDbi when SccSel_s = "10" else
(others => '1');
-- SCC address decoder
SccSel_s <=
"10" when -- memory access (scc_wave)
addr_i(8) = '0' and SccModeB(4) = '0' and map_type_i(0) = '0' and
(DecSccA = '1' or DecSccB = '1') else
"01" when -- memory access (MEGA-ROM)
-- 4000-7FFFh(R/-, ASC8K/16K)
(addr_i(15 downto 14) = "01" and map_type_i(0) = '1' and rd_i = '1') or
-- 8000-BFFFh(R/-, ASC8K/16K)
(addr_i(15 downto 14) = "10" and map_type_i(0) = '1' and rd_i = '1') or
-- 4000-5FFFh(R/W, ASC8K/16K)
(addr_i(15 downto 13) = "010" and map_type_i(0) = '1' and SccBank0(7) = '1' ) or
-- 8000-9FFFh(R/W, ASC8K/16K)
(addr_i(15 downto 13) = "100" and map_type_i(0) = '1' and SccBank2(7) = '1' ) or
-- A000-BFFFh(R/W, ASC8K/16K)
(addr_i(15 downto 13) = "101" and map_type_i(0) = '1' and SccBank3(7) = '1' ) or
-- 4000-5FFFh(R/-, SCC)
(addr_i(15 downto 13) = "010" and SccModeA(6) = '0' and rd_i = '1') or
-- 6000-7FFFh(R/-, SCC)
(addr_i(15 downto 13) = "011" and rd_i = '1') or
-- 8000-9FFFh(R/-, SCC)
(addr_i(15 downto 13) = "100" and DecSccA = '0' and rd_i = '1') or
-- A000-BFFFh(R/-, SCC)
(addr_i(15 downto 13) = "101" and SccModeA(6) = '0' and DecSccB = '0' and rd_i = '1') or
-- 4000-5FFFh(R/W) ESCC-RAM
(addr_i(15 downto 13) = "010" and SccModeA(4) = '1') or
-- 6000-7FFDh(R/W) ESCC-RAM
(addr_i(15 downto 13) = "011" and SccModeA(4) = '1' and Dec1FFE /= '1') or
-- 4000-7FFFh(R/W) SNATCHER
(addr_i(15 downto 14) = "01" and SccModeB(4) = '1') or
-- 8000-9FFFh(R/W) SNATCHER
(addr_i(15 downto 13) = "100" and SccModeB(4) = '1') or
-- A000-BFFDh(R/W) SNATCHER
(addr_i(15 downto 13) = "101" and SccModeB(4) = '1' and Dec1FFE /= '1') else
"00"; -- MEGA-ROM bank register access
-- Mapped I/O port access on 7FFE-7FFFh / BFFE-BFFFh ... Write protect / SPC mode register
Dec1FFE <= '1' when addr_i(12 downto 1) = "111111111111" else '0';
-- Mapped I/O port access on 9800-9FFFh ... Wave memory
DecSccA <= '1' when addr_i(15 downto 11) = "10011" and SccModeB(5) = '0' and SccBank2(5 downto 0) = "111111" else '0';
-- Mapped I/O port access on B800-BFFFh ... Wave memory
DecSccB <= '1' when addr_i(15 downto 11) = "10111" and SccModeB(5) = '1' and SccBank3(7) = '1' else '0';
----------------------------------------------------------------
-- SCC bank register
----------------------------------------------------------------
process( reset_i, clock_i )
begin
if reset_i = '1' then
SccBank0 <= X"00";
SccBank1 <= X"01";
SccBank2 <= X"02";
SccBank3 <= X"03";
SccModeA <= (others => '0');
SccModeB <= (others => '0');
elsif rising_edge(clock_i) then
if map_type_i(0) = '0' then
-- Mapped I/O port access on 5000-57FFh ... Bank register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 11) = "01010" and
SccModeA(6) = '0' and SccModeA(4) = '0' and SccModeB(4) = '0' then
SccBank0 <= data_i;
end if;
-- Mapped I/O port access on 7000-77FFh ... Bank register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 11) = "01110" and
SccModeA(6) = '0' and SccModeA(4) = '0' and SccModeB(4) = '0' then
SccBank1 <= data_i;
end if;
-- Mapped I/O port access on 9000-97FFh ... Bank register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 11) = "10010" and
SccModeB(4) = '0' then
SccBank2 <= data_i;
end if;
-- Mapped I/O port access on B000-B7FFh ... Bank register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 11) = "10110" and
SccModeA(6) = '0' and SccModeA(4) = '0' and SccModeB(4) = '0' then
SccBank3 <= data_i;
end if;
-- Mapped I/O port access on 7FFE-7FFFh ... Register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 13) = "011" and
Dec1FFE = '1' and SccModeB(5 downto 4) = "00" then
SccModeA <= data_i;
end if;
-- Mapped I/O port access on BFFE-BFFFh ... Register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 13) = "101" and
Dec1FFE = '1' and SccModeA(6) = '0' and SccModeA(4) = '0' then
SccModeB <= data_i;
end if;
else
-- Mapped I/O port access on 6000-6FFFh ... Bank register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 12) = "0110" then
-- ASC8K / 6000-67FFh
if map_type_i(1) = '0' and addr_i(11) = '0' then
SccBank0 <= data_i;
-- ASC8K / 6800-6FFFh
elsif map_type_i(1) = '0' and addr_i(11) = '1' then
SccBank1 <= data_i;
-- ASC16K / 6000-67FFh
elsif addr_i(11) = '0' then
SccBank0 <= data_i(7) & data_i(5 downto 0) & '0';
SccBank1 <= data_i(7) & data_i(5 downto 0) & '1';
end if;
end if;
-- Mapped I/O port access on 7000-7FFFh ... Bank register write
if cs_i = '1' and SccSel_s = "00" and wr_i = '1' and addr_i(15 downto 12) = "0111" then
-- ASC8K / 7000-77FFh
if map_type_i(1) = '0' and addr_i(11) = '0' then
SccBank2 <= data_i;
-- ASC8K / 7800-7FFFh
elsif map_type_i(1) = '0' and addr_i(11) = '1' then
SccBank3 <= data_i;
-- ASC16K / 7000-77FFh
elsif addr_i(11) = '0' then
SccBank2 <= data_i(7) & data_i(5 downto 0) & '0';
SccBank3 <= data_i(7) & data_i(5 downto 0) & '1';
end if;
end if;
end if;
end if;
end process;
end architecture;
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