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------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml605.all;
use work.pcie.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF"
);
port (
reset : in std_ulogic;
errorn : out std_ulogic;
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
alatch : out std_ulogic;
-- DDR3 memory
ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_odt : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
gmiiclk_p : in std_ulogic;
gmiiclk_n : in std_ulogic;
egtx_clk : out std_ulogic;
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
erstn : out std_ulogic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
clk_33 : in std_ulogic; -- SYSACE clock
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- Output signals to LEDs
led : out std_logic_vector(6 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal lclk, clk_ddr, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
signal tb_rst : std_logic;
signal tb_clk : std_logic;
signal phy_init_done : std_logic;
signal lerrorn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- VGA
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal clk100 : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
-- IIC
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
-- SYSACE
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clk_ddr : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_preserve of clk_ddr : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
attribute keep of clk_ddr : signal is true;
constant VCO_FREQ : integer := 1200000; -- MMCM VCO frequency in KHz
constant CPU_FREQ : integer := VCO_FREQ / CFG_MIG_CLK4; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
alatch <= '0';
erstn <= rstn;
-- Glitch free reset that can be used for the Eth Phy and flash memory
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+CFG_PCIEXP,
nahbs => 9)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
lerrorn <= dbgo(0).error and rstn;
error_pad : odpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (errorn, lerrorn);
dsugen : if CFG_DSU = 1 generate
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (level => cmos, voltage => x15v, tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, iomask => 0, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 24)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (writen, memo.writen);
end generate;
bdr : iopadvv generic map (level => cmos, voltage => x25v, tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
-- mig_gen : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : ahb2mig_ml605
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#E00#,
MHz => 400, Mbyte => 512, nosync => boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst => rstn, clk_ahb => clkm, clk_ddr => clk_ddr,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
ddr3ctrl : entity work.mig_37
generic map (SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,CLKOUT_DIVIDE4 => work.config.CFG_MIG_CLK4)
port map(
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
ddr3_dq => ddr3_dq,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
app_wdf_wren => migi.app_wdf_wren,
app_wdf_data => migi.app_wdf_data,
app_wdf_mask => migi.app_wdf_mask,
app_wdf_end => migi.app_wdf_end,
app_addr => migi.app_addr,
app_cmd => migi.app_cmd,
app_en => migi.app_en,
app_rdy => migo.app_rdy,
app_wdf_rdy => migo.app_wdf_rdy,
app_rd_data => migo.app_rd_data,
app_rd_data_valid => migo.app_rd_data_valid,
tb_rst => open,
tb_clk => clk_ddr,
clk_ahb => clkm,
clk100 => clk100,
phy_init_done => phy_init_done,
sys_rst_13 => reset,
sys_rst_14 => rstraw
);
led(3) <= phy_init_done;
led(4) <= rstn;
led(5) <= reset;
led(6) <= '0';
lock <= phy_init_done; -- and cgo.clklock;
-- end generate;
-- noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= cgo.clklock; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 7, hirq => 10, mode => 2,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(7), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
clk_33_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (clk_33, clkace);
sysace_mpa_pads : outpadv generic map (level => cmos, voltage => x25v, width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (sysace_d(7 downto 0), aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpirq, acei.irq);
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
hslvndx => 8,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)
);
end generate;
------------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE),
dapbndx => 8, dapbaddr => 8,dapbirq => 8, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 8, apbndx => 5, apbaddr => 5, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(8),
dahbmo => ahbmo((CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)),
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 8, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 5, paddr => 5,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- VGA + IIC --------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 24000, clk2 => 20000, clk3 => 16000, burstlen => 4,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (clk100, ethi.gtx_clk, lock, clk_sel, vgao, clkvga, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 7, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (level => cmos, voltage => x25v, width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
-- greth1g: if CFG_GRETH1G = 1 generate
gtxclk0 : entity work.gtxclk port map (
clk_p => gmiiclk_p, clk_n => gmiiclk_n, clkint => ethi.gtx_clk,
clkout => egtx_clk);
-- end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1+CFG_PCIEXP) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Virtex6 ML605 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_split is
generic (
WIDTH : integer := 640
);
port (
clk : in std_logic;
rgb_in_0 : in std_logic_vector(23 downto 0);
rgb_in_1 : in std_logic_vector(23 downto 0);
x_addr : in std_logic_vector(9 downto 0);
rgb_out : out std_logic_vector(23 downto 0)
);
end vga_split;
architecture Behavioral of vga_split is
begin
process(clk)
begin
if rising_edge(clk) then
if unsigned(x_addr) < WIDTH / 2 then
rgb_out <= rgb_in_0;
else
rgb_out <= rgb_in_1;
end if;
end if;
end process;
end Behavioral;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
entity wait15 is
end entity;
architecture test of wait15 is
type wait_spec_t is record
delay : delay_length;
end record;
type wait_array_t is array (natural range <>) of wait_spec_t;
constant wait_list : wait_array_t := ( (delay => 1 ns),
(delay => 2 ns),
(delay => 5 us ) );
begin
process is
begin
for w in wait_list'range loop
wait for wait_list(w).delay;
end loop;
assert now = 5003 ns;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_d is
port (
Vactofk : in std_logic_vector(31 downto 0);
Voc : in std_logic_vector(31 downto 0);
clock : in std_logic;
D : out std_logic_vector(31 downto 0)
);
end k_ukf_d;
architecture struct of k_ukf_d is
component k_ukf_div IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
begin
M1 : k_ukf_div port map
( clock => clock,
dataa => Vactofk,
datab => Voc,
result => D);
end struct;
|
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3584)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
NNz/z22m3UJP37kwa6IFd50Z5x0r+GFc4rFR6jArAiXt8vj8/e91uShMEZyGpJLA4fIGeVIzLa6n
Rlgvwp5U0A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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DPmSqvScS8/u3peZEMo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UKxHPzVUVpqO4ThVo+RBVNlzhTk4nasm3vBbQ2rBuTvUH1oMNlAFl93cYPIRy+fAb+XN0cLtYIXp
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sI5VPnBJvnsznmi+9rSNonXojDwdNxAwjCZzXw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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n6f7oWLOv+3F3sKvkVI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ln1tl0SJvDonqv420pZIkybJL9NO5yznR+oglU5ke5gQ52e2hRdl7jp1pUClc9YUGotFrav0UTp/
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DhF1GxNED3yBp4jKj89A88X/+54cFrVrXEEolA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3584)
`protect data_block
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`protect end_protected
|
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_MUX_4to1 is
end TB_MUX_4to1;
architecture Behavioral of TB_MUX_4to1 is
component MUX_4to1 is
Port (
SEL : in STD_LOGIC_VECTOR (1 downto 0); -- 4 bits
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_3 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_4 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal SEL : STD_LOGIC_VECTOR (1 downto 0);
signal IN_1,IN_2,IN_3,IN_4 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal OUTPUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 4 TO 1 MUX
MUX1: MUX_4to1 port map(
SEL => SEL,
IN_1 => IN_1,
IN_2 => IN_2,
IN_3 => IN_3,
IN_4 => IN_4,
output => output
);
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
--Set up the four inputs
IN_1 <= x"111111";
IN_2 <= x"222222";
IN_3 <= x"333333";
IN_4 <= x"444444";
--Test the Select for each input
SEL <= "00"; wait for 2*period;
SEL <= "01"; wait for 2*period;
SEL <= "10"; wait for 2*period;
SEL <= "11"; wait for 2*period;
end process;
end Behavioral;
|
architecture ARCH of ENTITY1 is
begin
assert boolean report "Something" severity FAILURE;
process begin
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
assert boolean report "Something" severity FAILURE;
assert boolean
report "Something" severity FAILURE;
assert boolean report "Something"
severity FAILURE;
assert boolean
report "Something"
severity FAILURE;
if a then
assert (sel_0(4 downto 0) = "11001") report "Results wrong" severity warning;
else
assert (sel_0(4 downto 0) = "11001") report "Results wrong" severity warning;
end if;
end process;
assert boolean report "Something" severity FAILURE;
end architecture ARCH;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
H4URPv9EpcRhkuPfg29H1ZzBQu6E58ra8nWLS6or9vqljE8eUuMYTRR5FXv4Rv79+dW0YBbHJDL9
wpk/pM++Vw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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6Zg7UCBc9UmvCNd9skA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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wpk/pM++Vw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.ComFlow_pkg.all;
entity eth_marvell_88e1111_hal is
port (
clk_proc : in std_logic;
clk_hal : out std_logic;
reset_n : in std_logic;
---------------------- external ports --------------------
gtx_clk : out std_logic;
tx_en : out std_logic;
tx_data : out std_logic_vector(3 downto 0);
rx_clk : in std_logic;
rx_dv : in std_logic;
rx_data : in std_logic_vector(3 downto 0);
phy_reset_l : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic;
---------------------- hal com --------------------------
out_data_o : out std_logic_vector(7 downto 0);
out_data_wr_o : out std_logic;
out_data_full_i : in std_logic;
out_data_end_o : out std_logic;
in_data_i : in std_logic_vector(7 downto 0);
in_data_rd_o : out std_logic;
in_data_empty_i : in std_logic;
in_data_rdy_i : in std_logic;
in_data_size_packet : in std_logic_vector(15 downto 0)
);
end eth_marvell_88e1111_hal;
architecture rtl of eth_marvell_88e1111_hal is
component UDP_MAC_GE
port (
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
gtx_clk : out std_logic;
tx_en : out std_logic;
tx_data : out std_logic_vector(3 downto 0);
rx_clk : in std_logic;
rx_dv : in std_logic;
rx_data : in std_logic_vector(3 downto 0);
--phy
phy_reset_l : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic;
---------------------------------------------------------------------------
-- user Interface
---------------------------------------------------------------------------
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
CLK_OUT : OUT STD_LOGIC
);
end component;
-- udp
signal udp_tx_start : std_logic;
signal udp_txi : udp_tx_type;
signal udp_tx_result : std_logic_vector (1 downto 0);
signal udp_tx_data_out_ready : std_logic;
signal udp_rx_start : std_logic;
signal udp_rxo : udp_rx_type;
signal udp_header_valid_prev : std_logic;
signal out_data_end_s : std_logic;
signal CLK_OUT : std_logic;
constant IP_DEST : std_logic_vector(31 downto 0) := x"AC1B014A";
constant PORT_DEST : std_logic_vector(15 downto 0) := x"079B";
constant PORT_SRC : std_logic_vector(15 downto 0) := x"079B";
-- fsm read
type fsm_read_state_t is (Read_Idle, Read_Receive);
signal fsm_read_state : fsm_read_state_t := Read_Idle;
-- fsm write
type fsm_write_state_t is (Write_Idle, Wait_udp_tx_ready, wait_one_cycle_to_read_ff, transmit_tx);
signal fsm_write_state : fsm_write_state_t := Write_Idle;
begin
udp_mac_ge_inst : UDP_MAC_GE
port map (
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
gtx_clk => gtx_clk,
tx_en => tx_en,
tx_data => tx_data,
rx_clk => rx_clk,
rx_dv => rx_dv,
rx_data => rx_data,
--phy
phy_reset_l => phy_reset_l,
phy_mdc => phy_mdc,
phy_mdio => phy_mdio,
---------------------------------------------------------------------------
-- user Interface
---------------------------------------------------------------------------
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => open,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- UDP RX signals
udp_rx_start => udp_rx_start,
udp_rxo => udp_rxo,
CLK_OUT => CLK_OUT
);
clk_hal <= CLK_OUT;
--------------------------------------------
-----------------READ SIDE------------------
read_proc : process (CLK_OUT, reset_n)
begin
if(reset_n='0') then
fsm_read_state <= Read_Idle;
udp_header_valid_prev <= '0';
elsif(rising_edge(CLK_OUT)) then
udp_header_valid_prev <= udp_rxo.hdr.is_valid;
out_data_end_o <= out_data_end_s;
case fsm_read_state is
when Read_Idle =>
if(udp_header_valid_prev = '0'
and udp_rxo.hdr.is_valid = '1'
and udp_rxo.hdr.src_ip_addr = IP_DEST
and udp_rxo.hdr.src_port = PORT_DEST) then
fsm_read_state <= Read_Receive;
end if;
out_data_wr_o <= '0';
out_data_end_s <= '0';
when Read_Receive =>
if(udp_rxo.data.data_in_valid = '1') then
out_data_o <= udp_rxo.data.data_in;
out_data_wr_o <= '1';
if(udp_rxo.data.data_in_last = '1') then
out_data_end_s <= '1';
fsm_read_state <= Read_Idle;
else
out_data_end_s <= '0';
fsm_read_state <= Read_Receive;
end if;
end if;
when others =>
end case;
end if;
end process;
--------------------------------------------
-----------------WRITE SIDE------------------
udp_txi.hdr.dst_ip_addr <= IP_DEST;
udp_txi.hdr.dst_port <= PORT_DEST;
udp_txi.hdr.src_port <= PORT_SRC;
--udp_txi.hdr.data_length <= in_data_size_packet;
udp_txi.hdr.checksum <= (others => '0');
write_proc : process(CLK_OUT, reset_n)
begin
if(reset_n='0') then
in_data_rd_o <= '0';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= (others => '0');
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
fsm_write_state <= Write_Idle;
elsif rising_edge(CLK_OUT) then
case fsm_write_state is
------
when Write_Idle =>
if in_data_rdy_i = '1' and in_data_empty_i = '0' then
in_data_rd_o <= '0';
udp_tx_start <= '1';--
udp_txi.hdr.data_length <= in_data_size_packet;
fsm_write_state <= Wait_udp_tx_ready;
else
in_data_rd_o <= '0';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= (others => '0');
fsm_write_state <= Write_Idle;
end if;
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
------
when Wait_udp_tx_ready =>
if udp_tx_data_out_ready = '1' then
in_data_rd_o <= '1';--
udp_tx_start <= '0';--
fsm_write_state <= wait_one_cycle_to_read_ff;
else
in_data_rd_o <= '0';
udp_tx_start <= '1';--
fsm_write_state <= Wait_udp_tx_ready;
end if;
udp_txi.hdr.data_length <= udp_txi.hdr.data_length;
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
------
when wait_one_cycle_to_read_ff =>
in_data_rd_o <= '1';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= udp_txi.hdr.data_length;
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
fsm_write_state <= transmit_tx;
------
when transmit_tx =>
if in_data_rdy_i = '0' then --stop reading ff
in_data_rd_o <= '0';--stop
udp_txi.data.data_out_last <= '1';
fsm_write_state <= Write_Idle;
else
in_data_rd_o <= '1';--hold on
udp_txi.data.data_out_last <= '0';
fsm_write_state <= transmit_tx;
end if;
udp_tx_start <= '0';
udp_txi.hdr.data_length <= udp_txi.hdr.data_length;
udp_txi.data.data_out_valid <= '1';
udp_txi.data.data_out <= in_data_i;
when others =>
in_data_rd_o <= '0';
udp_tx_start <= '0';
udp_txi.hdr.data_length <= (others => '0');
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
udp_txi.data.data_out <= (others => '0');
fsm_write_state <= Write_Idle;
end case;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity picocpu is
port (
clk_in : in std_logic;
rst_n_in : in std_logic;
-- Signale zumdo Programmspeicher
inst_addr_out : out std_logic_vector( 9 downto 0) := ( others => '0' );
inst_data_in : in std_logic_vector(17 downto 0);
-- Output / Input Port
port_id_out : out std_logic_vector( 7 downto 0) := ( others => '0' );
port_wr_pulse_out : out std_logic := '0';
port_data_out : out std_logic_vector( 7 downto 0) := ( others => '0' );
port_rd_pulse_out : out std_logic := '0';
port_data_in : in std_logic_vector( 7 downto 0);
-- Interrupt Port
int_in : in std_logic;
int_ack_out : out std_logic := '0'
);
end picocpu;
architecture behavioral of picocpu is
------------------------------------
-- intern verwendete Definitionen --
------------------------------------
constant reg_num_c : natural := 16;
constant reg_width_c : natural := 8;
constant inst_depth_c : natural := 10;
constant zero_c : std_logic_vector( reg_width_c-1 downto 0) := ( others => '0' );
constant int_vec_c : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '1' );
constant opcode_msb_c : natural := inst_data_in'high;
constant opcode_width_c : natural := 8;
-- Instructions Codes
constant inst_msb_c : natural := inst_data_in'high;
constant inst_width_c : natural := 5;
-- write to register from (constant, register, read port or scratchpad - "000_00" bis "100_11" )
constant load_c : std_logic_vector(inst_width_c-1 downto 0) := b"000_00"; -- read from constant or register
--constant : std_logic_vector(inst_width_c downto 0) := b"000_01"; -- read from spare input (e.g ext ram or divider/multiplier/other calculator)
constant input_c : std_logic_vector(inst_width_c-1 downto 0) := b"000_10"; -- read from port value, write port id,
constant fetch_c : std_logic_vector(inst_width_c-1 downto 0) := b"000_11"; -- read from scratchpad
-- ALU
-- logical and arithmetik operations
--constant inv_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_00"; -- ALU logical not
constant and_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_01"; -- ALU logical and
constant or_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_10"; -- ALU locigal or
constant xor_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_11"; -- ALU logical xor
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"010_00"; -- ALU logical ??? ( don't write to register )
constant test_c : std_logic_vector(inst_width_c-1 downto 0) := b"010_01"; -- ALU logical and ( don't write to register )
constant compare_c : std_logic_vector(inst_width_c-1 downto 0) := b"010_10"; -- ALU logical sub ( don't write to register )
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"010_11"; -- ALU logical ??? ( don't write to register )
constant add_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_00"; -- ALU arithmetik add
constant addcy_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_01"; -- ALU arithmetik add with carry
constant sub_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_10"; -- ALU arithmetik sub
constant subcy_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_11"; -- ALU arithmetik sub with carry
-- shift operations
constant sr_c : std_logic_vector(inst_width_c-1 downto 0) := b"100_00"; -- ALU shift operation
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"100_01"; -- ALU spare (e.g. divider/multiplier/other calculator)
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"100_10"; -- ALU spare (e.g. divider/multiplier/other calculator)
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"100_11"; -- ALU spare (e.g. divider/multiplier/other calculator)
-- address operation (no write to register - "1010_0" bis "1111_1" )
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"1010_0"; -- spare
constant return_c : std_logic_vector(inst_width_c-1 downto 0) := b"1010_1"; -- jump to stack address
-- write operations
constant output_c : std_logic_vector(inst_width_c-1 downto 0) := b"1011_0"; -- write port id and port value
constant store_c : std_logic_vector(inst_width_c-1 downto 0) := b"1011_1"; -- write in scratchpad
-- (PC operation) Jump to address
constant call_c : std_logic_vector(inst_width_c-1 downto 0) := b"1100_0"; -- Jump to address, store pc to stack
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1100_1"; --
constant jump_c : std_logic_vector(inst_width_c-1 downto 0) := b"1101_0"; -- Jump to address
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1101_1"; --
constant returni_c : std_logic_vector(inst_width_c-1 downto 0) := b"1110_0"; -- Jump from interrupt, reload flags
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1110_1"; --
-- Setzt oder lösche Flags
constant interrupt_c : std_logic_vector(inst_width_c-1 downto 0) := b"1111_0"; -- enable / disable interrupts
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1111_1"; -- divide or multiply
-- Es fehlen noch überlegungen zu einer Memory management Unit
-- leider finde ich dazu gerade keine Informationen
constant sr_code_width_c : natural := 3;
-- ACHTUNG :: sub Codes für Shift right und shift Left sind nicht gleich !!! (x und rotate sind vertauscht)
-- Vermutlich wegen des Rotierens in der ALU
constant shift_a : std_logic_vector(sr_code_width_c-1 downto 0) := "000";
constant shift_x : std_logic_vector(sr_code_width_c-1 downto 0) := "010";
constant rotate : std_logic_vector(sr_code_width_c-1 downto 0) := "100";
constant shift_0 : std_logic_vector(sr_code_width_c-1 downto 0) := "110";
constant shift_1 : std_logic_vector(sr_code_width_c-1 downto 0) := "111";
-- Positionen wo in dem Befehl welche Informationen zu finden sind
constant condition_pos_c : natural := inst_data_in'high-inst_width_c;
constant addr_lsb_c : natural := 0;
constant addr_width_c : natural := inst_depth_c;
constant sX_msb_c : natural := inst_data_in'high-inst_width_c-1;
constant sX_width_c : natural := 4;
constant sY_msb_c : natural := inst_data_in'high-inst_width_c-sX_width_c-1;
constant sY_width_c : natural := 4;
constant const_lsb_c : natural := 0;
constant const_width_c : natural := reg_width_c;
constant direction_pos_c : natural := 3;
constant sr_code_lsb_c : natural := 0;
constant int_enable_pos_c : natural := 0;
-- Berechne die Bereiche der obrigen Informationen
subtype opcode_r is integer range opcode_msb_c downto opcode_msb_c-opcode_width_c+1;
subtype inst_r is integer range inst_msb_c downto inst_msb_c-inst_width_c+1;
subtype addr_r is integer range addr_lsb_c+addr_width_c-1 downto addr_lsb_c;
subtype sX_r is integer range sX_msb_c downto sX_msb_c-sX_width_c+1;
subtype sY_r is integer range sY_msb_c downto sY_msb_c-sX_width_c+1;
subtype const_r is integer range const_lsb_c+const_width_c-1 downto const_lsb_c;
subtype sr_code_r is integer range sr_code_lsb_c+sr_code_width_c-1 downto sr_code_lsb_c;
-- intern verwendete Bezeichnungen
alias opcode : std_logic_vector( opcode_width_c-1 downto 0) is inst_data_in(opcode_r); -- 17 downto 10
alias inst : std_logic_vector( inst_width_c-1 downto 0) is inst_data_in(inst_r); -- 17 downto 13
alias condition : std_logic is inst_data_in(condition_pos_c); -- 12
alias addr : std_logic_vector( addr_width_c-1 downto 0) is inst_data_in(addr_r); -- 9 downto 0
alias sX : std_logic_vector( sX_width_c-1 downto 0) is inst_data_in(sX_r); -- 11 downto 8
alias sY : std_logic_vector( sY_width_c-1 downto 0) is inst_data_in(sY_r); -- 7 downto 4
alias const : std_logic_vector( reg_width_c-1 downto 0) is inst_data_in(const_r); -- 7 downto 0
alias direction : std_logic is inst_data_in(direction_pos_c); -- 3
alias sr_code : std_logic_vector(sr_code_width_c-1 downto 0) is inst_data_in(sr_code_r); -- 2 downto 0
alias int_enable : std_logic is inst_data_in(int_enable_pos_c); -- 0
-------------------------------
-- intern verwendete Signale --
-------------------------------
type t_state is ( get, set ); -- PicoCPU State Maschine
signal state : t_state := get;
signal rst_n : std_logic := '1';
signal int : std_logic := '0';
signal pc : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal next_addr : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal last_addr : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal cond_valid : std_logic := '0';
signal zero : std_logic := '0';
signal not_zero : std_logic := '0';
signal carry : std_logic := '0';
signal not_carry : std_logic := '0';
signal alu_a : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal alu_b : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal alu_c : std_logic := '0';
signal res : std_logic_vector(reg_width_c downto 0) := ( others => '0' );
signal res_reg : std_logic_vector(reg_width_c downto 0) := ( others => '0' );
signal int_en_flag : std_logic := '0';
signal zero_flag : std_logic := '0';
alias carry_flag : std_logic is res_reg(res_reg'high);
signal preserved_zero : std_logic := '0';
signal preserved_carry : std_logic := '0';
attribute ram_style : string;
attribute keep : string;
type regs_t is array(0 to reg_num_c-1) of std_logic_vector(reg_width_c-1 downto 0);
signal regs_x : regs_t := ( others => ( others => '0' ));
signal regs_y : regs_t := ( others => ( others => '0' ));
attribute keep of regs_x : signal is "true";
attribute keep of regs_y : signal is "true";
attribute ram_style of regs_x : signal is "distributed";
attribute ram_style of regs_y : signal is "distributed";
signal wr_reg : std_logic := '0';
signal reg_in_addr : std_logic_vector(3 downto 0) := ( others => '0' );
signal reg_in : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal reg_x_out_addr : std_logic_vector(3 downto 0) := ( others => '0' );
signal reg_x_out : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal reg_y_out_addr : std_logic_vector(3 downto 0) := ( others => '0' );
signal reg_y_out : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
constant stack_width_c : natural := 5;
type stack_t is array (0 to (2**stack_width_c)-1) of std_logic_vector(addr'range);
signal stack : stack_t := ( others => ( others => '0'));
attribute keep of stack : signal is "true";
attribute ram_style of stack : signal is "distributed";
signal stack_ptr : std_logic_vector(stack_width_c-1 downto 0) := ( others => '0' );
signal stack_wr : std_logic := '0';
signal stack_rd : std_logic := '0';
signal stack_data_in : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal stack_top : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal stack_top_p : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal port_out_en : std_logic := '0';
signal port_in_en : std_logic := '0';
signal port_id_en : std_logic := '0';
signal port_id : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal port_data_i : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal port_data_o : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
constant scratchpad_width_c : natural := 2;
type scratchpad_t is array (0 to (2**scratchpad_width_c)-1) of std_logic_vector(reg_width_c-1 downto 0);
signal scratchpad : scratchpad_t := ( others => ( others => '0'));
attribute keep of scratchpad : signal is "true";
attribute ram_style of scratchpad : signal is "distributed";
signal wr_scratchpad : std_logic := '0';
signal scratchpad_addr : std_logic_vector(scratchpad_width_c-1 downto 0):= ( others => '0' );
signal scratchpad_in : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal scratchpad_out : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
function parity (din : std_logic_vector) return std_logic is
variable temp : std_logic := '0';
begin
for i in din'range loop
temp := temp xor din(i);
end loop;
return temp;
end parity;
begin
-- TODO::
-- Interrupts nochmal überprüfen, Interrups zeitgleich mit call, jump, return ???
-- Dynamischer gestallten: Registerbreite 4, 8, 16, 32, 64, 128
-- Anzahl der Register,
-- Größe des Scratchpad
-- Überlegungen zu prozessor skalierung
--
-- Slice Logic Utilization:
-- Number of Slice Registers: 89 out of 54576 0%
-- Number of Slice LUTs: 337 out of 27288 1%
-- Number used as Logic: 301 out of 27288 1%
-- Number used as Memory: 36 out of 6408 0%
-- Number used as RAM: 36
------------------------------------------------------------------
-- General Signals --
------------------------------------------------------------------
-- Reset und Interrupt Einsynchronisieren
socket_sync_ext_signal : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
rst_n <= rst_n_in;
int <= int_in;
end if;
end process;
-- PicoCPU State Maschine (da jeder Befehl genau zwei Takte benoetigen darf)
socket_picocpu_state_maschine : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
state <= get;
else
case state is
when get => state <= set;
when set => state <= get;
end case;
end if;
end if;
end process;
------------------------------------------------------------------
-- Operational Control & Instruction Decode --
------------------------------------------------------------------
zero <= '1' when opcode(1 downto 0) = "00" else '0';
not_zero <= '1' when opcode(1 downto 0) = "01" else '0';
carry <= '1' when opcode(1 downto 0) = "10" else '0';
not_carry <= '1' when opcode(1 downto 0) = "11" else '0';
------------------------------------------------------------------
-- Instruction Decode --
------------------------------------------------------------------
cond_valid <= '1' when condition = '0' else
'1' when condition = '1' and zero = '1' and zero_flag = '1' else
'1' when condition = '1' and not_zero = '1' and zero_flag = '0' else
'1' when condition = '1' and carry = '1' and carry_flag = '1' else
'1' when condition = '1' and not_carry = '1' and carry_flag = '0' else
'0';
stack_wr <= '1' when state = get and pc = int_vec_c else
'1' when state = get and inst = call_c and cond_valid = '1' else
'0';
stack_rd <= '1' when state = get and inst = return_c and cond_valid = '1' else
'1' when state = get and inst = returni_c else
'0';
wr_reg <= '1' when state = set and inst = load_c else
'1' when state = set and inst = input_c else
'1' when state = set and inst = fetch_c else
'1' when state = set and inst = and_c else
'1' when state = set and inst = or_c else
'1' when state = set and inst = xor_c else
'1' when state = set and inst = add_c else
'1' when state = set and inst = addcy_c else
'1' when state = set and inst = sub_c else
'1' when state = set and inst = subcy_c else
'1' when state = set and inst = sr_c else
'0';
port_out_en <= '1' when state = get and inst = output_c else '0';
port_in_en <= '1' when state = get and inst = input_c else '0';
port_id_en <= port_out_en or port_in_en;
wr_scratchpad <= '1' when state = set and inst = store_c else '0';
------------------------------------------------------------------
-- Program Counter --
------------------------------------------------------------------
next_addr <= addr when inst = jump_c and cond_valid = '1' else
addr when inst = call_c and cond_valid = '1' else
stack_top_p when inst = return_c and cond_valid = '1' else
stack_top when inst = returni_c else
std_logic_vector(unsigned(pc) + 1);
socket_test : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if state = get then
last_addr <= next_addr;
end if;
end if;
end process;
socket_program_counter : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
pc <= ( others => '0' );
else
if state = get then
if int = '1' and int_en_flag = '1' then
pc <= int_vec_c;
else
pc <= next_addr;
end if;
end if;
end if;
end if;
end process;
inst_addr_out <= pc;
------------------------------------------------------------------
-- Program Counter Stack --
------------------------------------------------------------------
stack_top <= std_logic_vector(unsigned(stack(to_integer(unsigned(stack_ptr)-1))));
stack_top_p <= std_logic_vector(unsigned(stack_top)+1);
stack_data_in <= last_addr when pc = int_vec_c else pc;
socket_stack_ptr : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
stack_ptr <= ( others => '0' );
else
if stack_wr = '1' then
stack(to_integer(unsigned(stack_ptr))) <= stack_data_in;
stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1);
elsif stack_rd = '1' then
stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1);
end if;
end if;
end if;
end process;
------------------------------------------------------------------
-- Arithmetic Logic Union --
------------------------------------------------------------------
alu_a <= reg_x_out;
alu_b <= const when condition = '0' else
reg_y_out;
alu_c <= parity(res_reg) when inst = test_c else
'0' when inst = sr_c and sr_code = shift_0 else
'1' when inst = sr_c and sr_code = shift_1 else
reg_x_out(reg_x_out'left) when inst = sr_c and sr_code = shift_x else
carry_flag when inst = sr_c and sr_code = shift_a else
reg_x_out(reg_x_out'right) when inst = sr_c and sr_code = rotate else
'0';
res <= alu_c & alu_a and alu_c & alu_b when inst = and_c else
alu_c & alu_a or alu_c & alu_b when inst = or_c else
alu_c & alu_a xor alu_c & alu_b when inst = xor_c else
alu_c & alu_a and alu_c & alu_b when inst = test_c else
-- Arithmetic Group
std_logic_vector(unsigned(alu_c & alu_a) + unsigned(alu_c & alu_b)) when inst = add_c else
std_logic_vector(unsigned(alu_c & alu_a) + unsigned(alu_c & alu_b) + unsigned(zero_c & carry_flag)) when inst = addcy_c else
std_logic_vector(unsigned(alu_c & alu_a) - unsigned(alu_c & alu_b)) when inst = sub_c else
std_logic_vector(unsigned(alu_c & alu_a) - unsigned(alu_c & alu_b) - unsigned(zero_c & carry_flag)) when inst = subcy_c else
std_logic_vector(unsigned(alu_c & alu_a) - unsigned(alu_c & alu_b)) when inst = compare_c else
-- Shift and Rotate Groupe
alu_a(alu_a'right) & alu_c & alu_a(reg_width_c-1 downto 1) when inst = sr_c and direction = '1' else
alu_a(alu_a'left) & alu_a(reg_width_c-2 downto 0) & alu_c when inst = sr_c and direction = '0' else
-- Return from Interrupt
preserved_carry & zero_c when inst = returni_c else
( others => '0' );
socket_alu : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
res_reg <= ( others => '0' );
else
if state = get then
res_reg <= res;
end if;
end if;
end if;
end process;
socket_flags : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
zero_flag <= '0';
else
if inst = returni_c and state = set then
zero_flag <= preserved_zero;
elsif res_reg(reg_width_c-1 downto 0) = zero_c then
zero_flag <= '1';
else
zero_flag <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------
-- 16 Registers -- 2x SLICEM / MLAB used as Dual-Port RAM on Spartan 6 / ARRIA II --
-------------------------------------------------------------------------------------------------
-- Hier werden die Register doppelt abgespeichert, das benötigt 9 Slices mehr --
-- hat aber den Vorteil, das mit sX und sY gleichzeitig zwei Register ausgelesen werden können --
-------------------------------------------------------------------------------------------------
reg_in_addr <= sX;
reg_in <= const when inst = load_c and condition = '0' else
reg_y_out when inst = load_c and condition = '1' else
scratchpad_out when inst = fetch_c else
port_data_i when inst = input_c else
res_reg(reg_in'range);
reg_x_out_addr <= sX;
reg_y_out_addr <= sY;
reg_x_out <= regs_x(to_integer(unsigned(reg_x_out_addr)));
reg_y_out <= regs_y(to_integer(unsigned(reg_y_out_addr)));
socket_regs_x : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if wr_reg = '1' then
regs_x(to_integer(unsigned(reg_in_addr))) <= reg_in;
end if;
end if;
end process;
socket_regs_y : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if wr_reg = '1' then
regs_y(to_integer(unsigned(reg_in_addr))) <= reg_in;
end if;
end if;
end process;
------------------------------------------------------------------
-- Port Address Control --
------------------------------------------------------------------
port_id <= const when inst = output_c and condition = '0' else
reg_y_out when inst = output_c and condition = '1' else
const when inst = input_c and condition = '0' else
reg_y_out when inst = input_c and condition = '1' else
( others => '0' );
port_data_o <= reg_x_out;
socket_port_id_ctrl : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
port_id_out <= ( others => '0' );
else
if port_id_en = '1' then
port_id_out <= port_id;
else
port_id_out <= ( others => '0' );
end if;
end if;
end if;
end process;
socket_port_output_ctrl : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
port_wr_pulse_out <= '0';
port_data_out <= ( others => '0' );
else
if port_out_en = '1' then
port_wr_pulse_out <= '1';
port_data_out <= port_data_o;
else
port_wr_pulse_out <= '0';
port_data_out <= ( others => '0' );
end if;
end if;
end if;
end process;
socket_port_input_ctrl : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
port_rd_pulse_out <= '0';
else
if port_in_en = '1' then
port_rd_pulse_out <= '1';
else
port_rd_pulse_out <= '0';
end if;
end if;
end if;
end process;
port_data_i <= port_data_in;
------------------------------------------------------------------
-- Scratch Pad Memory -- SLICEM / MLAB used as Singel-Port RAM --
------------------------------------------------------------------
scratchpad_addr <= const(scratchpad_addr'range) when condition = '0' else reg_x_out(scratchpad_addr'range);
scratchpad_in <= reg_x_out;
scratchpad_out <= scratchpad(to_integer(unsigned(scratchpad_addr)));
socket_scratchpad : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if wr_scratchpad = '1' then
scratchpad(to_integer(unsigned(scratchpad_addr))) <= scratchpad_in;
end if;
end if;
end process;
------------------------------------------------------------------
-- Interrupt Controller --
------------------------------------------------------------------
socket_interrupt_shadow_flags : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
preserved_zero <= '0';
preserved_carry <= '0';
else
if int = '1' and pc = int_vec_c and state = set then
preserved_zero <= zero_flag;
preserved_carry <= carry_flag;
end if;
end if;
end if;
end process;
socket_interrupt_enable_flag : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
int_en_flag <= '0';
else
if pc = int_vec_c then
int_en_flag <= '0';
elsif inst = returni_c then
int_en_flag <= int_enable;
elsif inst = interrupt_c then
int_en_flag <= int_enable;
end if;
end if;
end if;
end process;
socket_int_ack : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if state = set and pc = int_vec_c then
int_ack_out <= '1';
else
int_ack_out <= '0';
end if;
end if;
end process;
end behavioral;
|
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
-- Originally from http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity blockram is
generic (
DATA : integer := 72;
ADDR : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_en : in std_logic;
a_wr : in std_logic;
a_rst : in std_logic;
a_addr : in std_logic_vector(ADDR-1 downto 0);
a_din : in std_logic_vector(DATA-1 downto 0);
a_dout : out std_logic_vector(DATA-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_wr : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR-1 downto 0);
b_din : in std_logic_vector(DATA-1 downto 0);
b_dout : out std_logic_vector(DATA-1 downto 0)
);
end blockram;
architecture Behavioral of blockram is
-- Shared memory
type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(a_en, a_clk)
begin
if(a_en='1' and a_clk'event and a_clk='1') then
if(a_wr='1') then
mem(conv_integer(a_addr)) := a_din;
end if;
if(a_rst='1') then
a_dout <= (others => '0');
else
a_dout <= mem(conv_integer(a_addr));
end if;
end if;
end process;
-- Port B
process(b_en, b_clk)
begin
if(b_en='1' and b_clk'event and b_clk='1') then
if(b_wr='1') then
mem(conv_integer(b_addr)) := b_din;
end if;
if(b_rst='1') then
b_dout <= (others => '0');
else
b_dout <= mem(conv_integer(b_addr));
end if;
end if;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FSM_Conta is port(
CLK, RST, PIN: in std_logic;
NUM_clk: in std_logic_vector(2 downto 0);
contagem: out std_logic_vector(3 downto 0)
);
end FSM_Conta;
architecture bhv of FSM_Conta is
type states is (S0,S1,S2,S3,S4);
signal C50: std_logic;
signal contador: std_logic_vector(27 downto 0);
signal EA, PE: states;
begin
P1: process(CLK, RST, NUM_clk)
begin
if RST = '0' then
contador <= x"0000000";
EA <= S0;
elsif CLK'event and CLK = '1' then
contador <= contador + 1;
if C50 = '1' then
EA <= PE;
end if;
if NUM_clk = "001" and contador = x"2FAF080" then
contador <= x"0000000";
C50 <= '1';
elsif NUM_clk = "010" and contador = x"17D7840" then
contador <= x"0000000";
C50 <= '1';
elsif NUM_clk = "011" and contador = x"FE502B" then
contador <= x"0000000";
C50 <= '1';
elsif NUM_clk = "100" and contador = x"BEBC20" then
contador <= x"0000000";
C50 <= '1';
elsif NUM_clk = "100" and contador = x"989680" then
contador <= x"0000000";
C50 <= '1';
else
C50 <= '0';
end if;
end if;
end process;
P2: process(EA)
begin
case EA is
when S0 => contagem <= "0001";
PE <= S1;
when S1 => contagem <= "0010";
PE <= S2;
when S2 => contagem <= "0011";
PE <= S3;
when S3 => contagem <= "0100";
PE <= S4;
when S4 => contagem <= "0101";
PE <= S0;
end case;
end process;
end bhv;
|
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant a : in integer; signal b : in std_logic; variable c : in std_logic);
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
);
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic); -- variable ccc
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
);
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic); -- variable ccc
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic);
end package FIFO_PKG;
package body FIFO_PKG is
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic
) is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
) is
begin
end procedure AVERAGE_SAMPLES;
end package body FIFO_PKG;
architecture RTL of ENT is
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
) is
begin
end procedure AVERAGE_SAMPLES;
begin
TEST_PROCESS : process
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
) is
begin
end procedure AVERAGE_SAMPLES;
begin
end process TEST_PROCESS;
end architecture RTL;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo_generator_v9_3_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo_generator_v9_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 25,
C_DOUT_WIDTH => 25,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo_generator_v9_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 25,
C_DIN_WIDTH => 25,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo_generator_v9_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 25,
C_DIN_WIDTH => 25,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo_generator_v9_3_inst : fifo_generator_v9_3_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- Generated by tools/generate-rom.pl
-- Template: https://www.xilinx.com/support/answers/8183.html
-- But changed manually afterwards
library ieee;
use ieee.std_logic_1164.all;
use work.txt_utils.all;
use work.arch_defs.all;
use work.utils.all;
entity rom_default is
port ( a: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0);
en: in std_logic
);
attribute syn_romstyle : string;
attribute syn_romstyle of z : signal is "select_rom";
end rom_default;
architecture rtl of rom_default is
signal my_z : word_t;
begin
z <= my_z when en = '1' else HI_Z;
process(a)
begin
if en = '1' then
printf("Address = %s\n", a);
case a is
-- _start:
-- FIXME the first instruction won't be executed.
-- No idea why, so keep that in mind and place a nop there or something
when X"0000_0000" => my_z <= X"0000_0000";
when X"0000_0004" => my_z <= X"3421_f000"; -- ori $1,$1,0xf000
when X"0000_0008" => my_z <= X"0000_0000";
when X"0000_000C" => my_z <= X"3422_0bad"; -- ori $1,$2,0xbad
when X"0000_0010" => my_z <= X"0000_0000";
when X"0000_0014" => my_z <= X"3c03_A000"; -- lui $3,0xA000
when X"0000_0018" => my_z <= X"0000_0000";
when X"0000_001C" => my_z <= X"a062_0000"; -- sb $2,0($3)
when X"0000_0020" => my_z <= X"0000_0000";
when X"0000_0024" => my_z <= X"0000_0000";
when X"0000_0028" => my_z <= X"8064_0000"; -- lb $4,0($3)
when X"0000_002C" => my_z <= X"0800_0000"; -- j 0 <_start>
when X"0000_0030" => my_z <= X"0000_0000"; -- j 0 <_start>
when others => null;
end case;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: John Bieling ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 John Bieling ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use ieee.numeric_std.all;
entity readonly_register_with_readtrigger is
Generic (myaddress: natural := 16#FFFF#);
Port ( databus : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
addressbus : in STD_LOGIC_VECTOR (15 downto 0);
readsignal : in STD_LOGIC;
readtrigger : out STD_LOGIC;
CLK : in STD_LOGIC;
registerbits : in STD_LOGIC_VECTOR (31 downto 0));
end readonly_register_with_readtrigger;
architecture Behavioral of readonly_register_with_readtrigger is
begin
process (CLK) begin
if (rising_edge(CLK)) then
if (addressbus = myaddress and readsignal='1') then
databus <= registerbits;
readtrigger <= '1';
else
databus <= (others => 'Z');
readtrigger <= '0';
end if;
end if;
end process;
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library hynix;
use hynix.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => false, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile, fdelay => 340)
port map (DQ => ddr_dq(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 1)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
-- procedure FLUSH (file F : TEXT);
--
-- function MINIMUM (L, R : SIDE) return SIDE;
-- function MAXIMUM (L, R : SIDE) return SIDE;
--
-- function TO_STRING (VALUE : SIDE) return STRING;
--
-- function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
--
-- procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
-- alias STRING_READ is SREAD [LINE, STRING, NATURAL];
-- alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BREAD is READ [LINE, BIT_VECTOR];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR];
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- procedure TEE (file F : TEXT; L : inout LINE);
-- procedure WRITE (L : inout LINE; VALUE : in REAL;
-- FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
--pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
--ET: Below modification is required to avoid the following error in iSim
-- "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 7524 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."
-- swrite ( L => L, VALUE => to_string (VALUE, FORMAT));
swrite ( L, to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
|
------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
-- procedure FLUSH (file F : TEXT);
--
-- function MINIMUM (L, R : SIDE) return SIDE;
-- function MAXIMUM (L, R : SIDE) return SIDE;
--
-- function TO_STRING (VALUE : SIDE) return STRING;
--
-- function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
--
-- procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
-- alias STRING_READ is SREAD [LINE, STRING, NATURAL];
-- alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BREAD is READ [LINE, BIT_VECTOR];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR];
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- procedure TEE (file F : TEXT; L : inout LINE);
-- procedure WRITE (L : inout LINE; VALUE : in REAL;
-- FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
--pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
--ET: Below modification is required to avoid the following error in iSim
-- "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 7524 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."
-- swrite ( L => L, VALUE => to_string (VALUE, FORMAT));
swrite ( L, to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
|
------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
-- procedure FLUSH (file F : TEXT);
--
-- function MINIMUM (L, R : SIDE) return SIDE;
-- function MAXIMUM (L, R : SIDE) return SIDE;
--
-- function TO_STRING (VALUE : SIDE) return STRING;
--
-- function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
--
-- procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
-- alias STRING_READ is SREAD [LINE, STRING, NATURAL];
-- alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BREAD is READ [LINE, BIT_VECTOR];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR];
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- procedure TEE (file F : TEXT; L : inout LINE);
-- procedure WRITE (L : inout LINE; VALUE : in REAL;
-- FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
--pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
--ET: Below modification is required to avoid the following error in iSim
-- "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 7524 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."
-- swrite ( L => L, VALUE => to_string (VALUE, FORMAT));
swrite ( L, to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
|
-------------------------------------------------------------------------------
--! @file dpRamOpenmac-e.vhd
--
--! @brief Dual Port Ram Entity for openMAC IP-Core
--
--! @details This is the DPRAM entity for the openMAC IP-Core.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamOpenmac is
generic (
--! Data width [bit]
gWordWidth : natural := 32;
--! Number of words
gNumberOfWords : natural := 1024;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gWordWidth/8-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidth-1 downto 0);
--! Readdata of port A
oReaddata_A : out std_logic_vector(gWordWidth-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Write enable of port B
iWriteEnable_B : in std_logic;
--! Byteenable of port B
iByteenable_B : in std_logic_vector(gWordWidth/8-1 downto 0);
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Writedata of port B
iWritedata_B : in std_logic_vector(gWordWidth-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidth-1 downto 0)
);
end dpRamOpenmac;
|
architecture RTL of FIFO is
begin
process
begin
loop
a <= b;
end loop;
-- Violations below
loop
a <= b;
end loop;
end process;
end;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24384)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24384)
`protect data_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24384)
`protect data_block
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|
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24384)
`protect data_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
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`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:13:12 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/TbCUNEW.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbCUNEW IS
END TbCUNEW;
ARCHITECTURE behavior OF TbCUNEW IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
op3 : IN std_logic_vector(5 downto 0);
op : IN std_logic_vector(1 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal ALUOP : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
op3 => op3,
op => op,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
op <= "10";
op3 <="000000";
wait for 20 ns;
op <= "10";
op3 <="000001";
wait for 20 ns;
op <= "10";
op3 <="000010";
wait for 20 ns;
op <= "10";
op3 <="000011";
wait for 20 ns;
op <= "10";
op3 <="000111";
wait for 20 ns;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:13:12 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/TbCUNEW.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbCUNEW IS
END TbCUNEW;
ARCHITECTURE behavior OF TbCUNEW IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
op3 : IN std_logic_vector(5 downto 0);
op : IN std_logic_vector(1 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal ALUOP : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
op3 => op3,
op => op,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
op <= "10";
op3 <="000000";
wait for 20 ns;
op <= "10";
op3 <="000001";
wait for 20 ns;
op <= "10";
op3 <="000010";
wait for 20 ns;
op <= "10";
op3 <="000011";
wait for 20 ns;
op <= "10";
op3 <="000111";
wait for 20 ns;
-- insert stimulus here
wait;
end process;
END;
|
ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY design_1_axi_vdma_2_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC
);
END design_1_axi_vdma_2_0;
ARCHITECTURE design_1_axi_vdma_2_0_arch OF design_1_axi_vdma_2_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_vdma_2_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_vdma_2_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_vdma_2_0_arch : ARCHITECTURE IS "design_1_axi_vdma_2_0,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_vdma_2_0_arch: ARCHITECTURE IS "design_1_axi_vdma_2_0,axi_vdma,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=3,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=512,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=1,C_S2MM_GENLOCK_MODE=2,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 3,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 512,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 1,
C_S2MM_GENLOCK_MODE => 2,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut
);
END design_1_axi_vdma_2_0_arch;
|
entity sub is
generic (
width : integer );
port (
x : in bit_vector(width - 1 downto 0);
y : in bit_vector;
z : out bit_vector(width - 1 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y after 1 us;
end architecture;
-------------------------------------------------------------------------------
entity issue29 is
end entity;
architecture rtl of issue29 is
signal z : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
generic map (
width => 8 )
port map (
x => X"ab",
y => X"cd",
z => z );
process is
begin
wait for 2 us;
assert z = "10001001";
wait;
end process;
end architecture;
|
entity sub is
generic (
width : integer );
port (
x : in bit_vector(width - 1 downto 0);
y : in bit_vector;
z : out bit_vector(width - 1 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y after 1 us;
end architecture;
-------------------------------------------------------------------------------
entity issue29 is
end entity;
architecture rtl of issue29 is
signal z : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
generic map (
width => 8 )
port map (
x => X"ab",
y => X"cd",
z => z );
process is
begin
wait for 2 us;
assert z = "10001001";
wait;
end process;
end architecture;
|
entity sub is
generic (
width : integer );
port (
x : in bit_vector(width - 1 downto 0);
y : in bit_vector;
z : out bit_vector(width - 1 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y after 1 us;
end architecture;
-------------------------------------------------------------------------------
entity issue29 is
end entity;
architecture rtl of issue29 is
signal z : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
generic map (
width => 8 )
port map (
x => X"ab",
y => X"cd",
z => z );
process is
begin
wait for 2 us;
assert z = "10001001";
wait;
end process;
end architecture;
|
entity sub is
generic (
width : integer );
port (
x : in bit_vector(width - 1 downto 0);
y : in bit_vector;
z : out bit_vector(width - 1 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y after 1 us;
end architecture;
-------------------------------------------------------------------------------
entity issue29 is
end entity;
architecture rtl of issue29 is
signal z : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
generic map (
width => 8 )
port map (
x => X"ab",
y => X"cd",
z => z );
process is
begin
wait for 2 us;
assert z = "10001001";
wait;
end process;
end architecture;
|
entity sub is
generic (
width : integer );
port (
x : in bit_vector(width - 1 downto 0);
y : in bit_vector;
z : out bit_vector(width - 1 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y after 1 us;
end architecture;
-------------------------------------------------------------------------------
entity issue29 is
end entity;
architecture rtl of issue29 is
signal z : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
generic map (
width => 8 )
port map (
x => X"ab",
y => X"cd",
z => z );
process is
begin
wait for 2 us;
assert z = "10001001";
wait;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12080)
`protect data_block
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`protect end_protected
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_9.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_9.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_9.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10ns;
Ava_Wri <= '1';
wait for 10ns;
Ava_Wri <= '0';
wait for 10ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10ns;
Ava_Re <= '1';
wait for 10ns;
Ava_Re <= '0';
wait for 10ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
wait for 500ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100ns;
write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
wait for 100ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100ns;
--read
wait for 500ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
wait for 320ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10ns;
Ava_Wri <= '1';
wait for 10ns;
Ava_Wri <= '0';
wait for 10ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10ns;
Ava_Re <= '1';
wait for 10ns;
Ava_Re <= '0';
wait for 10ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
wait for 500ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100ns;
write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
wait for 100ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100ns;
--read
wait for 500ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
wait for 320ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10ns;
Ava_Wri <= '1';
wait for 10ns;
Ava_Wri <= '0';
wait for 10ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10ns;
Ava_Re <= '1';
wait for 10ns;
Ava_Re <= '0';
wait for 10ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
wait for 500ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100ns;
write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
wait for 100ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100ns;
--read
wait for 500ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
wait for 320ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: incrementadorCuenta10bits.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: albertomg994@gmail.com
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity incrementadorCuenta10bits is
Port ( num_in : in STD_LOGIC_VECTOR (9 downto 0);
num_out : out STD_LOGIC_VECTOR (9 downto 0)
);
end incrementadorCuenta10bits;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of incrementadorCuenta10bits is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal aux: std_logic_vector(8 downto 0);
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT adder1bit_comb
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
COMPONENT adder1bit_noCout
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
adder_0: adder1bit_comb port map(
A => num_in(0),
B => '1',
Cin => '0',
Z => num_out(0),
Cout => aux(0)
);
adder_1: adder1bit_comb port map(
A => num_in(1),
B => aux(0),
Cin => '0',
Z => num_out(1),
Cout => aux(1)
);
adder_2: adder1bit_comb port map(
A => num_in(2),
B => aux(1),
Cin => '0',
Z => num_out(2),
Cout => aux(2)
);
adder_3: adder1bit_comb port map(
A => num_in(3),
B => aux(2),
Cin => '0',
Z => num_out(3),
Cout => aux(3)
);
adder_4: adder1bit_comb port map(
A => num_in(4),
B => aux(3),
Cin => '0',
Z => num_out(4),
Cout => aux(4)
);
adder_5: adder1bit_comb port map(
A => num_in(5),
B => aux(4),
Cin => '0',
Z => num_out(5),
Cout => aux(5)
);
adder_6: adder1bit_comb port map(
A => num_in(6),
B => aux(5),
Cin => '0',
Z => num_out(6),
Cout => aux(6)
);
adder_7: adder1bit_comb port map(
A => num_in(7),
B => aux(6),
Cin => '0',
Z => num_out(7),
Cout => aux(7)
);
adder_8: adder1bit_comb port map(
A => num_in(8),
B => aux(7),
Cin => '0',
Z => num_out(8),
Cout => aux(8)
);
adder_9: adder1bit_noCout PORT MAP(
A => num_in(9),
B => aux(8),
Cin => '0',
Z => num_out(9)
);
end arq;
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut_base.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Single-port Base Decoder for decoding 8b/10b
-- encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
library work;
USE work.decode_8b10b_pkg.ALL;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_lut_base IS
GENERIC (
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
DISP_IN : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
ND : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_lut_base;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_lut_base IS
-----------------------------------------------------------------------------
-- Type Declarations
-----------------------------------------------------------------------------
TYPE disparity IS (neg, pos, zero, invalid, specneg, specpos) ;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
-- set the default decoder output for invalid codes
CONSTANT DEFAULTB5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11111" ;
CONSTANT DEFAULTB3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111" ;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
SIGNAL code_err_i : STD_LOGIC := '0';
SIGNAL symrd : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b6_disp : disparity := zero;
SIGNAL b4_disp : disparity := zero;
SIGNAL b5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := DEFAULTB5;
SIGNAL b3 : STD_LOGIC_VECTOR(7 DOWNTO 5) := DEFAULTB3;
SIGNAL k : STD_LOGIC := '0';
SIGNAL k28 : STD_LOGIC := '0';
ALIAS b6 : STD_LOGIC_VECTOR(5 DOWNTO 0) IS DIN(5 DOWNTO 0) ; --iedcba
ALIAS b4 : STD_LOGIC_VECTOR(3 DOWNTO 0) IS DIN(9 DOWNTO 6) ; --jhgf
ALIAS a : STD_LOGIC IS DIN(0) ;
ALIAS b : STD_LOGIC IS DIN(1) ;
ALIAS c : STD_LOGIC IS DIN(2) ;
ALIAS d : STD_LOGIC IS DIN(3) ;
ALIAS e : STD_LOGIC IS DIN(4) ;
ALIAS i : STD_LOGIC IS DIN(5) ;
ALIAS f : STD_LOGIC IS DIN(6) ;
ALIAS g : STD_LOGIC IS DIN(7) ;
ALIAS h : STD_LOGIC IS DIN(8) ;
ALIAS j : STD_LOGIC IS DIN(9) ;
--Signals for calculating code_error
SIGNAL p04 : STD_LOGIC := '0';
SIGNAL p13 : STD_LOGIC := '0';
SIGNAL p22 : STD_LOGIC := '0';
SIGNAL p31 : STD_LOGIC := '0';
SIGNAL p40 : STD_LOGIC := '0';
SIGNAL fghj : STD_LOGIC := '0';
SIGNAL eifgh : STD_LOGIC := '0';
SIGNAL sK28 : STD_LOGIC := '0';
SIGNAL e_i : STD_LOGIC := '0';
SIGNAL ighj : STD_LOGIC := '0';
SIGNAL i_ghj : STD_LOGIC := '0';
SIGNAL kx7 : STD_LOGIC := '0';
SIGNAL invr6 : STD_LOGIC := '0';
SIGNAL pdbr6 : STD_LOGIC := '0';
SIGNAL ndbr6 : STD_LOGIC := '0';
SIGNAL pdur6 : STD_LOGIC := '0';
SIGNAL pdbr4 : STD_LOGIC := '0';
SIGNAL ndrr4 : STD_LOGIC := '0';
SIGNAL ndur6 : STD_LOGIC := '0';
SIGNAL ndbr4 : STD_LOGIC := '0';
SIGNAL pdrr4 : STD_LOGIC := '0';
SIGNAL fgh : STD_LOGIC := '0';
SIGNAL invby_a : STD_LOGIC := '0';
SIGNAL invby_b : STD_LOGIC := '0';
SIGNAL invby_c : STD_LOGIC := '0';
SIGNAL invby_d : STD_LOGIC := '0';
SIGNAL invby_e : STD_LOGIC := '0';
SIGNAL invby_f : STD_LOGIC := '0';
SIGNAL invby_g : STD_LOGIC := '0';
SIGNAL invby_h : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------
-- Conditionally tie optional ports to internal signals
-----------------------------------------------------------------------------
----New Data-----------------------------------------------------------------
gnd : IF (C_HAS_ND = 1) GENERATE
----Update the New Data output-------------------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF ((CE = '1') AND (SINIT = '1')) THEN
ND <= '0' AFTER TFF;
ELSE
ND <= CE AFTER TFF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gnd ;
----Code Error---------------------------------------------------------------
gcerr : IF (C_HAS_CODE_ERR = 1) GENERATE
----Update CODE_ERR output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
CODE_ERR <= '0' AFTER TFF;
ELSE
CODE_ERR <= code_err_i AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gcerr ;
-- The following code uses notation and logic from the 8b/10b specification
-------------------------------------------------------------------------------
-- Set the value of k28 signal
-------------------------------------------------------------------------------
k28 <= NOT((c OR d OR e OR i) OR NOT(h XOR j)) ;
-------------------------------------------------------------------------------
-- Do the 6B/5B conversion
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000110" => b5 <= "00000" ; --D.0
WHEN "111001" => b5 <= "00000" ; --D.0
WHEN "010001" => b5 <= "00001" ; --D.1
WHEN "101110" => b5 <= "00001" ; --D.1
WHEN "010010" => b5 <= "00010" ; --D.2
WHEN "101101" => b5 <= "00010" ; --D.2
WHEN "100011" => b5 <= "00011" ; --D.3
WHEN "010100" => b5 <= "00100" ; --D.4
WHEN "101011" => b5 <= "00100" ; --D.4
WHEN "100101" => b5 <= "00101" ; --D.5
WHEN "100110" => b5 <= "00110" ; --D.6
WHEN "000111" => b5 <= "00111" ; --D.7
WHEN "111000" => b5 <= "00111" ; --D.7
WHEN "011000" => b5 <= "01000" ; --D.8
WHEN "100111" => b5 <= "01000" ; --D.8
WHEN "101001" => b5 <= "01001" ; --D.9
WHEN "101010" => b5 <= "01010" ; --D.10
WHEN "001011" => b5 <= "01011" ; --D.11
WHEN "101100" => b5 <= "01100" ; --D.12
WHEN "001101" => b5 <= "01101" ; --D.13
WHEN "001110" => b5 <= "01110" ; --D.14
WHEN "000101" => b5 <= "01111" ; --D.15
WHEN "111010" => b5 <= "01111" ; --D.15
WHEN "110110" => b5 <= "10000" ; --D.16
WHEN "001001" => b5 <= "10000" ; --D.16
WHEN "110001" => b5 <= "10001" ; --D.17
WHEN "110010" => b5 <= "10010" ; --D.18
WHEN "010011" => b5 <= "10011" ; --D.19
WHEN "110100" => b5 <= "10100" ; --D.20
WHEN "010101" => b5 <= "10101" ; --D.21
WHEN "010110" => b5 <= "10110" ; --D.22
WHEN "010111" => b5 <= "10111" ; --D/K.23
WHEN "101000" => b5 <= "10111" ; --D/K.23
WHEN "001100" => b5 <= "11000" ; --D.24
WHEN "110011" => b5 <= "11000" ; --D.24
WHEN "011001" => b5 <= "11001" ; --D.25
WHEN "011010" => b5 <= "11010" ; --D.26
WHEN "011011" => b5 <= "11011" ; --D/K.27
WHEN "100100" => b5 <= "11011" ; --D/K.27
WHEN "011100" => b5 <= "11100" ; --D.28
WHEN "111100" => b5 <= "11100" ; --K.28
WHEN "000011" => b5 <= "11100" ; --K.28
WHEN "011101" => b5 <= "11101" ; --D/K.29
WHEN "100010" => b5 <= "11101" ; --D/K.29
WHEN "011110" => b5 <= "11110" ; --D.30
WHEN "100001" => b5 <= "11110" ; --D.30
WHEN "110101" => b5 <= "11111" ; --D.31
WHEN "001010" => b5 <= "11111" ; --D.31
WHEN OTHERS => b5 <= DEFAULTB5 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 6B block
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000000" => b6_disp <= neg ; --invalid ;
WHEN "000001" => b6_disp <= neg ; --invalid ;
WHEN "000010" => b6_disp <= neg ; --invalid ;
WHEN "000011" => b6_disp <= neg ; --K.28
WHEN "000100" => b6_disp <= neg ; --invalid ;
WHEN "000101" => b6_disp <= neg ; --D.15
WHEN "000110" => b6_disp <= neg ; --D.0
WHEN "000111" => b6_disp <= specneg; --D.7
WHEN "001000" => b6_disp <= neg ; --invalid ;
WHEN "001001" => b6_disp <= neg ; --D.16
WHEN "001010" => b6_disp <= neg ; --D.31
WHEN "001011" => b6_disp <= zero ; --D.11
WHEN "001100" => b6_disp <= neg ; --D.24
WHEN "001101" => b6_disp <= zero ; --D.13
WHEN "001110" => b6_disp <= zero ; --D.14
WHEN "001111" => b6_disp <= pos ; --invalid ;
WHEN "010000" => b6_disp <= neg ; --invalid ;
WHEN "010001" => b6_disp <= neg ; --D.1
WHEN "010010" => b6_disp <= neg ; --D.2
WHEN "010011" => b6_disp <= zero ; --D.19
WHEN "010100" => b6_disp <= neg ; --D.4
WHEN "010101" => b6_disp <= zero ; --D.21
WHEN "010110" => b6_disp <= zero ; --D.22
WHEN "010111" => b6_disp <= pos ; --D.23
WHEN "011000" => b6_disp <= neg ; --D.8
WHEN "011001" => b6_disp <= zero ; --D.25
WHEN "011010" => b6_disp <= zero ; --D.26
WHEN "011011" => b6_disp <= pos ; --D.27
WHEN "011100" => b6_disp <= zero ; --D.28
WHEN "011101" => b6_disp <= pos ; --D.29
WHEN "011110" => b6_disp <= pos ; --D.30
WHEN "011111" => b6_disp <= pos ; --invalid ;
WHEN "100000" => b6_disp <= neg ; --invalid ;
WHEN "100001" => b6_disp <= neg ; --D.30 ;
WHEN "100010" => b6_disp <= neg ; --D.29 ;
WHEN "100011" => b6_disp <= zero ; --D.3
WHEN "100100" => b6_disp <= neg ; --D.27
WHEN "100101" => b6_disp <= zero ; --D.5
WHEN "100110" => b6_disp <= zero ; --D.6
WHEN "100111" => b6_disp <= pos ; --D.8
WHEN "101000" => b6_disp <= neg ; --D.23
WHEN "101001" => b6_disp <= zero ; --D.9
WHEN "101010" => b6_disp <= zero ; --D.10
WHEN "101011" => b6_disp <= pos ; --D.4
WHEN "101100" => b6_disp <= zero ; --D.12
WHEN "101101" => b6_disp <= pos ; --D.2
WHEN "101110" => b6_disp <= pos ; --D.1
WHEN "101111" => b6_disp <= pos ; --invalid ;
WHEN "110000" => b6_disp <= neg ; --invalid ;
WHEN "110001" => b6_disp <= zero ; --D.17
WHEN "110010" => b6_disp <= zero ; --D.18
WHEN "110011" => b6_disp <= pos ; --D.24
WHEN "110100" => b6_disp <= zero ; --D.20
WHEN "110101" => b6_disp <= pos ; --D.31
WHEN "110110" => b6_disp <= pos ; --D.16
WHEN "110111" => b6_disp <= pos ; --invalid ;
WHEN "111000" => b6_disp <= specpos; --D.7
WHEN "111001" => b6_disp <= pos ; --D.0
WHEN "111010" => b6_disp <= pos ; --D.15
WHEN "111011" => b6_disp <= pos ; --invalid ;
WHEN "111100" => b6_disp <= pos ; --K.28
WHEN "111101" => b6_disp <= pos ; --invalid ;
WHEN "111110" => b6_disp <= pos ; --invalid ;
WHEN "111111" => b6_disp <= pos ; --invalid ;
WHEN OTHERS => b6_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Do the 3B/4B conversion
-------------------------------------------------------------------------------
PROCESS (b4, k28)
BEGIN
CASE b4 IS
WHEN "0010" => b3 <= "000" ; --D/K.x.0
WHEN "1101" => b3 <= "000" ; --D/K.x.0
WHEN "1001" =>
IF (k28 = '0')
THEN b3 <= "001" ; --D/K.x.1
ELSE b3 <= "110" ; --K28.6
END IF ;
WHEN "0110" =>
IF (k28 = '1')
THEN b3 <= "001" ; --K.28.1
ELSE b3 <= "110" ; --D/K.x.6
END IF ;
WHEN "1010" =>
IF (k28 = '0')
THEN b3 <= "010" ; --D/K.x.2
ELSE b3 <= "101" ; --K28.5
END IF ;
WHEN "0101" =>
IF (k28 = '1')
THEN b3 <= "010" ; --K28.2
ELSE b3 <= "101" ; --D/K.x.5
END IF ;
WHEN "0011" => b3 <= "011" ; --D/K.x.3
WHEN "1100" => b3 <= "011" ; --D/K.x.3
WHEN "0100" => b3 <= "100" ; --D/K.x.4
WHEN "1011" => b3 <= "100" ; --D/K.x.4
WHEN "0111" => b3 <= "111" ; --D.x.7
WHEN "1000" => b3 <= "111" ; --D.x.7
WHEN "1110" => b3 <= "111" ; --D/K.x.7
WHEN "0001" => b3 <= "111" ; --D/K.x.7
WHEN OTHERS => b3 <= DEFAULTB3 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 4B block
-------------------------------------------------------------------------------
PROCESS (b4)
BEGIN
CASE b4 IS
WHEN "0000" => b4_disp <= neg ;
WHEN "0001" => b4_disp <= neg ;
WHEN "0010" => b4_disp <= neg ;
WHEN "0011" => b4_disp <= specneg;
WHEN "0100" => b4_disp <= neg ;
WHEN "0101" => b4_disp <= zero ;
WHEN "0110" => b4_disp <= zero ;
WHEN "0111" => b4_disp <= pos ;
WHEN "1000" => b4_disp <= neg ;
WHEN "1001" => b4_disp <= zero ;
WHEN "1010" => b4_disp <= zero ;
WHEN "1011" => b4_disp <= pos ;
WHEN "1100" => b4_disp <= specpos;
WHEN "1101" => b4_disp <= pos ;
WHEN "1110" => b4_disp <= pos ;
WHEN "1111" => b4_disp <= pos ;
WHEN OTHERS => b4_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Special Code for calculating symrd[3:0]
--
-- +---------+---------+-------+------------+-------+------------+
-- | | | symrd |
-- | | | + Start Disp | - Start Disp |
-- | b6_disp | b4_disp | Error | NewRunDisp | Error | NewRunDisp |
-- +---------+---------+-------+------------+-------+------------+
-- | + | + | 1 | 1 | 1 | 1 |
-- | + | - | 1 | 0 | 0 | 0 |
-- | + | 0 | 1 | 1 | 0 | 1 |
-- | - | + | 0 | 1 | 1 | 1 |
-- | - | - | 1 | 0 | 1 | 0 |
-- | - | 0 | 0 | 0 | 1 | 0 |
-- | 0 | + | 1 | 1 | 0 | 1 |
-- | 0 | - | 0 | 0 | 1 | 0 |
-- | 0 | 0 | 0 | 1 | 0 | 0 |
-- +---------+---------+-------+------------+-------+------------+
--
-------------------------------------------------------------------------------
PROCESS (b4_disp, b6_disp)
BEGIN
CASE b6_disp IS
WHEN pos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "1000";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1101"; --Ex: D1.3-
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000";
WHEN zero => symrd(3 DOWNTO 0) <= "1101";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN neg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "0111";
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "0010"; --Ex: D1.3+
WHEN zero => symrd(3 DOWNTO 0) <= "0010";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN zero =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101";
WHEN neg => symrd(3 DOWNTO 0) <= "0010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D11.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D11.3-
WHEN zero => symrd(3 DOWNTO 0) <= "0100";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specpos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "0010"; --Ex: D7.0+
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1010";
WHEN zero => symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.5+
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specneg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101"; --Ex: D7.0-
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.3-
WHEN zero => symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.5-
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
END PROCESS;
-- the new running disparity is calculated from the input disparity
-- and the disparity of the 10-bit word
grdi : IF (C_HAS_DISP_IN = 1 AND C_HAS_RUN_DISP=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (DISP_IN = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdi;
-- the new running disparity is calculated from the old running disparity
-- and the disparity of the 10-bit word. run_disp is also used to
-- calculate disp_err and sym_disp when disp_in is not present
grdni : IF (C_HAS_DISP_IN /= 1 AND (C_HAS_RUN_DISP=1 OR
C_HAS_DISP_ERR=1 OR
C_HAS_SYM_DISP=1)) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (run_disp_i = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdni;
gde : IF (C_HAS_DISP_ERR = 1) GENERATE
-- the new disparity error is calculated from the old running disparity
-- and the error information from the 10-bit word
gdei : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (DISP_IN='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdei;
gdeni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (run_disp_i='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdeni;
END GENERATE gde;
gsd : IF (C_HAS_SYM_DISP = 1) GENERATE
gsdi : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (DISP_IN='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdi;
gsdni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (run_disp_i='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdni;
END GENERATE gsd;
-- map internal signals to outputs
run_disp <= run_disp_i;
sym_disp <= sym_disp_i;
-------------------------------------------------------------------------------
-- Decode the K codes
-------------------------------------------------------------------------------
PROCESS (c, d, e, i, g, h, j)
BEGIN
k <= (c AND d AND e AND i) OR NOT(c OR d OR e OR i) OR
((e XOR i) AND ((i AND g AND h AND j) OR
NOT(i OR g OR h OR j))) ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Update the outputs on the clock
-------------------------------------------------------------------------------
----Update DOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
dout_i <= str_to_slv(C_SINIT_DOUT, 8) AFTER TFF ;
ELSE
dout_i <= (b3 & b5) AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
DOUT <= dout_i;
----Update KOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
kout_i <= bint_2_sl(C_SINIT_KOUT) AFTER TFF;
ELSE
kout_i <= k AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
KOUT <= kout_i;
-------------------------------------------------------------------------------
-- Calculate code_error (uses notation from IBM spec)
-------------------------------------------------------------------------------
bitcount: PROCESS (DIN)
BEGIN
CASE DIN(3 DOWNTO 0) IS
WHEN "0000" => p04 <= '1';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0001" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0010" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0011" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0100" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0101" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0110" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1000" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "1001" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1010" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1011" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1100" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1101" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1110" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '1';
WHEN OTHERS => NULL;
END CASE;
END PROCESS bitcount;
fghj <= (f AND g AND h AND j) OR (NOT f AND NOT g AND NOT h AND NOT j);
eifgh <= (e AND i AND f AND g AND h) OR (NOT e AND NOT i AND NOT f AND NOT g
AND NOT h);
sk28 <= (c AND d AND e AND i) OR (NOT c AND NOT d AND NOT e AND NOT i);
e_i <= (e AND NOT i) OR (NOT e AND i);
ighj <= (i AND g AND h AND j) OR (NOT i AND NOT g AND NOT h AND NOT j);
i_ghj <= (NOT i AND g AND h AND j) OR (i AND NOT g AND NOT h AND NOT j);
kx7 <= e_i AND ighj;
invr6 <= p40 OR p04 OR (p31 AND e AND i) OR (p13 AND NOT e AND NOT i);
pdbr6 <= (p31 AND (e OR i)) OR (p22 AND e AND i) OR p40;
ndbr6 <= (p13 AND (NOT e OR NOT i)) OR (p22 AND NOT e AND NOT i) OR p04;
pdur6 <= pdbr6 OR (d AND e AND i);
pdbr4 <= (f AND g AND (h OR j)) OR ((f OR g) AND h AND j);
ndrr4 <= pdbr4 OR (f AND g);
ndur6 <= ndbr6 OR (NOT d AND NOT e AND NOT i);
fgh <= (f AND g AND h) OR (NOT f AND NOT g AND NOT h);
ndbr4 <= (NOT f AND NOT g AND (NOT h OR NOT j)) OR ((NOT f OR NOT g) AND
NOT h AND NOT j);
pdrr4 <= ndbr4 OR (NOT f AND NOT g);
invby_a <= invr6;
invby_b <= fghj;
invby_c <= eifgh;
invby_d <= (NOT sk28 AND i_ghj);
invby_e <= (sk28 AND fgh);
invby_f <= (kx7 AND NOT pdbr6 AND NOT ndbr6);
invby_g <= (pdur6 AND ndrr4);
invby_h <= (ndur6 AND pdrr4);
--Update internal code error signal
code_err_i <= invby_a OR invby_b OR invby_c OR invby_d OR invby_e OR invby_f OR
invby_g OR invby_h;
END xilinx ;
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut_base.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Single-port Base Decoder for decoding 8b/10b
-- encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
library work;
USE work.decode_8b10b_pkg.ALL;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_lut_base IS
GENERIC (
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
DISP_IN : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
ND : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_lut_base;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_lut_base IS
-----------------------------------------------------------------------------
-- Type Declarations
-----------------------------------------------------------------------------
TYPE disparity IS (neg, pos, zero, invalid, specneg, specpos) ;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
-- set the default decoder output for invalid codes
CONSTANT DEFAULTB5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11111" ;
CONSTANT DEFAULTB3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111" ;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
SIGNAL code_err_i : STD_LOGIC := '0';
SIGNAL symrd : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b6_disp : disparity := zero;
SIGNAL b4_disp : disparity := zero;
SIGNAL b5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := DEFAULTB5;
SIGNAL b3 : STD_LOGIC_VECTOR(7 DOWNTO 5) := DEFAULTB3;
SIGNAL k : STD_LOGIC := '0';
SIGNAL k28 : STD_LOGIC := '0';
ALIAS b6 : STD_LOGIC_VECTOR(5 DOWNTO 0) IS DIN(5 DOWNTO 0) ; --iedcba
ALIAS b4 : STD_LOGIC_VECTOR(3 DOWNTO 0) IS DIN(9 DOWNTO 6) ; --jhgf
ALIAS a : STD_LOGIC IS DIN(0) ;
ALIAS b : STD_LOGIC IS DIN(1) ;
ALIAS c : STD_LOGIC IS DIN(2) ;
ALIAS d : STD_LOGIC IS DIN(3) ;
ALIAS e : STD_LOGIC IS DIN(4) ;
ALIAS i : STD_LOGIC IS DIN(5) ;
ALIAS f : STD_LOGIC IS DIN(6) ;
ALIAS g : STD_LOGIC IS DIN(7) ;
ALIAS h : STD_LOGIC IS DIN(8) ;
ALIAS j : STD_LOGIC IS DIN(9) ;
--Signals for calculating code_error
SIGNAL p04 : STD_LOGIC := '0';
SIGNAL p13 : STD_LOGIC := '0';
SIGNAL p22 : STD_LOGIC := '0';
SIGNAL p31 : STD_LOGIC := '0';
SIGNAL p40 : STD_LOGIC := '0';
SIGNAL fghj : STD_LOGIC := '0';
SIGNAL eifgh : STD_LOGIC := '0';
SIGNAL sK28 : STD_LOGIC := '0';
SIGNAL e_i : STD_LOGIC := '0';
SIGNAL ighj : STD_LOGIC := '0';
SIGNAL i_ghj : STD_LOGIC := '0';
SIGNAL kx7 : STD_LOGIC := '0';
SIGNAL invr6 : STD_LOGIC := '0';
SIGNAL pdbr6 : STD_LOGIC := '0';
SIGNAL ndbr6 : STD_LOGIC := '0';
SIGNAL pdur6 : STD_LOGIC := '0';
SIGNAL pdbr4 : STD_LOGIC := '0';
SIGNAL ndrr4 : STD_LOGIC := '0';
SIGNAL ndur6 : STD_LOGIC := '0';
SIGNAL ndbr4 : STD_LOGIC := '0';
SIGNAL pdrr4 : STD_LOGIC := '0';
SIGNAL fgh : STD_LOGIC := '0';
SIGNAL invby_a : STD_LOGIC := '0';
SIGNAL invby_b : STD_LOGIC := '0';
SIGNAL invby_c : STD_LOGIC := '0';
SIGNAL invby_d : STD_LOGIC := '0';
SIGNAL invby_e : STD_LOGIC := '0';
SIGNAL invby_f : STD_LOGIC := '0';
SIGNAL invby_g : STD_LOGIC := '0';
SIGNAL invby_h : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------
-- Conditionally tie optional ports to internal signals
-----------------------------------------------------------------------------
----New Data-----------------------------------------------------------------
gnd : IF (C_HAS_ND = 1) GENERATE
----Update the New Data output-------------------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF ((CE = '1') AND (SINIT = '1')) THEN
ND <= '0' AFTER TFF;
ELSE
ND <= CE AFTER TFF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gnd ;
----Code Error---------------------------------------------------------------
gcerr : IF (C_HAS_CODE_ERR = 1) GENERATE
----Update CODE_ERR output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
CODE_ERR <= '0' AFTER TFF;
ELSE
CODE_ERR <= code_err_i AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gcerr ;
-- The following code uses notation and logic from the 8b/10b specification
-------------------------------------------------------------------------------
-- Set the value of k28 signal
-------------------------------------------------------------------------------
k28 <= NOT((c OR d OR e OR i) OR NOT(h XOR j)) ;
-------------------------------------------------------------------------------
-- Do the 6B/5B conversion
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000110" => b5 <= "00000" ; --D.0
WHEN "111001" => b5 <= "00000" ; --D.0
WHEN "010001" => b5 <= "00001" ; --D.1
WHEN "101110" => b5 <= "00001" ; --D.1
WHEN "010010" => b5 <= "00010" ; --D.2
WHEN "101101" => b5 <= "00010" ; --D.2
WHEN "100011" => b5 <= "00011" ; --D.3
WHEN "010100" => b5 <= "00100" ; --D.4
WHEN "101011" => b5 <= "00100" ; --D.4
WHEN "100101" => b5 <= "00101" ; --D.5
WHEN "100110" => b5 <= "00110" ; --D.6
WHEN "000111" => b5 <= "00111" ; --D.7
WHEN "111000" => b5 <= "00111" ; --D.7
WHEN "011000" => b5 <= "01000" ; --D.8
WHEN "100111" => b5 <= "01000" ; --D.8
WHEN "101001" => b5 <= "01001" ; --D.9
WHEN "101010" => b5 <= "01010" ; --D.10
WHEN "001011" => b5 <= "01011" ; --D.11
WHEN "101100" => b5 <= "01100" ; --D.12
WHEN "001101" => b5 <= "01101" ; --D.13
WHEN "001110" => b5 <= "01110" ; --D.14
WHEN "000101" => b5 <= "01111" ; --D.15
WHEN "111010" => b5 <= "01111" ; --D.15
WHEN "110110" => b5 <= "10000" ; --D.16
WHEN "001001" => b5 <= "10000" ; --D.16
WHEN "110001" => b5 <= "10001" ; --D.17
WHEN "110010" => b5 <= "10010" ; --D.18
WHEN "010011" => b5 <= "10011" ; --D.19
WHEN "110100" => b5 <= "10100" ; --D.20
WHEN "010101" => b5 <= "10101" ; --D.21
WHEN "010110" => b5 <= "10110" ; --D.22
WHEN "010111" => b5 <= "10111" ; --D/K.23
WHEN "101000" => b5 <= "10111" ; --D/K.23
WHEN "001100" => b5 <= "11000" ; --D.24
WHEN "110011" => b5 <= "11000" ; --D.24
WHEN "011001" => b5 <= "11001" ; --D.25
WHEN "011010" => b5 <= "11010" ; --D.26
WHEN "011011" => b5 <= "11011" ; --D/K.27
WHEN "100100" => b5 <= "11011" ; --D/K.27
WHEN "011100" => b5 <= "11100" ; --D.28
WHEN "111100" => b5 <= "11100" ; --K.28
WHEN "000011" => b5 <= "11100" ; --K.28
WHEN "011101" => b5 <= "11101" ; --D/K.29
WHEN "100010" => b5 <= "11101" ; --D/K.29
WHEN "011110" => b5 <= "11110" ; --D.30
WHEN "100001" => b5 <= "11110" ; --D.30
WHEN "110101" => b5 <= "11111" ; --D.31
WHEN "001010" => b5 <= "11111" ; --D.31
WHEN OTHERS => b5 <= DEFAULTB5 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 6B block
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000000" => b6_disp <= neg ; --invalid ;
WHEN "000001" => b6_disp <= neg ; --invalid ;
WHEN "000010" => b6_disp <= neg ; --invalid ;
WHEN "000011" => b6_disp <= neg ; --K.28
WHEN "000100" => b6_disp <= neg ; --invalid ;
WHEN "000101" => b6_disp <= neg ; --D.15
WHEN "000110" => b6_disp <= neg ; --D.0
WHEN "000111" => b6_disp <= specneg; --D.7
WHEN "001000" => b6_disp <= neg ; --invalid ;
WHEN "001001" => b6_disp <= neg ; --D.16
WHEN "001010" => b6_disp <= neg ; --D.31
WHEN "001011" => b6_disp <= zero ; --D.11
WHEN "001100" => b6_disp <= neg ; --D.24
WHEN "001101" => b6_disp <= zero ; --D.13
WHEN "001110" => b6_disp <= zero ; --D.14
WHEN "001111" => b6_disp <= pos ; --invalid ;
WHEN "010000" => b6_disp <= neg ; --invalid ;
WHEN "010001" => b6_disp <= neg ; --D.1
WHEN "010010" => b6_disp <= neg ; --D.2
WHEN "010011" => b6_disp <= zero ; --D.19
WHEN "010100" => b6_disp <= neg ; --D.4
WHEN "010101" => b6_disp <= zero ; --D.21
WHEN "010110" => b6_disp <= zero ; --D.22
WHEN "010111" => b6_disp <= pos ; --D.23
WHEN "011000" => b6_disp <= neg ; --D.8
WHEN "011001" => b6_disp <= zero ; --D.25
WHEN "011010" => b6_disp <= zero ; --D.26
WHEN "011011" => b6_disp <= pos ; --D.27
WHEN "011100" => b6_disp <= zero ; --D.28
WHEN "011101" => b6_disp <= pos ; --D.29
WHEN "011110" => b6_disp <= pos ; --D.30
WHEN "011111" => b6_disp <= pos ; --invalid ;
WHEN "100000" => b6_disp <= neg ; --invalid ;
WHEN "100001" => b6_disp <= neg ; --D.30 ;
WHEN "100010" => b6_disp <= neg ; --D.29 ;
WHEN "100011" => b6_disp <= zero ; --D.3
WHEN "100100" => b6_disp <= neg ; --D.27
WHEN "100101" => b6_disp <= zero ; --D.5
WHEN "100110" => b6_disp <= zero ; --D.6
WHEN "100111" => b6_disp <= pos ; --D.8
WHEN "101000" => b6_disp <= neg ; --D.23
WHEN "101001" => b6_disp <= zero ; --D.9
WHEN "101010" => b6_disp <= zero ; --D.10
WHEN "101011" => b6_disp <= pos ; --D.4
WHEN "101100" => b6_disp <= zero ; --D.12
WHEN "101101" => b6_disp <= pos ; --D.2
WHEN "101110" => b6_disp <= pos ; --D.1
WHEN "101111" => b6_disp <= pos ; --invalid ;
WHEN "110000" => b6_disp <= neg ; --invalid ;
WHEN "110001" => b6_disp <= zero ; --D.17
WHEN "110010" => b6_disp <= zero ; --D.18
WHEN "110011" => b6_disp <= pos ; --D.24
WHEN "110100" => b6_disp <= zero ; --D.20
WHEN "110101" => b6_disp <= pos ; --D.31
WHEN "110110" => b6_disp <= pos ; --D.16
WHEN "110111" => b6_disp <= pos ; --invalid ;
WHEN "111000" => b6_disp <= specpos; --D.7
WHEN "111001" => b6_disp <= pos ; --D.0
WHEN "111010" => b6_disp <= pos ; --D.15
WHEN "111011" => b6_disp <= pos ; --invalid ;
WHEN "111100" => b6_disp <= pos ; --K.28
WHEN "111101" => b6_disp <= pos ; --invalid ;
WHEN "111110" => b6_disp <= pos ; --invalid ;
WHEN "111111" => b6_disp <= pos ; --invalid ;
WHEN OTHERS => b6_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Do the 3B/4B conversion
-------------------------------------------------------------------------------
PROCESS (b4, k28)
BEGIN
CASE b4 IS
WHEN "0010" => b3 <= "000" ; --D/K.x.0
WHEN "1101" => b3 <= "000" ; --D/K.x.0
WHEN "1001" =>
IF (k28 = '0')
THEN b3 <= "001" ; --D/K.x.1
ELSE b3 <= "110" ; --K28.6
END IF ;
WHEN "0110" =>
IF (k28 = '1')
THEN b3 <= "001" ; --K.28.1
ELSE b3 <= "110" ; --D/K.x.6
END IF ;
WHEN "1010" =>
IF (k28 = '0')
THEN b3 <= "010" ; --D/K.x.2
ELSE b3 <= "101" ; --K28.5
END IF ;
WHEN "0101" =>
IF (k28 = '1')
THEN b3 <= "010" ; --K28.2
ELSE b3 <= "101" ; --D/K.x.5
END IF ;
WHEN "0011" => b3 <= "011" ; --D/K.x.3
WHEN "1100" => b3 <= "011" ; --D/K.x.3
WHEN "0100" => b3 <= "100" ; --D/K.x.4
WHEN "1011" => b3 <= "100" ; --D/K.x.4
WHEN "0111" => b3 <= "111" ; --D.x.7
WHEN "1000" => b3 <= "111" ; --D.x.7
WHEN "1110" => b3 <= "111" ; --D/K.x.7
WHEN "0001" => b3 <= "111" ; --D/K.x.7
WHEN OTHERS => b3 <= DEFAULTB3 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 4B block
-------------------------------------------------------------------------------
PROCESS (b4)
BEGIN
CASE b4 IS
WHEN "0000" => b4_disp <= neg ;
WHEN "0001" => b4_disp <= neg ;
WHEN "0010" => b4_disp <= neg ;
WHEN "0011" => b4_disp <= specneg;
WHEN "0100" => b4_disp <= neg ;
WHEN "0101" => b4_disp <= zero ;
WHEN "0110" => b4_disp <= zero ;
WHEN "0111" => b4_disp <= pos ;
WHEN "1000" => b4_disp <= neg ;
WHEN "1001" => b4_disp <= zero ;
WHEN "1010" => b4_disp <= zero ;
WHEN "1011" => b4_disp <= pos ;
WHEN "1100" => b4_disp <= specpos;
WHEN "1101" => b4_disp <= pos ;
WHEN "1110" => b4_disp <= pos ;
WHEN "1111" => b4_disp <= pos ;
WHEN OTHERS => b4_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Special Code for calculating symrd[3:0]
--
-- +---------+---------+-------+------------+-------+------------+
-- | | | symrd |
-- | | | + Start Disp | - Start Disp |
-- | b6_disp | b4_disp | Error | NewRunDisp | Error | NewRunDisp |
-- +---------+---------+-------+------------+-------+------------+
-- | + | + | 1 | 1 | 1 | 1 |
-- | + | - | 1 | 0 | 0 | 0 |
-- | + | 0 | 1 | 1 | 0 | 1 |
-- | - | + | 0 | 1 | 1 | 1 |
-- | - | - | 1 | 0 | 1 | 0 |
-- | - | 0 | 0 | 0 | 1 | 0 |
-- | 0 | + | 1 | 1 | 0 | 1 |
-- | 0 | - | 0 | 0 | 1 | 0 |
-- | 0 | 0 | 0 | 1 | 0 | 0 |
-- +---------+---------+-------+------------+-------+------------+
--
-------------------------------------------------------------------------------
PROCESS (b4_disp, b6_disp)
BEGIN
CASE b6_disp IS
WHEN pos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "1000";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1101"; --Ex: D1.3-
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000";
WHEN zero => symrd(3 DOWNTO 0) <= "1101";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN neg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "0111";
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "0010"; --Ex: D1.3+
WHEN zero => symrd(3 DOWNTO 0) <= "0010";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN zero =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101";
WHEN neg => symrd(3 DOWNTO 0) <= "0010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D11.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D11.3-
WHEN zero => symrd(3 DOWNTO 0) <= "0100";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specpos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "0010"; --Ex: D7.0+
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1010";
WHEN zero => symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.5+
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specneg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101"; --Ex: D7.0-
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.3-
WHEN zero => symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.5-
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
END PROCESS;
-- the new running disparity is calculated from the input disparity
-- and the disparity of the 10-bit word
grdi : IF (C_HAS_DISP_IN = 1 AND C_HAS_RUN_DISP=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (DISP_IN = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdi;
-- the new running disparity is calculated from the old running disparity
-- and the disparity of the 10-bit word. run_disp is also used to
-- calculate disp_err and sym_disp when disp_in is not present
grdni : IF (C_HAS_DISP_IN /= 1 AND (C_HAS_RUN_DISP=1 OR
C_HAS_DISP_ERR=1 OR
C_HAS_SYM_DISP=1)) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (run_disp_i = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdni;
gde : IF (C_HAS_DISP_ERR = 1) GENERATE
-- the new disparity error is calculated from the old running disparity
-- and the error information from the 10-bit word
gdei : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (DISP_IN='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdei;
gdeni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (run_disp_i='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdeni;
END GENERATE gde;
gsd : IF (C_HAS_SYM_DISP = 1) GENERATE
gsdi : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (DISP_IN='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdi;
gsdni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (run_disp_i='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdni;
END GENERATE gsd;
-- map internal signals to outputs
run_disp <= run_disp_i;
sym_disp <= sym_disp_i;
-------------------------------------------------------------------------------
-- Decode the K codes
-------------------------------------------------------------------------------
PROCESS (c, d, e, i, g, h, j)
BEGIN
k <= (c AND d AND e AND i) OR NOT(c OR d OR e OR i) OR
((e XOR i) AND ((i AND g AND h AND j) OR
NOT(i OR g OR h OR j))) ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Update the outputs on the clock
-------------------------------------------------------------------------------
----Update DOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
dout_i <= str_to_slv(C_SINIT_DOUT, 8) AFTER TFF ;
ELSE
dout_i <= (b3 & b5) AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
DOUT <= dout_i;
----Update KOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
kout_i <= bint_2_sl(C_SINIT_KOUT) AFTER TFF;
ELSE
kout_i <= k AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
KOUT <= kout_i;
-------------------------------------------------------------------------------
-- Calculate code_error (uses notation from IBM spec)
-------------------------------------------------------------------------------
bitcount: PROCESS (DIN)
BEGIN
CASE DIN(3 DOWNTO 0) IS
WHEN "0000" => p04 <= '1';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0001" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0010" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0011" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0100" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0101" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0110" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1000" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "1001" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1010" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1011" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1100" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1101" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1110" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '1';
WHEN OTHERS => NULL;
END CASE;
END PROCESS bitcount;
fghj <= (f AND g AND h AND j) OR (NOT f AND NOT g AND NOT h AND NOT j);
eifgh <= (e AND i AND f AND g AND h) OR (NOT e AND NOT i AND NOT f AND NOT g
AND NOT h);
sk28 <= (c AND d AND e AND i) OR (NOT c AND NOT d AND NOT e AND NOT i);
e_i <= (e AND NOT i) OR (NOT e AND i);
ighj <= (i AND g AND h AND j) OR (NOT i AND NOT g AND NOT h AND NOT j);
i_ghj <= (NOT i AND g AND h AND j) OR (i AND NOT g AND NOT h AND NOT j);
kx7 <= e_i AND ighj;
invr6 <= p40 OR p04 OR (p31 AND e AND i) OR (p13 AND NOT e AND NOT i);
pdbr6 <= (p31 AND (e OR i)) OR (p22 AND e AND i) OR p40;
ndbr6 <= (p13 AND (NOT e OR NOT i)) OR (p22 AND NOT e AND NOT i) OR p04;
pdur6 <= pdbr6 OR (d AND e AND i);
pdbr4 <= (f AND g AND (h OR j)) OR ((f OR g) AND h AND j);
ndrr4 <= pdbr4 OR (f AND g);
ndur6 <= ndbr6 OR (NOT d AND NOT e AND NOT i);
fgh <= (f AND g AND h) OR (NOT f AND NOT g AND NOT h);
ndbr4 <= (NOT f AND NOT g AND (NOT h OR NOT j)) OR ((NOT f OR NOT g) AND
NOT h AND NOT j);
pdrr4 <= ndbr4 OR (NOT f AND NOT g);
invby_a <= invr6;
invby_b <= fghj;
invby_c <= eifgh;
invby_d <= (NOT sk28 AND i_ghj);
invby_e <= (sk28 AND fgh);
invby_f <= (kx7 AND NOT pdbr6 AND NOT ndbr6);
invby_g <= (pdur6 AND ndrr4);
invby_h <= (ndur6 AND pdrr4);
--Update internal code error signal
code_err_i <= invby_a OR invby_b OR invby_c OR invby_d OR invby_e OR invby_f OR
invby_g OR invby_h;
END xilinx ;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: TODO
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY PoC;
USE PoC.utils.ALL;
ENTITY arith_counter_ring IS
GENERIC (
BITS : POSITIVE;
INVERT_FEEDBACK : BOOLEAN := FALSE -- FALSE -> ring counter; TRUE -> johnson counter
);
PORT (
Clock : IN STD_LOGIC; -- Clock
Reset : IN STD_LOGIC; -- Reset
seed : IN STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0'); -- initial counter vector / load value
inc : IN STD_LOGIC := '0'; -- increment counter
dec : IN STD_LOGIC := '0'; -- decrement counter
value : OUT STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) -- counter value
);
END;
ARCHITECTURE rtl OF arith_counter_ring IS
CONSTANT INVERT : STD_LOGIC := to_sl(INVERT_FEEDBACK);
SIGNAL counter : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS(Clock)
BEGIN
IF rising_edge(Clock) THEN
IF (Reset = '1') THEN
counter <= seed;
ELSE
IF (inc = '1') THEN
counter <= counter(counter'high - 1 DOWNTO 0) & (counter(counter'high) XOR INVERT);
ELSIF (dec = '1') THEN
counter <= (counter(0) XOR INVERT) & counter(counter'high DOWNTO 1);
END IF;
END IF;
END IF;
END PROCESS;
value <= counter;
END;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: TODO
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY PoC;
USE PoC.utils.ALL;
ENTITY arith_counter_ring IS
GENERIC (
BITS : POSITIVE;
INVERT_FEEDBACK : BOOLEAN := FALSE -- FALSE -> ring counter; TRUE -> johnson counter
);
PORT (
Clock : IN STD_LOGIC; -- Clock
Reset : IN STD_LOGIC; -- Reset
seed : IN STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0'); -- initial counter vector / load value
inc : IN STD_LOGIC := '0'; -- increment counter
dec : IN STD_LOGIC := '0'; -- decrement counter
value : OUT STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) -- counter value
);
END;
ARCHITECTURE rtl OF arith_counter_ring IS
CONSTANT INVERT : STD_LOGIC := to_sl(INVERT_FEEDBACK);
SIGNAL counter : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS(Clock)
BEGIN
IF rising_edge(Clock) THEN
IF (Reset = '1') THEN
counter <= seed;
ELSE
IF (inc = '1') THEN
counter <= counter(counter'high - 1 DOWNTO 0) & (counter(counter'high) XOR INVERT);
ELSIF (dec = '1') THEN
counter <= (counter(0) XOR INVERT) & counter(counter'high DOWNTO 1);
END IF;
END IF;
END IF;
END PROCESS;
value <= counter;
END;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
ENTITY counter_fifo_tb IS
END ENTITY;
ARCHITECTURE counter_fifo_arch OF counter_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from counter_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of counter_fifo_synth
counter_fifo_synth_inst:counter_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.865e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.865e-05,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 7.395e-05
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.8e-06,
W => Wcm_1,
Wcm_1init => 6.2e-06,
scope => private
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.8e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.09e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net2
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:44:27 06/21/2014
-- Design Name:
-- Module Name: usbgen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity usbgen is generic (
bitclk_period : time := 1 ns );
PORT(
go : in std_logic := '0';
d_p : out std_logic := '0';
d_n : out std_logic := '1';
dummy_clk : out std_logic;
dummy_idle : out std_logic;
dummy_in_sop : out std_logic;
dummy_in_pid : out std_logic);
end usbgen;
architecture arch_usbgen of usbgen is
signal in_sop : std_logic := '1';
signal in_pid : std_logic := '1';
signal idle : std_logic := '1';
-- The source of the packet signals the Start of Packet (SOP) in high-speed mode by driving the D+ and D- lines
-- from the high-speed Idle state to the K state. This K is the first symbol of the SYNC pattern (NRZI sequence
-- KJKJKJKJ KJKJKJKJ KJKJKJKJ KJKJKJKK) as described in Section 7.1.10.
constant sop : std_logic_vector(31 downto 0) := "10101010101010101010101010101000";
constant pid : std_logic_vector(7 downto 0) := "11010111";
begin
idle <= not (not in_sop or not in_pid);
dummy_idle <= idle;
dummy_in_sop <= in_sop;
dummy_in_pid <= in_pid;
dummy_clk_process :process
begin
wait until (go'event and go = '1');
while go = '1' loop
dummy_clk <= '0';
wait for bitclk_period/2;
dummy_clk <= '1';
wait for bitclk_period/2;
end loop;
end process;
data_process: process
begin
wait until (go'event and go = '1');
wait for bitclk_period*10;
-- start of packet / sync period
in_sop <= '0';
for i in sop'low to sop'high loop
d_p <= sop(sop'high - i);
d_n <= not sop(sop'high - i);
wait for bitclk_period;
end loop;
in_sop <= '1';
-- PID data
in_pid <= '0';
for i in pid'low to pid'high loop
d_p <= pid(pid'high - i);
d_n <= not pid(pid'high - i);
wait for bitclk_period;
end loop;
in_pid <= '1';
end process;
end arch_usbgen;
|
-- Copyright (C) 2015, Charles Steinkuehler
-- <charles AT steinkuehler DOT net>
-- All rights reserved
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of the copyright holder nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package Reg_Pkg is
-- Handy data types
subtype NIBBLE_T is std_logic_vector( 3 downto 0);
subtype BYTE_T is std_logic_vector( 7 downto 0);
subtype WORD_T is std_logic_vector( 15 downto 0);
subtype DWORD_T is std_logic_vector( 31 downto 0);
subtype QWORD_T is std_logic_vector( 63 downto 0);
subtype DQWORD_T is std_logic_vector(127 downto 0);
type NIBBLE_A is array (natural range <>) of NIBBLE_T;
type BYTE_A is array (natural range <>) of BYTE_T;
type WORD_A is array (natural range <>) of WORD_T;
type DWORD_A is array (natural range <>) of DWORD_T;
type QWORD_A is array (natural range <>) of QWORD_T;
type DQWORD_A is array (natural range <>) of DQWORD_T;
-------------------------
-- Register Interfaces --
-------------------------
-- Generic single register write interface
type RegWr_T is record
data : QWORD_T;
be : std_logic_vector(7 downto 0);
we : std_logic;
end record RegWr_T;
type RegWr_A is array (natural range <>) of RegWr_T;
-- Generic register write interface (entire register space)
-- 256 individual 64-bit registers
type RegWrA_T is record
data : QWORD_T;
be : std_logic_vector(7 downto 0);
we : std_logic_vector(255 downto 0);
addr : std_logic_vector(7 downto 0);
wren : std_logic;
sel : std_logic;
end record RegWrA_T;
-- FIFO style interface that doesn't need decodes or full address space
-- ie: do a burst write to sequential addresses to write lots of data to
-- a single destination like a transmit FIFO
type FIFORegWrA_T is record
data : QWORD_T;
be : std_logic_vector(7 downto 0);
addr : std_logic_vector(1 downto 0);
wren : std_logic;
sel : std_logic;
end record FIFORegWrA_T;
-- Array of register readback values
type RegRd_A is array (natural range <>) of QWORD_T;
-- Calculate the number of bits required to represent a given value
function NumBits (val : integer) return integer;
end package Reg_Pkg;
package body Reg_Pkg is
-- Calculate the number of bits required to represent a given value
function NumBits(val : integer) return integer is
variable result : integer;
begin
if val=0 then
result := 0;
else
result := natural(ceil(log2(real(val))));
end if;
return result;
end;
end package body Reg_Pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1572.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01572ent IS
END c08s10b00x00p03n01i01572ent;
ARCHITECTURE c08s10b00x00p03n01i01572arch OF c08s10b00x00p03n01i01572ent IS
BEGIN
TESTING: PROCESS
-- Local variables
variable DIDIT : BOOLEAN;
variable CONSTONE : INTEGER := 1;
variable k : integer := 0;
BEGIN
-- TEST1: Should always go to outer loop.
OUTERLOOP:
for I in 1 to 10 loop
INNERLOOP:
for J in 1 to 10 loop
-- Skip to next iteration of outerloop.
next OUTERLOOP;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop INNERLOOP;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop OUTERLOOP;
-- TEST2: Should always go to inner loop.
-- Set the flag initially.
DIDIT := TRUE;
-- Execute the loops.
OUTERLOOP2:
for I in 1 to 10 loop
INNERLOOP2:
for J in 1 to 10 loop
-- Check that last statement of OUTERLOOP2 got done.
if (J = 1) then
assert (DIDIT)
report "Last statement of OUTERLOOP2 was not executed.";
if (DIDIT /= true) then
k := 1;
end if;
DIDIT := FALSE;
end if;
-- Skip to next iteration of outerloop.
next INNERLOOP2;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop INNERLOOP2;
-- This should ALWAYS be executed.
DIDIT := TRUE;
end loop OUTERLOOP2;
assert NOT(k=0)
report "***PASSED TEST: c08s10b00x00p03n01i01572"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s10b00x00p03n01i01572 - The NEXT statement did not properly associated with the loop whose label it matchs."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01572arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1572.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01572ent IS
END c08s10b00x00p03n01i01572ent;
ARCHITECTURE c08s10b00x00p03n01i01572arch OF c08s10b00x00p03n01i01572ent IS
BEGIN
TESTING: PROCESS
-- Local variables
variable DIDIT : BOOLEAN;
variable CONSTONE : INTEGER := 1;
variable k : integer := 0;
BEGIN
-- TEST1: Should always go to outer loop.
OUTERLOOP:
for I in 1 to 10 loop
INNERLOOP:
for J in 1 to 10 loop
-- Skip to next iteration of outerloop.
next OUTERLOOP;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop INNERLOOP;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop OUTERLOOP;
-- TEST2: Should always go to inner loop.
-- Set the flag initially.
DIDIT := TRUE;
-- Execute the loops.
OUTERLOOP2:
for I in 1 to 10 loop
INNERLOOP2:
for J in 1 to 10 loop
-- Check that last statement of OUTERLOOP2 got done.
if (J = 1) then
assert (DIDIT)
report "Last statement of OUTERLOOP2 was not executed.";
if (DIDIT /= true) then
k := 1;
end if;
DIDIT := FALSE;
end if;
-- Skip to next iteration of outerloop.
next INNERLOOP2;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop INNERLOOP2;
-- This should ALWAYS be executed.
DIDIT := TRUE;
end loop OUTERLOOP2;
assert NOT(k=0)
report "***PASSED TEST: c08s10b00x00p03n01i01572"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s10b00x00p03n01i01572 - The NEXT statement did not properly associated with the loop whose label it matchs."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01572arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1572.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01572ent IS
END c08s10b00x00p03n01i01572ent;
ARCHITECTURE c08s10b00x00p03n01i01572arch OF c08s10b00x00p03n01i01572ent IS
BEGIN
TESTING: PROCESS
-- Local variables
variable DIDIT : BOOLEAN;
variable CONSTONE : INTEGER := 1;
variable k : integer := 0;
BEGIN
-- TEST1: Should always go to outer loop.
OUTERLOOP:
for I in 1 to 10 loop
INNERLOOP:
for J in 1 to 10 loop
-- Skip to next iteration of outerloop.
next OUTERLOOP;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop INNERLOOP;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop OUTERLOOP;
-- TEST2: Should always go to inner loop.
-- Set the flag initially.
DIDIT := TRUE;
-- Execute the loops.
OUTERLOOP2:
for I in 1 to 10 loop
INNERLOOP2:
for J in 1 to 10 loop
-- Check that last statement of OUTERLOOP2 got done.
if (J = 1) then
assert (DIDIT)
report "Last statement of OUTERLOOP2 was not executed.";
if (DIDIT /= true) then
k := 1;
end if;
DIDIT := FALSE;
end if;
-- Skip to next iteration of outerloop.
next INNERLOOP2;
k := 1;
-- This should never be executed.
assert (FALSE)
report "Statement should never be executed.";
end loop INNERLOOP2;
-- This should ALWAYS be executed.
DIDIT := TRUE;
end loop OUTERLOOP2;
assert NOT(k=0)
report "***PASSED TEST: c08s10b00x00p03n01i01572"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s10b00x00p03n01i01572 - The NEXT statement did not properly associated with the loop whose label it matchs."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01572arch;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable concatted : string(1 to 6);
begin -- process doit
concatted := "foo" & "bar";
assert concatted = "foobar" report "TEST FAILED - concatted was not 'foobar'" severity failure;
assert not(concatted = "foobar") report "TEST PASSED" severity note;
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable concatted : string(1 to 6);
begin -- process doit
concatted := "foo" & "bar";
assert concatted = "foobar" report "TEST FAILED - concatted was not 'foobar'" severity failure;
assert not(concatted = "foobar") report "TEST PASSED" severity note;
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable concatted : string(1 to 6);
begin -- process doit
concatted := "foo" & "bar";
assert concatted = "foobar" report "TEST FAILED - concatted was not 'foobar'" severity failure;
assert not(concatted = "foobar") report "TEST PASSED" severity note;
wait;
end process doit;
end only;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fx2async is
port (
fx2_wr_full_i : in STD_LOGIC;
fx2_rd_empty_i : in STD_LOGIC;
fx2_data_io : inout STD_LOGIC_VECTOR (7 downto 0);
fx2_fifo_addr_o : out STD_LOGIC_VECTOR (1 downto 0);
fx2_slwr_o : out STD_LOGIC;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slcs_o : out std_logic;
fx2_pktend_o : out STD_LOGIC;
usb_data_i : in std_logic_vector(7 downto 0);
usb_data_o : out std_logic_vector(7 downto 0);
usb_wr_en_i : in std_logic;
usb_rd_en_i : in std_logic;
usb_wr_strobe_o : out std_logic;
usb_rd_strobe_o : out std_logic;
usb_pktend_i : in std_logic;
usb_pktstart_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end fx2async;
architecture Behavioral of fx2async is
type mode is (USB_RD1, USB_RD2, USB_WR1, USB_WR2);
signal state: mode;
signal wr, rd: std_logic;
signal rd_empty, wr_full: std_logic;
signal delay: std_logic_vector(3 downto 0);
signal data_i, data_i_r1, data_i_r2 : std_logic_vector(7 downto 0);
signal rd_empty_r1, rd_empty_r2 : std_logic;
signal wr_full_r1, wr_full_r2 : std_logic;
signal pktend_pending : std_logic;
signal usb_rd_strobe, usb_wr_strobe : std_logic;
begin
fx2_slcs_o <= '0';
fx2_slrd_o <= not rd;
fx2_sloe_o <= not rd;
fx2_slwr_o <= not wr;
usb_wr_strobe_o <= usb_wr_strobe;
usb_rd_strobe_o <= usb_rd_strobe;
process
begin
wait until rising_edge(clk_i);
-- flags und daten eintakten
rd_empty_r1 <= fx2_rd_empty_i;
rd_empty_r2 <= rd_empty_r1;
rd_empty <= rd_empty_r2;
wr_full_r1 <= fx2_wr_full_i;
wr_full_r2 <= wr_full_r1;
wr_full <= wr_full_r2;
data_i_r1 <= fx2_data_io;
data_i_r2 <= data_i_r1;
data_i <= data_i_r2;
usb_wr_strobe <= '0';
usb_rd_strobe <= '0';
if usb_rd_strobe = '1' and rd_empty = '1' then
usb_pktstart_o <= '0';
end if;
if rd_empty = '0' then
usb_pktstart_o <= '1';
end if;
if rst_i = '1' then
wr <= '0';
rd <= '0';
fx2_data_io <= (others => 'Z');
fx2_pktend_o <= '1';
state <= USB_RD1;
fx2_fifo_addr_o <= "00"; -- read - write: 10
pktend_pending <= '0';
else
if usb_pktend_i = '1' then
pktend_pending <= '1';
end if;
delay <= delay + 1;
if delay = "0000" then
wr <= '0';
rd <= '0';
fx2_data_io <= (others => 'Z');
fx2_pktend_o <= '1';
if pktend_pending = '1' then
fx2_pktend_o <= '0';
pktend_pending <= '0';
end if;
case state is
when USB_RD1 =>
if usb_rd_en_i = '1' and rd_empty = '1' then
rd <= '1';
state <= USB_RD2;
elsif usb_wr_en_i = '1' and wr_full = '1' then
state <= USB_WR1;
fx2_fifo_addr_o <= "10";
end if;
when USB_RD2 =>
usb_data_o <= data_i;
usb_rd_strobe <= '1';
state <= USB_RD1;
when USB_WR1 =>
if usb_wr_en_i = '1' and wr_full = '1' then
fx2_data_io <= usb_data_i;
usb_wr_strobe <= '1';
wr <= '1';
state <= USB_WR2;
elsif usb_rd_en_i = '1' and rd_empty = '1' then
state <= USB_RD1;
fx2_fifo_addr_o <= "00";
end if;
when USB_WR2 =>
state <= USB_WR1;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:13 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top RAT_slice_12_8_0 -prefix
-- RAT_slice_12_8_0_ RAT_xlslice_0_0_stub.vhdl
-- Design : RAT_xlslice_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_slice_12_8_0 is
Port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end RAT_slice_12_8_0;
architecture stub of RAT_slice_12_8_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Din[17:0],Dout[4:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "xlslice,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:13 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top RAT_slice_12_8_0 -prefix
-- RAT_slice_12_8_0_ RAT_xlslice_0_0_stub.vhdl
-- Design : RAT_xlslice_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_slice_12_8_0 is
Port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end RAT_slice_12_8_0;
architecture stub of RAT_slice_12_8_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Din[17:0],Dout[4:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "xlslice,Vivado 2016.4";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera_mf;
use altera_mf.all;
entity adqin is
port(
clk : in std_logic;
dq_pad : in std_logic; -- DQ pad
dq_h : out std_logic;
dq_l : out std_logic;
config_clk : in std_logic;
config_clken : in std_logic;
config_datain : in std_logic;
config_update : in std_logic
);
end;
architecture rtl of adqin is
component cycloneiii_io_ibuf is
generic (
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
port (
i : in std_logic := '0';
ibar : in std_logic := '0';
o : out std_logic
);
end component;
component altddio_in
generic (
intended_device_family : string;
invert_input_clocks : string;
lpm_type : string;
power_up_high : string;
width : natural
);
port (
datain : in std_logic_vector (0 downto 0);
inclock : in std_logic ;
dataout_h : out std_logic_vector (0 downto 0);
dataout_l : out std_logic_vector (0 downto 0)
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal inputdelay : std_logic_vector(3 downto 0);
signal dq_buf, dq_h_tmp, dq_l_tmp : std_logic_vector(0 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
-- In buffer (DQ) --------------------------------------------------------------------
dq_buf0 : cycloneiii_io_ibuf
generic map(
differential_mode => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_ibuf"
)
port map(
i => dq_pad,
ibar => open,
o => dq_buf(0)
);
-- Input capture register (DQ) -------------------------------------------------------
altddio_in_component : altddio_in
generic map (
intended_device_family => "Cyclone III",
invert_input_clocks => "off",
lpm_type => "altddio_in",
power_up_high => "off",
width => 1
)
port map (
datain => dq_buf,
inclock => clk,
dataout_h => dq_h_tmp,
dataout_l => dq_l_tmp
);
dq_h <= dq_h_tmp(0); dq_l <= dq_l_tmp(0);
-- dq_reg0 : cycloneiii_ddio_in
-- generic map(
-- power_up => "low",
-- async_mode => "clear",
-- sync_mode => "none",
-- use_clkn => "false",
-- lpm_type => "cycloneiii_ddio_in"
-- )
-- port map(
-- datain => dq_dq_buf,
-- clk => clk,
-- clkn => open,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- regoutlo => dq_l,
-- regouthi => dq_h
-- --dfflo : out std_logic;
-- --devclrn : in std_logic := '1';
-- --devpor : in std_logic := '1'
-- );
end;
|
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