content stringlengths 1 1.04M ⌀ |
|---|
PACKAGE p IS
CONSTANT a : INTEGER := 2#1101#;
CONSTANT b : INTEGER := 3#20#;
CONSTANT c : INTEGER := 8#7#;
CONSTANT d : INTEGER := 10#1234#;
CONSTANT e : INTEGER := 16#beef01#;
CONSTANT f : INTEGER := 2#1_0#;
CONSTANT g : INTEGER := 2:1_0:;
CONSTANT h : INTEGER := 16#abababab#;
CONSTANT i : INTEGER := 16#1A#;
CONSTANT j : INTEGER := 2#1111_1111#;
CONSTANT k : INTEGER := 16#FF#;
CONSTANT l : INTEGER := 016#0FF#;
CONSTANT m : INTEGER := 16#E#E1;
CONSTANT n : INTEGER := 2#1110_0000#;
CONSTANT o : REAL := 16#F.FF#E+2;
CONSTANT p : REAL := 2#1.1111_1111_111#E11;
CONSTANT n : INTEGER := 2:1110_0000:;
CONSTANT o : REAL := 16:F.FF:E+2;
END PACKAGE;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- USE ieee.numeric_std.ALL;
use std.textio.all;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
entity testbench is
generic(
width : natural :=16
);
port(
output : out std_logic_vector(width-1 downto 0)
);
end testbench;
architecture arch_testbench of testbench is
signal clock : std_logic := '0';
signal reset_signal : std_logic;
signal endoffile : std_logic := '0';
signal dataread : real ;
signal datawrite : real ;
signal linenumber : natural;
signal input_signal : std_logic_vector(width-1 downto 0);
signal output_signal: std_logic_vector(width-1 downto 0);
signal output_signal1: SIGNED(width-1 downto 0);
-- COMPONENT StructuralDecimator is
-- Port ( input: in std_logic_vector(11 downto 0);
-- output: out std_logic_vector(15 downto 0);
-- clk :in std_logic;
-- reset:in std_logic
-- );
-- END COMPONENT StructuralDecimator;
-- COMPONENT EffectEcho is
-- generic (
-- wordLength : natural := 16;
-- constantsWordLength : natural := 16
-- );
-- port (
-- input : in std_logic_vector(wordLength-1 downto 0);
-- output : out std_logic_vector(wordLength-1 downto 0);
--
-- clk : in std_logic;
-- reset : in std_logic
-- );
--end COMPONENT ;
begin
-- decimator_comp: COMPONENT StructuralDecimator
-- PORT MAP(clk=>clock,
-- reset=>reset_signal,
-- input=>input_signal,
-- output=>output_signal
-- );
-- EffectEcho_comp: COMPONENT EffectEcho
-- PORT MAP(clk=>clock,
-- reset=>reset_signal,
-- input=>input_signal,
-- output=>output_signal
-- );
test_comp: entity work.Generic_Equalizer_Low_Pass
port map (input => input_signal,
output => output_signal,
clk=> clock,
reset => reset_signal
);
reset_signal<='0',
'1' AFTER 15 ns,
'0' AFTER 25 ns;
clk_proc:process
begin
wait for 25 us;
clock<=NOT(clock);
end process clk_proc;
reading:process
file infile : text is in "Input.txt"; --declare input file
variable inline : line; --line number declaration
variable dataread1 : real;
begin
wait until clock = '1' and clock'event;
if (not endfile(infile)) then --checking the "END OF FILE" is not reached.
readline(infile, inline);
read(inline, dataread1);
dataread <=dataread1; --put the value available in variable in a signal.
else
endoffile <='1'; --set signal to tell end of file read file is reached.
end if;
end process reading;
input_signal <= STD_LOGIC_VECTOR(CONV_SIGNED(INTEGER(dataread*65536.0),width));-- 12 =width
output_signal1 <= SIGNED(output_signal(15 downto 0));
--output_signal1 <= SIGNED(input_signal(15 downto 0));
datawrite <= REAL(CONV_INTEGER(output_signal1))/65536.0 ;
writing:process
file outfile : text is out "Output_Low.txt"; --declare output file
variable outline : line; --line number declaration
begin
wait until clock = '0' and clock'event;
if(endoffile='0') then write(outline, datawrite, left, 16, 12);--write(linenumber,value(real type),justified(side),field(width),digits(natural));
writeline(outfile, outline);
linenumber <= linenumber + 1;
else
null;
end if;
end process writing;
end arch_testbench; |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Syndrome_Calculator_1
-- Module Name: Tb_Syndrome_Calculator_1
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for syndrome_calculator_1 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- file_memory_L :
--
-- The file that holds all support elements L.
-- This is part of the private key of the cryptosystem.
--
-- file_memory_h :
--
-- The file that holds all inverted evaluations of support elements L in polynomial g.
-- Therefore, g(L)^-1.
-- This is part of the private key of the cryptosystem.
--
-- file_memory_codeword :
--
-- The file that holds the received ciphertext necessary for computing the syndrome.
--
-- file_memory_syndrome :
--
-- The file that holds the syndrome previously computed.
-- This is necessary to be compared with circuit computed syndrome to verify if it worked.
--
-- dump_file_memory_syndrome :
--
-- The file that will hold the computed syndrome by the circuit.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_1 Rev 1.0
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_syndrome_calculator_1 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
gf_2_m : integer range 1 to 20 := 6;
length_codeword : integer := 52;
size_codeword : integer := 6;
length_syndrome : integer := 8;
size_syndrome : integer := 3;
file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_52_28_4_6.dat";
dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_2048_1751_27_11.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_2048_1498_50_11.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 132;
-- size_syndrome : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_3307_2515_66_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 64;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_2528_2144_32_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_2816_2048_64_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_3328_2560_64_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_7296_5632_128_13.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_7296_5632_128_13.dat"
);
end tb_syndrome_calculator_1;
architecture Behavioral of tb_syndrome_calculator_1 is
component syndrome_calculator_1
Generic(
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer;
size_codeword : integer;
length_syndrome : integer;
size_syndrome : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_h : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(0 downto 0);
signal syndrome_finalized : STD_LOGIC;
signal write_enable_new_syndrome : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal address_h : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_L : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal test_address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal true_address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal test_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal error_syndrome : STD_LOGIC;
signal test_syndrome_dump : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for mem_L : ram use entity work.ram(file_load);
for mem_h : ram use entity work.ram(file_load);
for mem_codeword : ram use entity work.ram(file_load);
for test_syndrome : ram use entity work.ram(simple);
for true_syndrome : ram use entity work.ram(file_load);
begin
test : syndrome_calculator_1
Generic Map(
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
length_syndrome => length_syndrome,
size_syndrome => size_syndrome
)
Port Map(
clk => clk,
rst => rst,
value_h => value_h,
value_L => value_L,
value_syndrome => test_value_syndrome,
value_codeword => value_codeword,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
new_value_syndrome => new_value_syndrome,
address_h => address_h,
address_L => address_L,
address_codeword => address_codeword,
address_syndrome => test_address_syndrome
);
mem_L : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_L,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_L,
rst_value => (others => '0'),
data_out => value_L
);
mem_h : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_h,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_h,
rst_value => (others => '0'),
data_out => value_h
);
mem_codeword : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_codeword,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_codeword,
rst_value => (others => '0'),
data_out => value_codeword
);
test_syndrome : ram
Generic Map(
ram_address_size => size_syndrome,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_file_memory_syndrome
)
Port Map(
data_in => new_value_syndrome,
rw => write_enable_new_syndrome,
clk => clk,
rst => rst,
dump => test_syndrome_dump,
address => address_syndrome,
rst_value => (others => '0'),
data_out => test_value_syndrome
);
true_syndrome : ram
Generic Map(
ram_address_size => size_syndrome,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_syndrome,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_syndrome,
rst_value => (others => '0'),
data_out => true_value_syndrome
);
address_syndrome <= true_address_syndrome when syndrome_finalized = '1' else test_address_syndrome;
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
process
variable i : integer;
begin
true_address_syndrome <= (others => '0');
rst <= '1';
error_syndrome <= '0';
test_syndrome_dump <= '0';
wait for PERIOD*2;
rst <= '0';
wait until syndrome_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_syndrome)) loop
true_address_syndrome <= std_logic_vector(to_unsigned(i, test_address_syndrome'Length));
wait for PERIOD*2;
if (true_value_syndrome = test_value_syndrome) then
error_syndrome <= '0';
else
error_syndrome <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_syndrome <= '0';
wait for PERIOD;
i := i + 1;
end loop;
test_syndrome_dump <= '1';
wait for PERIOD;
test_syndrome_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- The BUS unit.
-- Implements the BUS port logic.
--
-- $Id: db_bus.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity t48_db_bus is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
ea_i : in std_logic;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_bus_i : in boolean;
read_bus_i : in boolean;
-- BUS Interface ----------------------------------------------------------
output_pcl_i : in boolean;
bidir_bus_i : in boolean;
pcl_i : in word_t;
db_i : in word_t;
db_o : out word_t;
db_dir_o : out std_logic
);
end t48_db_bus;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.to_stdLogic;
architecture rtl of t48_db_bus is
-- the BUS output register
signal bus_q : word_t;
-- BUS direction marker
signal db_dir_q,
db_dir_qq : std_logic;
begin
-----------------------------------------------------------------------------
-- Process bus_regs
--
-- Purpose:
-- Implements the BUS output register.
--
bus_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
bus_q <= (others => '0');
db_dir_q <= '0';
db_dir_qq <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_bus_i then
db_dir_qq <= '1';
else
-- extend bus direction by one machine cycle
db_dir_qq <= db_dir_q;
end if;
if write_bus_i then
bus_q <= data_i;
db_dir_q <= '1';
elsif ea_i = '1' or bidir_bus_i then
db_dir_q <= '0';
end if;
end if;
end if;
end process bus_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
db_o <= pcl_i
when output_pcl_i else
bus_q;
db_dir_o <= db_dir_qq or
to_stdLogic(output_pcl_i);
data_o <= (others => bus_idle_level_c)
when not read_bus_i else
db_i;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/06/09 22:16:26 arniml
-- Implement db_dir_o glitch-safe
--
-- Revision 1.3 2004/10/25 20:30:18 arniml
-- delay db_dir_o by one machine cycle
-- this fixes the timing relation between BUS data and WR'
--
-- Revision 1.2 2004/04/04 14:15:45 arniml
-- add dump_compare support
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(74-1 DOWNTO 0);
DOUT : OUT std_logic_vector(74-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
--library synplify;
--use synplify.attributes.all;
-- pragma translate_on
entity pcstack is
generic(
depth:integer:=16;
awidth:integer:=4;
width:integer:=8
);
port (
reset : in std_logic;
clk: in std_logic;
en: in std_logic;
pop_push: in std_logic;
din: in std_logic_vector(width-1 downto 0);
dout: out std_logic_vector(width-1 downto 0)
);
end pcstack;
architecture behavior of pcstack is
type mem is array(0 to depth-1) of std_logic_vector(width-1 downto 0);
signal ram: mem:=(others=>(others=>'0'));
signal addr:std_logic_vector( awidth-1 downto 0 ):=(others=>'0');
component StackP is
generic (
width : integer
);
port(
reset: in std_logic;
en: in std_logic;
clk: in std_logic;
pop_push: in std_logic;
addr: out std_logic_vector(width-1 downto 0)
);
end component;
begin
astackP:stackP
generic map(
width => awidth
)
port map(
reset => reset,
en => en,
clk => clk,
pop_push => pop_push,
addr => addr
);
dout <= ram(conv_integer(addr));
process(clk)
begin
if rising_edge(clk) then
if en='1' and pop_push='1' then
--push stack
ram(conv_integer(addr))<=din;
end if;
end if;
end process;
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoBCD is
port(
ena: in std_logic; --Estara conectado al anodo del BCD para habilitarlo o no
count: in std_logic_vector(3 downto 0); --Bits del contador
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic;
anod: out std_logic
);
end;
architecture decoBCD_arq of decoBCD is
begin
--El 7 segmentos funciona con logica invertida
process(count,ena) --Se va a activar con un cambio de valor o con un cambio de enable
begin
--Seteo todas las salidas en 0 para solo "apagar" las que necesite por cada numero
a <= '0';
b <='0';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
g <= '0';
dp <= '1'; --En este caso siempre apagado
CHECK: case to_integer(unsigned(count)) is
when 0 =>
g <= '1';
when 1 =>
a <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
when 2 =>
c <= '1';
f <= '1';
when 3 =>
e <= '1';
f <= '1';
when 4 =>
a <= '1';
d <= '1';
e <= '1';
when 5 =>
b <= '1';
e <= '1';
when 6 =>
b <= '1';
when 7 =>
d <= '1';
e <= '1';
f <= '1';
g <= '1';
when 8 =>
--no cambia nada
when 9 =>
d <= '1';
e <= '1';
when others =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
end case CHECK;
anod <= not(ena);
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoBCD is
port(
ena: in std_logic; --Estara conectado al anodo del BCD para habilitarlo o no
count: in std_logic_vector(3 downto 0); --Bits del contador
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic;
anod: out std_logic
);
end;
architecture decoBCD_arq of decoBCD is
begin
--El 7 segmentos funciona con logica invertida
process(count,ena) --Se va a activar con un cambio de valor o con un cambio de enable
begin
--Seteo todas las salidas en 0 para solo "apagar" las que necesite por cada numero
a <= '0';
b <='0';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
g <= '0';
dp <= '1'; --En este caso siempre apagado
CHECK: case to_integer(unsigned(count)) is
when 0 =>
g <= '1';
when 1 =>
a <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
when 2 =>
c <= '1';
f <= '1';
when 3 =>
e <= '1';
f <= '1';
when 4 =>
a <= '1';
d <= '1';
e <= '1';
when 5 =>
b <= '1';
e <= '1';
when 6 =>
b <= '1';
when 7 =>
d <= '1';
e <= '1';
f <= '1';
g <= '1';
when 8 =>
--no cambia nada
when 9 =>
d <= '1';
e <= '1';
when others =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
end case CHECK;
anod <= not(ena);
end process;
end; |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- testbench for classicalMIPS
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity tb_cMIPS is
end tb_cMIPS;
architecture TB of tb_cMIPS is
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector; -- a03, a02
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_miso_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end component SDCard;
component DISK is
port (rst : in std_logic;
clk : in std_logic;
strobe : in std_logic; -- strobe for file reads/writes
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
busFree : in std_logic; -- '1' = bus will be free next cycle
busReq : out std_logic; -- '1' = bus will be used next cycle
busGrant : in std_logic; -- '1' = bus is free in this cycle
addr : in reg3;
data_inp : in reg32;
data_out : out reg32;
irq : out std_logic;
dma_addr : out reg32;
dma_dinp : in reg32;
dma_dout : out reg32;
dma_wr : out std_logic;
dma_aval : out std_logic;
dma_type : out reg4);
end component DISK;
component LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic);
end component LCD_display;
component to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out std_logic_vector;
display1 : out std_logic_vector;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
end component to_7seg;
component read_keys is
generic (DEB_CYCLES : natural);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
end component read_keys;
component to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component to_stdout;
component from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out std_logic_vector);
end component from_stdin;
component print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component print_data;
component write_data_file is
generic (OUTPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : in std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : out std_logic);
end component write_data_file;
component read_data_file is
generic (INPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
byte_sel: in std_logic_vector);
end component read_data_file;
component do_interrupt is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
end component do_interrupt;
component simple_uart is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic;
rxdat : in std_logic;
rts : out std_logic;
cts : in std_logic;
irq : out std_logic;
bit_rt : out std_logic_vector);-- communication speed - TB only
end component simple_uart;
component FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component FPU;
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
start : in std_logic;
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in std_logic_vector);
end component remota;
component sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end component sys_stats;
component ram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component ram_addr_decode;
component sdram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component sdram_addr_decode;
component io_addr_decode is
port (rst : in std_logic;
clk : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
dev_select : out std_logic_vector;
print_sel : out std_logic;
stdout_sel : out std_logic;
stdin_sel : out std_logic;
read_sel : out std_logic;
write_sel : out std_logic;
counter_sel : out std_logic;
FPU_sel : out std_logic;
uart_sel : out std_logic;
sstats_sel : out std_logic;
dsp7seg_sel : out std_logic;
keybd_sel : out std_logic;
lcd_sel : out std_logic;
sdc_sel : out std_logic;
dma_sel : out std_logic;
not_waiting : in std_logic);
end component io_addr_decode;
component busError_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in reg32;
d_busError : out std_logic); -- decoded address not in range (act=0)
end component busError_addr_decode;
component inst_addr_decode is
port (rst : in std_logic;
cpu_i_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
i_busError : out std_logic);
end component inst_addr_decode;
component ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component ROM;
component RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component RAM;
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE;
component I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE_fpga;
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component D_CACHE;
component core is
port (rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out std_logic_vector;
instr : in std_logic_vector;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
wr : out std_logic;
b_sel : out std_logic_vector;
busFree : out std_logic;
nmi : in std_logic;
irq : in std_logic_vector;
i_busErr : in std_logic;
d_busErr : in std_logic);
end component core;
component mf_altpll port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC);
end component mf_altpll;
component mf_altpll_io port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC);
end component mf_altpll_io;
component mf_altclkctrl port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component mf_altclkctrl;
-- use simulation / fake
for U_from_stdin : from_stdin use entity work.from_stdin(simulation);
-- use simulation / fake
for U_print_data : print_data use entity work.print_data(simulation);
-- use simulation / fake
for U_to_stdout : to_stdout use entity work.to_stdout(simulation);
-- use simulation / fake
for U_write_out : write_data_file
use entity work.write_data_file(simulation);
-- use simulation / fake
for U_read_inp : read_data_file
use entity work.read_data_file(simulation);
-- use fake / behavioral
for U_I_CACHE : I_cache use entity work.I_cache(fake);
-- use simulation / rtl
for U_ROM : ROM use entity work.ROM(simulation);
-- use simulation / rtl
for U_RAM : RAM use entity work.RAM(simulation);
-- use fake / behavioral
for U_D_CACHE : D_cache use entity work.D_cache(fake);
-- use fake / rtl
for U_FPU: FPU use entity work.FPU(fake); -- rtl);
-- use fake / simple
for U_SDRAMc : SDRAM_controller
use entity work.SDRAM_controller(fake);
-- use simulation / fake
for U_DISK : DISK use entity work.DISK(fake); -- simulation);
-- use fake / rtl
for U_SDcard : SDcard use entity work.SDcard(fake);
-- use fake / rtl
for U_LCD_display : LCD_display use entity work.LCD_display(fake);
-- use simulation / fake
for U_uart_remota: remota use entity work.remota(simulation);
signal clock_50mhz, clk,clkin : std_logic;
signal clk4x,clk4x0, clk4x180, clk2x : std_logic;
signal phi0,phi1,phi2,phi3,phi0in,phi1in,phi2in,phi3in, phi2_dlyd : std_logic;
signal rst,ic_reset,a_rst1,a_rst2,a_rst3, cpu_reset : std_logic;
signal a_reset, async_reset : std_logic;
signal cpu_i_aVal, cpu_i_wait, wr, cpu_d_aVal, cpu_d_wait : std_logic;
signal busFree, nmi, i_busError, d_busError : std_logic;
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic;
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal sdram_aVal, sdram_wait, sdram_wr : std_logic;
signal cpu_xfer, mem_xfer : reg4;
signal dev_select, dev_select_ram, dev_select_io, dev_select_sdram : reg4;
signal io_print_sel : std_logic := '1';
signal io_stdout_sel : std_logic := '1';
signal io_stdin_sel : std_logic := '1';
signal io_write_sel : std_logic := '1';
signal io_read_sel : std_logic := '1';
signal io_counter_sel : std_logic := '1';
signal io_uart_sel : std_logic := '1';
signal io_sstats_sel : std_logic := '1';
signal io_7seg_sel : std_logic := '1';
signal io_keys_sel : std_logic := '1';
signal io_fpu_sel, io_fpu_wait : std_logic := '1';
signal io_lcd_sel, io_lcd_wait : std_logic := '1';
signal io_sdc_sel, io_sdc_wait : std_logic := '1';
signal io_dma_sel : std_logic := '1';
signal d_cache_d_out, stdin_d_out, read_d_out, counter_d_out : reg32;
signal fpu_d_out, uart_d_out, sstats_d_out, keybd_d_out : reg32;
signal lcd_d_out, sdc_d_out, sdram_d_out, dma_d_out : reg32;
signal counter_irq : std_logic;
signal io_wait, not_waiting : std_logic;
signal i_addr,d_addr,p_addr : reg32;
signal datrom, datram_inp,datram_out, cpu_instr : reg32;
signal cpu_data_inp, cpu_data_out, cpu_data : reg32;
signal mem_i_sel, mem_d_sel: std_logic;
signal mem_i_addr, mem_addr, mem_d_addr: reg32;
signal cnt_i_ref,cnt_i_hit : integer;
signal cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush : integer;
signal dump_ram : std_logic;
signal bit_rt : reg3;
-- Macnica development board's peripherals
signal disp0,disp1 : reg8; -- 7 segment displays
signal key : reg12; -- 12 key telephone keyboard
signal sw : reg4; -- 4 slide switches
signal led_r, led_g, led_b : std_logic; -- RGB leds (on board signals)
signal LCD_D : std_logic_vector(7 downto 0); -- LCD data bus
signal LCD_RS, LCD_RW, LCD_EN, LCD_BACKLIGHT : std_logic; -- LCD control
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
signal sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i : std_logic;
signal sdcke, sdscs, sdras, sdcas, sdwe : std_logic; -- SDRAM
signal sddqm0, sddqm1, sdba0, sdba1 : std_logic;
signal sdaddr : reg12;
signal sddata : reg16;
signal hDinp, hDout : reg32;
-- disk device, simulation only
signal dma_addr, dma_dinp, dma_dout, ram_addr, ram_inp : reg32;
signal dma_wr, ram_wr, dma_aval, dma_irq, ram_sel : std_logic;
signal dma_type, ram_xfer : reg4;
signal busReq, busFree_dly, dma_grant : std_logic;
begin -- TB
pll : mf_altpll port map (areset => a_reset, inclk0 => clock_50mhz,
c0 => phi0in, c1 => phi1in, c2 => phi2in, c3 => phi3in, c4 => clkin);
-- pll_io : mf_altpll_io port map (areset => a_reset, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk4x0 <= '0';
clk4x180 <= '0';
mf_altclkctrl_inst_clk : mf_altclkctrl port map (
inclk => clkin, outclk => clk);
mf_altclkctrl_inst_clk4x : mf_altclkctrl port map (
inclk => clk4x180, outclk => clk4x);
mf_altclkctrl_inst_phi0 : mf_altclkctrl port map (
inclk => phi0in, outclk => phi0);
mf_altclkctrl_inst_phi1 : mf_altclkctrl port map (
inclk => phi1in, outclk => phi1);
mf_altclkctrl_inst_phi2 : mf_altclkctrl port map (
inclk => phi2in, outclk => phi2);
mf_altclkctrl_inst_phi3 : mf_altclkctrl port map (
inclk => phi3in, outclk => phi3);
-- synchronize reset
a_rst1 <= a_reset or rst;
U_SYNC_RESET1: FFD port map (clk, a_rst2, '1', a_rst1, rst);
U_SYNC_RESET2: FFD port map (clk, a_reset, '1', '1', a_rst2);
async_reset <= rst and ic_reset;
U_SYNC_RESET3: FFD port map (clk, rst, '1', async_reset, a_rst3);
U_SYNC_RESET4: FFD port map (clk, rst, '1', a_rst3, cpu_reset);
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait and sdram_wait;
io_wait <= io_lcd_wait and io_fpu_wait and io_sdc_wait;
not_waiting <= (inst_wait and data_wait and sdram_wait); -- and io_wait);
-- Count=Compare at IRQ7, UART at IRQ6, DMA at IRQ5, extCounter at IRQ4,
-- C=C U D E 0 0 sw1 sw0
-- uart+dma_disk+counter interrupts
irq <= ZERO & uart_irq & dma_irq & counter_irq & ZERO & ZERO;
-- irq <= b"000000"; -- NO interrupt requests
nmi <= NO; -- input port to TB
U_CORE: core
port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, busFree, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
U_I_CACHE: i_cache
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
U_ROM: ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
-- d_busError <= '1'; -- only while testing the SDRAM
U_IO_ADDR_DEC: io_addr_decode
port map (rst, phi0, cpu_d_aVal, d_addr, dev_select_io,
io_print_sel, io_stdout_sel, io_stdin_sel, io_read_sel,
io_write_sel, io_counter_sel, io_fpu_sel, io_uart_sel,
io_sstats_sel, io_7seg_sel, io_keys_sel, io_lcd_sel,
io_sdc_sel, io_dma_sel, not_waiting);
U_DATA_ADDR_DEC: ram_addr_decode
port map (rst, cpu_d_aVal, d_addr,data_aVal, dev_select_ram);
U_SDRAM_ADDR_DEC: sdram_addr_decode
port map (rst, cpu_d_aVal, d_addr,sdram_aVal, dev_select_sdram);
dev_select <= dev_select_io or dev_select_ram; -- or dev_select_sdram;
with dev_select select
cpu_data_inp <= d_cache_d_out when b"0001",
stdin_d_out when b"0100",
read_d_out when b"0101",
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
-- sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
sdc_d_out when b"1110",
-- sdram_d_out when b"1110",
dma_d_out when b"1111",
(others => 'X') when others;
U_D_CACHE: d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
mem_d_sel, ram_rdy, mem_wr,
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
U_BUSFREE_DLY: FFD port map (clk, rst, '1', busFree, busFree_dly);
dma_grant <= busFree_dly and busReq;
ram_xfer <= dma_type when dma_grant = YES else mem_xfer;
ram_addr <= dma_addr when dma_grant = YES else mem_addr;
ram_wr <= dma_wr when dma_grant = YES else mem_wr;
ram_sel <= '0' when dma_grant = YES else mem_d_sel;
ram_inp <= dma_dout when dma_grant = YES else datram_out;
U_RAM: RAM generic map ("data.bin", "dump.data")
port map (rst, clk, ram_sel, ram_rdy, ram_wr, phi3,
ram_addr, ram_inp, datram_inp, ram_xfer, dump_ram);
-- U_RAM: RAM generic map ("data.bin", "dump.data")
-- port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
-- mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
-- busReq <= '0';
U_DISK: DISK
port map (rst,clk, phi1, io_dma_sel, open, wr, -- '1', open,
busFree, busReq, dma_grant,
d_addr(4 downto 2), cpu_data, dma_d_out, dma_irq,
dma_addr, datram_inp, dma_dout, dma_wr, dma_aval, dma_type);
U_SDRAMc: SDRAM_controller port map
(rst, clk, clk2x, sdram_aVal, sdram_wait, wr,
cpu_xfer, d_addr(25 downto 0), hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
sdcke <= '1';
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
U_from_stdin: from_stdin
port map (rst,clk, io_stdin_sel, wr, stdin_d_out);
U_read_inp: read_data_file generic map ("input.data")
port map (rst,clk, io_read_sel, wr, d_addr,read_d_out, cpu_xfer);
U_write_out: write_data_file generic map ("output.data")
port map (rst,clk, io_write_sel, wr, d_addr,cpu_data, cpu_xfer, dump_ram);
U_print_data: print_data
port map (rst,clk, io_print_sel, wr, cpu_data);
U_interrupt_counter: do_interrupt -- external counter+interrupt
port map (rst,clk, io_counter_sel, wr, cpu_data,
counter_d_out, counter_irq);
U_to_7seg: to_7seg
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1,
led_r, led_g, led_b);
key <= b"000000000000", b"000000000100" after 1 us, b"000000000000" after 2 us, b"001000000000" after 3 us, b"000000000000" after 4 us, b"000001000000" after 5 us, b"000000000000" after 6 us;
sw <= b"0000";
U_read_keys: read_keys
generic map (6) -- debouncing interval, in clock cycles
port map (rst,clk, io_keys_sel, keybd_d_out, key, sw);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
wr, d_addr(2), cpu_data, lcd_d_out,
lcd_d, lcd_rs, lcd_rw, lcd_en, lcd_backlight);
U_simple_uart: simple_uart
port map (rst,clk, io_uart_sel, wr, d_addr(3 downto 2),
cpu_data, uart_d_out,
uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq, bit_rt);
-- uncoment next line for loop back, comment out previous line
-- uart_txd, uart_txd, uart_rts, uart_cts, uart_irq, bit_rt);
uart_cts <= uart_rts;
U_uart_remota: remota generic map ("serial.out","serial.inp")
port map (rst, clk, uart_rts, uart_txd, uart_rxd, bit_rt);
U_sdcard: SDcard
port map (rst, clk, io_sdc_sel, io_sdc_wait,
wr, d_addr(3 downto 2), cpu_data, sdc_d_out,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i, open);
U_FPU: FPU
port map (rst,clk, io_FPU_sel, io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data, fpu_d_out);
-- U_sys_stats: sys_stats -- CPU reads system counters
-- port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
-- cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush,
-- cnt_i_ref,cnt_i_hit);
U_clock: process -- simulate external clock
begin
clock_50mhz <= '1';
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
clock_50mhz <= '0';
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
end process; -- -------------------------------------------------------
-- simulate reset switch bounces
a_reset <= '1', '0' after 5 ns, '1' after 8 ns, '0' after 12 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns;
end architecture TB;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity inst_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_i_aVal : in std_logic; -- CPU instr addr valid (act=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- decoded address in range (act=0)
i_busError : out std_logic); -- decoded address not in range (act=0)
end entity inst_addr_decode;
architecture behavioral of inst_addr_decode is
constant HI_ADDR : integer := HI_SEL_BITS;
constant LO_ADDR : integer := log2_ceil(INST_BASE_ADDR + INST_MEM_SZ);
constant PREFIX : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'0');
signal in_range : boolean;
begin
in_range <= (addr(HI_ADDR downto LO_ADDR) = PREFIX);
aVal <= '0' when ( cpu_i_aVal = '0' and in_range ) else
'1';
i_busError <= '0' when ( cpu_i_aVal = '0' and not(in_range) ) else
'1';
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity ram_addr_decode;
architecture behavioral of ram_addr_decode is
-- constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
-- constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant RAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant RAM_ADDR_RANGE : natural :=
(to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_DATA_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant RAM_ADDR_TOP : natural := RAM_ADDR_BOTTOM + RAM_ADDR_RANGE;
begin
-- in_range <= ( rst = '1'
-- and ((addr and a_mask) = x_DATA_BASE_ADDR)
-- and ((addr and r_mask) = x_DATA_BASE_ADDR) );
-- this works only for small RAMS
-- in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
-- =
-- x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
RAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
RAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report LF & "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- busError address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity busError_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
d_busError : out std_logic); -- decoded address not in range (act=0)
end entity busError_addr_decode;
architecture behavioral of busError_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
-- RAM constants
constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo; -- 0..0110..0
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo; -- 1..10..0
signal in_range, io_in_range : boolean;
begin
in_range <= ( rst = '1' and
((addr and a_mask) = x_DATA_BASE_ADDR) and
((addr and r_mask) = x_DATA_BASE_ADDR) );
io_in_range <= ( (addr and x_mask) = x_IO_BASE_ADDR );
d_busError <= '0' when ( (cpu_d_aVal = '0') and
(not(in_range) and not(io_in_range)) ) else '1';
assert TRUE -- cpu_d_aVal = '1'
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
assert TRUE -- cpu_d_aVal = '1' and io_busError
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
" LO_DEV " & integer'image(LO_DEV) &
" HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- I/O address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
clk : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
print_sel : out std_logic; -- std_out (integer) (act=0)
stdout_sel : out std_logic; -- std_out (character) (act=0)
stdin_sel : out std_logic; -- std_inp (character) (act=0)
read_sel : out std_logic; -- file read (act=0)
write_sel : out std_logic; -- file write (act=0)
counter_sel : out std_logic; -- interrupt counter (act=0)
FPU_sel : out std_logic; -- floating point unit (act=0)
UART_sel : out std_logic; -- floating point unit (act=0)
SSTATS_sel : out std_logic; -- system statistics (act=0)
dsp7seg_sel : out std_logic; -- 7 segments display (act=0)
keybd_sel : out std_logic; -- telephone keyboard (act=0)
lcd_sel : out std_logic; -- LCD 2x16 char display (act=0)
sdc_sel : out std_logic; -- SDcard reader/writer (act=0)
dma_sel : out std_logic; -- DMA/disk controller (act=0)
not_waiting : in std_logic); -- no other device is waiting
end entity io_addr_decode;
architecture behavioral of io_addr_decode is
constant LO_SEL_ADDR : integer := log2_ceil(IO_ADDR_RANGE);
constant HI_SEL_ADDR : integer := LO_SEL_ADDR + log2_ceil(IO_ADDR_BITS);
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
signal in_range : boolean;
signal aVal : std_logic;
signal dev : integer; -- DEBUGGING only
begin
-- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
aVal <= '0' when ( cpu_d_aVal = '0' and not_waiting = '1' and
in_range ) else '1';
dev <= to_integer(signed(addr(IO_ADDR_BITS downto LO_SEL_ADDR)))
when aVal = '0' else 0;
U_decode: process(clk, aVal, addr, dev)
variable dev_sel : reg4;
constant is_noise : integer := 0;
constant is_print : integer := 2;
constant is_stdout : integer := 3;
constant is_stdin : integer := 4;
constant is_read : integer := 5;
constant is_write : integer := 6;
constant is_count : integer := 7;
constant is_FPU : integer := 8;
constant is_UART : integer := 9;
constant is_SSTATS : integer := 10;
constant is_dsp7seg : integer := 11;
constant is_keybd : integer := 12;
constant is_lcd : integer := 13;
constant is_sdc : integer := 14;
constant is_dma : integer := 15;
begin
print_sel <= '1';
stdout_sel <= '1';
stdin_sel <= '1';
read_sel <= '1';
write_sel <= '1';
counter_sel <= '1';
FPU_sel <= '1';
UART_sel <= '1';
SSTATS_sel <= '1';
dsp7seg_sel <= '1';
keybd_sel <= '1';
lcd_sel <= '1';
sdc_sel <= '1';
dma_sel <= '1';
case dev is -- to_integer(signed(addr(HI_ADDR downto LO_ADDR))) is
when 0 => dev_sel := std_logic_vector(to_unsigned(is_print, 4));
print_sel <= aVal or clk;
when 1 => dev_sel := std_logic_vector(to_unsigned(is_stdout, 4));
stdout_sel <= aVal or clk;
when 2 => dev_sel := std_logic_vector(to_unsigned(is_stdin, 4));
stdin_sel <= aVal or clk;
when 3 => dev_sel := std_logic_vector(to_unsigned(is_read, 4));
read_sel <= aVal or clk;
when 4 => dev_sel := std_logic_vector(to_unsigned(is_write, 4));
write_sel <= aVal or clk;
when 5 => dev_sel := std_logic_vector(to_unsigned(is_count, 4));
counter_sel <= aVal or clk;
when 6 => dev_sel := std_logic_vector(to_unsigned(is_FPU, 4));
FPU_sel <= aVal;
when 7 => dev_sel := std_logic_vector(to_unsigned(is_UART, 4));
UART_sel <= aVal;
when 8 => dev_sel := std_logic_vector(to_unsigned(is_SSTATS, 4));
SSTATS_sel <= aVal;
when 9 => dev_sel := std_logic_vector(to_unsigned(is_dsp7seg, 4));
dsp7seg_sel <= aVal;
when 10 => dev_sel := std_logic_vector(to_unsigned(is_keybd, 4));
keybd_sel <= aVal;
when 11 => dev_sel := std_logic_vector(to_unsigned(is_lcd, 4));
lcd_sel <= aVal;
when 12 => dev_sel := std_logic_vector(to_unsigned(is_sdc, 4));
sdc_sel <= aVal;
when 13 => dev_sel := std_logic_vector(to_unsigned(is_dma, 4));
dma_sel <= aVal or clk;
when others => dev_sel := std_logic_vector(to_unsigned(is_noise, 4));
end case;
assert TRUE report "IO_addr "& SLV32HEX(addr); -- DEBUG
if aVal = '0' then
dev_select <= dev_sel;
else
dev_select <= std_logic_vector(to_unsigned(is_noise, 4));
end if;
end process U_decode;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- SDRAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity sdram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR + SDRAM_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity sdram_addr_decode;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture behavioral of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
SDRAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
SDRAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
in_range <= FALSE;
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
-- in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
-- >=
-- SDRAM_ADDR_BOTTOM)
-- and
-- (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
-- <
-- SDRAM_ADDR_TOP)
-- );
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
use work.all;
configuration CFG_TB of TB_CMIPS is
for TB
end for;
end configuration CFG_TB;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- $Id: pdp11_statleds.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_statleds - syn
-- Description: pdp11: status leds
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-20 649 1.0 Initial version
------------------------------------------------------------------------------
-- LED (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_statleds is -- status leds
port (
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
STATLEDS : out slv8 -- 8 bit CPU status
);
end pdp11_statleds;
architecture syn of pdp11_statleds is
begin
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_EXP.dp_psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
STATLEDS <= iled;
end process proc_led;
end syn;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F9LRRL
-- /___/ /\ Timestamp : 04/06/2014 00:33:54
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity RAM_MEMORY is
port (
clk : IN std_logic;
address : IN std_logic_vector(31 downto 0);
read_en : IN std_logic;
data_out: OUT std_logic_vector(7 downto 0)
);
end RAM_MEMORY;
architecture BEHAVIORAL of PointBuffer is
signal sPointSet: T_POINT_SET := others => (others => '0'));
signal enables: std_logic_vector(N_POINTS-2 downto 0);
signal counter1: integer range 0 to N_POINTS*NUMBER_OF_SCALES-1 = 0;
signal counter2: integer range 0 to NUMBER_OF_SCALES-1 := 0;
component PointFifo
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputValue: out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end component;
begin
pointFifo0: PointFifo
port map(
clk => clk,
enableIn => enableIn,
inputValue => inputValue,
rst => rst,
enableOut => enables(0),
outputValue => sPointSet(1)
);
genPointBuffer: for i in 1 to N_POINTS-2 generate
pointFifoX: PointFifo
port map(
clk => clk,
enableIn => enables(i-1),
inputValue => sPointSet(i),
rst => rst,
enableOut => enables(i),
outputValue => sPointSet(i+1)
);
end generate genPointBuffer;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter1 <= 0;
counter2 <= 0;
enableOut <= '0';
else
if enableIn = '1' then
sPointSet(0) <= inputValue;
if counter1 = N_POINTS*NUMBER_OF_SCALES-1 then
if counter2 = NUMBER_OF_SCALES-1 then
counter2 <= 0;
counter1 <= 0;
else
counter2 <= counter2+1;
end if;
enableOut <= '1';
else
counter1 <= counter1+1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;
end process;
pointSet <= sPointSet;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ben_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ben_mem_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ben_mem_exdes;
ARCHITECTURE xilinx OF ben_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ben_mem IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ben_mem
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:53 wig Exp $
-- $Date: 2004/04/06 10:50:53 $
-- $Log: inst_ed_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:53 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ed_e
--
architecture rtl of inst_ed_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eda_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eda_e
-- End of Generated Generics for Entity inst_eda_e
-- No Generated Port
end component;
-- ---------
component inst_edb_e --
-- No Generated Generics
-- Generated Generics for Entity inst_edb_e
-- End of Generated Generics for Entity inst_edb_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eda
inst_eda: inst_eda_e
;
-- End of Generated Instance Port Map for inst_eda
-- Generated Instance Port Map for inst_edb
inst_edb: inst_edb_e
;
-- End of Generated Instance Port Map for inst_edb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--VHDL MIPI CSI-2 Rx designed for Xilinx 7-series FPGAs
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This driver is designed for 4 lane links and has been tested with the Omnivison OV13850
--It supports resolutions up to 4k at 30fps (higher has not been tested but may work) with
--10-bit Bayer data (support for other output formats is not yet implemented). This is output
--in traditional parallel video format with a few tweaks
--For improved timing performance up to 4 pixels per clock can be output. For the ease of debayering blocks,
--the previous line's data; and whether the current line is even (BGBG) or odd (GRGR) is also output.
--At minimum you will need to provide it with suitable clocks from a PLL (the pixel clock input
--should in general either be phase locked to the master clock input to the camera or the CSI byte clock)
--and configure skew parameters and video port timings for your camera setup
--The primary testing platform is a Digilent Genesys 2 (Kintex-7 XC7K325T) with a
--custom FMC breakout board to connect two Firefly OV13850 modules.
--A previous version has also been tested on a ML605 Virtex-6 development board;
--however functioning support is not guaranteed
entity csi_rx_4lane is
generic (
--FPGA series to control SERDES/buffer generation
--either "VIRTEX6" or "7SERIES"
fpga_series : string := "7SERIES";
--Low-level PHY parameters
dphy_term_en : boolean := true; --Enable internal termination on all pairs
--Use these to invert channels if needed on your PCB
d0_invert : boolean := false;
d1_invert : boolean := false;
d2_invert : boolean := false;
d3_invert : boolean := false;
--These skew values are the delay settings for the IDELAYs on each lane
--Adjust these for optimum stability with your PCB layout and cameras
d0_skew : natural := 0;
d1_skew : natural := 0;
d2_skew : natural := 0;
d3_skew : natural := 0;
--Output port pixel timings (for included OV13850 config at 23.98fps with MCLK 24.399MHz and output clock 145Mz)
video_hlength : natural := 4041; --total visible and blanking pixels per line
video_vlength : natural := 2992; --total visible and blanking lines per frame
video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync
video_hsync_len : natural := 48; --horizontal sync length in pixels
video_hbp_len : natural := 122; --horizontal back porch length (excluding sync)
video_h_visible : natural := 3840; --number of visible pixels per line
video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync
video_vsync_len : natural := 3; --vertical sync length in lines
video_vbp_len : natural := 23; --vertical back porch length (excluding sync)
video_v_visible : natural := 2160; --number of visible lines per frame
pixels_per_clock : natural := 2; --Number of pixels per clock to output; 1, 2 or 4
--Set this to false if this is not the first CSI rx or other IDELAY using device in the system
generate_idelayctrl : boolean := false
);
port(
ref_clock_in : in std_logic; --IDELAY reference clock (nominally 200MHz)
pixel_clock_in : in std_logic; --Output pixel clock from PLL
byte_clock_out : out std_logic; --DSI byte clock output
enable : in std_logic; --system enable input
reset : in std_logic; --synchronous active high reset input
video_valid : out std_logic; --goes high when valid frames are being received
--DSI signals, signal 1 is P and signal 0 is N
dphy_clk : in std_logic_vector(1 downto 0);
dphy_d0 : in std_logic_vector(1 downto 0);
dphy_d1 : in std_logic_vector(1 downto 0);
dphy_d2 : in std_logic_vector(1 downto 0);
dphy_d3 : in std_logic_vector(1 downto 0);
--Pixel data output
video_hsync : out std_logic;
video_vsync : out std_logic;
video_den : out std_logic;
video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines
video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block
video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel
video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use
);
end csi_rx_4lane;
architecture Behavioral of csi_rx_4lane is
signal csi_byte_clock : std_logic;
signal link_reset_out : std_logic;
signal wait_for_sync : std_logic;
signal packet_done : std_logic;
signal word_clock : std_logic;
signal word_data : std_logic_vector(31 downto 0);
signal word_valid : std_logic;
signal packet_payload : std_logic_vector(31 downto 0);
signal packet_payload_valid : std_logic;
signal csi_vsync : std_logic;
signal csi_in_frame, csi_in_line : std_logic;
signal unpack_data : std_logic_vector(39 downto 0);
signal unpack_data_valid : std_logic;
begin
link : entity work.csi_rx_4_lane_link
generic map(
fpga_series => fpga_series,
dphy_term_en => dphy_term_en,
d0_invert => d0_invert,
d1_invert => d1_invert,
d2_invert => d2_invert,
d3_invert => d3_invert,
d0_skew => d0_skew,
d1_skew => d1_skew,
d2_skew => d2_skew,
d3_skew => d3_skew,
generate_idelayctrl => generate_idelayctrl)
port map(
dphy_clk => dphy_clk,
dphy_d0 => dphy_d0,
dphy_d1 => dphy_d1,
dphy_d2 => dphy_d2,
dphy_d3 => dphy_d3,
ref_clock => ref_clock_in,
reset => reset,
enable => enable,
wait_for_sync => wait_for_sync,
packet_done => packet_done,
reset_out => link_reset_out,
word_clock => csi_byte_clock,
word_data => word_data,
word_valid => word_valid);
depacket : entity work.csi_rx_packet_handler
port map (
clock => csi_byte_clock,
reset => link_reset_out,
enable => enable,
data => word_data,
data_valid => word_valid,
sync_wait => wait_for_sync,
packet_done => packet_done,
payload_out => packet_payload,
payload_valid => packet_payload_valid,
vsync_out => csi_vsync,
in_frame => csi_in_frame,
in_line => csi_in_line);
unpack10 : entity work.csi_rx_10bit_unpack
port map (
clock => csi_byte_clock,
reset => link_reset_out,
enable => enable,
data_in => packet_payload,
din_valid => packet_payload_valid,
data_out => unpack_data,
dout_valid => unpack_data_valid);
vout : entity work.csi_rx_video_output
generic map (
video_hlength => video_hlength,
video_vlength => video_vlength,
video_hsync_pol => video_hsync_pol,
video_hsync_len => video_hsync_len,
video_hbp_len => video_hbp_len,
video_h_visible => video_h_visible,
video_vsync_pol => video_vsync_pol,
video_vsync_len => video_vsync_len,
video_vbp_len => video_vbp_len,
video_v_visible => video_v_visible,
pixels_per_clock => pixels_per_clock)
port map (
output_clock => pixel_clock_in,
csi_byte_clock => csi_byte_clock,
enable => enable,
reset => reset,
pixel_data_in => unpack_data,
pixel_data_valid => unpack_data_valid,
csi_in_frame => csi_in_frame,
csi_in_line => csi_in_line,
csi_vsync => csi_vsync,
video_valid => video_valid,
video_hsync => video_hsync,
video_vsync => video_vsync,
video_den => video_den,
video_line_start => video_line_start,
video_odd_line => video_odd_line,
video_data => video_data,
video_prev_line_data => video_prev_line_data
);
byte_clock_out <= csi_byte_clock;
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
package p is
function id(val : natural) return natural;
end package;
package body p is
function id(val : natural) return natural is
begin
return val;
end function;
end package body;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY reg IS
GENERIC
(
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data_in : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
wr : IN std_logic;
rd : IN std_logic
);
END reg;
ARCHITECTURE rtl OF reg IS
SIGNAL regval : std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
BEGIN
WITH rd SELECT
data_out <= regval WHEN '1',
"ZZZZZZZZ" WHEN OTHERS;
PROCESS (clock, wr)
BEGIN
IF (clock'event AND clock = '0' AND wr = '1') THEN
regval <= data_in;
END IF;
END PROCESS;
END rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_btb_cache_config_pkg.all;
use work.cpu_btb_cache_replace_pkg.all;
use work.cpu_types_pkg.all;
package cpu_btb_cache_pkg is
constant cpu_btb_cache_assoc : natural := 2**cpu_btb_cache_log2_assoc;
constant cpu_btb_cache_state_bits : natural := (cpu_btb_cache_assoc + -- way
cpu_btb_cache_assoc + -- replace_way
cpu_btb_cache_replace_state_bits -- replace_state
);
subtype cpu_btb_cache_state_type is std_ulogic_vector(cpu_btb_cache_state_bits-1 downto 0);
type cpu_btb_cache_ctrl_in_type is record
ren : std_ulogic;
wen : std_ulogic;
end record;
type cpu_btb_cache_dp_in_type is record
raddr : cpu_ivaddr_type;
waddr : cpu_ivaddr_type;
wstate : cpu_btb_cache_state_type;
wtarget : cpu_ivaddr_type;
end record;
type cpu_btb_cache_ctrl_out_type is record
rvalid : std_ulogic;
end record;
type cpu_btb_cache_dp_out_type is record
rstate : cpu_btb_cache_state_type;
rtarget : cpu_ivaddr_type;
end record;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package guarded_fifo_pkg is
component guarded_fifo
generic (
depth : integer;
bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
push_i, pop_i : in std_logic;
full_o, empty_o : out std_logic;
d_i : in std_logic_vector ( bit_width-1 downto 0 );
q_o : out std_logic_vector ( bit_width-1 downto 0 )
);
end component;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package guarded_fifo_pkg is
component guarded_fifo
generic (
depth : integer;
bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
push_i, pop_i : in std_logic;
full_o, empty_o : out std_logic;
d_i : in std_logic_vector ( bit_width-1 downto 0 );
q_o : out std_logic_vector ( bit_width-1 downto 0 )
);
end component;
end package;
|
----------------------------------------------------------------------
-- brdConst_pkg (for SCS Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 48_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 24_000_000; -- divided
--constant BRD_OSC_CLK_MHZ : positive := 10_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switches
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '0';
end brdConst_pkg;
----------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-e.vhd,v 1.1 2004/04/06 11:19:53 wig Exp $
-- $Date: 2004/04/06 11:19:53 $
-- $Log: inst_aa_e-e.vhd,v $
-- Revision 1.1 2004/04/06 11:19:53 wig
-- Adding result/autoopen
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.28 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa_e
--
entity inst_aa_e is
-- Generics:
-- No Generated Generics for Entity inst_aa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa_e
p_mix_s_ai14_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ai16_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ai6_go : out std_ulogic;
p_mix_s_ai8_gi : in std_ulogic;
p_mix_s_aio17_gc : inout std_ulogic;
p_mix_s_aio18_gc : inout std_ulogic;
p_mix_s_aio19_gc : inout std_ulogic;
p_mix_s_ao10_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao11_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao12_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ao13_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ao1_go : out std_ulogic;
p_mix_s_ao2_go : out std_ulogic;
p_mix_s_ao3_go : out std_ulogic;
p_mix_s_ao4_gi : in std_ulogic;
p_mix_s_ao5_go : out std_ulogic;
p_mix_s_ao9_go : out std_ulogic_vector(7 downto 0);
port_aa : out std_ulogic
-- End of Generated Port for Entity inst_aa_e
);
end inst_aa_e;
--
-- End of Generated Entity inst_aa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03000_good.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description: Handbook example: Comments for objects declaration statements: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03000_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03000_good;
--CODE
architecture Behavioral of STD_03000_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Enable = '1') then -- D Flip-Flop enabled
Q <= i_D;
end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
|
--------------------------------------------------------------------------------
--
-- File:
-- user_logic.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author(s):
-- Sam Bobrowicz
-- Karol Gugala <kgugala@antmicro.com>
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_TDATA_WIDTH : integer := 32; --must be 32
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 13;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT mmcme2_drp
GENERIC(
DIV_F : integer
);
PORT(
SEN : IN std_logic;
SCLK : IN std_logic;
RST : IN std_logic;
S1_CLKOUT0 : IN std_logic_vector(35 downto 0);
S1_CLKFBOUT : IN std_logic_vector(35 downto 0);
S1_DIVCLK : IN std_logic_vector(13 downto 0);
S1_LOCK : IN std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : IN std_logic_vector(9 downto 0);
REF_CLK : IN std_logic;
SRDY : OUT std_logic;
PXL_CLK : OUT std_logic;
PXL_CLK_INV : OUT std_logic;
CLKFBOUT_O : OUT std_logic;
CLKFBOUT_I : IN std_logic;
LOCKED_O : OUT std_logic
);
END COMPONENT;
COMPONENT vdma_to_vga
GENERIC(
C_RED_WIDTH : integer;
C_GREEN_WIDTH : integer;
C_BLUE_WIDTH : integer;
C_S_AXIS_TDATA_WIDTH : integer
);
PORT(
LOCKED_I : IN std_logic;
ENABLE_I : IN std_logic;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
USR_WIDTH_I : IN std_logic_vector(11 downto 0);
USR_HEIGHT_I : IN std_logic_vector(11 downto 0);
USR_HPS_I : IN std_logic_vector(11 downto 0);
USR_HPE_I : IN std_logic_vector(11 downto 0);
USR_HPOL_I : IN std_logic;
USR_HMAX_I : IN std_logic_vector(11 downto 0);
USR_VPS_I : IN std_logic_vector(11 downto 0);
USR_VPE_I : IN std_logic_vector(11 downto 0);
USR_VPOL_I : IN std_logic;
USR_VMAX_I : IN std_logic_vector(11 downto 0);
RUNNING_O : OUT std_logic;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0)
);
END COMPONENT;
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal mmcm_clk_inv : std_logic;
signal pxl_clk : std_logic;
signal pxl_clk_inv : std_logic;
signal pxl_clk_inv5x : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal vga_running : std_logic;
signal clk_state : CLK_STATE_TYPE := RESET;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal CTRL_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal STAT_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal FRAME_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_O_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FB_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FRAC_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_DIV_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_LOCK_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FLTR_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg_write_sel : std_logic_vector(12 downto 0);
signal slv_reg_read_sel : std_logic_vector(12 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFG_inst: BUFG port map(
O => pxl_clk_inv5x, -- 1-bit output: Clock output port
I => mmcm_clk_inv -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFR_inst_inv : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output port
CE => enable_reg, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => pxl_clk_inv5x -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
ENABLE_O <= enable_reg;
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
BUFG_inst_inv : BUFG
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output
I => mmcm_clk_inv -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
pxl_clk_mux: BUFGMUX
port map (
O => PXL_CLK_O, -- 1-bit output: Clock output
I0 => pxl_clk, -- 1-bit input: Clock input (S=0)
I1 => pxl_clk_inv, -- 1-bit input: Clock input (S=1)
S => CTRL_REG(1) -- 1-bit input: Clock select
);
VDMA_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED => --This state ensures that the initial SRDY pulse doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
GENERIC MAP(
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => pxl_clk,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
DEBUG_O => DEBUG_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(12 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(12 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
CTRL_REG <= (others => '0');
--STAT_REG <= (others => '0');
FRAME_REG <= (others => '0');
HPARAM1_REG <= (others => '0');
HPARAM2_REG <= (others => '0');
VPARAM1_REG <= (others => '0');
VPARAM2_REG <= (others => '0');
CLK_O_REG <= (others => '0');
CLK_FB_REG <= (others => '0');
CLK_FRAC_REG <= (others => '0');
CLK_DIV_REG <= (others => '0');
CLK_LOCK_REG <= (others => '0');
CLK_FLTR_REG <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CTRL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--***Status register is read only***
-- when "0100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- STAT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "0010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
FRAME_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_O_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FB_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FRAC_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_DIV_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_LOCK_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FLTR_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, CTRL_REG, STAT_REG, FRAME_REG, HPARAM1_REG, HPARAM2_REG, VPARAM1_REG, VPARAM2_REG, CLK_O_REG, CLK_FB_REG, CLK_FRAC_REG, CLK_DIV_REG, CLK_LOCK_REG, CLK_FLTR_REG ) is
begin
case slv_reg_read_sel is
when "1000000000000" => slv_ip2bus_data <= CTRL_REG;
when "0100000000000" => slv_ip2bus_data <= STAT_REG;
when "0010000000000" => slv_ip2bus_data <= FRAME_REG;
when "0001000000000" => slv_ip2bus_data <= HPARAM1_REG;
when "0000100000000" => slv_ip2bus_data <= HPARAM2_REG;
when "0000010000000" => slv_ip2bus_data <= VPARAM1_REG;
when "0000001000000" => slv_ip2bus_data <= VPARAM2_REG;
when "0000000100000" => slv_ip2bus_data <= CLK_O_REG;
when "0000000010000" => slv_ip2bus_data <= CLK_FB_REG;
when "0000000001000" => slv_ip2bus_data <= CLK_FRAC_REG;
when "0000000000100" => slv_ip2bus_data <= CLK_DIV_REG;
when "0000000000010" => slv_ip2bus_data <= CLK_LOCK_REG;
when "0000000000001" => slv_ip2bus_data <= CLK_FLTR_REG;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
--------------------------------------------------------------------------------
--
-- File:
-- user_logic.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author(s):
-- Sam Bobrowicz
-- Karol Gugala <kgugala@antmicro.com>
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_TDATA_WIDTH : integer := 32; --must be 32
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 13;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT mmcme2_drp
GENERIC(
DIV_F : integer
);
PORT(
SEN : IN std_logic;
SCLK : IN std_logic;
RST : IN std_logic;
S1_CLKOUT0 : IN std_logic_vector(35 downto 0);
S1_CLKFBOUT : IN std_logic_vector(35 downto 0);
S1_DIVCLK : IN std_logic_vector(13 downto 0);
S1_LOCK : IN std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : IN std_logic_vector(9 downto 0);
REF_CLK : IN std_logic;
SRDY : OUT std_logic;
PXL_CLK : OUT std_logic;
PXL_CLK_INV : OUT std_logic;
CLKFBOUT_O : OUT std_logic;
CLKFBOUT_I : IN std_logic;
LOCKED_O : OUT std_logic
);
END COMPONENT;
COMPONENT vdma_to_vga
GENERIC(
C_RED_WIDTH : integer;
C_GREEN_WIDTH : integer;
C_BLUE_WIDTH : integer;
C_S_AXIS_TDATA_WIDTH : integer
);
PORT(
LOCKED_I : IN std_logic;
ENABLE_I : IN std_logic;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
USR_WIDTH_I : IN std_logic_vector(11 downto 0);
USR_HEIGHT_I : IN std_logic_vector(11 downto 0);
USR_HPS_I : IN std_logic_vector(11 downto 0);
USR_HPE_I : IN std_logic_vector(11 downto 0);
USR_HPOL_I : IN std_logic;
USR_HMAX_I : IN std_logic_vector(11 downto 0);
USR_VPS_I : IN std_logic_vector(11 downto 0);
USR_VPE_I : IN std_logic_vector(11 downto 0);
USR_VPOL_I : IN std_logic;
USR_VMAX_I : IN std_logic_vector(11 downto 0);
RUNNING_O : OUT std_logic;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0)
);
END COMPONENT;
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal mmcm_clk_inv : std_logic;
signal pxl_clk : std_logic;
signal pxl_clk_inv : std_logic;
signal pxl_clk_inv5x : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal vga_running : std_logic;
signal clk_state : CLK_STATE_TYPE := RESET;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal CTRL_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal STAT_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal FRAME_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_O_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FB_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FRAC_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_DIV_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_LOCK_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FLTR_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg_write_sel : std_logic_vector(12 downto 0);
signal slv_reg_read_sel : std_logic_vector(12 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFG_inst: BUFG port map(
O => pxl_clk_inv5x, -- 1-bit output: Clock output port
I => mmcm_clk_inv -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFR_inst_inv : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output port
CE => enable_reg, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => pxl_clk_inv5x -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
ENABLE_O <= enable_reg;
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
BUFG_inst_inv : BUFG
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output
I => mmcm_clk_inv -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
pxl_clk_mux: BUFGMUX
port map (
O => PXL_CLK_O, -- 1-bit output: Clock output
I0 => pxl_clk, -- 1-bit input: Clock input (S=0)
I1 => pxl_clk_inv, -- 1-bit input: Clock input (S=1)
S => CTRL_REG(1) -- 1-bit input: Clock select
);
VDMA_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED => --This state ensures that the initial SRDY pulse doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
GENERIC MAP(
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => pxl_clk,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
DEBUG_O => DEBUG_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(12 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(12 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
CTRL_REG <= (others => '0');
--STAT_REG <= (others => '0');
FRAME_REG <= (others => '0');
HPARAM1_REG <= (others => '0');
HPARAM2_REG <= (others => '0');
VPARAM1_REG <= (others => '0');
VPARAM2_REG <= (others => '0');
CLK_O_REG <= (others => '0');
CLK_FB_REG <= (others => '0');
CLK_FRAC_REG <= (others => '0');
CLK_DIV_REG <= (others => '0');
CLK_LOCK_REG <= (others => '0');
CLK_FLTR_REG <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CTRL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--***Status register is read only***
-- when "0100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- STAT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "0010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
FRAME_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_O_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FB_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FRAC_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_DIV_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_LOCK_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FLTR_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, CTRL_REG, STAT_REG, FRAME_REG, HPARAM1_REG, HPARAM2_REG, VPARAM1_REG, VPARAM2_REG, CLK_O_REG, CLK_FB_REG, CLK_FRAC_REG, CLK_DIV_REG, CLK_LOCK_REG, CLK_FLTR_REG ) is
begin
case slv_reg_read_sel is
when "1000000000000" => slv_ip2bus_data <= CTRL_REG;
when "0100000000000" => slv_ip2bus_data <= STAT_REG;
when "0010000000000" => slv_ip2bus_data <= FRAME_REG;
when "0001000000000" => slv_ip2bus_data <= HPARAM1_REG;
when "0000100000000" => slv_ip2bus_data <= HPARAM2_REG;
when "0000010000000" => slv_ip2bus_data <= VPARAM1_REG;
when "0000001000000" => slv_ip2bus_data <= VPARAM2_REG;
when "0000000100000" => slv_ip2bus_data <= CLK_O_REG;
when "0000000010000" => slv_ip2bus_data <= CLK_FB_REG;
when "0000000001000" => slv_ip2bus_data <= CLK_FRAC_REG;
when "0000000000100" => slv_ip2bus_data <= CLK_DIV_REG;
when "0000000000010" => slv_ip2bus_data <= CLK_LOCK_REG;
when "0000000000001" => slv_ip2bus_data <= CLK_FLTR_REG;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
--------------------------------------------------------------------------------
--
-- File:
-- user_logic.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author(s):
-- Sam Bobrowicz
-- Karol Gugala <kgugala@antmicro.com>
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_TDATA_WIDTH : integer := 32; --must be 32
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 13;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT mmcme2_drp
GENERIC(
DIV_F : integer
);
PORT(
SEN : IN std_logic;
SCLK : IN std_logic;
RST : IN std_logic;
S1_CLKOUT0 : IN std_logic_vector(35 downto 0);
S1_CLKFBOUT : IN std_logic_vector(35 downto 0);
S1_DIVCLK : IN std_logic_vector(13 downto 0);
S1_LOCK : IN std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : IN std_logic_vector(9 downto 0);
REF_CLK : IN std_logic;
SRDY : OUT std_logic;
PXL_CLK : OUT std_logic;
PXL_CLK_INV : OUT std_logic;
CLKFBOUT_O : OUT std_logic;
CLKFBOUT_I : IN std_logic;
LOCKED_O : OUT std_logic
);
END COMPONENT;
COMPONENT vdma_to_vga
GENERIC(
C_RED_WIDTH : integer;
C_GREEN_WIDTH : integer;
C_BLUE_WIDTH : integer;
C_S_AXIS_TDATA_WIDTH : integer
);
PORT(
LOCKED_I : IN std_logic;
ENABLE_I : IN std_logic;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
USR_WIDTH_I : IN std_logic_vector(11 downto 0);
USR_HEIGHT_I : IN std_logic_vector(11 downto 0);
USR_HPS_I : IN std_logic_vector(11 downto 0);
USR_HPE_I : IN std_logic_vector(11 downto 0);
USR_HPOL_I : IN std_logic;
USR_HMAX_I : IN std_logic_vector(11 downto 0);
USR_VPS_I : IN std_logic_vector(11 downto 0);
USR_VPE_I : IN std_logic_vector(11 downto 0);
USR_VPOL_I : IN std_logic;
USR_VMAX_I : IN std_logic_vector(11 downto 0);
RUNNING_O : OUT std_logic;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0)
);
END COMPONENT;
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal mmcm_clk_inv : std_logic;
signal pxl_clk : std_logic;
signal pxl_clk_inv : std_logic;
signal pxl_clk_inv5x : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal vga_running : std_logic;
signal clk_state : CLK_STATE_TYPE := RESET;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal CTRL_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal STAT_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal FRAME_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_O_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FB_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FRAC_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_DIV_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_LOCK_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FLTR_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg_write_sel : std_logic_vector(12 downto 0);
signal slv_reg_read_sel : std_logic_vector(12 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFG_inst: BUFG port map(
O => pxl_clk_inv5x, -- 1-bit output: Clock output port
I => mmcm_clk_inv -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFR_inst_inv : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output port
CE => enable_reg, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => pxl_clk_inv5x -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
ENABLE_O <= enable_reg;
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
BUFG_inst_inv : BUFG
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output
I => mmcm_clk_inv -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
pxl_clk_mux: BUFGMUX
port map (
O => PXL_CLK_O, -- 1-bit output: Clock output
I0 => pxl_clk, -- 1-bit input: Clock input (S=0)
I1 => pxl_clk_inv, -- 1-bit input: Clock input (S=1)
S => CTRL_REG(1) -- 1-bit input: Clock select
);
VDMA_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED => --This state ensures that the initial SRDY pulse doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
GENERIC MAP(
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => pxl_clk,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
DEBUG_O => DEBUG_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(12 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(12 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
CTRL_REG <= (others => '0');
--STAT_REG <= (others => '0');
FRAME_REG <= (others => '0');
HPARAM1_REG <= (others => '0');
HPARAM2_REG <= (others => '0');
VPARAM1_REG <= (others => '0');
VPARAM2_REG <= (others => '0');
CLK_O_REG <= (others => '0');
CLK_FB_REG <= (others => '0');
CLK_FRAC_REG <= (others => '0');
CLK_DIV_REG <= (others => '0');
CLK_LOCK_REG <= (others => '0');
CLK_FLTR_REG <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CTRL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--***Status register is read only***
-- when "0100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- STAT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "0010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
FRAME_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_O_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FB_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FRAC_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_DIV_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_LOCK_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FLTR_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, CTRL_REG, STAT_REG, FRAME_REG, HPARAM1_REG, HPARAM2_REG, VPARAM1_REG, VPARAM2_REG, CLK_O_REG, CLK_FB_REG, CLK_FRAC_REG, CLK_DIV_REG, CLK_LOCK_REG, CLK_FLTR_REG ) is
begin
case slv_reg_read_sel is
when "1000000000000" => slv_ip2bus_data <= CTRL_REG;
when "0100000000000" => slv_ip2bus_data <= STAT_REG;
when "0010000000000" => slv_ip2bus_data <= FRAME_REG;
when "0001000000000" => slv_ip2bus_data <= HPARAM1_REG;
when "0000100000000" => slv_ip2bus_data <= HPARAM2_REG;
when "0000010000000" => slv_ip2bus_data <= VPARAM1_REG;
when "0000001000000" => slv_ip2bus_data <= VPARAM2_REG;
when "0000000100000" => slv_ip2bus_data <= CLK_O_REG;
when "0000000010000" => slv_ip2bus_data <= CLK_FB_REG;
when "0000000001000" => slv_ip2bus_data <= CLK_FRAC_REG;
when "0000000000100" => slv_ip2bus_data <= CLK_DIV_REG;
when "0000000000010" => slv_ip2bus_data <= CLK_LOCK_REG;
when "0000000000001" => slv_ip2bus_data <= CLK_FLTR_REG;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT rgbfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_exdes IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END rgbfifo_pkg;
PACKAGE BODY rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END rgbfifo_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT rgbfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_exdes IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END rgbfifo_pkg;
PACKAGE BODY rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END rgbfifo_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT rgbfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_exdes IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END rgbfifo_pkg;
PACKAGE BODY rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END rgbfifo_pkg;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package sync_rst_pkg is
component sync_rst is
generic (
N_SYNC_FFS : integer := 2;
RST_POLARITY : std_logic := '1'
);
port (
arst_i : in std_logic;
sclk_i : in std_logic;
srst_o : out std_logic;
);
end component sync_rst;
end package sync_rst_pkg;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sync_rst is
generic (
N_SYNC_FFS : integer := 2;
RST_POLARITY : std_logic := '1'
);
port (
arst_i : in std_logic;
sclk_i : in std_logic;
srst_o : out std_logic;
);
begin
assert N_SYNC_FFS >= 2
report "Entity sync_rst: Invalid generic value."
severity ERROR;
end entity sync_rst;
architecture rtl of sync_rst is
signal srst_ffs : std_logic_vector(N_SYNC_FFS-1 downto 0);
begin
p_sync_rst: process (sclk_i, arst_i) is
begin
if (arst_i = RST_POLARITY) then
srst_ffs <= (others => RST_POLARITY);
elsif (rising_edge(sclk_i)) then
srst_ffs <= srst_ffs(N_SYNC_FFS-2 downto 0) & not RST_POLARITY;
end if;
end process p_sync_rst;
srst_o <= srst_ffs(N_SYNC_FFS-1);
end architecture rtl;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4256)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4256)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect key_block
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`protect data_block
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|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 74,
C_DOUT_WIDTH => 74,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Wed Oct 19 08:55:30 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_UAMN -nodelta -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-conf-c.vhd,v 1.2 2005/10/24 12:14:02 wig Exp $
-- $Date: 2005/10/24 12:14:02 $
-- $Log: ent_b-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/10/24 12:14:02 wig
-- added output.language.verilog = ansistyle,2001param
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.61 2005/10/18 09:34:36 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_b_rtl_conf / ent_b
--
configuration ent_b_rtl_conf of ent_b is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_ba : ent_ba
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ba_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_bb : ent_bb
use configuration work.ent_bb_rtl_conf;
end for;
end for;
end ent_b_rtl_conf;
--
-- End of Generated Configuration ent_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v34_v1_02_a;
use plb_v34_v1_02_a.All;
entity plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_ordered : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end plb_bus_wrapper;
architecture STRUCTURE of plb_bus_wrapper is
component plb_v34 is
generic (
C_PLB_NUM_MASTERS : integer;
C_PLB_NUM_SLAVES : integer;
C_PLB_MID_WIDTH : integer;
C_PLB_AWIDTH : integer;
C_PLB_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_NUM_OPBCLK_PLB2OPB_REARB : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1);
M_BE : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*(C_PLB_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_compress : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_guarded : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*2)-1);
M_ordered : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*C_PLB_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_MErr : in std_logic_vector(0 to (C_PLB_NUM_SLAVES*C_PLB_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLB_NUM_SLAVES*C_PLB_NUM_MASTERS - 1);
Sl_rdBTerm : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLB_NUM_SLAVES*C_PLB_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLB_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLB_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
PLB_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : out std_logic_vector(0 to (C_PLB_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLB_NUM_MASTERS*C_PLB_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLB_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLB_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
plb_bus : plb_v34
generic map (
C_PLB_NUM_MASTERS => 2,
C_PLB_NUM_SLAVES => 2,
C_PLB_MID_WIDTH => 1,
C_PLB_AWIDTH => 32,
C_PLB_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 0,
C_IRQ_ACTIVE => '1',
C_NUM_OPBCLK_PLB2OPB_REARB => 5
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MErr => Sl_MErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMErr => PLB_SMErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
ArbAddrVldReg => ArbAddrVldReg,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard (james@gibbard.me)
-- Date : 2017-03-25
-- File : fir_filter_tb.vhd
---------------------------------------------------------------------------
-- Description :
---------------------------------------------------------------------------
-- Change Log
-- Version 0.0.1 : Initial version
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
use work.signed_array_pkg.all;
entity fir_filter_tb is
end fir_filter_tb;
architecture testbench of fir_filter_tb is
constant coeficient_width : integer := 16;
constant data_width : integer := 16;
constant num_taps : integer := 15;
signal clk : std_logic;
signal rst : std_logic;
signal en_in : std_logic;
signal data_in : signed(data_width - 1 downto 0);
signal taps : signed_array_15 := (X"0001", X"0002", X"0003", X"0004", X"0005", X"0006",X"0007", X"0008", X"0009", X"000A", X"000B", X"000C", X"000D", X"000E", X"000F");
signal data_valid_in : std_logic;
signal data_out : signed(data_width - 1 downto 0);
signal data_valid_out : std_logic;
signal ready_out : std_logic;
signal scale_factor : unsigned(5 downto 0) := (others => '0');
signal counter : unsigned(3 downto 0);
file test_vector_file : text;
constant clk_period : time := 20 ns;
begin
uut : entity work.fir_filter
generic map (
data_in_width_g => data_width,
data_out_width_g => data_width,
num_taps_g => num_taps
)
port map (
clk => clk,
rst => rst,
en_in => en_in,
data_in => data_in,
taps_in => taps,
scale_factor_in => scale_factor,
data_valid_in => data_valid_in,
data_out => data_out,
data_valid_out => data_valid_out,
ready_out => ready_out
);
--Make a clock signal with a 50% duty cycle
clk_gen_p : process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
--Take module out of reset
enable_p : process
begin
rst <= '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
rst <= '0';
wait;
end process;
stimulus_p : process(clk)
variable row : line;
variable test_vector : integer := 0;
begin
file_open(test_vector_file, "test.txt", read_mode);
if rising_edge(clk) then
if rst = '1' then
data_in <= (others => '0');
data_valid_in <= '0';
counter <= (others => '0');
else
if counter = 15 then
--if ready_out = '1' then
if(not endfile(test_vector_file)) then
readline(test_vector_file,row);
end if;
read(row, test_vector);
data_in <= to_signed(test_vector, data_width);
data_valid_in <= '1';
else
data_valid_in <= '0';
data_in <= (others => '0');
end if;
if ready_out = '1' then
counter <= counter + 1;
end if;
end if;
end if;
end process;
end testbench;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
fxclk_in : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd0,rd1 : std_logic := '1';
signal wr : std_logic := '1';
signal wr0,wr1 : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
signal fxclk : std_logic; -- 96 MHz
signal fxclk_fb : std_logic;
begin
-- PLL is used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => fxclk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd1 or rd0 or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if (wr1 = '1') and (wr0 = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd1 = '1') and (rd0 = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd0 <= rd;
rd1 <= rd0;
wr0 <= wr;
wr1 <= wr0;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
fxclk_in : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd0,rd1 : std_logic := '1';
signal wr : std_logic := '1';
signal wr0,wr1 : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
signal fxclk : std_logic; -- 96 MHz
signal fxclk_fb : std_logic;
begin
-- PLL is used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => fxclk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd1 or rd0 or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if (wr1 = '1') and (wr0 = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd1 = '1') and (rd0 = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd0 <= rd;
rd1 <= rd0;
wr0 <= wr;
wr1 <= wr0;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
fxclk_in : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd0,rd1 : std_logic := '1';
signal wr : std_logic := '1';
signal wr0,wr1 : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
signal fxclk : std_logic; -- 96 MHz
signal fxclk_fb : std_logic;
begin
-- PLL is used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => fxclk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd1 or rd0 or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if (wr1 = '1') and (wr0 = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd1 = '1') and (rd0 = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd0 <= rd;
rd1 <= rd0;
wr0 <= wr;
wr1 <= wr0;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
fxclk_in : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd0,rd1 : std_logic := '1';
signal wr : std_logic := '1';
signal wr0,wr1 : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
signal fxclk : std_logic; -- 96 MHz
signal fxclk_fb : std_logic;
begin
-- PLL is used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => fxclk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd1 or rd0 or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if (wr1 = '1') and (wr0 = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd1 = '1') and (rd0 = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd0 <= rd;
rd1 <= rd0;
wr0 <= wr;
wr1 <= wr0;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff07 is
port (q : out std_logic;
d : std_logic;
clk : std_logic);
end dff07;
architecture behav of dff07 is
begin
process (clk) is
variable a, b : std_logic;
begin
if rising_edge (clk) then
a := d;
b := a;
q <= b;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity qcounterate is
generic ( defaultrate : std_logic_vector(11 downto 0));
port ( ibus : in std_logic_vector (11 downto 0);
loadrate : in std_logic;
rateout : out std_logic;
clk : in std_logic);
end qcounterate;
architecture Behavioral of qcounterate is
signal rate: std_logic_vector (11 downto 0) := defaultrate; -- divides by n+2, 0x800 for divide by 1
signal count: std_logic_vector (11 downto 0);
alias countmsb: std_logic is count(11);
begin
arate: process (clk,count)
begin
if rising_edge(clk) then
if countmsb= '0' then
count <= count -1;
else
count <= rate;
end if;
if loadrate = '1' then
rate <= ibus;
end if;
end if;
rateout <= countmsb;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity antirebote is
Port ( CLK : in STD_LOGIC;
a : in STD_LOGIC;
b : out STD_LOGIC);
end antirebote;
architecture Behavioral of antirebote is
signal cont : integer := 9999999;
begin
process begin
wait until rising_edge(CLK);
-- 10'000.000 -> reloj 50 Hz -> 200*(10**-3) / 20*(10**-9) = 10'000.000
b <= '0';
if (a = '0' and cont < 10000000) then
cont <= cont + 1;
end if;
if (a = '1' and cont < 10000000) then
cont <= cont + 1;
end if;
if (a = '1' and cont >= 10000000) then
b <= '1';
cont <= 0;
end if;
end process;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_rotkey is
end tb_rotkey;
architecture behav of tb_rotkey is
signal clk : std_logic := '0';
signal rotA : std_logic := '0';
signal rotB : std_logic := '0';
signal rotPush : std_logic := '0';
signal rotRightEvent : std_logic := '0';
signal rotLeftEvent : std_logic := '0';
signal rotPushEvent : std_logic := '0';
begin
process
begin
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
begin
wait for 1400 ns;
rotPush <= '1';
wait for 1400 ns;
rotPush <= '0';
wait for 1400 ns;
rotA <= '1';
wait for 1400 ns;
rotB <= '1';
wait for 1400 ns;
rotA <= '0';
wait for 1400 ns;
rotB <= '0';
wait for 2000 ns;
rotB <= '1';
wait for 1400 ns;
rotA <= '1';
wait for 1400 ns;
rotB <= '0';
wait for 1400 ns;
rotA <= '0';
wait for 3000 ns;
assert false report "done" severity failure;
wait;
end process;
rotkey: entity work.rotkey
generic map(
CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns
)
port map(
clk => clk,
rotA => rotA,
rotB => rotB,
rotPush => rotPush,
rotRightEvent => rotRightEvent,
rotLeftEvent => rotLeftEvent,
rotPushEvent => rotPushEvent
);
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype imm_type_t is std_logic_vector(2 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constant ALU_NONE : alu_func_t := "0000";
constant ALU_ADD : alu_func_t := "0001";
constant ALU_ADDU : alu_func_t := "0010";
constant ALU_SUB : alu_func_t := "0011";
constant ALU_SUBU : alu_func_t := "0100";
constant ALU_SLT : alu_func_t := "0101";
constant ALU_SLTU : alu_func_t := "0110";
constant ALU_AND : alu_func_t := "0111";
constant ALU_OR : alu_func_t := "1000";
constant ALU_XOR : alu_func_t := "1001";
constant ALU_SLL : alu_func_t := "1010";
constant ALU_SRA : alu_func_t := "1011";
constant ALU_SRL : alu_func_t := "1100";
subtype insn_type_t is std_logic_vector(3 downto 0);
constant OP_ILLEGAL : insn_type_t := "0000";
constant OP_LUI : insn_type_t := "0001";
constant OP_AUIPC : insn_type_t := "0010";
constant OP_JAL : insn_type_t := "0011";
constant OP_JALR : insn_type_t := "0100";
constant OP_BRANCH : insn_type_t := "0101";
constant OP_LOAD : insn_type_t := "0110";
constant OP_STORE : insn_type_t := "0111";
constant OP_ALU : insn_type_t := "1000";
subtype branch_type_t is std_logic_vector(2 downto 0);
constant BRANCH_NONE : branch_type_t := "000";
constant BEQ : branch_type_t := "001";
constant BNE : branch_type_t := "010";
constant BLT : branch_type_t := "011";
constant BGE : branch_type_t := "100";
constant BLTU : branch_type_t := "101";
constant BGEU : branch_type_t := "110";
subtype load_type_t is std_logic_vector(2 downto 0);
constant LOAD_NONE : load_type_t := "000";
constant LB : load_type_t := "001";
constant LH : load_type_t := "010";
constant LW : load_type_t := "011";
constant LBU : load_type_t := "100";
constant LHU : load_type_t := "101";
subtype store_type_t is std_logic_vector(1 downto 0);
constant STORE_NONE : store_type_t := "00";
constant SB : store_type_t := "01";
constant SH : store_type_t := "10";
constant SW : store_type_t := "11";
-- print a string with a newline
procedure println (str : in string);
procedure print (slv : in std_logic_vector);
procedure write(l : inout line; slv : in std_logic_vector);
function hstr(slv : std_logic_vector) return string;
-- instruction formats
type r_insn_t is (R_ADD, R_SLT, R_SLTU, R_AND, R_OR, R_XOR, R_SLL, R_SRL, R_SUB, R_SRA);
type i_insn_t is (I_JALR, I_LB, I_LH, I_LW, I_LBU, I_LHU, I_ADDI, I_SLTI, I_SLTIU, I_XORI, I_ORI, I_ANDI, I_SLLI, I_SRLI, I_SRAI);
type s_insn_t is (S_SB, S_SH, S_SW);
type sb_insn_t is (SB_BEQ, SB_BNE, SB_BLT, SB_BGE, SB_BLTU, SB_BGEU);
type u_insn_t is (U_LUI, U_AUIPC);
type uj_insn_t is (UJ_JAL);
-- ADDI r0, r0, r0
constant NOP : word := "00000000000000000000000000010011";
end package common;
package body common is
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- print a string with a newline
procedure println (str : in string) is
variable l : line;
begin -- procedure println
write(l, str);
writeline(output, l);
end procedure println;
procedure write(l : inout line; slv : in std_logic_vector) is
begin
for i in slv'range loop
if slv(i) = '0' then
write(l, string'("0"));
elsif slv(i) = '1' then
write(l, string'("1"));
elsif slv(i) = 'X' then
write(l, string'("X"));
elsif slv(i) = 'U' then
write(l, string'("U"));
end if;
end loop; -- i
end procedure write;
procedure print (slv : in std_logic_vector) is
variable l : line;
begin -- procedure print
write(l, slv);
writeline(output, l);
end procedure print;
end package body common;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype imm_type_t is std_logic_vector(2 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constant ALU_NONE : alu_func_t := "0000";
constant ALU_ADD : alu_func_t := "0001";
constant ALU_ADDU : alu_func_t := "0010";
constant ALU_SUB : alu_func_t := "0011";
constant ALU_SUBU : alu_func_t := "0100";
constant ALU_SLT : alu_func_t := "0101";
constant ALU_SLTU : alu_func_t := "0110";
constant ALU_AND : alu_func_t := "0111";
constant ALU_OR : alu_func_t := "1000";
constant ALU_XOR : alu_func_t := "1001";
constant ALU_SLL : alu_func_t := "1010";
constant ALU_SRA : alu_func_t := "1011";
constant ALU_SRL : alu_func_t := "1100";
subtype insn_type_t is std_logic_vector(3 downto 0);
constant OP_ILLEGAL : insn_type_t := "0000";
constant OP_LUI : insn_type_t := "0001";
constant OP_AUIPC : insn_type_t := "0010";
constant OP_JAL : insn_type_t := "0011";
constant OP_JALR : insn_type_t := "0100";
constant OP_BRANCH : insn_type_t := "0101";
constant OP_LOAD : insn_type_t := "0110";
constant OP_STORE : insn_type_t := "0111";
constant OP_ALU : insn_type_t := "1000";
subtype branch_type_t is std_logic_vector(2 downto 0);
constant BRANCH_NONE : branch_type_t := "000";
constant BEQ : branch_type_t := "001";
constant BNE : branch_type_t := "010";
constant BLT : branch_type_t := "011";
constant BGE : branch_type_t := "100";
constant BLTU : branch_type_t := "101";
constant BGEU : branch_type_t := "110";
subtype load_type_t is std_logic_vector(2 downto 0);
constant LOAD_NONE : load_type_t := "000";
constant LB : load_type_t := "001";
constant LH : load_type_t := "010";
constant LW : load_type_t := "011";
constant LBU : load_type_t := "100";
constant LHU : load_type_t := "101";
subtype store_type_t is std_logic_vector(1 downto 0);
constant STORE_NONE : store_type_t := "00";
constant SB : store_type_t := "01";
constant SH : store_type_t := "10";
constant SW : store_type_t := "11";
-- print a string with a newline
procedure println (str : in string);
procedure print (slv : in std_logic_vector);
procedure write(l : inout line; slv : in std_logic_vector);
function hstr(slv : std_logic_vector) return string;
-- instruction formats
type r_insn_t is (R_ADD, R_SLT, R_SLTU, R_AND, R_OR, R_XOR, R_SLL, R_SRL, R_SUB, R_SRA);
type i_insn_t is (I_JALR, I_LB, I_LH, I_LW, I_LBU, I_LHU, I_ADDI, I_SLTI, I_SLTIU, I_XORI, I_ORI, I_ANDI, I_SLLI, I_SRLI, I_SRAI);
type s_insn_t is (S_SB, S_SH, S_SW);
type sb_insn_t is (SB_BEQ, SB_BNE, SB_BLT, SB_BGE, SB_BLTU, SB_BGEU);
type u_insn_t is (U_LUI, U_AUIPC);
type uj_insn_t is (UJ_JAL);
-- ADDI r0, r0, r0
constant NOP : word := "00000000000000000000000000010011";
end package common;
package body common is
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- print a string with a newline
procedure println (str : in string) is
variable l : line;
begin -- procedure println
write(l, str);
writeline(output, l);
end procedure println;
procedure write(l : inout line; slv : in std_logic_vector) is
begin
for i in slv'range loop
if slv(i) = '0' then
write(l, string'("0"));
elsif slv(i) = '1' then
write(l, string'("1"));
elsif slv(i) = 'X' then
write(l, string'("X"));
elsif slv(i) = 'U' then
write(l, string'("U"));
end if;
end loop; -- i
end procedure write;
procedure print (slv : in std_logic_vector) is
variable l : line;
begin -- procedure print
write(l, slv);
writeline(output, l);
end procedure print;
end package body common;
|
-- test bench for the PCG pseudorandom number generator
--
-- Original author: Blake Johnson
-- Copyright 2017 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PCG_XSH_RR_tb is
end;
architecture bench of PCG_XSH_RR_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '0';
constant clock_period : time := 4.0 ns;
signal stop_the_clock : boolean := false;
signal checking_finished : boolean := false;
constant LATENCY : natural := 3;
signal seed : std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(1234, 64));
signal rand_out : std_logic_vector(31 downto 0);
signal valid : std_logic;
type rand_array is array(0 to 7) of std_logic_vector(31 downto 0);
signal rand_outs : rand_array := (others => (others => '0'));
-- expected outs computed using PCG.jl:
-- julia> include("PCG.jl")
-- julia> using PCG
-- julia> g = PCG(1234)
-- julia> [rand(g) for _ in 1:8]
signal expected_outs : rand_array := (
0 => x"00000000",
1 => x"cb267ac2",
2 => x"035401a4",
3 => x"3db8c0ea",
4 => x"45b49a87",
5 => x"42f4a7aa",
6 => x"d6016e1c",
7 => x"3922cc67"
);
type TestBenchState_t is (RESET, TEST_RAND, FINISHED);
signal test_bench_state : TestBenchState_t;
begin
uut: entity work.PCG_XSH_RR
port map (
clk => clk,
rst => rst,
seed => seed,
rand => rand_out,
valid => valid
);
clk <= not clk after clock_period / 2 when not stop_the_clock;
stimulus : process
begin
---------------------------
test_bench_state <= RESET;
rst <= '1';
wait for 20 ns;
wait until rising_edge(clk);
rst <= '0';
test_bench_state <= TEST_RAND;
for ct in rand_outs'range loop
wait until rising_edge(valid);
rand_outs(ct) <= rand_out;
end loop;
test_bench_state <= FINISHED;
wait for 100 ns;
stop_the_clock <= true;
wait;
end process;
checking : process
begin
wait until rising_edge(clk) and test_bench_state = FINISHED;
for ct in rand_outs'range loop
-- compare against a known result
assert rand_outs(ct) = expected_outs(ct) report "PCG output error: expected " &
integer'image( to_integer( unsigned(expected_outs(ct) ) )) & " but got " &
integer'image( to_integer( unsigned(rand_outs(ct) ) ));
end loop;
report "FINISHED PCG output checking";
checking_finished <= true;
end process;
end;
|
-- Xilinx XPort Language Converter, Version 4.1 (110)
--
-- ABEL Design Source: C:\home\kirill\xillinx\testing.abl
-- VHDL Design Output: testing.vhd
-- Created 02-Sep-2005 12:24 PM
--
-- Copyright (c) 2005, Xilinx, Inc. All Rights Reserved.
-- Xilinx Inc makes no warranty, expressed or implied, with respect to
-- the operation and/or functionality of the converted output files.
--
-- ee200 assignment 1
Library IEEE;
use IEEE.std_logic_1164.all;
entity testing is
Port (
A40, A39, A73: buffer std_logic;
A299, A265, A298: in std_logic;
A105: buffer std_logic;
A202, A201: in std_logic;
A43, A8, A41: buffer std_logic;
A269, A232, A170: in std_logic;
A106: buffer std_logic;
A166: in std_logic;
A76: buffer std_logic;
A234, A236, A167: in std_logic;
A109, A140: buffer std_logic;
A300: in std_logic;
A42: buffer std_logic;
A203, A267: in std_logic;
A108: buffer std_logic;
A235, A233: in std_logic;
A74: buffer std_logic;
A301, A168: in std_logic;
A138, A7, A139, A142, A6: buffer std_logic;
A268: in std_logic;
A141, A10, A72: buffer std_logic;
A200: in std_logic;
A75: buffer std_logic;
A169: in std_logic;
A107, A9: buffer std_logic;
A266, A302, A199: in std_logic
);
end testing;
architecture testing_behav of testing is
signal A165, A12, A137, A188, A270, A317, A314, A61, A258, A119, A66, A220,
A309, A230, A112, A295, A69, A310, A121, A325, A284, A91, A93, A257,
A34, A195, A160, A57, A321, A173, A281, A186, A89, A179, A48, A239,
A13, A120, A253, A23, A154, A50, A211, A190, A206, A175, A16, A68,
A38, A17, A225, A44, A129, A244, A85, A131, A192, A104, A273, A254,
A113, A223, A243, A4, A96, A101, A311, A318, A117, A124, A78, A147,
A324, A216, A161, A259, A31, A56, A315, A97, A231, A128, A278, A178,
A3, A22, A60, A198, A250, A26, A100, A306, A287, A261, A171, A227,
A94, A59, A82, A288, A172, A246, A185, A151, A155, A132, A30, A35,
A183, A224, A79, A189, A328, A14, A323, A116, A293, A65, A320, A207,
A88, A193, A305, A249, A327, A237, A215, A219, A277, A176, A53, A18,
A296, A125, A294, A228, A47, A280, A25, A217, A102, A205, A46, A67,
A5, A255, A251, A204, A272, A222, A64, A98, A95, A164, A135, A285,
A70, A149, A32, A312, A81, A49, A275, A248, A208, A123, A282, A289,
A146, A177, A159, A2, A118, A90, A297, A182, A242, A110, A152, A283,
A197, A83, A319, A307, A36, A241, A264, A326, A63, A260, A194, A144,
A330, A163, A212, A158, A291, A114, A133, A51, A229, A304, A29, A316,
A87, A28, A62, A54, A33, A276, A290, A322, A303, A145, A184, A111,
A274, A214, A58, A20, A226, A126, A245, A80, A86, A196, A52, A313,
A143, A218, A103, A209, A156, A11, A174, A187, A115, A71, A240, A256,
A92, A1, A247, A292, A150, A210, A134, A238, A162, A286, A329, A148,
A252, A213, A45, A21, A27, A127, A221, A99, A153, A263, A191, A19,
A37, A77, A24, A157, A279, A181, A55, A15, A271, A84, A262, A308,
A122, A180, A136, A130: std_logic;
begin
-- Start of original equations
A198 <= A176 and A191;
A197 <= (not A176) and (not A198);
A196 <= A176 or A191;
A195 <= (not A169) or (not A170);
A194 <= A176 or A191;
A193 <= (not A192) and (not A176);
A192 <= A176 and A191;
A191 <= (not A167) or (not A168);
A190 <= A168 and A180;
A189 <= A169 or A176;
A188 <= A169 or A170;
A187 <= (not A197) or (not A196);
A186 <= A195 and A188;
A185 <= ((not A169) and A176) or (A169 and (not A176));
A184 <= (not A193) or (not A194);
A183 <= (A168 and A180) or ((not A168) and (not A180));
A182 <= A190 or A167;
A181 <= A187 and A168;
A180 <= A189 and A188;
A179 <= A184 and A168;
A178 <= A186 and A185;
A177 <= ((not A178) and A168) or (A178 and (not A168));
A176 <= ((not A166) and A167) or (A166 and (not A167));
A175 <= A176 and A183;
A174 <= A176 and A182;
A173 <= A181 or A180;
A172 <= A179 or A178;
A171 <= A177 and A176;
A204 <= A210 and A209;
A205 <= A212 or A211;
A206 <= A214 or A213;
A207 <= A209 and A215;
A208 <= A209 and A216;
A209 <= ((not A199) and A200) or (A199 and (not A200));
A210 <= ((not A211) and A201) or (A211 and (not A201));
A211 <= A219 and A218;
A212 <= A217 and A201;
A213 <= A222 and A221;
A214 <= A220 and A201;
A215 <= A223 or A200;
A216 <= (A201 and A213) or ((not A201) and (not A213));
A217 <= (not A226) or (not A227);
A218 <= ((not A202) and A209) or (A202 and (not A209));
A219 <= A228 and A221;
A220 <= (not A230) or (not A229);
A221 <= A202 or A203;
A222 <= A202 or A209;
A223 <= A201 and A213;
A224 <= (not A200) or (not A201);
A225 <= A209 and A224;
A226 <= (not A225) and (not A209);
A227 <= A209 or A224;
A228 <= (not A202) or (not A203);
A229 <= A209 or A224;
A230 <= (not A209) and (not A231);
A231 <= A209 and A224;
A237 <= A243 and A242;
A238 <= A245 or A244;
A239 <= A247 or A246;
A240 <= A242 and A248;
A241 <= A242 and A249;
A242 <= ((not A232) and A233) or (A232 and (not A233));
A243 <= ((not A244) and A234) or (A244 and (not A234));
A244 <= A252 and A251;
A245 <= A250 and A234;
A246 <= A255 and A254;
A247 <= A253 and A234;
A248 <= A256 or A233;
A249 <= (A234 and A246) or ((not A234) and (not A246));
A250 <= (not A259) or (not A260);
A251 <= ((not A235) and A242) or (A235 and (not A242));
A252 <= A261 and A254;
A253 <= (not A263) or (not A262);
A254 <= A235 or A236;
A255 <= A235 or A242;
A256 <= A234 and A246;
A257 <= (not A233) or (not A234);
A258 <= A242 and A257;
A259 <= (not A258) and (not A242);
A260 <= A242 or A257;
A261 <= (not A235) or (not A236);
A262 <= A242 or A257;
A263 <= (not A235) or A235;
A264 <= A242 and A257;
A270 <= A276 and A275;
A271 <= A278 or A277;
A272 <= A280 or A279;
A273 <= A275 and A281;
A274 <= A275 and A282;
A275 <= ((not A265) and A266) or (A265 and (not A266));
A276 <= ((not A277) and A267) or (A277 and (not A267));
A277 <= A285 and A284;
A278 <= A283 and A267;
A279 <= A288 and A287;
A280 <= A286 and A267;
A281 <= A289 or A266;
A282 <= (A267 and A279) or ((not A267) and (not A279));
A283 <= (not A292) or (not A293);
A284 <= ((not A268) and A275) or (A268 and (not A275));
A285 <= A294 and A287;
A286 <= (not A296) or (not A295);
A287 <= A268 or A269;
A288 <= A268 or A275;
A289 <= A267 and A279;
A290 <= (not A266) or (not A267);
A291 <= A275 and A290;
A292 <= (not A291) and (not A275);
A293 <= A275 or A290;
A294 <= (not A268) or (not A269);
A295 <= A275 or A290;
A296 <= (not A275) and (not A297);
A297 <= A275 and A290;
A303 <= A309 and A308;
A304 <= A311 or A310;
A305 <= A313 or A312;
A306 <= A308 and A314;
A307 <= A308 and A315;
A308 <= ((not A298) and A299) or (A298 and (not A299));
A309 <= ((not A310) and A300) or (A310 and (not A300));
A310 <= A318 and A317;
A311 <= A316 and A300;
A312 <= A321 and A320;
A313 <= A319 and A300;
A314 <= A322 or A299;
A315 <= (A300 and A312) or ((not A300) and (not A312));
A316 <= (not A325) or (not A326);
A317 <= ((not A301) and A308) or (A301 and (not A308));
A318 <= A327 and A320;
A319 <= (not A329) or (not A328);
A320 <= A301 or A302;
A321 <= A301 or A308;
A322 <= A300 and A312;
A323 <= (not A299) or (not A300);
A324 <= A308 and A323;
A325 <= (not A324) and (not A308);
A326 <= A308 or A323;
A327 <= (not A301) or (not A302);
A328 <= A308 or A323;
A329 <= (not A308) and (not A330);
A330 <= A308 and A323;
A165 <= A143 and A158;
A164 <= (not A143) and (not A165);
A163 <= A143 or A158;
A162 <= (not A136) or (not A137);
A161 <= A143 or A158;
A160 <= (not A159) and (not A143);
A159 <= A143 and A158;
A158 <= (not A134) or (not A135);
A157 <= A135 and A147;
A156 <= A136 or A143;
A155 <= A136 or A137;
A154 <= (not A164) or (not A163);
A153 <= A162 and A155;
A152 <= ((not A136) and A143) or (A136 and (not A143));
A151 <= (not A160) or (not A161);
A150 <= (A135 and A147) or ((not A135) and (not A147));
A149 <= A157 or A134;
A148 <= A154 and A135;
A147 <= A156 and A155;
A146 <= A151 and A135;
A145 <= A153 and A152;
A144 <= ((not A145) and A135) or (A145 and (not A135));
A143 <= ((not A133) and A134) or (A133 and (not A134));
A142 <= A143 and A150;
A141 <= A143 and A149;
A140 <= A148 or A147;
A139 <= A146 or A145;
A138 <= A144 and A143;
A137 <= A307;
A136 <= A274;
A135 <= A241;
A134 <= A208;
A133 <= A171;
A132 <= A110 and A125;
A131 <= (not A110) and (not A132);
A130 <= A110 or A125;
A129 <= (not A103) or (not A104);
A128 <= A110 or A125;
A127 <= (not A126) and (not A110);
A126 <= A110 and A125;
A125 <= (not A101) or (not A102);
A124 <= A102 and A114;
A123 <= A103 or A110;
A122 <= A103 or A104;
A121 <= (not A131) or (not A130);
A120 <= A129 and A122;
A119 <= ((not A103) and A110) or (A103 and (not A110));
A118 <= (not A127) or (not A128);
A117 <= (A102 and A114) or ((not A102) and (not A114));
A116 <= A124 or A101;
A115 <= A121 and A102;
A114 <= A123 and A122;
A113 <= A118 and A102;
A112 <= A120 and A119;
A111 <= ((not A112) and A102) or (A112 and (not A102));
A110 <= ((not A100) and A101) or (A100 and (not A101));
A109 <= A110 and A117;
A108 <= A110 and A116;
A107 <= A115 or A114;
A106 <= A113 or A112;
A105 <= A111 and A110;
A104 <= A306;
A103 <= A273;
A102 <= A240;
A101 <= A207;
A100 <= A172;
A99 <= A77 and A92;
A98 <= (not A77) and (not A99);
A97 <= A77 or A92;
A96 <= (not A70) or (not A71);
A95 <= A77 or A92;
A94 <= (not A93) and (not A77);
A93 <= A77 and A92;
A92 <= (not A68) or (not A69);
A91 <= A69 and A81;
A90 <= A70 or A77;
A89 <= A70 or A71;
A88 <= (not A98) or (not A97);
A87 <= A96 and A89;
A86 <= ((not A70) and A77) or (A70 and (not A77));
A85 <= (not A94) or (not A95);
A84 <= (A69 and A81) or ((not A69) and (not A81));
A83 <= A91 or A68;
A82 <= A88 and A69;
A81 <= A90 and A89;
A80 <= A85 and A69;
A79 <= A87 and A86;
A78 <= ((not A79) and A69) or (A79 and (not A69));
A77 <= ((not A67) and A68) or (A67 and (not A68));
A76 <= A77 and A84;
A75 <= A77 and A83;
A74 <= A82 or A81;
A73 <= A80 or A79;
A72 <= A78 and A77;
A71 <= A305;
A70 <= A272;
A69 <= A239;
A68 <= A206;
A67 <= A173;
A66 <= A44 and A59;
A65 <= (not A44) and (not A66);
A64 <= A44 or A59;
A63 <= (not A37) or (not A38);
A62 <= A44 or A59;
A61 <= (not A60) and (not A44);
A60 <= A44 and A59;
A59 <= (not A35) or (not A36);
A58 <= A36 and A48;
A57 <= A37 or A44;
A56 <= A37 or A38;
A55 <= (not A65) or (not A64);
A54 <= A63 and A56;
A53 <= ((not A37) and A44) or (A37 and (not A44));
A52 <= (not A61) or (not A62);
A51 <= (A36 and A48) or ((not A36) and (not A48));
A50 <= A58 or A35;
A49 <= A55 and A36;
A48 <= A57 and A56;
A47 <= A52 and A36;
A46 <= A54 and A53;
A45 <= ((not A46) and A36) or (A46 and (not A36));
A44 <= ((not A34) and A35) or (A34 and (not A35));
A43 <= A44 and A51;
A42 <= A44 and A50;
A41 <= A49 or A48;
A40 <= A47 or A46;
A39 <= A45 and A44;
A38 <= A304;
A37 <= A271;
A36 <= A238;
A35 <= A205;
A34 <= A174;
A1 <= A303;
A2 <= A270;
A3 <= A237;
A4 <= A204;
A5 <= A175;
A6 <= A12 and A11;
A7 <= A14 or A13;
A8 <= A16 or A15;
A9 <= A11 and A17;
A10 <= A11 and A18;
A11 <= ((not A1) and A2) or (A1 and (not A2));
A12 <= ((not A13) and A3) or (A13 and (not A3));
A13 <= A21 and A20;
A14 <= A19 and A3;
A15 <= A24 and A23;
A16 <= A22 and A3;
A17 <= A25 or A2;
A18 <= (A3 and A15) or ((not A3) and (not A15));
A19 <= (not A28) or (not A29);
A20 <= ((not A4) and A11) or (A4 and (not A11));
A21 <= A30 and A23;
A22 <= (not A32) or (not A31);
A23 <= A4 or A5;
A24 <= A4 or A11;
A25 <= A3 and A15;
A26 <= (not A2) or (not A3);
A27 <= A11 and A26;
A28 <= (not A27) and (not A11);
A29 <= A11 or A26;
A30 <= (not A4) or (not A5);
A31 <= A11 or A26;
A32 <= (not A11) and (not A33);
A33 <= A11 and A26;
end testing_behav;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
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BSg=
`protect end_protected
|
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