content stringlengths 1 1.04M ⌀ |
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 257072)
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BSg=
`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_icache
-- File: mmu_icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.leon3.all;
entity mmu_icache is
generic (
fabtech : integer := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 2 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end;
architecture rtl of mmu_icache is
constant MUXDATA : boolean := (is_fpga(fabtech) = 1);
constant M_EN : boolean := (mmuen = 1);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
type valid_type is array (0 to ISETS-1) of std_logic_vector(ilinesize - 1 downto 0);
subtype lock_type is std_logic_vector(0 to ISETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset : std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type istatetype is (idle, trans, streaming, stop);
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic;
underrun : std_ulogic;
istate : istatetype; -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
vaddress : std_logic_vector(31 downto 2); -- virtual address buffer
valid : valid_type; --std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
cache : std_logic;
trans_op : std_logic;
cmiss : std_ulogic;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : icache_control_type := (
req => '0',
burst => '0',
holdn => '1',
overrun => '0',
underrun => '0',
istate => idle,
waddress => (others => '0'), -- has special handling
vaddress => (others => '0'), -- has special handling
valid => (others => (others => '0')),
hit => '0',
su => '0',
flush => '0',
flush2 => '0',
faddr => (others => '0'),
diagrdy => '0',
rndcnt => (others => '0'),
lrr => '0',
setrepl => (others => '0'),
diagset => (others => '0'),
lock => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
cache => '0',
trans_op => '0',
cmiss => '0',
bpmiss => '0',
eocl => '0'
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant LRAM_EN : integer := conv_integer(conv_std_logic(lram /= 0));
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0,
LRAM_EN, lramsize, lramstart, mmuen);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn, mmuico, mmudci)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((ilinesize -1) downto 0);
variable vmask : valid_type;
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid, nvalid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv, nvalidv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock : std_ulogic;
variable tag : cdatatype;
variable lramacc, ilramwr, lramcs : std_ulogic;
variable iladdr : std_logic_vector(TAG_HIGH downto LINE_LOW);
variable pftag : std_logic_vector(31 downto 2);
variable mmuici_trans_op : std_logic;
variable mmuici_su : std_logic;
variable mhold : std_ulogic;
variable shtag : std_logic_vector(ilinesize-1 downto 0);
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
v.cmiss := '0'; mhold := '0';
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not (r.flush
);
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.vaddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0'; iladdr := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0');
pftag := (others => '0'); validv := (others => '0');
v.trans_op := r.trans_op and (not mmuico.grant);
mmuici_trans_op := r.trans_op;
mmuici_su := ici.su;
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram /= 0) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
if irepl = dir then
set := conv_integer(ici.fpc(OFFSET_HIGH + SETBITS downto OFFSET_HIGH+1));
if (icramo.tag(set)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(set) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; end if;
validv(set) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(set)(ilinesize -1 downto 0));
else
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(i) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
end if;
for i in ISETS-1 downto 0 loop
shtag := (others => '0');
shtag(ilinesize-2 downto 0) := icramo.tag(i)(ilinesize-1 downto 1);
nvalidv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), shtag);
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
nvalid := nvalidv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
xaddr_inc := r.vaddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.vaddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when idle => -- main state and cache hit
for i in 0 to ISETS-1 loop
v.valid(i) := icramo.tag(i)(ilinesize-1 downto 0);
end loop;
--v.hit := '0';
v.hit := hit;
v.su := ici.su;
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and lramacc)='1' then v.bpmiss:='0'; v.eocl:='0'; end if;
if (eholdn and not (ici.inull or lramacc)) = '1' then
v.bpmiss := not (cacheon and hit and valid) and ici.nobpmiss;
v.eocl := not nvalid;
if not (cacheon and hit and valid) = '1' and ici.nobpmiss='0' then
v.istate := streaming;
v.holdn := '0'; v.overrun := '1'; v.cmiss := '1';
if M_EN and (mmudci.mmctrl1.e = '1') then
v.istate := trans;
mmuici_trans_op := '1';
v.trans_op := not mmuico.grant;
v.cache := '0';
--v.req := '0';
else
v.req := '1';
v.cache := '1';
end if;
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := ici.fpc(OFFSET_HIGH+SETBITS downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when trans =>
if M_EN then
v.holdn := '0';
if (mmuico.transdata.finish = '1') then
if mmuico.transdata.accexc = '1' then
-- if su then always do mexc
error := r.su or not mmudci.mmctrl1.nf; mds := '0';
v.holdn := '0'; v.istate := stop; v.burst := '0';
else
v.cache := mmuico.transdata.cache;
v.waddress := mmuico.transdata.data(31 downto 2);
v.istate := streaming; v.req := '1';
end if;
end if;
mhold := '1';
end if;
when streaming => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.vaddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
v.istate := stop; v.holdn := '0';
end if;
when stop => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := idle; v.flush := r.flush2;
when others => v.istate := idle;
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram /= 0 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => (others => '0'));
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
for i in 0 to ISETS-1 loop
vmask(i) := icramo.tag(i)(ilinesize-1 downto 0) or vmaskraw;
end loop;
else
for i in 0 to ISETS-1 loop
if r.hit = '1' then vmask(i) := r.valid(i) or vmaskraw;
else vmask(i) := vmaskraw; end if;
end loop;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram /= 0) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram /= 0) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := (others => dci.maddress(ilinesize -1 downto 0));
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
if MUXDATA then
rdata(0) := rdata(set); set := 0;
end if;
-- cache flush
if ((ici.flush or
dco.icdiag.flush) = '1') and (icen /= 0)
then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
v.pflush := dco.icdiag.pflush; wtag := (others => '0');
v.pflushr := '1';
v.pflushaddr := dco.icdiag.pflushaddr;
v.pflushtyp := dco.icdiag.pflushtyp;
end if;
if lram /= 0 then iladdr := taddr; end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => (others => '0'));
v.faddr := r.faddr + 1;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if ((r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1))
) = '1' then
v.flush2 := '0';
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
v.pflushr := not r.pflushr;
if r.pflushr = '0' then
for i in ISETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := icramo.tag(i)(TAG_HIGH downto TAG_LOW); --icramo.itramout(i).tag;
--if (icramo.itramout(i).ctx = mmudci.mmctrl1.ctx) and
-- ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
-- (r.pflushtyp = '1')) then
ctwrite(i) := '1';
--end if;
end loop;
end if;
end if;
end if;
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.istate := idle; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0';
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
v.trans_op := '0';
v.bpmiss := '0';
end if;
if (not RESET_ALL and rst = '0') or (r.flush = '1') then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.ctx <= mmudci.mmctrl1.ctx;
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.address <= iladdr(19+LINE_LOW downto LINE_LOW);
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc);
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst and r.req;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- mmu <-> icache
mmuici.trans_op <= mmuici_trans_op;
mmuici.transdata.data <= r.waddress(31 downto 2) & "00";
mmuici.transdata.su <= r.su;
mmuici.transdata.isid <= id_icache;
mmuici.transdata.read <= '1';
mmuici.transdata.wb_data <= (others => '0');
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.bpmiss <= r.bpmiss;
ico.eocl <= r.eocl;
ico.cstat.chold <= not r.holdn;
ico.cstat.mhold <= mhold;
ico.cstat.tmiss <= mmuico.tlbmiss;
ico.cstat.cmiss <= r.cmiss;
if r.istate = idle then ico.idle <= '1'; else ico.idle <= '0'; end if;
end process;
-- Local registers
regs1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
r.waddress <= ici.fpc(31 downto 2);
r.vaddress <= ici.fpc(31 downto 2);
end if;
end if;
end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then
rl <= LRES;
end if;
end if;
end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
entity whide is
end entity;
architecture a of whide is
signal a : boolean;
begin
process(a)
variable whide : boolean;
begin
case a is
when false => report "FALSE";
when true => report "TRUE";
when others => report "others";
end case;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03033ent IS
END c12s02b01x00p01n02i03033ent;
ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
subtype subi is integer range 1 to 10;
signal s1,s2,s3 : subi;
BEGIN
bl1: block
generic (gi : subi);
generic map (gi => 1);
port (s11 : OUT subi);
port map (s11 => s1);
begin
assert (gi=1)
report "Generic GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic (gi : subi);
generic map (gi => 5);
port (s22 : OUT subi);
port map (s22 => s2);
begin
assert (gi=5)
report "Generic GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic (gi : subi);
generic map (gi => 10);
port (s33 : OUT subi);
port map (s33 => s3);
begin
assert (gi=10)
report "Generic GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
report "***PASSED TEST: c12s02b01x00p01n02i03033"
severity NOTE;
assert ( s1 = 1 and s2 = 5 and s3 = 10 )
report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03033arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03033ent IS
END c12s02b01x00p01n02i03033ent;
ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
subtype subi is integer range 1 to 10;
signal s1,s2,s3 : subi;
BEGIN
bl1: block
generic (gi : subi);
generic map (gi => 1);
port (s11 : OUT subi);
port map (s11 => s1);
begin
assert (gi=1)
report "Generic GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic (gi : subi);
generic map (gi => 5);
port (s22 : OUT subi);
port map (s22 => s2);
begin
assert (gi=5)
report "Generic GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic (gi : subi);
generic map (gi => 10);
port (s33 : OUT subi);
port map (s33 => s3);
begin
assert (gi=10)
report "Generic GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
report "***PASSED TEST: c12s02b01x00p01n02i03033"
severity NOTE;
assert ( s1 = 1 and s2 = 5 and s3 = 10 )
report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03033arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03033ent IS
END c12s02b01x00p01n02i03033ent;
ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
subtype subi is integer range 1 to 10;
signal s1,s2,s3 : subi;
BEGIN
bl1: block
generic (gi : subi);
generic map (gi => 1);
port (s11 : OUT subi);
port map (s11 => s1);
begin
assert (gi=1)
report "Generic GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic (gi : subi);
generic map (gi => 5);
port (s22 : OUT subi);
port map (s22 => s2);
begin
assert (gi=5)
report "Generic GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic (gi : subi);
generic map (gi => 10);
port (s33 : OUT subi);
port map (s33 => s3);
begin
assert (gi=10)
report "Generic GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
report "***PASSED TEST: c12s02b01x00p01n02i03033"
severity NOTE;
assert ( s1 = 1 and s2 = 5 and s3 = 10 )
report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03033arch;
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
|
-------------------------------------------------------------------------------
--
-- File: AD9717_RegisterDecode.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module implements the register set for the AD9717 simulation model
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodDAC.all;
entity AD9717_RegisterDecode is
Generic (
-- Parameter identifying the Zmod:
-- 7 -> Zmod AWG 1411 - (AD9717)
kZmodID : integer range 7 to 7 := 7;
-- Register address width
kAddrWidth : integer range 0 to 32 := 5;
-- Register data width: only 8 data bits currently supported
kRegDataWidth : integer range 0 to 32 := 8
);
Port (
-- 100MHZ clock input
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous reading for register address x01
InsertError : in STD_LOGIC;
-- Signal indicating that the data phase of he register write SPI transaction is completed and aDataDecode is valid
sDataWriteDecodeReady : in STD_LOGIC;
-- Signal indicating that the address phase of the SPI transaction is completed and aAddrDecode is valid
sAddrDecodeReady : in STD_LOGIC;
-- Input register data used to update internal egister values for write register operations
sDataDecode : in STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0);
-- Register address input
sAddrDecode : in STD_LOGIC_VECTOR (kAddrWidth-1 downto 0);
-- Output register data produced by this module upon address decode for register read operations
sRegDataOut : out STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0)
);
end AD9717_RegisterDecode;
architecture Behavioral of AD9717_RegisterDecode is
signal sAddrDecodeReadyPulse, sAddrDecodeReadyDly : std_logic := '0';
signal sDataWriteDecodeReadyPulse, sDataWriteDecodeReadyDly : std_logic := '0';
signal sReg00 : std_logic_vector(7 downto 0) := x"00";
signal sReg01 : std_logic_vector(7 downto 0) := x"40";
signal sReg02 : std_logic_vector(7 downto 0) := x"34";
signal sReg03 : std_logic_vector(7 downto 0) := x"00";
signal sReg04 : std_logic_vector(7 downto 0) := x"00";
signal sReg05 : std_logic_vector(7 downto 0) := x"00";
signal sReg06 : std_logic_vector(7 downto 0) := x"00";
signal sReg07 : std_logic_vector(7 downto 0) := x"00";
signal sReg08 : std_logic_vector(7 downto 0) := x"00";
signal sReg09 : std_logic_vector(7 downto 0) := x"00";
signal sReg0A : std_logic_vector(7 downto 0) := x"00";
signal sReg0B : std_logic_vector(7 downto 0) := x"00";
signal sReg0C : std_logic_vector(7 downto 0) := x"00";
signal sReg0D : std_logic_vector(7 downto 0) := x"00";
signal sReg0E : std_logic_vector(7 downto 0) := x"00";
signal sReg0F : std_logic_vector(7 downto 0) := x"00";
signal sReg10 : std_logic_vector(7 downto 0) := x"00";
signal sReg11 : std_logic_vector(7 downto 0) := x"34";
signal sReg12 : std_logic_vector(7 downto 0) := x"00";
signal sReg14 : std_logic_vector(7 downto 0) := x"00";
signal sReg1F : std_logic_vector(7 downto 0) := x"04";
signal sCalstatQ_TimerRst_n, sCalstatI_TimerRst_n : std_logic;
signal sCalstatQ_Timer, sCalstatI_Timer : unsigned (23 downto 0);
signal sSetCalstatQ, sSetCalstatI : std_logic;
signal sAddrAux : integer range 0 to 511;
begin
sAddrAux <= to_integer (unsigned (std_logic_vector'((sAddrDecode))));
-- The following section generates a pulse when sAddrDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI read transaction is
-- completed and that sAddrDecode contains valid data.
ProcAddrDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sAddrDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sAddrDecodeReadyDly <= sAddrDecodeReady;
end if;
end process;
sAddrDecodeReadyPulse <= sAddrDecodeReady and (not sAddrDecodeReadyDly);
-- Process managing register read operations
ReadRegister: process(SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRegDataOut <= (others => '0');
elsif (rising_edge (SysClk100)) then
if (sAddrDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "00000" =>
sRegDataOut <= sReg00;
when "00001" =>
if (InsertError = '0') then
sRegDataOut <= sReg01;
else
sRegDataOut <= x"00";
end if;
when "00010" =>
sRegDataOut <= sReg02;
when "00011" =>
sRegDataOut <= sReg03;
when "00100" =>
sRegDataOut <= sReg04;
when "00101" =>
sRegDataOut <= sReg05;
when "00110" =>
sRegDataOut <= sReg06;
when "00111" =>
sRegDataOut <= sReg07;
when "01000" =>
sRegDataOut <= sReg08;
when "01001" =>
sRegDataOut <= sReg09;
when "01010" =>
sRegDataOut <= sReg0A;
when "01011" =>
sRegDataOut <= sReg0B;
when "01100" =>
sRegDataOut <= sReg0C;
when "01101" =>
sRegDataOut <= sReg0D;
when "01110" =>
sRegDataOut <= sReg0E;
when "01111" =>
sRegDataOut <= sReg0F;
when "10000" =>
sRegDataOut <= sReg10;
when "10001" =>
sRegDataOut <= sReg11;
when "10010" =>
sRegDataOut <= sReg12;
when "10100" =>
sRegDataOut <= sReg14;
when "11111" =>
sRegDataOut <= sReg1F;
when others =>
sRegDataOut <= x"00";
report "Invalid Read Address." & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process ReadRegister;
-- The following section generates a pulse when sDataWriteDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI write transaction is
-- completed and that sAddrDecode contains valid data.
ProcDataDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDataWriteDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sDataWriteDecodeReadyDly <= sDataWriteDecodeReady;
end if;
end process;
sDataWriteDecodeReadyPulse <= sDataWriteDecodeReady and (not sDataWriteDecodeReadyDly);
-- Process managing register write operations (Reg0F is treated separately).
WriteRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00 <= x"00";
sReg01 <= x"40";
sReg02 <= x"34";
sReg03 <= x"00";
sReg04 <= x"00";
sReg05 <= x"00";
sReg06 <= x"00";
sReg07 <= x"00";
sReg08 <= x"00";
sReg09 <= x"00";
sReg0A <= x"00";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0D <= x"00";
sReg0E(7 downto 6) <= "00";
sReg0E(3 downto 0) <= x"0";
sReg10 <= x"00";
sReg11 <= x"34";
sReg12 <= x"00";
sReg14 <= x"00";
sReg1F <= x"04";
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "00000" =>
sReg00(7 downto 4) <= sDataDecode(7 downto 4);
when "00001" =>
sReg01 <= sDataDecode;
when "00010" =>
sReg02 <= sDataDecode;
when "00011" =>
sReg03(5 downto 0) <= sDataDecode(5 downto 0);
when "00100" =>
sReg04(7) <= sDataDecode(7);
sReg04(5 downto 0) <= sDataDecode(5 downto 0);
when "00101" =>
sReg05(7) <= sDataDecode(7);
sReg05(5 downto 0) <= sDataDecode(5 downto 0);
when "00110" =>
sReg06(5 downto 0) <= sDataDecode(5 downto 0);
when "00111" =>
sReg07(7) <= sDataDecode(7);
sReg07(5 downto 0) <= sDataDecode(5 downto 0);
when "01000" =>
sReg08(7) <= sDataDecode(7);
sReg08(5 downto 0) <= sDataDecode(5 downto 0);
when "01001" =>
sReg09 <= sDataDecode;
when "01010" =>
sReg0A <= sDataDecode;
when "01011" =>
sReg0B <= sDataDecode;
when "01100" =>
sReg0C <= sDataDecode;
when "01101" =>
sReg0D(5 downto 0) <= sDataDecode(5 downto 0);
when "01110" =>
sReg0E(7 downto 6) <= sDataDecode(7 downto 6);
sReg0E(3 downto 0) <= sDataDecode(3 downto 0);
when "01111" =>
-- sReg0F(7 downto 6) <= sDataDecode(7 downto 6);
-- sReg0F(3 downto 0) <= sDataDecode(3 downto 0);
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "10000" =>
sReg10(5 downto 0) <= sDataDecode(5 downto 0);
when "10001" =>
sReg11(5 downto 0) <= sDataDecode(5 downto 0);
when "10010" =>
sReg12(7 downto 6) <= sDataDecode(7 downto 6);
sReg12(4 downto 0) <= sDataDecode(4 downto 0);
when "10100" =>
sReg14(7 downto 6) <= sDataDecode(7 downto 6);
sReg14(4 downto 0) <= sDataDecode(4 downto 0);
when "11111" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when others =>
report "Invalid Write Address." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end case;
-- Soft Reset
elsif (sReg00(5) = '1') then
sReg01 <= x"40";
sReg02 <= x"34";
sReg03 <= x"00";
sReg04 <= x"00";
sReg05 <= x"00";
sReg06 <= x"00";
sReg07 <= x"00";
sReg08 <= x"00";
sReg09 <= x"00";
sReg0A <= x"00";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0D <= x"00";
sReg0E(7 downto 6) <= "00";
sReg0E(3 downto 0) <= x"0";
sReg10 <= x"00";
sReg11 <= x"34";
sReg12 <= x"00";
sReg14 <= x"00";
sReg1F <= x"04";
end if;
end if;
end process WriteRegister;
-- Counter used to implement the CALSTATQ bit behavior
ProcCalstatQ_Tmr: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatQ_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCalstatQ_TimerRst_n = '0') then
sCalstatQ_Timer <= (others => '0');
else
sCalstatQ_Timer <= sCalstatQ_Timer + 1;
end if;
end if;
end process;
-- Counter used to implement the CALSTATI bit behavior
ProcCalstatI_Tmr: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatI_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCalstatI_TimerRst_n = '0') then
sCalstatI_Timer <= (others => '0');
else
sCalstatI_Timer <= sCalstatI_Timer + 1;
end if;
end if;
end process;
ProcEnCalstatQ_TmrRst: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatQ_TimerRst_n <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg0E(5) = '1') then
sCalstatQ_TimerRst_n <= '1';
else
sCalstatQ_TimerRst_n <= '0';
end if;
end if;
end process;
ProcEnCalstatI_TmrRst: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatI_TimerRst_n <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg0E(4) = '1') then
sCalstatI_TimerRst_n <= '1';
else
sCalstatI_TimerRst_n <= '0';
end if;
end if;
end process;
-- Configure the CALSELQ bit in the Cal Control register (0x0E)
-- for register write operations.
-- Clear CALSELQ when the Q DAC self-calibration is complete.
WriteReg0E_CALSELQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0E(5) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01110") then
sReg0E(5) <= sDataDecode(5);
end if;
elsif (sSetCalstatQ = '1') then
sReg0E(5) <= '0';
end if;
end if;
end process;
-- Configure the CALSELI bit in the Cal Control register (0x0E)
-- for register write operations.
-- Clear CALSELQ when the I DAC self-calibration is complete.
WriteReg0E_CALSELI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0E(4) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01110") then
sReg0E(4) <= sDataDecode(5);
end if;
elsif (sSetCalstatI = '1') then
sReg0E(4) <= '0';
end if;
end if;
end process;
-- Manage the CALSTATQ bit in the Cal Memory register (0x0F).
-- Write operations at this address have no effect (except
-- reporting an error).
-- CALSTATQ is set at a predefined interval after the CALSETQ
-- bit in the Cal Control register is set.
-- CALSTATQ is cleared when he CALRSTQ bit in the Memory R/W
-- register (0x12) is set.
WriteReg0F_CALSTATQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0F(7) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01111") then
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end if;
elsif (sReg12(7) = '1') then
sReg0F(7) <= '0';
elsif (sSetCalstatQ = '1') then
sReg0F(7) <= '1';
end if;
end if;
end process;
-- Manage the CALSTATI bit in the Cal Memory register (0x0F).
-- Write operations at this address have no effect (except
-- reporting an error).
-- CALSTATI is set at a predefined interval after the CALSETI
-- bit in the Cal Control register is set.
-- CALSTATI is cleared when he CALRSTI bit in the Memory R/W
-- register (0x12) is set.
WriteReg0F_CALSTATI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0F(6) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01111") then
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end if;
elsif (sReg12(6) = '1') then
sReg0F(6) <= '0';
elsif (sSetCalstatI = '1') then
sReg0F(6) <= '1';
end if;
end if;
end process;
-- Process used to set CALSTATQ in 300 calibration clock cycles (kCalTimeout) after
-- the self calibration process has been enabled
ProcStCalstatQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sSetCalstatQ <= '0';
elsif (rising_edge(SysClk100)) then
if (sCalstatQ_Timer = kCalTimeout) then
sSetCalstatQ <= '1';
else
sSetCalstatQ <= '0';
end if;
end if;
end process;
-- Process used to set CALSTATI in 300 calibration clock cycles (kCalTimeout) after
-- the self calibration process has been enabled
ProcStCalstatI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sSetCalstatI <= '0';
elsif (rising_edge(SysClk100)) then
if (sCalstatI_Timer = kCalTimeout) then
sSetCalstatI <= '1';
else
sSetCalstatI <= '0';
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.filter_shared_package.all;
entity filter_generic_iir_biquad is
generic
(
BIQUADS : natural := B;
CHANNELS : natural := C;
PRECISION : natural := PREC;
FPMULT_PIPE_LENGTH : P_T := PM;
FPADD_PIPE_LENGTH : P_T := PA;
MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation
RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled.
MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled.
ENVELOPE_EN : natural := ENV;
ENV_MAC_ID : natural := ENV_MAC;
SETZERO_EN : natural := SETZ
);
port
(
clk : in std_logic;
rstn : in std_logic;
envelope : in std_logic_vector(CHANNELS-1 downto 0):= (others => '0');
give_rms : in std_logic:= '0';
give_mean : in std_logic:= '0';
set_zero : in std_logic_vector(CHANNELS-1 downto 0):= (others => '0');
sink_data : in std_logic_vector(SINGLE_EXT-1 downto 0);
sink_valid : in std_logic;
sink_startofpacket : in std_logic;
sink_endofpacket : in std_logic;
sink_ready : out std_logic;
coeff_wren : in std_logic;
coeff_wraddr : in COEFF_ADD_T;
coeff_data : in DATA_IO_PORT_T;
source_data : out std_logic_vector(SINGLE_EXT-1 downto 0);
source_valid : out std_logic;
source_rms_valid : out std_logic:= '1';
source_mean_valid : out std_logic:= '0';
source_startofpacket : out std_logic;
source_endofpacket : out std_logic
);
end filter_generic_iir_biquad;
architecture structural of filter_generic_iir_biquad is
component filter_main_controller is
generic
(
BIQUADS : natural := B;
CHANNELS : natural := C;
FPMULT_PIPE_LENGTH : P_T := PM;
FPADD_PIPE_LENGTH : P_T := PA;
MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation
RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled.
MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled.
ENVELOPE_EN : natural := ENV;
ENV_MAC_ID : natural := ENV_MAC;
SETZERO_EN : natural := SETZ
);
port
(
-- Input Ports
clk : in std_logic;
rstn : in std_logic;
envelope : in std_logic_vector(CHANNELS-1 downto 0);
give_rms : in std_logic;
give_mean : in std_logic;
set_zero : in std_logic_vector(CHANNELS-1 downto 0);
sink_valid : in std_logic;
sink_startofpacket : in std_logic;
sink_endofpacket : in std_logic;
-- Output ports
x_rdaddr : out X_ADD_T;
x_rden : out std_logic;
x_wraddr : out X_ADD_T;
x_wren : out std_logic;
coeff_rdaddr : out COEFF_ADD_T;
coeff_rden : out std_logic;
acc_rdaddr : out ACC_ADD_T;
acc_rden : out std_logic;
acc_wraddr : out ACC_ADD_T;
acc_wren : out std_logic;
zero_acc : out std_logic;
y_rdaddr : out Y_ADD_T;
y_rden : out std_logic;
y_wraddr : out Y_ADD_T;
y_wren : out std_logic;
zero_y : out std_logic;
is_abs : out std_logic;
mac_x_y_sel : out std_logic;
mac_coeff_y_sel : out std_logic;
sink_ready : out std_logic;
source_valid : out std_logic;
source_rms_valid : out std_logic;
source_mean_valid : out std_logic;
source_startofpacket : out std_logic;
source_endofpacket : out std_logic
);
end component filter_main_controller;
component filter_datapath is
generic
(
FPMULT_PIPE_LENGTH : P_T := PM;
FPADD_PIPE_LENGTH : P_T := PA;
PRECISION : natural := PREC
);
port
(
-- Input ports
clk : in std_logic;
rstn : in std_logic;
aclr : in std_logic;
x_rdaddr : in X_ADD_T;
x_rden : in std_logic;
x_wraddr : in X_ADD_T;
x_wren : in std_logic;
sink_data : in std_logic_vector(SINGLE_EXT-1 downto 0);
coeff_rdaddr : in COEFF_ADD_T;
coeff_rden : in std_logic;
coeff_wraddr : in COEFF_ADD_T;
coeff_wren : in std_logic;
coeff_data : in DATA_IO_PORT_T;
acc_rdaddr : in ACC_ADD_T;
acc_rden : in std_logic;
acc_wraddr : in ACC_ADD_T;
acc_wren : in std_logic;
zero_acc : in std_logic;
y_rdaddr : in Y_ADD_T;
y_rden : in std_logic;
y_wraddr : in Y_ADD_T;
y_wren : in std_logic;
zero_y : in std_logic;
is_abs : in std_logic;
mac_x_y_sel : in std_logic;
mac_coeff_y_sel : in std_logic;
-- Output ports
source_data : out std_logic_vector(SINGLE_EXT-1 downto 0)
);
end component filter_datapath;
-- Signals
signal x_rdaddr_s : X_ADD_T;
signal x_rden_s : std_logic;
signal x_wraddr_s : X_ADD_T;
signal x_wren_s : std_logic;
signal coeff_rdaddr_s : COEFF_ADD_T;
signal coeff_rden_s : std_logic;
signal acc_rdaddr_s : ACC_ADD_T;
signal acc_rden_s : std_logic;
signal acc_wraddr_s : ACC_ADD_T;
signal acc_wren_s : std_logic;
signal zero_acc_s : std_logic;
signal y_rdaddr_s : Y_ADD_T;
signal y_rden_s : std_logic;
signal y_wraddr_s : Y_ADD_T;
signal y_wren_s : std_logic;
signal zero_y_s : std_logic;
signal is_abs_s : std_logic;
signal mac_x_y_sel_s : std_logic;
signal mac_coeff_y_sel_s : std_logic;
signal aclr_s : std_logic;
begin
aclr_s <= not rstn;
main_controller_inst : component filter_main_controller
generic map
(
BIQUADS => BIQUADS,
CHANNELS => CHANNELS,
FPMULT_PIPE_LENGTH => FPMULT_PIPE_LENGTH,
FPADD_PIPE_LENGTH => FPADD_PIPE_LENGTH,
MAC_FILTER_CH => MAC_FILTER_CH,
RMS_CH_EN => RMS_CH_EN,
MEAN_CH_EN => MEAN_CH_EN,
ENVELOPE_EN => ENVELOPE_EN,
ENV_MAC_ID => ENV_MAC_ID,
SETZERO_EN => SETZERO_EN
)
port map
(
clk => clk,
rstn => rstn,
envelope => envelope,
give_rms => give_rms,
give_mean => give_mean,
set_zero => set_zero,
sink_valid => sink_valid,
sink_startofpacket => sink_startofpacket,
sink_endofpacket => sink_endofpacket,
x_rdaddr => x_rdaddr_s,
x_rden => x_rden_s,
x_wraddr => x_wraddr_s,
x_wren => x_wren_s,
coeff_rdaddr => coeff_rdaddr_s,
coeff_rden => coeff_rden_s,
acc_rdaddr => acc_rdaddr_s,
acc_rden => acc_rden_s,
acc_wraddr => acc_wraddr_s,
acc_wren => acc_wren_s,
zero_acc => zero_acc_s,
y_rdaddr => y_rdaddr_s,
y_rden => y_rden_s,
y_wraddr => y_wraddr_s,
y_wren => y_wren_s,
zero_y => zero_y_s,
is_abs => is_abs_s,
mac_x_y_sel => mac_x_y_sel_s,
mac_coeff_y_sel => mac_coeff_y_sel_s,
sink_ready => sink_ready,
source_valid => source_valid,
source_rms_valid => source_rms_valid,
source_mean_valid => source_mean_valid,
source_startofpacket => source_startofpacket,
source_endofpacket => source_endofpacket
);
filter_datapath_inst : component filter_datapath
generic map
(
FPMULT_PIPE_LENGTH => FPMULT_PIPE_LENGTH,
FPADD_PIPE_LENGTH => FPADD_PIPE_LENGTH,
PRECISION => PRECISION
)
port map
(
clk => clk,
rstn => rstn,
aclr => aclr_s,
x_rdaddr => x_rdaddr_s,
x_rden => x_rden_s,
x_wraddr => x_wraddr_s,
x_wren => x_wren_s,
sink_data => sink_data,
coeff_rdaddr => coeff_rdaddr_s,
coeff_rden => coeff_rden_s,
coeff_wraddr => coeff_wraddr,
coeff_wren => coeff_wren,
coeff_data => coeff_data,
acc_rdaddr => acc_rdaddr_s,
acc_rden => acc_rden_s,
acc_wraddr => acc_wraddr_s,
acc_wren => acc_wren_s,
zero_acc => zero_acc_s,
y_rdaddr => y_rdaddr_s,
y_rden => y_rden_s,
y_wraddr => y_wraddr_s,
y_wren => y_wren_s,
zero_y => zero_y_s,
is_abs => is_abs_s,
mac_x_y_sel => mac_x_y_sel_s,
mac_coeff_y_sel => mac_coeff_y_sel_s,
source_data => source_data
);
end structural;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb565_to_rgb888_1_0 -prefix
-- system_rgb565_to_rgb888_1_0_ system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_1_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_1_0;
architecture stub of system_rgb565_to_rgb888_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
|
architecture RTL of ENT is
begin
-- Align left = no align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = no align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
end architecture RTL;
|
-- Frank Vanbever 06/03/13
-------------------------------------------------------------------------------
--! @file
--! @brief Data Memory implementation for a MIPS processor
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
--! Data memory implementation for a MIPS processor. Allows storage for 64 words currently.
-------------------------------------------------------------------------------
entity data_memory is
port(
-- input signals
clk : in std_logic; -- clock
-- control signals
--! Write enable signal. Warning: mutually exclusive with MemRead!
MemWrite : in std_logic;
--! Read enable signal. Warning: mutually exclusive with MemWrite!
MemRead : in std_logic;
-- input vectors
--! Adress from which the value should be read or to which it should be
--! written
adress : in std_logic_vector(31 downto 0);
--! Data to be written at the given adress in write mode
write_data : in std_logic_vector(31 downto 0);
--! Data to be read from the given adress in read mode
read_data : out std_logic_vector(31 downto 0)
);
end data_memory;
-------------------------------------------------------------------------------
--! @brief The architecture of the data memory is based on an array of 64
--! 32-bit words
--! @detailed MemWrite and MemRead are mutually exclusive, only one can be 1 at
--! a time. This is a problem that needs to be adressed.
-------------------------------------------------------------------------------
architecture behavioral of data_memory is
subtype word is std_logic_vector(31 downto 0);
type memory_array is array (0 to 63) of word;
shared variable dataMem : memory_array :=
(X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000");
begin --behavioral
---------------------------------------------------------------
--! process that governs reading from or writing to the memory.
--! reads or writes values accordingly.
---------------------------------------------------------------
data_mem_proc : process(MemRead,MemWrite,write_data,adress)
begin
-- trick to avoid undefined address error(should give no problems,only delays the read/write untill adress is defined well)
if(conv_integer(adress)<63)then
if (MemRead = '1') and (MemWrite = '0') then
read_data <= dataMem(conv_integer(adress));
elsif (MemRead = '0') and (MemWrite = '1') then
dataMem(conv_integer(adress)) := write_data;
end if;
end if;
end process;
end behavioral;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity comb_alu_1 is
port(
clk : in std_logic;
reset_in : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in std_logic_vector( 5 downto 0);
c_alu : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of comb_alu_1 is
signal HOLDN : STD_LOGIC;
signal CLK_LDPC : STD_LOGIC;
signal ldpc_instruction : STD_LOGIC_VECTOR(12 downto 0);
signal OUTPUT_LDPC : STD_LOGIC_VECTOR(31 downto 0);
signal sDESIGN_ID : STD_LOGIC_VECTOR(31 downto 0);
signal INTPUT_LDPC : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_3 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_4 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_5 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_6 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_7 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_8 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_9 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_10 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_11 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_12 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_13 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_14 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_15 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_16 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_17 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_18 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_19 : STD_LOGIC_VECTOR(31 downto 0);
begin
FX1 : ENTITY WORK.function_1 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_1 );
FX2 : ENTITY WORK.function_2 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_2 );
FX3 : ENTITY WORK.function_3 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_3 );
FX4 : ENTITY WORK.function_4 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_4 );
FX5 : ENTITY WORK.function_5 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_5 );
FX6 : ENTITY WORK.function_6 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_6 );
FX7 : ENTITY WORK.function_7 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_7 );
FX8 : ENTITY WORK.function_8 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_8 );
FX9 : ENTITY WORK.function_9 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_9 );
FX10 : ENTITY WORK.function_10 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_10 );
FX11 : ENTITY WORK.function_11 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_11 );
FX12 : ENTITY WORK.function_12 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_12 );
FX13 : ENTITY WORK.function_13 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_13 );
FX14 : ENTITY WORK.function_14 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_14 );
FX15 : ENTITY WORK.function_15 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_15 );
FX16 : ENTITY WORK.function_16 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_16 );
FX17 : ENTITY WORK.function_17 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_17 );
FX18 : ENTITY WORK.function_18 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_18 );
-- FX19 : ENTITY WORK.function_19 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_19 );
with alu_function select
c_alu <=
RESULT_1 WHEN "000001",-- (01)
RESULT_2 WHEN "000101",-- (05)
RESULT_3 WHEN "001010",-- (0A)
RESULT_4 WHEN "011110",-- (1E)
RESULT_5 WHEN "011111",-- (1F)
RESULT_6 WHEN "101001",-- (29)
RESULT_7 WHEN "101100",-- (2C)
RESULT_8 WHEN "101110",-- (2E)
RESULT_9 WHEN "101111",-- (2F)
RESULT_10 WHEN "110000",-- (30)
RESULT_11 WHEN "110101",-- (35)
RESULT_12 WHEN "110111",-- (37)
RESULT_13 WHEN "111000",-- (38)
RESULT_14 WHEN "111001",-- (39)
RESULT_15 WHEN "111010",-- (3A)
RESULT_16 WHEN "111011",-- (3B)
RESULT_17 WHEN "111100",-- (3C)
RESULT_18 WHEN "111101",-- (3D)
-- RESULT_19 WHEN "111110",-- (3E)
"00000000000000000000000000000000" WHEN OTHERS; -- nop
end; --architecture logic
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_autobram_histo is
generic (
constant TV_IN : STRING (1 to 43) := "../tv/cdatafile/c.doHist.autotvin_histo.dat";
constant TV_OUT : STRING (1 to 48) := "../tv/rtldatafile/rtl.doHist.autotvout_histo.dat";
constant DATA_WIDTH : INTEGER := 32;
constant ADDR_WIDTH : integer := 32;
constant DEPTH : integer := 256
);
port (
Clk_A : IN STD_LOGIC;
Rst_A : IN STD_LOGIC;
EN_A : IN STD_LOGIC;
WEN_A : IN STD_LOGIC_VECTOR (DATA_WIDTH/8 - 1 downto 0);
Addr_A : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
Din_A : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Dout_A : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Clk_B : IN STD_LOGIC;
Rst_B : IN STD_LOGIC;
EN_B : IN STD_LOGIC;
WEN_B : IN STD_LOGIC_VECTOR (DATA_WIDTH/8 - 1 downto 0);
Addr_B : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
Din_B : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Dout_B : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobram_histo;
architecture behav of AESL_autobram_histo is
-- Inner signals
type arr2D is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem : arr2D := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
begin
---------------------------Read array-------------------
-- Read data from file to array
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable token_len : INTEGER;
variable token_int : INTEGER;
variable transaction_idx : INTEGER;
variable idx : INTEGER;
begin
wait until Rst_A = '0';
transaction_idx := 0;
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait for 0.2 ns;
while(ready /= '1') loop
wait until Clk_A'event and Clk_A = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
wait until Clk_A'event and Clk_A = '1';
end loop;
file_close(fp);
wait;
end process;
-- Read data from array to RTL
read_proc_A : process(Clk_A, Rst_A)
begin
if(Rst_A = '1') then
Dout_A <= (others => '0');
elsif (Clk_A'event and Clk_A = '1') then
if(EN_A = '1' and (CONV_INTEGER(Addr_A)*8/32 < DEPTH)) then
Dout_A <= mem(CONV_INTEGER(Addr_A)*8/32);
end if;
end if;
end process;
read_proc_B : process(Clk_B, Rst_B)
begin
if(Rst_B = '1') then
Dout_B <= (others => '0');
elsif (Clk_B'event and Clk_B = '1') then
if(EN_B = '1' and (CONV_INTEGER(Addr_B)*8/32 < DEPTH)) then
Dout_B <= mem(CONV_INTEGER(Addr_B)*8/32);
end if;
end if;
end process;
----------------------Write array------------------------
--Write data from RTL to array
write_proc_A : process(Clk_A)
begin
if(EN_A = '1') then
if(WEN_A(0) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(0*8+7 downto 0*8) := Din_A(0*8+7 downto 0*8);
end if;
if(WEN_A(1) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(1*8+7 downto 1*8) := Din_A(1*8+7 downto 1*8);
end if;
if(WEN_A(2) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(2*8+7 downto 2*8) := Din_A(2*8+7 downto 2*8);
end if;
if(WEN_A(3) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(3*8+7 downto 3*8) := Din_A(3*8+7 downto 3*8);
end if;
end if;
end process;
write_proc_B : process(Clk_B)
begin
if(EN_B = '1') then
if(WEN_B(0) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(0*8+7 downto 0*8) := Din_B(0*8+7 downto 0*8);
end if;
if(WEN_B(1) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(1*8+7 downto 1*8) := Din_B(1*8+7 downto 1*8);
end if;
if(WEN_B(2) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(2*8+7 downto 2*8) := Din_B(2*8+7 downto 2*8);
end if;
if(WEN_B(3) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(3*8+7 downto 3*8) := Din_B(3*8+7 downto 3*8);
end if;
end if;
end process;
-- Write data from array to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable transaction_idx : INTEGER;
begin
wait until (Rst_A = '0');
transaction_idx := 0;
while(true) loop
wait for 0.1 ns;
while(done /= '1') loop
wait until Clk_A'event and Clk_A = '1';
wait for 0.1 ns;
end loop;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
wait until Clk_A'event and Clk_A = '1';
end loop;
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--
--Module Title: 4dig_7seg
--Module Description:
-- This is a 4-digit, 7-segment display decoder. It outputs in 16-bit values
-- on the Digilent Nexys 2 board's 4-digit display in hexadecimal. Simply
-- give it a 50 MHz clock and data and it'll start working.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end four_dig_7seg;
architecture Behavioral of four_dig_7seg is
--//Signals\\--
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
--\\Signals//--
begin
--This process takes the data to display and
--multiplexes 4-bit chunks of it according
--to the input clock. The 4-bit chunks are
--sent to the decoder and the anode lines
--are switched to activate one digit at a time
disp_data: process(display_data, clock) is
variable clk_count : integer := 0; --A variable to count the clock ticks
variable disp_count : integer := 0; --A variable to hold on to which digit
begin --is currently being displayed
if rising_edge(clock) then
clk_count := clk_count + 1;
if clk_count = 100000 then --Refresh rate with 100000 is about 125 Hz for the entire display
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then --First digit
anodes <= "1110";
to_decoder <= display_data(3 downto 0);
elsif disp_count = 1 then --Second digit
anodes <= "1101";
to_decoder <= display_data(7 downto 4);
elsif disp_count = 2 then --Third digit
anodes <= "1011";
to_decoder <= display_data(11 downto 8);
elsif disp_count = 3 then --Fourth digit
anodes <= "0111";
to_decoder <= display_data(15 downto 12);
end if;
end process;
--This represents a ROM that will act as the
--individual 7-segment decoder for each digit
--of the display
with to_decoder select
to_display <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"0000001" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--
--Module Title: 4dig_7seg
--Module Description:
-- This is a 4-digit, 7-segment display decoder. It outputs in 16-bit values
-- on the Digilent Nexys 2 board's 4-digit display in hexadecimal. Simply
-- give it a 50 MHz clock and data and it'll start working.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end four_dig_7seg;
architecture Behavioral of four_dig_7seg is
--//Signals\\--
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
--\\Signals//--
begin
--This process takes the data to display and
--multiplexes 4-bit chunks of it according
--to the input clock. The 4-bit chunks are
--sent to the decoder and the anode lines
--are switched to activate one digit at a time
disp_data: process(display_data, clock) is
variable clk_count : integer := 0; --A variable to count the clock ticks
variable disp_count : integer := 0; --A variable to hold on to which digit
begin --is currently being displayed
if rising_edge(clock) then
clk_count := clk_count + 1;
if clk_count = 100000 then --Refresh rate with 100000 is about 125 Hz for the entire display
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then --First digit
anodes <= "1110";
to_decoder <= display_data(3 downto 0);
elsif disp_count = 1 then --Second digit
anodes <= "1101";
to_decoder <= display_data(7 downto 4);
elsif disp_count = 2 then --Third digit
anodes <= "1011";
to_decoder <= display_data(11 downto 8);
elsif disp_count = 3 then --Fourth digit
anodes <= "0111";
to_decoder <= display_data(15 downto 12);
end if;
end process;
--This represents a ROM that will act as the
--individual 7-segment decoder for each digit
--of the display
with to_decoder select
to_display <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"0000001" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--
--Module Title: 4dig_7seg
--Module Description:
-- This is a 4-digit, 7-segment display decoder. It outputs in 16-bit values
-- on the Digilent Nexys 2 board's 4-digit display in hexadecimal. Simply
-- give it a 50 MHz clock and data and it'll start working.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end four_dig_7seg;
architecture Behavioral of four_dig_7seg is
--//Signals\\--
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
--\\Signals//--
begin
--This process takes the data to display and
--multiplexes 4-bit chunks of it according
--to the input clock. The 4-bit chunks are
--sent to the decoder and the anode lines
--are switched to activate one digit at a time
disp_data: process(display_data, clock) is
variable clk_count : integer := 0; --A variable to count the clock ticks
variable disp_count : integer := 0; --A variable to hold on to which digit
begin --is currently being displayed
if rising_edge(clock) then
clk_count := clk_count + 1;
if clk_count = 100000 then --Refresh rate with 100000 is about 125 Hz for the entire display
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then --First digit
anodes <= "1110";
to_decoder <= display_data(3 downto 0);
elsif disp_count = 1 then --Second digit
anodes <= "1101";
to_decoder <= display_data(7 downto 4);
elsif disp_count = 2 then --Third digit
anodes <= "1011";
to_decoder <= display_data(11 downto 8);
elsif disp_count = 3 then --Fourth digit
anodes <= "0111";
to_decoder <= display_data(15 downto 12);
end if;
end process;
--This represents a ROM that will act as the
--individual 7-segment decoder for each digit
--of the display
with to_decoder select
to_display <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"0000001" when others;
end Behavioral;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: lconf
-- File: lconf.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON configuration register. Returns the configuration
-- of the processor.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity lconf is
port (
rst : rst_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of lconf is
begin
beh : process(rst)
variable regsd : std_logic_vector(31 downto 0);
begin
regsd := (others => '0');
if WPROTEN then regsd(1 downto 0) := "01"; end if;
case PCICORE is
when insilicon => regsd(3 downto 2) := "01";
when esa => regsd(3 downto 2) := "10";
when others => regsd(3 downto 2) := "11";
end case;
if FPEN then
if (FPCORE = meiko) then regsd(5 downto 4) := "01";
else regsd(5 downto 4) := "10"; end if;
end if;
if AHBSTATEN then regsd(6) := '1'; end if;
if WDOGEN then regsd(7) := '1'; end if;
if MULTIPLIER /= none then regsd(8) := '1'; end if;
if DIVIDER /= none then regsd(9) := '1'; end if;
regsd(11 downto 10) := std_logic_vector(conv_unsigned(DLINE_BITS, 2));
regsd(14 downto 12) := std_logic_vector(conv_unsigned(DLINE_BITS+DOFFSET_BITS-8, 3));
regsd(16 downto 15) := std_logic_vector(conv_unsigned(ILINE_BITS, 2));
regsd(19 downto 17) := std_logic_vector(conv_unsigned(ILINE_BITS+IOFFSET_BITS-8, 3));
regsd(24 downto 20) := std_logic_vector(conv_unsigned(NWINDOWS-1,5));
if MACEN then regsd(25) := '1'; end if;
regsd(28 downto 26) := std_logic_vector(conv_unsigned(WATCHPOINTS,3));
apbo.prdata <= regsd;
end process;
end;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU - TLB
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The TLB (translation lookaside buffer) caches the last
-- address translations for faster access.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity tlb is
generic (
C_TLB_SIZE : integer := 128;
C_TAG_SIZE : integer := 20;
C_DATA_SIZE : integer := 32
);
port (
-- TLB ports
TLB_Tag : in std_logic_vector(C_TAG_SIZE - 1 downto 0);
TLB_DI : in std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_DO : out std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_WE : in std_logic;
TLB_Hit : out std_logic;
TLB_Clk : in std_logic;
TLB_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of TLB_Clk : signal is "Clk";
attribute SIGIS of TLB_Rst : signal is "Rst";
end entity tlb;
architecture implementation of tlb is
signal clk : std_logic;
signal rst : std_logic;
signal do : std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal hit : std_logic;
type TAG_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_TAG_SIZE - 1 downto 0);
type DATA_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal valid : std_logic_vector(0 to C_TLB_SIZE - 1);
signal tag_mem : TAG_MEM_T;
signal data_mem : DATA_MEM_T;
signal wrptr : std_logic_vector(clog2(C_TLB_SIZE) - 1 downto 0);
begin
clk <= TLB_Clk;
rst <= TLB_Rst;
TLB_DO <= do;
TLB_Hit <= hit;
write_proc : process(clk,rst) is
begin
if rst = '1' then
wrptr <= (others => '0');
valid <= (others => '0');
elsif rising_edge(clk) then
if TLB_WE = '1' then
tag_mem(CONV_INTEGER(wrptr)) <= TLB_Tag;
data_mem(CONV_INTEGER(wrptr)) <= TLB_DI;
valid(CONV_INTEGER(wrptr)) <= '1';
wrptr <= wrptr + 1;
end if;
end if;
end process write_proc;
read_proc : process(TLB_Tag,data_mem,valid,tag_mem) is
begin
hit <= '0';
do <= (others => '0');
-- loop over all tlb entries and take the first hit
for i in 0 to C_TLB_SIZE - 1 loop
if valid(i) = '1' and tag_mem(i) = TLB_Tag then
hit <= '1';
do <= data_mem(i);
exit;
end if;
end loop;
end process read_proc;
end architecture implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU - TLB
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The TLB (translation lookaside buffer) caches the last
-- address translations for faster access.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity tlb is
generic (
C_TLB_SIZE : integer := 128;
C_TAG_SIZE : integer := 20;
C_DATA_SIZE : integer := 32
);
port (
-- TLB ports
TLB_Tag : in std_logic_vector(C_TAG_SIZE - 1 downto 0);
TLB_DI : in std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_DO : out std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_WE : in std_logic;
TLB_Hit : out std_logic;
TLB_Clk : in std_logic;
TLB_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of TLB_Clk : signal is "Clk";
attribute SIGIS of TLB_Rst : signal is "Rst";
end entity tlb;
architecture implementation of tlb is
signal clk : std_logic;
signal rst : std_logic;
signal do : std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal hit : std_logic;
type TAG_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_TAG_SIZE - 1 downto 0);
type DATA_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal valid : std_logic_vector(0 to C_TLB_SIZE - 1);
signal tag_mem : TAG_MEM_T;
signal data_mem : DATA_MEM_T;
signal wrptr : std_logic_vector(clog2(C_TLB_SIZE) - 1 downto 0);
begin
clk <= TLB_Clk;
rst <= TLB_Rst;
TLB_DO <= do;
TLB_Hit <= hit;
write_proc : process(clk,rst) is
begin
if rst = '1' then
wrptr <= (others => '0');
valid <= (others => '0');
elsif rising_edge(clk) then
if TLB_WE = '1' then
tag_mem(CONV_INTEGER(wrptr)) <= TLB_Tag;
data_mem(CONV_INTEGER(wrptr)) <= TLB_DI;
valid(CONV_INTEGER(wrptr)) <= '1';
wrptr <= wrptr + 1;
end if;
end if;
end process write_proc;
read_proc : process(TLB_Tag,data_mem,valid,tag_mem) is
begin
hit <= '0';
do <= (others => '0');
-- loop over all tlb entries and take the first hit
for i in 0 to C_TLB_SIZE - 1 loop
if valid(i) = '1' and tag_mem(i) = TLB_Tag then
hit <= '1';
do <= data_mem(i);
exit;
end if;
end loop;
end process read_proc;
end architecture implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU - TLB
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The TLB (translation lookaside buffer) caches the last
-- address translations for faster access.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity tlb is
generic (
C_TLB_SIZE : integer := 128;
C_TAG_SIZE : integer := 20;
C_DATA_SIZE : integer := 32
);
port (
-- TLB ports
TLB_Tag : in std_logic_vector(C_TAG_SIZE - 1 downto 0);
TLB_DI : in std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_DO : out std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_WE : in std_logic;
TLB_Hit : out std_logic;
TLB_Clk : in std_logic;
TLB_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of TLB_Clk : signal is "Clk";
attribute SIGIS of TLB_Rst : signal is "Rst";
end entity tlb;
architecture implementation of tlb is
signal clk : std_logic;
signal rst : std_logic;
signal do : std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal hit : std_logic;
type TAG_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_TAG_SIZE - 1 downto 0);
type DATA_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal valid : std_logic_vector(0 to C_TLB_SIZE - 1);
signal tag_mem : TAG_MEM_T;
signal data_mem : DATA_MEM_T;
signal wrptr : std_logic_vector(clog2(C_TLB_SIZE) - 1 downto 0);
begin
clk <= TLB_Clk;
rst <= TLB_Rst;
TLB_DO <= do;
TLB_Hit <= hit;
write_proc : process(clk,rst) is
begin
if rst = '1' then
wrptr <= (others => '0');
valid <= (others => '0');
elsif rising_edge(clk) then
if TLB_WE = '1' then
tag_mem(CONV_INTEGER(wrptr)) <= TLB_Tag;
data_mem(CONV_INTEGER(wrptr)) <= TLB_DI;
valid(CONV_INTEGER(wrptr)) <= '1';
wrptr <= wrptr + 1;
end if;
end if;
end process write_proc;
read_proc : process(TLB_Tag,data_mem,valid,tag_mem) is
begin
hit <= '0';
do <= (others => '0');
-- loop over all tlb entries and take the first hit
for i in 0 to C_TLB_SIZE - 1 loop
if valid(i) = '1' and tag_mem(i) = TLB_Tag then
hit <= '1';
do <= data_mem(i);
exit;
end if;
end loop;
end process read_proc;
end architecture implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU - TLB
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The TLB (translation lookaside buffer) caches the last
-- address translations for faster access.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity tlb is
generic (
C_TLB_SIZE : integer := 128;
C_TAG_SIZE : integer := 20;
C_DATA_SIZE : integer := 32
);
port (
-- TLB ports
TLB_Tag : in std_logic_vector(C_TAG_SIZE - 1 downto 0);
TLB_DI : in std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_DO : out std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_WE : in std_logic;
TLB_Hit : out std_logic;
TLB_Clk : in std_logic;
TLB_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of TLB_Clk : signal is "Clk";
attribute SIGIS of TLB_Rst : signal is "Rst";
end entity tlb;
architecture implementation of tlb is
signal clk : std_logic;
signal rst : std_logic;
signal do : std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal hit : std_logic;
type TAG_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_TAG_SIZE - 1 downto 0);
type DATA_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal valid : std_logic_vector(0 to C_TLB_SIZE - 1);
signal tag_mem : TAG_MEM_T;
signal data_mem : DATA_MEM_T;
signal wrptr : std_logic_vector(clog2(C_TLB_SIZE) - 1 downto 0);
begin
clk <= TLB_Clk;
rst <= TLB_Rst;
TLB_DO <= do;
TLB_Hit <= hit;
write_proc : process(clk,rst) is
begin
if rst = '1' then
wrptr <= (others => '0');
valid <= (others => '0');
elsif rising_edge(clk) then
if TLB_WE = '1' then
tag_mem(CONV_INTEGER(wrptr)) <= TLB_Tag;
data_mem(CONV_INTEGER(wrptr)) <= TLB_DI;
valid(CONV_INTEGER(wrptr)) <= '1';
wrptr <= wrptr + 1;
end if;
end if;
end process write_proc;
read_proc : process(TLB_Tag,data_mem,valid,tag_mem) is
begin
hit <= '0';
do <= (others => '0');
-- loop over all tlb entries and take the first hit
for i in 0 to C_TLB_SIZE - 1 loop
if valid(i) = '1' and tag_mem(i) = TLB_Tag then
hit <= '1';
do <= data_mem(i);
exit;
end if;
end loop;
end process read_proc;
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sns01 is
port (a : natural range 0 to 15;
b : out unsigned (3 downto 0);
clk : std_logic);
end sns01;
architecture behav of sns01 is
begin
process (clk)
begin
if rising_edge(clk) then
b <= conv_unsigned (a, 4);
end if;
end process;
end behav;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_divider is
generic (
SIGNED : natural := 0;
WIDTH : natural := 8;
PIPELINE : natural := 0
);
port (
user_aclr : in std_logic := '0';
denom : in std_logic_vector(width-1 downto 0) := (others=>'0');
quotient : out std_logic_vector(width-1 downto 0);
remain : out std_logic_vector(width-1 downto 0);
numer : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_divider;
architecture rtl of alt_dspbuilder_divider is
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
SIGNED : natural := 0;
WIDTH : natural := 24;
PIPELINE : natural := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
denom : in std_logic_vector(24-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
numer : in std_logic_vector(24-1 downto 0) := (others=>'0');
quotient : out std_logic_vector(24-1 downto 0);
remain : out std_logic_vector(24-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
begin
alt_dspbuilder_divider_GNKAPZN5MO_0: if ((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_divider_GNKAPZN5MO_0: alt_dspbuilder_divider_GNKAPZN5MO
generic map(SIGNED => 0, WIDTH => 24, PIPELINE => 0)
port map(aclr => aclr, clock => clock, denom => denom, ena => ena, numer => numer, quotient => quotient, remain => remain, user_aclr => user_aclr);
end generate;
assert not (((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_divider is
generic (
SIGNED : natural := 0;
WIDTH : natural := 8;
PIPELINE : natural := 0
);
port (
user_aclr : in std_logic := '0';
denom : in std_logic_vector(width-1 downto 0) := (others=>'0');
quotient : out std_logic_vector(width-1 downto 0);
remain : out std_logic_vector(width-1 downto 0);
numer : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_divider;
architecture rtl of alt_dspbuilder_divider is
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
SIGNED : natural := 0;
WIDTH : natural := 24;
PIPELINE : natural := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
denom : in std_logic_vector(24-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
numer : in std_logic_vector(24-1 downto 0) := (others=>'0');
quotient : out std_logic_vector(24-1 downto 0);
remain : out std_logic_vector(24-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
begin
alt_dspbuilder_divider_GNKAPZN5MO_0: if ((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_divider_GNKAPZN5MO_0: alt_dspbuilder_divider_GNKAPZN5MO
generic map(SIGNED => 0, WIDTH => 24, PIPELINE => 0)
port map(aclr => aclr, clock => clock, denom => denom, ena => ena, numer => numer, quotient => quotient, remain => remain, user_aclr => user_aclr);
end generate;
assert not (((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal a : std_logic;
signal b : std_logic;
signal z : std_logic;
begin
dut: entity work.ent
port map (a, b, z);
process
constant av : std_logic_vector := b"1101";
constant bv : std_logic_vector := b"0111";
constant zv : std_logic_vector := b"0101";
begin
for i in av'range loop
a <= av (i);
b <= bv (i);
wait for 1 ns;
assert z = zv(i) severity failure;
end loop;
wait;
end process;
end behav;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Sample decoder. Extract sample words and write to sample ----
---- buffer. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, gedra@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
-- Revision 1.3 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.2 2004/06/16 19:04:09 gedra
-- Fixed a few bugs.
--
-- Revision 1.1 2004/06/13 18:07:47 gedra
-- Frame decoder and sample extractor
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx_decode is
generic (DATA_WIDTH: integer range 16 to 32;
ADDR_WIDTH: integer range 8 to 64);
port (
up_clk: in std_logic;
conf_rxen: in std_logic;
conf_sample: in std_logic;
conf_valid: in std_logic;
conf_mode: in std_logic_vector(3 downto 0);
conf_blken: in std_logic;
conf_valen: in std_logic;
conf_useren: in std_logic;
conf_staten: in std_logic;
conf_paren: in std_logic;
lock: in std_logic;
rx_data: in std_logic;
rx_data_en: in std_logic;
rx_block_start: in std_logic;
rx_frame_start: in std_logic;
rx_channel_a: in std_logic;
wr_en: out std_logic;
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
stat_paritya: out std_logic;
stat_parityb: out std_logic;
stat_lsbf: out std_logic;
stat_hsbf: out std_logic);
end rx_decode;
architecture rtl of rx_decode is
signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
signal sampst : samp_states;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal samp_start : integer range 0 to 15;
signal tmp_data : std_logic_vector(31 downto 0);
signal tmp_stat : std_logic_vector(4 downto 0);
signal valid, next_is_a, blk_start : std_logic;
begin
-- output data
OD32: if DATA_WIDTH = 32 generate
--wr_data(31 downto 27) <= tmp_stat;
wr_data(31 downto 0) <= tmp_data(31 downto 0);
end generate OD32;
OD16: if DATA_WIDTH = 16 generate
wr_data(15 downto 0) <= tmp_data(15 downto 0);
end generate OD16;
-- State machine extracting audio samples
SAEX: process (up_clk, conf_rxen)
begin -- process SAEX
if conf_rxen = '0' then
adr_cnt <= 0;
next_is_a <= '1';
wr_en <= '0';
wr_addr <= (others => '0');
tmp_data <= (others => '0');
par_cnt <= 0;
blk_start <= '0';
stat_paritya <= '0';
stat_parityb <= '0';
stat_lsbf <= '0';
stat_hsbf <= '0';
valid <= '0';
bit_cnt <= 0;
sampst <= IDLE;
tmp_stat <= (others => '0');
elsif rising_edge(up_clk) then
--extract and store samples
case sampst is
when IDLE =>
next_is_a <= '1';
if lock = '1' and conf_sample = '1' then
sampst <= CHA_SYNC;
end if;
when CHA_SYNC =>
wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
wr_en <= '0';
bit_cnt <= 0;
valid <= '0';
par_cnt <= 0;
stat_paritya <= '0';
stat_parityb <= '0';
stat_lsbf <= '0';
stat_hsbf <= '0';
--tmp_data(31 downto 0) <= (others => '0');
if rx_block_start = '1' and conf_blken = '1' then
blk_start <= '1';
end if;
if rx_frame_start = '1' then --and rx_channel_a = '1' then --next_is_a then
next_is_a <= rx_channel_a;
if(rx_channel_a = '1') then
tmp_data(31 downto 0) <= (others => '0');
end if;
sampst <= GET_SAMP;
end if;
when GET_SAMP =>
tmp_stat(0) <= blk_start;
if rx_data_en = '1' then
bit_cnt <= bit_cnt + 1;
-- audio part
if bit_cnt >= samp_start and bit_cnt <= 23 then
if(next_is_a = '1') then
tmp_data(bit_cnt - samp_start) <= rx_data;
else
tmp_data(bit_cnt + 16 - samp_start) <= rx_data;
end if;
end if;
-- status bits
case bit_cnt is
when 24 => -- validity bit
valid <= rx_data;
if conf_valen = '1' then
tmp_stat(1) <= rx_data;
else
tmp_stat(1) <= '0';
end if;
when 25 => -- user data
if conf_useren = '1' then
tmp_stat(2) <= rx_data;
else
tmp_stat(2) <= '0';
end if;
when 26 => -- channel status
if conf_staten = '1' then
tmp_stat(3) <= rx_data;
else
tmp_stat(3) <= '0';
end if;
when 27 => -- parity bit
if conf_paren = '1' then
tmp_stat(4) <= rx_data;
else
tmp_stat(4) <= '0';
end if;
when others =>
null;
end case;
-- parity: count number of 1's
if rx_data = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
if bit_cnt = 28 then
sampst <= PAR_CHK;
end if;
when PAR_CHK =>
blk_start <= '0';
if (((valid = '0' and conf_valid = '1') or conf_valid = '0') and (next_is_a = '0')) then
wr_en <= '1';
end if;
-- parity check
if par_cnt mod 2 /= 0 then
if rx_channel_a = '1' then
stat_paritya <= '1';
else
stat_parityb <= '1';
end if;
end if;
-- address counter
if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then
adr_cnt <= adr_cnt + 1;
else
adr_cnt <= 0;
stat_hsbf <= '1'; -- signal high buffer full
end if;
if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then
stat_lsbf <= '1'; -- signal low buffer full
end if;
sampst <= CHA_SYNC;
when others =>
sampst <= IDLE;
end case;
end if;
end process SAEX;
-- determine sample resolution from mode bits in 32bit mode
M32: if DATA_WIDTH = 32 generate
samp_start <= 8 when conf_mode = "0000" else
7 when conf_mode = "0001" else
6 when conf_mode = "0010" else
5 when conf_mode = "0011" else
4 when conf_mode = "0100" else
3 when conf_mode = "0101" else
2 when conf_mode = "0110" else
1 when conf_mode = "0111" else
0 when conf_mode = "1000" else
8;
end generate M32;
-- in 16bit mode only 16bit of audio is supported
M16: if DATA_WIDTH = 16 generate
samp_start <= 8;
end generate M16;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decodeur_uni is
Port ( E : in std_logic_vector(3 downto 0);
Suni : out std_logic_vector(6 downto 0));
end decodeur_uni;
architecture Behavioral of decodeur_uni is
begin
P1 : process (E)
begin
case E is
when "0000" => Suni <= "0000001";
when "0001" => Suni <= "1001111";
when "0010" => Suni <= "0010010";
when "0011" => Suni <= "0000110";
when "0100" => Suni <= "1001100";
when "0101" => Suni <= "0100100";
when "0110" => Suni <= "0100000";
when "0111" => Suni <= "0001111";
when "1000" => Suni <= "0000000";
when "1001" => Suni <= "0000100";
when "1010" => Suni <= "0000001";
when "1011" => Suni <= "1001111";
when "1100" => Suni <= "0010010";
when "1101" => Suni <= "0000110";
when "1110" => Suni <= "1001100";
when "1111" => Suni <= "0100100";
when others => Suni <= "0000000";
end case;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2624.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02624ent IS
END c13s03b01x00p02n01i02624ent;
ARCHITECTURE c13s03b01x00p02n01i02624arch OF c13s03b01x00p02n01i02624ent IS
BEGIN
TESTING: PROCESS
variable k{k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02624 - Identifier can not contain '{'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2624.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02624ent IS
END c13s03b01x00p02n01i02624ent;
ARCHITECTURE c13s03b01x00p02n01i02624arch OF c13s03b01x00p02n01i02624ent IS
BEGIN
TESTING: PROCESS
variable k{k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02624 - Identifier can not contain '{'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2624.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02624ent IS
END c13s03b01x00p02n01i02624ent;
ARCHITECTURE c13s03b01x00p02n01i02624arch OF c13s03b01x00p02n01i02624ent IS
BEGIN
TESTING: PROCESS
variable k{k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02624 - Identifier can not contain '{'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02624arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal limit_in : electrical;
terminal ll_in : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
f2 => 2000.0,
f1 => 5.0,
k => 400.0
)
port map(
input => ll_in,
output => limit_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => limit_in,
output => servo_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- library IEEE;
-- use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_sine.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
-- Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
-- voltage.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_Mech_Domain is
end TB_CS2_Mech_Domain;
architecture TB_CS2_Mech_Domain of TB_CS2_Mech_Domain is
-- Component declarations
-- Signal declarations
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => mot_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
XCMP35 : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP36 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
v6 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 4.8
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
end TB_CS2_Mech_Domain;
--
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal limit_in : electrical;
terminal ll_in : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
f2 => 2000.0,
f1 => 5.0,
k => 400.0
)
port map(
input => ll_in,
output => limit_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => limit_in,
output => servo_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- library IEEE;
-- use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_sine.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
-- Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
-- voltage.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_Mech_Domain is
end TB_CS2_Mech_Domain;
architecture TB_CS2_Mech_Domain of TB_CS2_Mech_Domain is
-- Component declarations
-- Signal declarations
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => mot_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
XCMP35 : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP36 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
v6 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 4.8
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
end TB_CS2_Mech_Domain;
--
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal limit_in : electrical;
terminal ll_in : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
f2 => 2000.0,
f1 => 5.0,
k => 400.0
)
port map(
input => ll_in,
output => limit_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => limit_in,
output => servo_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- library IEEE;
-- use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_sine.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
-- Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
-- voltage.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_Mech_Domain is
end TB_CS2_Mech_Domain;
architecture TB_CS2_Mech_Domain of TB_CS2_Mech_Domain is
-- Component declarations
-- Signal declarations
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => mot_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
XCMP35 : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP36 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
v6 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 4.8
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
end TB_CS2_Mech_Domain;
--
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: ip_add_header - Behavioral
--
-- Description: Add the IP header fields to a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ip_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_data_length : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end ip_add_header;
architecture Behavioral of ip_add_header is
type a_data_delay is array(0 to 20) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
-------------------------------------------------------
-- Note: Set the initial state to pass the data through
-------------------------------------------------------
signal count : unsigned(4 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
constant ip_version : STD_LOGIC_VECTOR ( 3 downto 0) := x"4";
constant ip_header_len : STD_LOGIC_VECTOR ( 3 downto 0) := x"5";
constant ip_type_of_service : STD_LOGIC_VECTOR ( 7 downto 0) := x"00"; --zzz
constant ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); --zzz
constant ip_flags : STD_LOGIC_VECTOR ( 2 downto 0) := (others => '0'); --zzz
constant ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0'); --zzz
constant ip_ttl : STD_LOGIC_VECTOR ( 7 downto 0) := x"FF";
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_checksum_1a : unsigned(19 downto 0) := (others => '0');
signal ip_checksum_1b : unsigned(19 downto 0) := (others => '0');
signal ip_checksum_2 : unsigned(19 downto 0) := (others => '0');
signal ip_checksum_3 : unsigned(16 downto 0) := (others => '0');
signal ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_0 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_1 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_2 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_3 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_4 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_5 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_6 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_7 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_8 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_9 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
begin
ip_length <= std_logic_vector(unsigned(ip_data_length)+20);
ip_word_0 <= ip_version & ip_header_len & ip_type_of_service;
ip_word_1 <= ip_length;
ip_word_2 <= ip_identification;
ip_word_3 <= ip_flags & ip_fragment_offset;
ip_word_4 <= ip_ttl & ip_protocol;
ip_word_5 <= ip_checksum;
ip_word_6 <= ip_src_ip( 7 downto 0) & ip_src_ip(15 downto 8);
ip_word_7 <= ip_src_ip(23 downto 16) & ip_src_ip(31 downto 24);
ip_word_8 <= ip_dst_ip( 7 downto 0) & ip_dst_ip(15 downto 8);
ip_word_9 <= ip_dst_ip(23 downto 16) & ip_dst_ip(31 downto 24);
process(clk)
begin
if rising_edge(clk) then
case count is
when "00000" => data_out <= ip_word_0(15 downto 8); data_valid_out <= '1';
when "00001" => data_out <= ip_word_0( 7 downto 0); data_valid_out <= '1';
when "00010" => data_out <= ip_word_1(15 downto 8); data_valid_out <= '1';
when "00011" => data_out <= ip_word_1( 7 downto 0); data_valid_out <= '1';
when "00100" => data_out <= ip_word_2(15 downto 8); data_valid_out <= '1';
when "00101" => data_out <= ip_word_2( 7 downto 0); data_valid_out <= '1';
when "00110" => data_out <= ip_word_3(15 downto 8); data_valid_out <= '1';
when "00111" => data_out <= ip_word_3( 7 downto 0); data_valid_out <= '1';
when "01000" => data_out <= ip_word_4(15 downto 8); data_valid_out <= '1';
when "01001" => data_out <= ip_word_4( 7 downto 0); data_valid_out <= '1';
when "01010" => data_out <= ip_word_5(15 downto 8); data_valid_out <= '1';
when "01011" => data_out <= ip_word_5( 7 downto 0); data_valid_out <= '1';
when "01100" => data_out <= ip_word_6(15 downto 8); data_valid_out <= '1';
when "01101" => data_out <= ip_word_6( 7 downto 0); data_valid_out <= '1';
when "01110" => data_out <= ip_word_7(15 downto 8); data_valid_out <= '1';
when "01111" => data_out <= ip_word_7( 7 downto 0); data_valid_out <= '1';
when "10000" => data_out <= ip_word_8(15 downto 8); data_valid_out <= '1';
when "10001" => data_out <= ip_word_8( 7 downto 0); data_valid_out <= '1';
when "10010" => data_out <= ip_word_9(15 downto 8); data_valid_out <= '1';
when "10011" => data_out <= ip_word_9( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "11111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "11111" then
count <= count + 1;
end if;
end if;
--------------------------------------------------------------------------------
-- Checksum is calculated in a pipeline, it will be ready by the time we need it
--------------------------------------------------------------------------------
ip_checksum_1a <= to_unsigned(0,20)
+ unsigned(ip_word_0)
+ unsigned(ip_word_1)
+ unsigned(ip_word_2)
+ unsigned(ip_word_3)
+ unsigned(ip_word_4);
ip_checksum_1b <= to_unsigned(0,20)
+ unsigned(ip_word_6)
+ unsigned(ip_word_7)
+ unsigned(ip_word_8)
+ unsigned(ip_word_9);
ip_checksum_2 <= ip_checksum_1a + ip_checksum_1b;
ip_checksum_3 <= to_unsigned(0,17) + ip_checksum_2(15 downto 0) + ip_checksum_2(19 downto 16);
ip_checksum <= not std_logic_vector(ip_checksum_3(15 downto 0) + ip_checksum_3(16 downto 16));
data_valid_in_last <= data_valid_in;
end if;
end process;
end Behavioral;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_bkb_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_bkb_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00010101", 2 => "00011100", 3 => "00100010",
4 => "00100111", 5 => "00101011", 6 => "00101110", 7 => "00110010",
8 => "00110101", 9 => "00111000", 10 => "00111011", 11 => "00111101",
12 => "01000000", 13 => "01000010", 14 => "01000100", 15 => "01000110",
16 => "01001000", 17 => "01001010", 18 => "01001100", 19 => "01001110",
20 => "01010000", 21 => "01010010", 22 => "01010100", 23 => "01010101",
24 => "01010111", 25 => "01011001", 26 => "01011010", 27 => "01011100",
28 => "01011101", 29 => "01011111", 30 => "01100000", 31 => "01100010",
32 => "01100011", 33 => "01100101", 34 => "01100110", 35 => "01100111",
36 => "01101001", 37 => "01101010", 38 => "01101011", 39 => "01101101",
40 => "01101110", 41 => "01101111", 42 => "01110000", 43 => "01110010",
44 => "01110011", 45 => "01110100", 46 => "01110101", 47 => "01110110",
48 => "01110111", 49 => "01111000", 50 => "01111010", 51 => "01111011",
52 => "01111100", 53 => "01111101", 54 => "01111110", 55 => "01111111",
56 => "10000000", 57 => "10000001", 58 => "10000010", 59 => "10000011",
60 => "10000100", 61 => "10000101", 62 => "10000110", 63 => "10000111",
64 => "10001000", 65 => "10001001", 66 => "10001010", 67 => "10001011",
68 => "10001100", 69 => "10001101", 70 => "10001110", 71 => "10001111",
72 to 73=> "10010000", 74 => "10010001", 75 => "10010010", 76 => "10010011",
77 => "10010100", 78 => "10010101", 79 => "10010110", 80 to 81=> "10010111",
82 => "10011000", 83 => "10011001", 84 => "10011010", 85 => "10011011",
86 to 87=> "10011100", 88 => "10011101", 89 => "10011110", 90 => "10011111",
91 to 92=> "10100000", 93 => "10100001", 94 => "10100010", 95 => "10100011",
96 to 97=> "10100100", 98 => "10100101", 99 => "10100110", 100 to 101=> "10100111",
102 => "10101000", 103 => "10101001", 104 to 105=> "10101010", 106 => "10101011",
107 => "10101100", 108 to 109=> "10101101", 110 => "10101110", 111 to 112=> "10101111",
113 => "10110000", 114 => "10110001", 115 to 116=> "10110010", 117 => "10110011",
118 to 119=> "10110100", 120 => "10110101", 121 to 122=> "10110110", 123 => "10110111",
124 to 125=> "10111000", 126 => "10111001", 127 to 128=> "10111010", 129 => "10111011",
130 to 131=> "10111100", 132 => "10111101", 133 to 134=> "10111110", 135 => "10111111",
136 to 137=> "11000000", 138 => "11000001", 139 to 140=> "11000010", 141 to 142=> "11000011",
143 => "11000100", 144 to 145=> "11000101", 146 => "11000110", 147 to 148=> "11000111",
149 to 150=> "11001000", 151 => "11001001", 152 to 153=> "11001010", 154 to 155=> "11001011",
156 => "11001100", 157 to 158=> "11001101", 159 to 160=> "11001110", 161 to 162=> "11001111",
163 => "11010000", 164 to 165=> "11010001", 166 to 167=> "11010010", 168 => "11010011",
169 to 170=> "11010100", 171 to 172=> "11010101", 173 to 174=> "11010110", 175 to 176=> "11010111",
177 => "11011000", 178 to 179=> "11011001", 180 to 181=> "11011010", 182 to 183=> "11011011",
184 to 185=> "11011100", 186 to 187=> "11011101", 188 => "11011110", 189 to 190=> "11011111",
191 to 192=> "11100000", 193 to 194=> "11100001", 195 to 196=> "11100010", 197 to 198=> "11100011",
199 to 200=> "11100100", 201 to 202=> "11100101", 203 to 204=> "11100110", 205 to 206=> "11100111",
207 to 208=> "11101000", 209 to 210=> "11101001", 211 to 212=> "11101010", 213 to 214=> "11101011",
215 to 216=> "11101100", 217 to 218=> "11101101", 219 to 220=> "11101110", 221 to 222=> "11101111",
223 to 224=> "11110000", 225 to 226=> "11110001", 227 to 228=> "11110010", 229 to 230=> "11110011",
231 to 232=> "11110100", 233 to 234=> "11110101", 235 to 236=> "11110110", 237 to 238=> "11110111",
239 to 240=> "11111000", 241 to 243=> "11111001", 244 to 245=> "11111010", 246 to 247=> "11111011",
248 to 249=> "11111100", 250 to 251=> "11111101", 252 to 253=> "11111110", 254 to 255=> "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00010101", 2 => "00011100", 3 => "00100010",
4 => "00100111", 5 => "00101011", 6 => "00101110", 7 => "00110010",
8 => "00110101", 9 => "00111000", 10 => "00111011", 11 => "00111101",
12 => "01000000", 13 => "01000010", 14 => "01000100", 15 => "01000110",
16 => "01001000", 17 => "01001010", 18 => "01001100", 19 => "01001110",
20 => "01010000", 21 => "01010010", 22 => "01010100", 23 => "01010101",
24 => "01010111", 25 => "01011001", 26 => "01011010", 27 => "01011100",
28 => "01011101", 29 => "01011111", 30 => "01100000", 31 => "01100010",
32 => "01100011", 33 => "01100101", 34 => "01100110", 35 => "01100111",
36 => "01101001", 37 => "01101010", 38 => "01101011", 39 => "01101101",
40 => "01101110", 41 => "01101111", 42 => "01110000", 43 => "01110010",
44 => "01110011", 45 => "01110100", 46 => "01110101", 47 => "01110110",
48 => "01110111", 49 => "01111000", 50 => "01111010", 51 => "01111011",
52 => "01111100", 53 => "01111101", 54 => "01111110", 55 => "01111111",
56 => "10000000", 57 => "10000001", 58 => "10000010", 59 => "10000011",
60 => "10000100", 61 => "10000101", 62 => "10000110", 63 => "10000111",
64 => "10001000", 65 => "10001001", 66 => "10001010", 67 => "10001011",
68 => "10001100", 69 => "10001101", 70 => "10001110", 71 => "10001111",
72 to 73=> "10010000", 74 => "10010001", 75 => "10010010", 76 => "10010011",
77 => "10010100", 78 => "10010101", 79 => "10010110", 80 to 81=> "10010111",
82 => "10011000", 83 => "10011001", 84 => "10011010", 85 => "10011011",
86 to 87=> "10011100", 88 => "10011101", 89 => "10011110", 90 => "10011111",
91 to 92=> "10100000", 93 => "10100001", 94 => "10100010", 95 => "10100011",
96 to 97=> "10100100", 98 => "10100101", 99 => "10100110", 100 to 101=> "10100111",
102 => "10101000", 103 => "10101001", 104 to 105=> "10101010", 106 => "10101011",
107 => "10101100", 108 to 109=> "10101101", 110 => "10101110", 111 to 112=> "10101111",
113 => "10110000", 114 => "10110001", 115 to 116=> "10110010", 117 => "10110011",
118 to 119=> "10110100", 120 => "10110101", 121 to 122=> "10110110", 123 => "10110111",
124 to 125=> "10111000", 126 => "10111001", 127 to 128=> "10111010", 129 => "10111011",
130 to 131=> "10111100", 132 => "10111101", 133 to 134=> "10111110", 135 => "10111111",
136 to 137=> "11000000", 138 => "11000001", 139 to 140=> "11000010", 141 to 142=> "11000011",
143 => "11000100", 144 to 145=> "11000101", 146 => "11000110", 147 to 148=> "11000111",
149 to 150=> "11001000", 151 => "11001001", 152 to 153=> "11001010", 154 to 155=> "11001011",
156 => "11001100", 157 to 158=> "11001101", 159 to 160=> "11001110", 161 to 162=> "11001111",
163 => "11010000", 164 to 165=> "11010001", 166 to 167=> "11010010", 168 => "11010011",
169 to 170=> "11010100", 171 to 172=> "11010101", 173 to 174=> "11010110", 175 to 176=> "11010111",
177 => "11011000", 178 to 179=> "11011001", 180 to 181=> "11011010", 182 to 183=> "11011011",
184 to 185=> "11011100", 186 to 187=> "11011101", 188 => "11011110", 189 to 190=> "11011111",
191 to 192=> "11100000", 193 to 194=> "11100001", 195 to 196=> "11100010", 197 to 198=> "11100011",
199 to 200=> "11100100", 201 to 202=> "11100101", 203 to 204=> "11100110", 205 to 206=> "11100111",
207 to 208=> "11101000", 209 to 210=> "11101001", 211 to 212=> "11101010", 213 to 214=> "11101011",
215 to 216=> "11101100", 217 to 218=> "11101101", 219 to 220=> "11101110", 221 to 222=> "11101111",
223 to 224=> "11110000", 225 to 226=> "11110001", 227 to 228=> "11110010", 229 to 230=> "11110011",
231 to 232=> "11110100", 233 to 234=> "11110101", 235 to 236=> "11110110", 237 to 238=> "11110111",
239 to 240=> "11111000", 241 to 243=> "11111001", 244 to 245=> "11111010", 246 to 247=> "11111011",
248 to 249=> "11111100", 250 to 251=> "11111101", 252 to 253=> "11111110", 254 to 255=> "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_bkb is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_bkb is
component Loop_loop_height_bkb_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_bkb_rom_U : component Loop_loop_height_bkb_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc599.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00599ent IS
END c03s04b01x00p01n01i00599ent;
ARCHITECTURE c03s04b01x00p01n01i00599arch OF c03s04b01x00p01n01i00599ent IS
type time_vector is array (natural range <>) of time;
type time_vector_file is file of time_vector;
BEGIN
TESTING: PROCESS
file filein : time_vector_file open write_mode is "iofile.27";
BEGIN
for i in 1 to 100 loop
write(filein,(1 ns,2 ns,3 ns,4 ns));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00599 - The output file will be verified by test s010232.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00599arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc599.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00599ent IS
END c03s04b01x00p01n01i00599ent;
ARCHITECTURE c03s04b01x00p01n01i00599arch OF c03s04b01x00p01n01i00599ent IS
type time_vector is array (natural range <>) of time;
type time_vector_file is file of time_vector;
BEGIN
TESTING: PROCESS
file filein : time_vector_file open write_mode is "iofile.27";
BEGIN
for i in 1 to 100 loop
write(filein,(1 ns,2 ns,3 ns,4 ns));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00599 - The output file will be verified by test s010232.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00599arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc599.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00599ent IS
END c03s04b01x00p01n01i00599ent;
ARCHITECTURE c03s04b01x00p01n01i00599arch OF c03s04b01x00p01n01i00599ent IS
type time_vector is array (natural range <>) of time;
type time_vector_file is file of time_vector;
BEGIN
TESTING: PROCESS
file filein : time_vector_file open write_mode is "iofile.27";
BEGIN
for i in 1 to 100 loop
write(filein,(1 ns,2 ns,3 ns,4 ns));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00599 - The output file will be verified by test s010232.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00599arch;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux_64.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux_64 is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 64 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux_64.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux_64 is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 64 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux_64.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux_64 is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 64 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux_64.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux_64.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux_64 is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 64 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: car_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY car_tb IS
END ENTITY;
ARCHITECTURE car_tb_ARCH OF car_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
car_synth_inst:ENTITY work.car_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
vunit verif4 (assert2(behav))
{
default clock is rising_edge(clk);
function check_val (v : unsigned) return boolean is
begin
return v < 10;
end check_val;
assume always check_val (val);
assert always val /= 5 abort rst;
}
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee_proposed;
use ieee.fixed_float_types.all;
use ieee.fixed_pkg.all;
entity Fixed_Point_ALU is
port( clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
result : out std_logic_vector(31 downto 0);
sel : in std_logic);
end Fixed_Point_ALU;
architecture behavioral of Fixed_Point_ALU is
signal A_fixed : sfixed(2 downto -29);
signal B_fixed : sfixed(2 downto -29);
signal result_fixed : sfixed(2 downto -29);
begin
--reg_inputs : process(clk, rst)
-- begin
-- if rst = '1' then
-- A_fixed <= (others => '0');
-- B_fixed <= (others => '0');
-- elsif rising_edge(clk) then
-- A_fixed <= to_sfixed(A, 2, -29);
-- B_fixed <= to_sfixed(B, 2, -29);
-- end if;
-- end process;
A_fixed <= to_sfixed(A, 2, -29);
B_fixed <= to_sfixed(B, 2, -29);
process (A_fixed, B_fixed, sel)
begin
if sel = '1' then --multiply
result_fixed <= resize(A_fixed * B_fixed, result_fixed'high, result_fixed'low);
result <= to_slv(result_fixed);
else --divide
result_fixed <= resize(A_fixed / B_fixed, result_fixed'high, result_fixed'low);
result <= to_slv(result_fixed);
end if;
end process;
end behavioral;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY mux_2x1 IS
PORT(a, b, ctrl: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux_2x1;
ARCHITECTURE dataflow OF mux_2x1 IS
BEGIN
q<=a when ctrl='0' else b;
END dataflow; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory is
Port (
clk80 : in std_logic;
rst : in std_logic;
cam_vs : in STD_LOGIC;
vid_vs : in STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
CQ_write_en : in STD_LOGIC;
-- CQ_write_clk : in STD_LOGIC;
CQ_data_in : in STD_LOGIC_VECTOR(15 downto 0);
VQ_read_en : in STD_LOGIC;
-- VQ_read_clk : in STD_LOGIC;
VQ_data_out : out STD_LOGIC_VECTOR(15 downto 0);
RAM_addr : out std_logic_vector(22 downto 0);
RAM_data_out : out std_logic_vector(15 downto 0);
RAM_data_in : in std_logic_vector(15 downto 0);
RAM_oe : out std_logic;
RAM_we : out std_logic;
RAM_adv : out std_logic;
RAM_clk_en : out std_logic;
RAM_ub : out std_logic;
RAM_lb : out std_logic;
RAM_ce : out std_logic;
RAM_cre : out std_logic;
RAM_wait : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end memory;
architecture Behavioral of memory is
type state_type is (start, cfgmem, cfgmem_wait, cfgmem_done, cfgReadAry, cfgReadAry_wait, waitstate,
mem_write_init, mem_write_init_wait_high, mem_write_init_wait, mem_write_data,
mem_write_end, mem_read_init, mem_read_init_wait_high, mem_read_init_wait,
mem_read_data, mem_read_end);
signal state, next_state : state_type;
signal RAM_addr_s : std_logic_vector(22 downto 0);
signal RAM_oe_s : std_logic;
signal latency_cnt : integer;
signal data_in_reg : std_logic_vector(15 downto 0);
signal CQ_empty : STD_LOGIC;
signal CQ_read_en : STD_LOGIC;
signal CQ_data_out : STD_LOGIC_VECTOR(15 downto 0);
signal VQ_full : STD_LOGIC;
signal VQ_write_en : STD_LOGIC;
signal VQ_data_in : STD_LOGIC_VECTOR(15 downto 0);
signal write_addr_reg : STD_LOGIC_VECTOR(22 downto 0);
signal write_addr_inc : STD_LOGIC;
signal read_addr_reg : STD_LOGIC_VECTOR(22 downto 0);
signal read_addr_inc : STD_LOGIC;
signal RAM_data_in_reg : STD_LOGIC_VECTOR(15 downto 0);
signal VQ_data_in_reg : STD_LOGIC_VECTOR(15 downto 0);
signal VQ_write_en_reg : STD_LOGIC;
signal CQ_read_en_reg : STD_LOGIC;
----Queue component delcaration
--component FIFO
-- port (
-- din: IN std_logic_VECTOR(15 downto 0);
-- rd_clk: IN std_logic;
-- rd_en: IN std_logic;
-- rst: IN std_logic;
-- wr_clk: IN std_logic;
-- wr_en: IN std_logic;
-- dout: OUT std_logic_VECTOR(15 downto 0);
-- empty: OUT std_logic;
-- full: OUT std_logic);
--end component;
--
---- Synplicity black box declaration
--attribute syn_black_box : boolean;
--attribute syn_black_box of FIFO: component is true;
component fifo is
port(
CLR : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
DATA : in std_logic_vector(15 downto 0);
EMPTY : out std_logic;
FULL : out std_logic;
Q : out std_logic_vector(15 downto 0)
);
end component;
begin
RAM_oe <= RAM_oe_s;
RAM_addr <= RAM_addr_s;
empty <= CQ_empty;
full <= VQ_full;
CQ : fifo
port map (
clr => rst,
clk => clk80,
rd => CQ_read_en,
wr => CQ_write_en,
data => CQ_data_in,
empty => CQ_empty,
q => CQ_data_out);
VQ : fifo
port map (
clr => rst,
clk => clk80,
rd => VQ_read_en,
wr => VQ_write_en,
data => VQ_data_in,
full => VQ_full,
q => VQ_data_out);
----The camera queue
--CQ : FIFO
-- port map (
-- din => CQ_data_in,
-- rd_clk => clk80,
-- rd_en => CQ_read_en_reg,
-- rst => rst,
-- wr_clk => CQ_write_clk,
-- wr_en => CQ_write_en,
-- dout => CQ_data_out,
-- empty => CQ_empty);
--
----The video queue
--VQ : FIFO
-- port map (
-- din => VQ_data_in_reg,
-- rd_clk => VQ_read_clk,
-- rd_en => VQ_read_en,
-- rst => rst,
-- wr_clk => clk80,
-- wr_en => VQ_write_en_reg,
-- dout => VQ_data_out,
-- full => VQ_full);
RAM_control_SM: process(clk80, rst)
begin
if rst='1' then
state <= start;
latency_cnt <= 0;
elsif clk80'event and clk80='1' then
if state /= next_state then
latency_cnt <= 1;
else
latency_cnt <= latency_cnt + 1;
end if;
state <= next_state;
end if;
end process;
RAM_control_NextState: process(state, latency_cnt, RAM_wait)
begin
case state is
--Configuring the memory
when start =>
next_state <= cfgMem;
when cfgmem =>
if latency_cnt < 7 then
next_state <= cfgmem;
else
next_state <= cfgMem_wait;
end if;
when cfgmem_wait =>
--wait is active high (default)
if latency_cnt < 7 then
next_state <= cfgMem_wait;
else
next_state <= cfgmem_done;
end if;
when cfgmem_done =>
if latency_cnt < 4 then
next_state <= cfgmem_done;
else
next_state <= cfgReadAry;
end if;
when cfgReadAry =>
if latency_cnt < 7 then
next_state <= cfgReadAry;
else
next_state <= cfgReadAry_wait;
end if;
when cfgReadAry_wait =>
if latency_cnt < 7 then
next_state <= cfgReadAry_wait;
else
next_state <= waitstate;
end if;
when waitstate =>
if latency_cnt < 7 then
next_state <= waitstate;
else
next_state <= mem_write_init;
end if;
--Initiate a write to memory
when mem_write_init =>
next_state <= mem_write_init_wait_high;
when mem_write_init_wait_high =>
if RAM_wait = '1' then
next_state <= mem_write_init_wait;
else
next_state <= mem_write_init_wait_high;
end if;
when mem_write_init_wait =>
if RAM_wait = '1' then
next_state <= mem_write_init_wait;
else
next_state <= mem_write_data;
end if;
--Write data
when mem_write_data =>
if CQ_empty = '1' then
next_state <= mem_write_end;
else
next_state <= mem_write_data;
end if;
when mem_write_end =>
if latency_cnt <= 2 then
next_state <= mem_write_end;
else
next_state <= mem_read_init;
end if;
--Initiate a read from memory
when mem_read_init =>
next_state <= mem_read_init_wait_high;
when mem_read_init_wait_high =>
if RAM_wait = '1' then
next_state <= mem_read_init_wait;
else
next_state <= mem_read_init_wait_high;
end if;
when mem_read_init_wait =>
if RAM_wait = '1' then
next_state <= mem_read_init_wait;
else
next_state <= mem_read_data;
end if;
--Read data from memory
when mem_read_data =>
if VQ_full = '1' then
next_state <= mem_read_end;
else
next_state <= mem_read_data;
end if;
when mem_read_end =>
if latency_cnt <= 2 then
next_state <= mem_read_end;
else
next_state <= mem_write_init;
end if;
when others => null;
end case;
end process;
RAM_controller: process(state, RAM_data_in, latency_cnt)
begin
RAM_clk_en <= '1';
RAM_oe_s <= '1';
RAM_we <= '1';
RAM_adv <= '1';
RAM_ub <= '0';
RAM_lb <= '0';
RAM_ce <= '1';
RAM_cre <= '0';
RAM_addr_s <= (others => '0');
RAM_data_out <= (others => '0');
CQ_read_en <= '0';
VQ_write_en <= '0';
VQ_data_in <= (others => '0');
write_addr_inc <= '0';
read_addr_inc <= '0';
case state is
--Configure the memory
when start =>
RAM_clk_en <= '0';
when cfgmem =>
RAM_clk_en <= '0';
RAM_addr_s <= "00010000001110100011111";
RAM_cre <= '1';
RAM_adv <= '0';
RAM_ce <= '0';
RAM_we <= '0';
when cfgmem_wait =>
--wait is active high (default)
RAM_clk_en <= '0';
RAM_addr_s <= "00010000001110100011111";
RAM_ce <= '0';
when cfgmem_done =>
RAM_clk_en <= '0';
RAM_ce <= '1';
when cfgReadAry =>
RAM_clk_en <= '0';
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe_s <= '0';
when cfgReadAry_wait =>
RAM_clk_en <= '0';
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe_s <= '0';
if latency_cnt >= 3 then
RAM_adv <= '1';
end if;
when waitstate =>
--Initiate a write to memory
when mem_write_init =>
RAM_addr_s <= write_addr_reg;
RAM_ce <= '0';
RAM_adv <= '0';
RAM_we <= '0';
when mem_write_init_wait_high =>
RAM_ce <= '0';
when mem_write_init_wait =>
RAM_ce <= '0';
if RAM_wait = '1' then
CQ_read_en <= '1';
end if;
--Write data
when mem_write_data =>
RAM_ce <= '0';
RAM_data_out <= CQ_data_out;
write_addr_inc <= '1';
if CQ_empty = '0' then
CQ_read_en <= '1';
end if;
when mem_write_end =>
--All taken care of in defaults
--Initiate a read from memory
when mem_read_init =>
RAM_addr_s <= read_addr_reg;
RAM_ce <= '0';
RAM_adv <= '0';
when mem_read_init_wait_high =>
RAM_ce <= '0';
RAM_oe_s <= '0';
when mem_read_init_wait =>
RAM_ce <= '0';
RAM_oe_s <= '0';
--Read data
when mem_read_data =>
RAM_ce <= '0';
if VQ_full = '0' then
VQ_data_in <= RAM_data_in_reg;
VQ_write_en <= '1';
read_addr_inc <= '1';
end if;
when mem_read_end =>
--Taken care of up top in defaults
when others => null;
end case;
end process;
datainreg: process (clk80, rst)
begin
if rst='1' then
RAM_data_in_reg <= (others => '0');
elsif clk80'event and clk80='1' then
RAM_data_in_reg <= RAM_data_in;
end if;
end process;
address_regs: process (clk80, rst, cam_vs, vid_vs)
begin
if rst = '1' then
write_addr_reg <= (others => '0');
read_addr_reg <= (others => '0');
elsif cam_vs = '1' then --syncs high
write_addr_reg <= (others => '0');
elsif vid_vs = '0' then
read_addr_reg <= (others => '0');
elsif falling_edge(clk80) then
if write_addr_inc = '1' then
write_addr_reg <= write_addr_reg + 1;
end if;
if read_addr_inc = '1' then
read_addr_reg <= read_addr_reg + 1;
end if;
end if;
end process;
fifo_regs: process (clk80, rst)
begin
if rst = '1' then
CQ_read_en_reg <= '0';
VQ_write_en_reg <= '0';
VQ_data_in_reg <= (others => '0');
elsif falling_edge(clk80) then
CQ_read_en_reg <= CQ_read_en;
VQ_write_en_reg <= VQ_write_en;
VQ_data_in_reg <= VQ_data_in;
end if;
end process;
end Behavioral;
|
-- This VHDL implementation of a BRAM fifo is from www.asic-world.com
-------------------------------------------------------------------------------
-- Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
-- Coder : Alex Claros F.
-- Date : 15/May/2005.
-- Notes : This implementation is based on the article
-- 'Asynchronous FIFO in Virtex-II FPGAs'
-- writen by Peter Alfke. This TechXclusive
-- article can be downloaded from the
-- Xilinx website. It has some minor modifications.
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator: Alexander H Pham (VHDL)
-------------------------------------------------------------------------------
-- Grey counter definition
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity GrayCounter is
generic (
COUNTER_WIDTH : integer
) ;
port (
GrayCount_out : out STD_LOGIC_VECTOR(COUNTER_WIDTH-1 downto 0) ;
Enable_in : in STD_LOGIC ;
Clear_in : in STD_LOGIC ;
clk : in STD_LOGIC
) ;
end GrayCounter;
architecture handwritten of GrayCounter is
signal BinaryCount : std_logic_vector(COUNTER_WIDTH-1 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then
if (Clear_in = '1') then
BinaryCount <= conv_std_logic_vector(1, COUNTER_WIDTH) ;
GrayCount_out <= (others => '0') ;
elsif (Enable_in = '1') then
BinaryCount <= BinaryCount + 1 ;
GrayCount_out <= BinaryCount(COUNTER_WIDTH-1) &
(BinaryCount(COUNTER_WIDTH-2 downto 0) xor
BinaryCount(COUNTER_WIDTH-1 downto 1)) ;
end if;
end if;
end process ;
end handwritten;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity InferredBRAMFifo is
generic (
DATA_WIDTH :integer;
DATA_DEPTH :integer
);
port (
-- Reading port.
Data_out :out std_logic_vector (DATA_WIDTH-1 downto 0);
Empty_out :out std_logic;
ReadEn_in :in std_logic;
RClk :in std_logic;
-- Writing port.
Data_in :in std_logic_vector (DATA_WIDTH-1 downto 0);
Full_out :out std_logic;
WriteEn_in :in std_logic;
WClk :in std_logic;
Clear_in:in std_logic
);
end entity;
architecture rtl of InferredBRAMFifo is
--function to discern internal address size from data depth
function log2_ceil(N : integer) return integer is
begin
if( N <= 2 ) then
return 1;
else
if( N mod 2 = 0 ) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
----/Internal connections & variables------
constant ADDR_WIDTH :integer := log2_ceil(DATA_DEPTH);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
signal Mem : RAM (0 to DATA_DEPTH-1);
attribute syn_ramstyle : string;
attribute syn_ramstyle of Mem : signal is "block_ram";
signal pNextWordToWrite :std_logic_vector (ADDR_WIDTH-1 downto 0);
signal pNextWordToRead :std_logic_vector (ADDR_WIDTH-1 downto 0);
signal EqualAddresses :std_logic;
signal NextWriteAddressEn :std_logic;
signal NextReadAddressEn :std_logic;
signal Set_Status :std_logic;
signal Rst_Status :std_logic;
signal Status :std_logic;
signal PresetFull :std_logic;
signal PresetEmpty :std_logic;
signal empty,full :std_logic;
component GrayCounter is
generic (
COUNTER_WIDTH :integer
);
port (
GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);
Enable_in :in std_logic; --Count enable.
Clear_in :in std_logic; --Count reset.
clk :in std_logic
);
end component;
begin
--------------Code--------------/
--Data ports logic:
--(Uses a dual-port RAM).
--'Data_out' logic:
process (RClk, Clear_in) begin
if( Clear_in = '1' ) then
Data_out <= (others=>'0');
elsif (rising_edge(RClk)) then
if (ReadEn_in = '1' and empty = '0') then
Data_out <= Mem(conv_integer(pNextWordToRead));
end if;
end if;
end process;
--'Data_in' logic:
process (WClk) begin
if (rising_edge(WClk)) then
if (WriteEn_in = '1' and full = '0') then
Mem(conv_integer(pNextWordToWrite)) <= Data_in;
end if;
end if;
end process;
--Fifo addresses support logic:
--'Next Addresses' enable logic:
NextWriteAddressEn <= WriteEn_in and (not full);
NextReadAddressEn <= ReadEn_in and (not empty);
--Addreses (Gray counters) logic:
GrayCounter_pWr : GrayCounter
generic map (
COUNTER_WIDTH => ADDR_WIDTH
)
port map (
GrayCount_out => pNextWordToWrite,
Enable_in => NextWriteAddressEn,
Clear_in => Clear_in,
clk => WClk
);
GrayCounter_pRd : GrayCounter
generic map (
COUNTER_WIDTH => ADDR_WIDTH
)
port map (
GrayCount_out => pNextWordToRead,
Enable_in => NextReadAddressEn,
Clear_in => Clear_in,
clk => RClk
);
--'EqualAddresses' logic:
EqualAddresses <= '1' when (pNextWordToWrite = pNextWordToRead) else '0';
--'Quadrant selectors' logic:
process (pNextWordToWrite, pNextWordToRead)
variable set_status_bit0 :std_logic;
variable set_status_bit1 :std_logic;
variable rst_status_bit0 :std_logic;
variable rst_status_bit1 :std_logic;
begin
set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor pNextWordToRead(ADDR_WIDTH-1);
set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor pNextWordToRead(ADDR_WIDTH-2);
Set_Status <= set_status_bit0 and set_status_bit1;
rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor pNextWordToRead(ADDR_WIDTH-1);
rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor pNextWordToRead(ADDR_WIDTH-2);
Rst_Status <= rst_status_bit0 and rst_status_bit1;
end process;
--'Status' latch logic:
process (Set_Status, Rst_Status, Clear_in) begin--D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status = '1' or Clear_in = '1') then
Status <= '0'; --Going 'Empty'.
elsif (Set_Status = '1') then
Status <= '1'; --Going 'Full'.
end if;
end process;
--'Full_out' logic for the writing port:
PresetFull <= Status and EqualAddresses; --'Full' Fifo.
process (WClk, PresetFull) begin --D Flip-Flop w/ Asynchronous Preset.
if (PresetFull = '1') then
full <= '1';
elsif (rising_edge(WClk)) then
full <= '0';
end if;
end process;
Full_out <= full;
--'Empty_out' logic for the reading port:
PresetEmpty <= not Status and EqualAddresses; --'Empty' Fifo.
process (RClk, PresetEmpty) begin --D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty = '1') then
empty <= '1';
elsif (rising_edge(RClk)) then
empty <= '0';
end if;
end process;
Empty_out <= empty;
end architecture;
|
-- megafunction wizard: %DDR2 SDRAM Controller with UniPHY v15.0%
-- GENERATION: XML
-- uniphy.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity uniphy is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => '0'); -- afi.afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => '0'); -- .afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => '0'); -- .afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => '0'); -- .afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- .afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- .afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => '0'); -- .afi_mem_clk_disable
afi_init_req : in std_logic := '0'; -- .afi_init_req
afi_cal_req : in std_logic := '0'; -- .afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- .afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- .afi_rlat
afi_cal_success : out std_logic; -- .afi_cal_success
afi_cal_fail : out std_logic; -- .afi_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end entity uniphy;
architecture rtl of uniphy is
component uniphy_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => 'X'); -- afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => 'X'); -- afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => 'X'); -- afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => 'X'); -- afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_mem_clk_disable
afi_init_req : in std_logic := 'X'; -- afi_init_req
afi_cal_req : in std_logic := 'X'; -- afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- afi_rlat
afi_cal_success : out std_logic; -- afi_cal_success
afi_cal_fail : out std_logic; -- afi_cal_fail
oct_rdn : in std_logic := 'X'; -- rdn
oct_rup : in std_logic := 'X' -- rup
);
end component uniphy_0002;
begin
uniphy_inst : component uniphy_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
afi_addr => afi_addr, -- afi.afi_addr
afi_ba => afi_ba, -- .afi_ba
afi_cke => afi_cke, -- .afi_cke
afi_cs_n => afi_cs_n, -- .afi_cs_n
afi_ras_n => afi_ras_n, -- .afi_ras_n
afi_we_n => afi_we_n, -- .afi_we_n
afi_cas_n => afi_cas_n, -- .afi_cas_n
afi_odt => afi_odt, -- .afi_odt
afi_dqs_burst => afi_dqs_burst, -- .afi_dqs_burst
afi_wdata_valid => afi_wdata_valid, -- .afi_wdata_valid
afi_wdata => afi_wdata, -- .afi_wdata
afi_dm => afi_dm, -- .afi_dm
afi_rdata => afi_rdata, -- .afi_rdata
afi_rdata_en => afi_rdata_en, -- .afi_rdata_en
afi_rdata_en_full => afi_rdata_en_full, -- .afi_rdata_en_full
afi_rdata_valid => afi_rdata_valid, -- .afi_rdata_valid
afi_mem_clk_disable => afi_mem_clk_disable, -- .afi_mem_clk_disable
afi_init_req => afi_init_req, -- .afi_init_req
afi_cal_req => afi_cal_req, -- .afi_cal_req
afi_wlat => afi_wlat, -- .afi_wlat
afi_rlat => afi_rlat, -- .afi_rlat
afi_cal_success => afi_cal_success, -- .afi_cal_success
afi_cal_fail => afi_cal_fail, -- .afi_cal_fail
oct_rdn => oct_rdn, -- oct.rdn
oct_rup => oct_rup -- .rup
);
end architecture rtl; -- of uniphy
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr2_emif" version="15.0" >
-- Retrieval info: <generic name="RATE" value="Full" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="333.3333" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-- Retrieval info: <generic name="MEM_FORMAT" value="UNBUFFERED" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="64" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="2" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="DUPLICATE_AC" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="AP_MODE_EN" value="0" />
-- Retrieval info: <generic name="AP_MODE" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="4" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="2x refresh rate" />
-- Retrieval info: <generic name="MEM_PD" value="Fast exit" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="Full" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="50" />
-- Retrieval info: <generic name="MEM_ATCL" value="0" />
-- Retrieval info: <generic name="MEM_TCL" value="6" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="375" />
-- Retrieval info: <generic name="TIMING_TIH" value="500" />
-- Retrieval info: <generic name="TIMING_TDS" value="250" />
-- Retrieval info: <generic name="TIMING_TDH" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQHS" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="350" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TDQSH" value="0.35" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="200" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="5" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="40.0" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="127.5" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="3" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="7.5" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="2" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="8" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="false" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-- Retrieval info: <generic name="TREFI" value="35100" />
-- Retrieval info: <generic name="REFRESH_INTERVAL" value="15000" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL_TEST" value="false" />
-- Retrieval info: <generic name="TRFC" value="350" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="true" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.6" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: <generic name="AUTO_DEVICE_SPEEDGRADE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : uniphy.vho
-- RELATED_FILES: uniphy.vhd, uniphy_0002.v, uniphy_pll0.sv, uniphy_p0_clock_pair_generator.v, uniphy_p0_read_valid_selector.v, uniphy_p0_addr_cmd_datapath.v, uniphy_p0_reset.v, uniphy_p0_acv_ldc.v, uniphy_p0_memphy.sv, uniphy_p0_reset_sync.v, uniphy_p0_new_io_pads.v, uniphy_p0_fr_cycle_shifter.v, uniphy_p0_fr_cycle_extender.v, uniphy_p0_read_datapath.sv, uniphy_p0_write_datapath.v, uniphy_p0_simple_ddio_out.sv, uniphy_p0_phy_csr.sv, uniphy_p0_iss_probe.v, uniphy_p0_addr_cmd_pads.v, uniphy_p0_flop_mem.v, uniphy_p0.sv, uniphy_p0_altdqdqs.v, altdq_dqs2_ddio_3reg_stratixiv.sv, afi_mux_ddrx.v, uniphy_s0.v, altera_mem_if_sequencer_rst.sv, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, sequencer_scc_siii_phase_decode.v, sequencer_scc_sv_wrapper.sv, sequencer_scc_sv_phase_decode.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_acv_phase_decode.v, sequencer_scc_reg_file.v, sequencer_reg_file.sv, sequencer_phy_mgr.sv, sequencer_data_mgr.sv, rw_manager_ddr2.v, rw_manager_ac_ROM_reg.v, rw_manager_bitcheck.v, rw_manager_core.sv, rw_manager_data_broadcast.v, rw_manager_data_decoder.v, rw_manager_datamux.v, rw_manager_di_buffer.v, rw_manager_di_buffer_wrap.v, rw_manager_dm_decoder.v, rw_manager_generic.sv, rw_manager_inst_ROM_reg.v, rw_manager_jumplogic.v, rw_manager_lfsr72.v, rw_manager_lfsr36.v, rw_manager_lfsr12.v, rw_manager_pattern_fifo.v, rw_manager_ram.v, rw_manager_ram_csr.v, rw_manager_read_datapath.v, rw_manager_write_decoder.v, rw_manager_ac_ROM_no_ifdef_params.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, uniphy_s0_mm_interconnect_0.v, uniphy_s0_irq_mapper.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, uniphy_s0_mm_interconnect_0_router.sv, uniphy_s0_mm_interconnect_0_router_001.sv, uniphy_s0_mm_interconnect_0_router_002.sv, uniphy_s0_mm_interconnect_0_router_005.sv, uniphy_s0_mm_interconnect_0_cmd_demux.sv, uniphy_s0_mm_interconnect_0_cmd_demux_001.sv, altera_merlin_arbitrator.sv, uniphy_s0_mm_interconnect_0_cmd_mux.sv, uniphy_s0_mm_interconnect_0_cmd_mux_003.sv, uniphy_s0_mm_interconnect_0_rsp_demux_003.sv, uniphy_s0_mm_interconnect_0_rsp_mux.sv, uniphy_s0_mm_interconnect_0_rsp_mux_001.sv, uniphy_s0_mm_interconnect_0_avalon_st_adapter.v, uniphy_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv, altera_mem_if_oct_stratixiv.sv, altera_mem_if_dll_stratixiv.sv
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwxsh
-- File: grfpwxsh.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwxsh is
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grfpwxsh is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grfpwsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0);
start : out std_logic;
nonstd : out std_logic;
flop : out std_logic_vector(8 downto 0);
op1 : out std_logic_vector(63 downto 0);
op2 : out std_logic_vector(63 downto 0);
opid : out std_logic_vector(7 downto 0);
flush : out std_logic;
flushid : out std_logic_vector(5 downto 0);
rndmode : out std_logic_vector(1 downto 0);
req : out std_logic_vector(2 downto 0);
res : in std_logic_vector(63 downto 0);
exc : in std_logic_vector(5 downto 0);
allow : in std_logic_vector(2 downto 0);
rdy : in std_logic;
cc : in std_logic_vector(1 downto 0);
idout : in std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpwsh generic map (tech, pclow, dsu, disas,
id)
port map (rst,
clk,
holdn,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2 ,
fpui.start ,
fpui.nonstd ,
fpui.flop ,
fpui.op1 ,
fpui.op2 ,
fpui.opid ,
fpui.flush ,
fpui.flushid ,
fpui.rndmode ,
fpui.req ,
fpuo.res ,
fpuo.exc ,
fpuo.allow ,
fpuo.rdy ,
fpuo.cc ,
fpuo.idout
);
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
entity led8_sseg is
generic(
clock_freq_hz : natural := 50_000_000;
refresh_rate_hz : natural := 800
);
port
(
clk : in std_logic ;
reset : in std_logic ;
led: in std_logic_vector(7 downto 0);
an : out std_logic_vector(4 downto 0);
sseg_out : out std_logic_vector(7 downto 0)
);
end led8_sseg ;
architecture Behavioral of led8_sseg is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal sseg0, sseg1, sseg2, sseg3, sseg_clk: std_logic_vector(7 downto 0);
signal divider_counter : std_logic_vector(31 downto 0);
signal divider_end : std_logic ;
signal an_r : std_logic_vector(4 downto 0) := "00001";
begin
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, 32));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, 32));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
an_r(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
an_r(4 downto 1) <= an_r(3 downto 0);
an_r(0) <= an_r(4);
end if ;
end if ;
end process ;
with an_r select
sseg_out <= sseg0 when "00001",
sseg1 when "00010",
sseg2 when "00100",
sseg3 when "01000",
sseg_clk when "10000",
(others => '0') when others ;
an <= an_r ;
-- --CONVERT THE LEDS TO THE 4X SEVEN SEGMENTS LED segements
with led(1 downto 0) select
sseg0 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(3 downto 2) select
sseg1 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(5 downto 4) select
sseg2 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(7 downto 6) select
sseg3 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
entity led8_sseg is
generic(
clock_freq_hz : natural := 50_000_000;
refresh_rate_hz : natural := 800
);
port
(
clk : in std_logic ;
reset : in std_logic ;
led: in std_logic_vector(7 downto 0);
an : out std_logic_vector(4 downto 0);
sseg_out : out std_logic_vector(7 downto 0)
);
end led8_sseg ;
architecture Behavioral of led8_sseg is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal sseg0, sseg1, sseg2, sseg3, sseg_clk: std_logic_vector(7 downto 0);
signal divider_counter : std_logic_vector(31 downto 0);
signal divider_end : std_logic ;
signal an_r : std_logic_vector(4 downto 0) := "00001";
begin
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, 32));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, 32));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
an_r(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
an_r(4 downto 1) <= an_r(3 downto 0);
an_r(0) <= an_r(4);
end if ;
end if ;
end process ;
with an_r select
sseg_out <= sseg0 when "00001",
sseg1 when "00010",
sseg2 when "00100",
sseg3 when "01000",
sseg_clk when "10000",
(others => '0') when others ;
an <= an_r ;
-- --CONVERT THE LEDS TO THE 4X SEVEN SEGMENTS LED segements
with led(1 downto 0) select
sseg0 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(3 downto 2) select
sseg1 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(5 downto 4) select
sseg2 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(7 downto 6) select
sseg3 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
end Behavioral;
|
package interfaces is
type text is file of string;
component comp1 is
port (
signal p1 : integer; -- OK
p2 : integer -- OK
);
end component;
component comp2 is
port (variable p : integer); -- Error
end component;
component comp3 is
port (constant p : integer); -- Error
end component;
component comp4 is
port (file p : text); -- Error
end component;
component comp5 is
generic (constant p1 : integer; -- OK
p2 : integer);-- OK
end component;
component comp6 is
generic (signal p : integer); -- Error
end component;
component comp7 is
generic (variable p : integer); -- Error
end component;
component comp8 is
generic (file p : text); -- Error
end component;
procedure proc1(c : buffer integer); -- Error
procedure proc2(c : linkage integer); -- Error
procedure proc3(constant c : inout integer); -- Error
procedure proc3a(constant c : out integer); -- Error
procedure proc4(file c : integer); -- Error
procedure proc5(constant c : text); -- Error
end package interfaces;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
entity sim_channel_tb is
generic (
log_file: string := "res.log"
);
end sim_channel_tb;
architecture sim_channel_tb_arch of sim_channel_tb is
component channel_tb is
port ( clk_50mhz: in std_logic;
btn_south: in std_logic;
btn_north: in std_logic;
sw: in std_logic_vector(3 downto 0);
aud_l: out std_logic;
aud_r: out std_logic;
aux_aud_l: out std_logic;
aux_aud_r: out std_logic;
output: out std_logic_vector(7 downto 0)
);
end component;
signal clk : std_logic := '0';
constant clk_half_period : time := 10 ns;
signal btn_south : std_logic := '1';
signal btn_north : std_logic := '0';
signal sw : std_logic_vector(3 downto 0) := "0100";
signal aud_l : std_logic;
signal aud_r : std_logic;
signal aux_aud_l : std_logic;
signal aux_aud_r : std_logic;
signal output : std_logic_vector(7 downto 0);
file l_file: TEXT open write_mode is log_file;
begin
channel_tb0: channel_tb port map (
clk_50mhz => clk,
btn_south => btn_south,
btn_north => btn_north,
sw => sw,
aud_l => aud_l,
aud_r => aud_r,
aux_aud_l => aux_aud_l,
aux_aud_r => aux_aud_r,
output => output
);
clk <= not clk after clk_half_period;
my_process : process
begin
wait for 1us;
btn_south <= '0';
wait for 2us;
btn_north <= '1';
while true loop
wait until clk = '1';
end loop;
end process;
-- write data and control information to a file
write_data: process
variable my_line : line;
variable my_counter : integer := 0;
begin
wait until btn_north='1';
while true loop
if (my_counter mod (50000000 / 44100) = 0) then
write(my_line, to_integer(unsigned(output)));
writeline(l_file, my_line);
end if;
my_counter := my_counter + 1;
wait until clk = '1';
end loop;
end process;
end sim_channel_tb_arch; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:22:43 02/25/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/GitHub/fpga-bits/mandelbrot_monochromatic/tb_top.vhd
-- Project Name: mandelbrot_monochromatic
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mandel_mono
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mandel_mono
PORT(
CLK : IN std_logic;
SW : IN std_logic_vector(7 downto 0);
DIR_UP : IN std_logic;
DIR_DOWN : IN std_logic;
DIR_LEFT : IN std_logic;
DIR_RIGHT : IN std_logic;
VGA_RED : OUT std_logic_vector(3 downto 0);
VGA_GREEN : OUT std_logic_vector(3 downto 0);
VGA_BLUE : OUT std_logic_vector(3 downto 0);
VGA_VSYNC : OUT std_logic;
VGA_HSYNC : OUT std_logic;
LED : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal SW : std_logic_vector(7 downto 0) := (others => '0');
signal DIR_UP : std_logic := '0';
signal DIR_DOWN : std_logic := '0';
signal DIR_LEFT : std_logic := '0';
signal DIR_RIGHT : std_logic := '0';
--Outputs
signal VGA_RED : std_logic_vector(3 downto 0);
signal VGA_GREEN : std_logic_vector(3 downto 0);
signal VGA_BLUE : std_logic_vector(3 downto 0);
signal VGA_VSYNC : std_logic;
signal VGA_HSYNC : std_logic;
signal LED : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mandel_mono PORT MAP (
CLK => CLK,
SW => SW,
DIR_UP => DIR_UP,
DIR_DOWN => DIR_DOWN,
DIR_LEFT => DIR_LEFT,
DIR_RIGHT => DIR_RIGHT,
VGA_RED => VGA_RED,
VGA_GREEN => VGA_GREEN,
VGA_BLUE => VGA_BLUE,
VGA_VSYNC => VGA_VSYNC,
VGA_HSYNC => VGA_HSYNC,
LED => LED
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01073ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
SUBTYPE A8 IS A (1 TO 8);
SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
ELSE
IF (a=3) THEN
RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
ELSE
RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
END IF;
END IF;
END;
END c06s04b00x00p03n01i01073ent;
ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,0)(1,1,1);
q(2) := func1(0,3)(2,2,2);
q(3) := func1(0,0)(3,3,3);
q(4) := func1(4,4,4); -- Indexed name - function params defaulted
q(5) := func1(5,5,5);
q(6) := func1(6,6,6);
q(7) := func1(3,3,3);
q(8) := func1(1,1,1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***PASSED TEST: c06s04b00x00p03n01i01073"
severity NOTE;
assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01073arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01073ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
SUBTYPE A8 IS A (1 TO 8);
SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
ELSE
IF (a=3) THEN
RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
ELSE
RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
END IF;
END IF;
END;
END c06s04b00x00p03n01i01073ent;
ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,0)(1,1,1);
q(2) := func1(0,3)(2,2,2);
q(3) := func1(0,0)(3,3,3);
q(4) := func1(4,4,4); -- Indexed name - function params defaulted
q(5) := func1(5,5,5);
q(6) := func1(6,6,6);
q(7) := func1(3,3,3);
q(8) := func1(1,1,1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***PASSED TEST: c06s04b00x00p03n01i01073"
severity NOTE;
assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01073arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01073ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
SUBTYPE A8 IS A (1 TO 8);
SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
ELSE
IF (a=3) THEN
RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
ELSE
RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
END IF;
END IF;
END;
END c06s04b00x00p03n01i01073ent;
ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,0)(1,1,1);
q(2) := func1(0,3)(2,2,2);
q(3) := func1(0,0)(3,3,3);
q(4) := func1(4,4,4); -- Indexed name - function params defaulted
q(5) := func1(5,5,5);
q(6) := func1(6,6,6);
q(7) := func1(3,3,3);
q(8) := func1(1,1,1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***PASSED TEST: c06s04b00x00p03n01i01073"
severity NOTE;
assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01073arch;
|
--Libraries imports
library ieee;
use ieee.std_logic_1164.all;
--Entity declaration
ENTITY subNbits IS
GENERIC(
N : IN NATURAL := 16
);
PORT(
A, B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Cin : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Cout : OUT STD_LOGIC
);
END;
--Architecture behavior
ARCHITECTURE behavior OF subNbits IS
COMPONENT minNbits IS
GENERIC(
N : IN NATURAL := 16
);
PORT(
A : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT faG IS
GENERIC(
N : IN NATURAL := 16
);
PORT(
A, B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Cin : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Cout : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL tempB : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL tempCo : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
min : minNbits GENERIC MAP (N) PORT MAP (B, tempB);
add : faG GENERIC MAP (N) PORT MAP (A, tempB, Cin, S, Cout);
END; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes;
architecture xilinx of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes;
architecture xilinx of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes;
architecture xilinx of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:StackPointer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_StackPointer_0_0 IS
PORT (
DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RST : IN STD_LOGIC;
LD : IN STD_LOGIC;
INCR : IN STD_LOGIC;
DECR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_StackPointer_0_0;
ARCHITECTURE RAT_StackPointer_0_0_arch OF RAT_StackPointer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT StackPointer IS
PORT (
DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RST : IN STD_LOGIC;
LD : IN STD_LOGIC;
INCR : IN STD_LOGIC;
DECR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT StackPointer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : StackPointer
PORT MAP (
DATA => DATA,
RST => RST,
LD => LD,
INCR => INCR,
DECR => DECR,
CLK => CLK,
DOUT => DOUT
);
END RAT_StackPointer_0_0_arch;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter_oe0.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter_oe0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
updown : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_counter_oe0;
ARCHITECTURE SYN OF lpm_counter_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
updown : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UNUSED",
lpm_port_updown => "PORT_USED",
lpm_type => "LPM_COUNTER",
lpm_width => 32
)
PORT MAP (
aclr => aclr,
clock => clock,
updown => updown,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "2"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_USED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: updown 0 0 0 0 INPUT NODEFVAL updown
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-- Retrieval info: CONNECT: @updown 0 0 0 0 updown 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
--
-- VHDL Architecture width_depth.width_depth.rtl
--
-- Created:
-- by - Ray.UNKNOWN (WRITINGMACHINE)
-- at - 07:46:00 05/ 4/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY width_depth IS
END ENTITY width_depth;
--
ARCHITECTURE rtl OF width_depth IS
signal halfbyte : std_logic_vector( 3 downto 0 ) ;
type reversebits_mem_type is array (7 downto 0) of std_logic_vector(1 to 8);
signal reversebits_mem: reversebits_mem_type;
BEGIN
END ARCHITECTURE rtl;
|
---------------------------------------------------------------------------------------------------
--
-- Title : Control Bus Master
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : CMaster.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Control bus master
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
use work.contr_config.all;
entity CMaster is
generic(
Bwidth : natural := 16;
POS : natural := 0;
MyBusID : natural := 0
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- send to bus
tx: out std_logic_vector(Bwidth-1 downto 0);
Req : out std_logic;
tx_sop : in std_logic;
en : in std_logic;
-- read from bus
rx_sop : in std_logic;
rx: in std_logic_vector(Bwidth-1 downto 0);
-- Local Bus
CS : in std_logic;
addr : in std_logic_vector(3 downto 0);
Din : in STD_LOGIC_VECTOR(7 downto 0);
Dout : out STD_LOGIC_VECTOR(7 downto 0);
cpuClk : in std_logic;
wr : in std_logic;
rd : in std_logic
--
);
end CMaster;
architecture behave of CMaster is
signal addr_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
signal word3_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
signal cs_wr : std_logic := '0';
signal inCommand : std_logic_vector( command_end downto command_start ) := (others => '0');
signal inDBUSID : std_logic_vector( dbusid_end downto dbusid_start ) := (others => '0');
signal inAddr : std_logic_vector( daddr_end downto daddr_start ) := (others => '0');
signal inTag, returnTag, rdTag : std_logic_vector( len_length-1 downto 0 ) := ( others=>'0' );
signal TagState : std_logic_vector( 2**len_length-1 downto 0 ) := ( others=>'0' );
signal req_cpu : std_logic := '0';
signal tstate,rstate : natural := 0;
signal busy_i : std_logic := '0';
signal tagen : std_logic := '0';
signal TagData : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
component AAI
generic(
width : natural := 32;
Baddr : std_logic_vector( 3 downto 0 ) := "0000"
);
port(
-- system signal
rst : in STD_LOGIC;
-- CPU bus
CS : in std_logic;
addr : in std_logic_vector( 3 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
Q : out std_logic_vector( width-1 downto 0 )
);
end component;
component blockdram
generic(
depth: integer := 256;
Dwidth: integer := 8;
Awidth: integer := 8
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
reb: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
begin
cs_wr <= cs and wr;
ADDR_AAI:AAI
generic map(
width => Bwidth,
Baddr => reg_Control_ADDR
)
port map(
rst => rst,
CS => cs_wr,
addr => addr,
Din => Din,
cpuClk => cpuClk,
Q => addr_cpu
);
DATA_AAI:AAI
generic map(
width => Bwidth,
Baddr => reg_Control_DATA
)
port map(
rst => rst,
CS => cs_wr,
addr => addr,
Din => Din,
cpuClk => cpuClk,
Q => word3_cpu
);
tagmem:blockdram
generic map(
depth => 2**len_length,
Dwidth => Bwidth,
Awidth => len_length
)
port map(
addra => returnTag,
clka => clk,
addrb => rdTag,
clkb => clk,
dia => rx,
wea => tagen,
reb => '1',
dob => TagData
);
cpuwriteP:process( cpuClk, rst, tstate )
begin
if rst='1' then
inAddr<=( others=>'0' );
inDBUSID<=( others=>'0' );
inCommand<=( others=>'0' );
inTag<=( others=>'0' );
rdTag<=( others=>'0' );
elsif rising_edge(cpuClk) then
if cs_wr='1' then
case addr is
when reg_Control_BADDR =>
inAddr<=Din( addr_length-1 downto 0 );
when reg_Control_BID =>
inDBUSID<=Din( busid_length-1 downto 0 );
when reg_Control_Tag =>
inTag<=Din( len_length-1 downto 0 );
when reg_Control_rdTag =>
rdTag<=Din( len_length-1 downto 0 );
when reg_Control_Command =>
inCommand<=Din( command_length-1 downto 0 );
when others =>
null;
end case;
end if;
end if;
if tstate=state_loading then
req_cpu<='0';
elsif rising_edge(cpuClk) then
if cs_wr='1' and addr=reg_Control_START then
req_cpu<='1';
end if;
end if;
end process;
TagStateP:process(clk,rst)
begin
if rst='1' then
TagState<=( others=>'0' );
elsif rising_edge(clk) then
if tstate=state_ADDR and inCommand=command_read then
TagState(conv_integer(inTag))<='1';
end if;
if tagen='1' then
TagState(conv_integer(returnTag))<='0';
end if;
end if;
end process;
FSMT:process(clk,rst)
begin
if rst='1' then
tstate<=state_IDLE;
req<='0';
busy_i<='0';
tx <= zeros( Bwidth-1 downto 0 );
elsif rising_edge(clk) then
case tstate is
when state_IDLE =>
if req_cpu='1' then
tstate<=state_LOADING;
busy_i<='1';
else
busy_i<='0';
end if;
req<='0';
when state_LOADING =>
tx( command_end downto command_start )<=inCommand;
tx( dbusid_end downto dbusid_start )<=inDBUSID;
tx( daddr_end downto daddr_start )<=inAddr;
tx( len_end downto len_start ) <= zeros(len_end downto len_start)+2;
req<='1';
tstate<=state_SENDING;
when state_SENDING =>
if en='1' and tx_sop='1' then
tx<=addr_cpu;
tstate<=state_ADDR;
req<='0';
end if;
when state_ADDR =>
if inCommand=command_write then
tx<=word3_cpu;
else
tx( command_end downto command_start )<=command_complete;
tx( dbusid_end downto dbusid_start )<=zeros( dbusid_end downto dbusid_start )+MyBusID;
tx( daddr_end downto daddr_start )<=zeros( daddr_end downto daddr_start )+POS;
tx( len_end downto len_start )<=inTag;
end if;
tstate<=state_IDLE;
busy_i<='0';
when others =>
req<='0';
tstate<=state_IDLE;
end case;
end if;
end process;
FSMR:process(clk,rst)
begin
if rst='1' then
rstate<=state_IDLE;
returnTag<=( others=>'0' );
tagen<='0';
elsif rising_edge(clk) then
case rstate is
when state_IDLE =>
if rx_sop='1' and rx( command_end downto command_start )=command_complete then
rstate<=state_ADDR;
tagen<='0';
end if;
tagen<='0';
when state_ADDR =>
returnTag<=rx( len_end downto len_start );
tagen<='1';
rstate<=state_IDLE;
when others =>
rstate<=state_IDLE;
end case;
end if;
end process;
rdP:process(rd,addr,cs,rdTag)
begin
if rd='1' and cs='1' then
case addr is
when reg_Control_Busy =>
Dout(0)<=busy_i;
Dout( 7 downto 1 )<=(others=>'Z');
when reg_Control_TagState =>
Dout(0)<=TagState(conv_integer(rdTag));
Dout( 7 downto 1 )<=(others=>'Z');
when reg_Control_TagData =>
Dout<=TagData( 7 downto 0 );
when others =>
Dout<=(others=>'Z');
end case;
end if;
end process;
end behave;
|
---------------------------------------------------------------------------------------------------
--
-- Title : Control Bus Master
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : CMaster.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Control bus master
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
use work.contr_config.all;
entity CMaster is
generic(
Bwidth : natural := 16;
POS : natural := 0;
MyBusID : natural := 0
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- send to bus
tx: out std_logic_vector(Bwidth-1 downto 0);
Req : out std_logic;
tx_sop : in std_logic;
en : in std_logic;
-- read from bus
rx_sop : in std_logic;
rx: in std_logic_vector(Bwidth-1 downto 0);
-- Local Bus
CS : in std_logic;
addr : in std_logic_vector(3 downto 0);
Din : in STD_LOGIC_VECTOR(7 downto 0);
Dout : out STD_LOGIC_VECTOR(7 downto 0);
cpuClk : in std_logic;
wr : in std_logic;
rd : in std_logic
--
);
end CMaster;
architecture behave of CMaster is
signal addr_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
signal word3_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
signal cs_wr : std_logic := '0';
signal inCommand : std_logic_vector( command_end downto command_start ) := (others => '0');
signal inDBUSID : std_logic_vector( dbusid_end downto dbusid_start ) := (others => '0');
signal inAddr : std_logic_vector( daddr_end downto daddr_start ) := (others => '0');
signal inTag, returnTag, rdTag : std_logic_vector( len_length-1 downto 0 ) := ( others=>'0' );
signal TagState : std_logic_vector( 2**len_length-1 downto 0 ) := ( others=>'0' );
signal req_cpu : std_logic := '0';
signal tstate,rstate : natural := 0;
signal busy_i : std_logic := '0';
signal tagen : std_logic := '0';
signal TagData : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
component AAI
generic(
width : natural := 32;
Baddr : std_logic_vector( 3 downto 0 ) := "0000"
);
port(
-- system signal
rst : in STD_LOGIC;
-- CPU bus
CS : in std_logic;
addr : in std_logic_vector( 3 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
Q : out std_logic_vector( width-1 downto 0 )
);
end component;
component blockdram
generic(
depth: integer := 256;
Dwidth: integer := 8;
Awidth: integer := 8
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
reb: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
begin
cs_wr <= cs and wr;
ADDR_AAI:AAI
generic map(
width => Bwidth,
Baddr => reg_Control_ADDR
)
port map(
rst => rst,
CS => cs_wr,
addr => addr,
Din => Din,
cpuClk => cpuClk,
Q => addr_cpu
);
DATA_AAI:AAI
generic map(
width => Bwidth,
Baddr => reg_Control_DATA
)
port map(
rst => rst,
CS => cs_wr,
addr => addr,
Din => Din,
cpuClk => cpuClk,
Q => word3_cpu
);
tagmem:blockdram
generic map(
depth => 2**len_length,
Dwidth => Bwidth,
Awidth => len_length
)
port map(
addra => returnTag,
clka => clk,
addrb => rdTag,
clkb => clk,
dia => rx,
wea => tagen,
reb => '1',
dob => TagData
);
cpuwriteP:process( cpuClk, rst, tstate )
begin
if rst='1' then
inAddr<=( others=>'0' );
inDBUSID<=( others=>'0' );
inCommand<=( others=>'0' );
inTag<=( others=>'0' );
rdTag<=( others=>'0' );
elsif rising_edge(cpuClk) then
if cs_wr='1' then
case addr is
when reg_Control_BADDR =>
inAddr<=Din( addr_length-1 downto 0 );
when reg_Control_BID =>
inDBUSID<=Din( busid_length-1 downto 0 );
when reg_Control_Tag =>
inTag<=Din( len_length-1 downto 0 );
when reg_Control_rdTag =>
rdTag<=Din( len_length-1 downto 0 );
when reg_Control_Command =>
inCommand<=Din( command_length-1 downto 0 );
when others =>
null;
end case;
end if;
end if;
if tstate=state_loading then
req_cpu<='0';
elsif rising_edge(cpuClk) then
if cs_wr='1' and addr=reg_Control_START then
req_cpu<='1';
end if;
end if;
end process;
TagStateP:process(clk,rst)
begin
if rst='1' then
TagState<=( others=>'0' );
elsif rising_edge(clk) then
if tstate=state_ADDR and inCommand=command_read then
TagState(conv_integer(inTag))<='1';
end if;
if tagen='1' then
TagState(conv_integer(returnTag))<='0';
end if;
end if;
end process;
FSMT:process(clk,rst)
begin
if rst='1' then
tstate<=state_IDLE;
req<='0';
busy_i<='0';
tx <= zeros( Bwidth-1 downto 0 );
elsif rising_edge(clk) then
case tstate is
when state_IDLE =>
if req_cpu='1' then
tstate<=state_LOADING;
busy_i<='1';
else
busy_i<='0';
end if;
req<='0';
when state_LOADING =>
tx( command_end downto command_start )<=inCommand;
tx( dbusid_end downto dbusid_start )<=inDBUSID;
tx( daddr_end downto daddr_start )<=inAddr;
tx( len_end downto len_start ) <= zeros(len_end downto len_start)+2;
req<='1';
tstate<=state_SENDING;
when state_SENDING =>
if en='1' and tx_sop='1' then
tx<=addr_cpu;
tstate<=state_ADDR;
req<='0';
end if;
when state_ADDR =>
if inCommand=command_write then
tx<=word3_cpu;
else
tx( command_end downto command_start )<=command_complete;
tx( dbusid_end downto dbusid_start )<=zeros( dbusid_end downto dbusid_start )+MyBusID;
tx( daddr_end downto daddr_start )<=zeros( daddr_end downto daddr_start )+POS;
tx( len_end downto len_start )<=inTag;
end if;
tstate<=state_IDLE;
busy_i<='0';
when others =>
req<='0';
tstate<=state_IDLE;
end case;
end if;
end process;
FSMR:process(clk,rst)
begin
if rst='1' then
rstate<=state_IDLE;
returnTag<=( others=>'0' );
tagen<='0';
elsif rising_edge(clk) then
case rstate is
when state_IDLE =>
if rx_sop='1' and rx( command_end downto command_start )=command_complete then
rstate<=state_ADDR;
tagen<='0';
end if;
tagen<='0';
when state_ADDR =>
returnTag<=rx( len_end downto len_start );
tagen<='1';
rstate<=state_IDLE;
when others =>
rstate<=state_IDLE;
end case;
end if;
end process;
rdP:process(rd,addr,cs,rdTag)
begin
if rd='1' and cs='1' then
case addr is
when reg_Control_Busy =>
Dout(0)<=busy_i;
Dout( 7 downto 1 )<=(others=>'Z');
when reg_Control_TagState =>
Dout(0)<=TagState(conv_integer(rdTag));
Dout( 7 downto 1 )<=(others=>'Z');
when reg_Control_TagData =>
Dout<=TagData( 7 downto 0 );
when others =>
Dout<=(others=>'Z');
end case;
end if;
end process;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1987.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01987ent IS
END c07s02b02x00p02n01i01987ent;
ARCHITECTURE c07s02b02x00p02n01i01987arch OF c07s02b02x00p02n01i01987ent IS
BEGIN
TESTING: PROCESS
variable r1, r2, r3, r4 : real;
BEGIN
r1 := 69.0;
r2 := 50.0;
r3 := (-69.0);
r4 := (-50.0);
assert NOT( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***PASSED TEST: c07s02b02x00p02n01i01987"
severity NOTE;
assert ( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***FAILED TEST: c07s02b02x00p02n01i01987 - Relational operators truth table test for data type of Real failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01987arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1987.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01987ent IS
END c07s02b02x00p02n01i01987ent;
ARCHITECTURE c07s02b02x00p02n01i01987arch OF c07s02b02x00p02n01i01987ent IS
BEGIN
TESTING: PROCESS
variable r1, r2, r3, r4 : real;
BEGIN
r1 := 69.0;
r2 := 50.0;
r3 := (-69.0);
r4 := (-50.0);
assert NOT( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***PASSED TEST: c07s02b02x00p02n01i01987"
severity NOTE;
assert ( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***FAILED TEST: c07s02b02x00p02n01i01987 - Relational operators truth table test for data type of Real failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01987arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1987.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01987ent IS
END c07s02b02x00p02n01i01987ent;
ARCHITECTURE c07s02b02x00p02n01i01987arch OF c07s02b02x00p02n01i01987ent IS
BEGIN
TESTING: PROCESS
variable r1, r2, r3, r4 : real;
BEGIN
r1 := 69.0;
r2 := 50.0;
r3 := (-69.0);
r4 := (-50.0);
assert NOT( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***PASSED TEST: c07s02b02x00p02n01i01987"
severity NOTE;
assert ( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***FAILED TEST: c07s02b02x00p02n01i01987 - Relational operators truth table test for data type of Real failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01987arch;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00241
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00241)
-- ENT00241_Test_Bench(ARCH00241_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00241 of GENERIC_STANDARD_TYPES is
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
begin
L1:
block
port (
i_boolean_1, i_boolean_2 : linkage boolean
;
i_bit_1, i_bit_2 : linkage bit
;
i_severity_level_1, i_severity_level_2 : linkage severity_level
;
i_character_1, i_character_2 : linkage character
;
i_t_enum1_1, i_t_enum1_2 : linkage t_enum1
;
i_st_enum1_1, i_st_enum1_2 : linkage st_enum1
;
i_integer_1, i_integer_2 : linkage integer
;
i_t_int1_1, i_t_int1_2 : linkage t_int1
;
i_st_int1_1, i_st_int1_2 : linkage st_int1
;
i_time_1, i_time_2 : linkage time
;
i_t_phys1_1, i_t_phys1_2 : linkage t_phys1
;
i_st_phys1_1, i_st_phys1_2 : linkage st_phys1
;
i_real_1, i_real_2 : linkage real
;
i_t_real1_1, i_t_real1_2 : linkage t_real1
;
i_st_real1_1, i_st_real1_2 : linkage st_real1
) ;
port map (
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00241" ,
"Associated scalar linkage ports with generic subtypes" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00241 ;
--
entity ENT00241_Test_Bench is
end ENT00241_Test_Bench ;
--
architecture ARCH00241_Test_Bench of ENT00241_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00241 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00241_Test_Bench ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag_bsd is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end;
architecture struct of ahbjtag_bsd is
constant REVISION : integer := 0;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
jtagcom0 : jtagcom generic map (isel => 1, nsync => nsync, ainst => ainst, dinst => dinst)
port map (rst, clk, ltapo, ltapi, dmao, dmai);
ltapo.asel <= asel;
ltapo.dsel <= dsel;
ltapo.tck <= tck;
ltapo.tdi <= regi;
ltapo.shift <= shift;
ltapo.reset <= '0';
ltapo.inst <= (others => '0');
rego <= ltapi.tdo;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag_bsd is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end;
architecture struct of ahbjtag_bsd is
constant REVISION : integer := 0;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
jtagcom0 : jtagcom generic map (isel => 1, nsync => nsync, ainst => ainst, dinst => dinst)
port map (rst, clk, ltapo, ltapi, dmao, dmai);
ltapo.asel <= asel;
ltapo.dsel <= dsel;
ltapo.tck <= tck;
ltapo.tdi <= regi;
ltapo.shift <= shift;
ltapo.reset <= '0';
ltapo.inst <= (others => '0');
rego <= ltapi.tdo;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_a
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-struct-conf-c.vhd,v 1.1 2005/11/02 12:53:46 wig Exp $
-- $Date: 2005/11/02 12:53:46 $
-- $Log: ent_a-struct-conf-c.vhd,v $
-- Revision 1.1 2005/11/02 12:53:46 wig
-- fixed issue 20051018d and more
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.66 2005/10/24 15:43:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.38 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_a_struct_conf / ent_a
--
configuration ent_a_struct_conf of ent_a is
for struct
-- Generated Configuration
for inst_aa : ent_aa
use configuration work.ent_aa_struct_conf;
end for;
for inst_ab : ent_ab
use configuration work.ent_ab_struct_conf;
end for;
end for;
end ent_a_struct_conf;
--
-- End of Generated Configuration ent_a_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity dff06 is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
rst : std_logic);
end dff06;
architecture behav of dff06 is
signal p : std_logic_vector(7 downto 0);
begin
process (clk, rst) is
begin
if rst = '1' then
p <= x"00";
elsif rising_edge (clk) then
q <= d;
end if;
end process;
end behav;
|
entity wait7 is
end entity;
architecture test of wait7 is
signal state : integer := 0;
signal x : integer := 0;
begin
wakeup: process is
begin
wait until x = 1;
state <= 1;
wait until x = 5;
state <= 2;
wait until x > 10;
state <= 3;
wait;
end process;
stim: process is
begin
x <= -1;
wait for 1 ns;
assert state = 0;
x <= 6;
wait for 1 ns;
assert state = 0;
x <= 1;
wait for 1 ns;
assert state = 1;
x <= 0;
wait for 1 ns;
assert state = 1;
x <= 5;
wait for 1 ns;
assert state = 2;
x <= 50;
wait for 1 ns;
assert state = 3;
wait;
end process;
end architecture;
|
entity wait7 is
end entity;
architecture test of wait7 is
signal state : integer := 0;
signal x : integer := 0;
begin
wakeup: process is
begin
wait until x = 1;
state <= 1;
wait until x = 5;
state <= 2;
wait until x > 10;
state <= 3;
wait;
end process;
stim: process is
begin
x <= -1;
wait for 1 ns;
assert state = 0;
x <= 6;
wait for 1 ns;
assert state = 0;
x <= 1;
wait for 1 ns;
assert state = 1;
x <= 0;
wait for 1 ns;
assert state = 1;
x <= 5;
wait for 1 ns;
assert state = 2;
x <= 50;
wait for 1 ns;
assert state = 3;
wait;
end process;
end architecture;
|
entity wait7 is
end entity;
architecture test of wait7 is
signal state : integer := 0;
signal x : integer := 0;
begin
wakeup: process is
begin
wait until x = 1;
state <= 1;
wait until x = 5;
state <= 2;
wait until x > 10;
state <= 3;
wait;
end process;
stim: process is
begin
x <= -1;
wait for 1 ns;
assert state = 0;
x <= 6;
wait for 1 ns;
assert state = 0;
x <= 1;
wait for 1 ns;
assert state = 1;
x <= 0;
wait for 1 ns;
assert state = 1;
x <= 5;
wait for 1 ns;
assert state = 2;
x <= 50;
wait for 1 ns;
assert state = 3;
wait;
end process;
end architecture;
|
entity wait7 is
end entity;
architecture test of wait7 is
signal state : integer := 0;
signal x : integer := 0;
begin
wakeup: process is
begin
wait until x = 1;
state <= 1;
wait until x = 5;
state <= 2;
wait until x > 10;
state <= 3;
wait;
end process;
stim: process is
begin
x <= -1;
wait for 1 ns;
assert state = 0;
x <= 6;
wait for 1 ns;
assert state = 0;
x <= 1;
wait for 1 ns;
assert state = 1;
x <= 0;
wait for 1 ns;
assert state = 1;
x <= 5;
wait for 1 ns;
assert state = 2;
x <= 50;
wait for 1 ns;
assert state = 3;
wait;
end process;
end architecture;
|
entity wait7 is
end entity;
architecture test of wait7 is
signal state : integer := 0;
signal x : integer := 0;
begin
wakeup: process is
begin
wait until x = 1;
state <= 1;
wait until x = 5;
state <= 2;
wait until x > 10;
state <= 3;
wait;
end process;
stim: process is
begin
x <= -1;
wait for 1 ns;
assert state = 0;
x <= 6;
wait for 1 ns;
assert state = 0;
x <= 1;
wait for 1 ns;
assert state = 1;
x <= 0;
wait for 1 ns;
assert state = 1;
x <= 5;
wait for 1 ns;
assert state = 2;
x <= 50;
wait for 1 ns;
assert state = 3;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
---
--- Gigabit Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A gigabit ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 1Gbit/s ethernet only via a gmii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component used two clocks, the local clock used to transfer data
---between components, and a 125MHz clock source for sending data to the
---Ethernet physical interface. This clock is also forwarded along with the
---data to the ethernet phy.
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity gigabit_ethernet;
architecture RTL of gigabit_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 511) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE_0, PREAMBLE_1,
PREAMBLE_2, PREAMBLE_3, PREAMBLE_4, PREAMBLE_5, PREAMBLE_6, SFD,
SEND_DATA_HI, SEND_DATA_LO, SEND_CRC_3, SEND_CRC_2, SEND_CRC_1,
SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE, DATA_HIGH, DATA_LOW,
END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET,
SEND_DATA, PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1513;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1513;
signal TX_READ_ADDRESS : integer range 0 to 1513;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1513;
signal TX_OUT_COUNT : integer range 0 to 1513;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(7 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK_125_MHZ);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the local clock domain
LOCAL_TO_CLK_125 : process
begin
wait until rising_edge(CLK_125_MHZ);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
CLK_125_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
begin
wait until rising_edge(CLK_125_MHZ);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE_0;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
end if;
when PREAMBLE_0 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_1;
TXEN <= '1';
when PREAMBLE_1 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_2;
when PREAMBLE_2 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_3;
when PREAMBLE_3 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_4;
when PREAMBLE_4 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_5;
when PREAMBLE_5 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_6;
when PREAMBLE_6 =>
TXD <= X"55";
TX_PHY_STATE <= SFD;
when SFD =>
TXD <= X"D5";
TX_PHY_STATE <= SEND_DATA_HI;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_HI =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 8);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_3;
else
TX_PHY_STATE <= SEND_DATA_LO;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_LO =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 0);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_3;
else
TX_PHY_STATE <= SEND_DATA_HI;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_3 =>
TXD <= not REVERSED(TX_CRC(31 downto 24));
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
TXD <= not REVERSED(TX_CRC(23 downto 16));
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
TXD <= not REVERSED(TX_CRC(15 downto 8));
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
TXD <= not REVERSED(TX_CRC(7 downto 0));
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
GTXCLK <= CLK_125_MHZ;
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(RXCLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = X"55" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = X"d5" then
RX_PHY_STATE <= DATA_HIGH;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= X"55" or RXDV_D = '0' then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_HIGH =>
RX_WRITE_DATA(15 downto 8) <= RXD_D;
if RXDV_D = '1' then
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_LOW;
RX_CRC <= nextCRC32_D8(RXD_D, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_LOW =>
RX_WRITE_DATA(7 downto 0) <= RXD_D;
RX_WRITE_ENABLE <= '1';
if RXDV_D = '1' then
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_HIGH;
RX_CRC <= nextCRC32_D8(RXD_D, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(RXCLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(RXCLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := true;
g_read_first_b : boolean := true;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
end entity;
architecture xilinx of dpram is
function string_select(a,b: string; s:boolean) return string is
begin
if s then
return a;
end if;
return b;
end function;
-- Error (14271): Illegal value NEW_DATA for port_a_read_during_write_mode parameter in WYSIWYG primitive "ram_block1a0" -- value must be new_data_no_nbe_read, new_data_with_nbe_read or old_data
constant a_new_data : string := string_select("OLD_DATA", "new_data_with_nbe_read", g_read_first_a);
constant b_new_data : string := string_select("OLD_DATA", "new_data_with_nbe_read", g_read_first_b);
signal wren_a : std_logic;
signal wren_b : std_logic;
begin
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 2 ** g_depth_bits,
numwords_b => 2 ** g_depth_bits,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => g_depth_bits,
widthad_b => g_depth_bits,
width_a => g_width_bits,
width_b => g_width_bits,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => std_logic_vector(a_address),
address_b => std_logic_vector(b_address),
clock0 => a_clock,
clock1 => b_clock,
data_a => a_wdata,
data_b => b_wdata,
rden_a => a_en,
rden_b => b_en,
wren_a => wren_a,
wren_b => wren_b,
q_a => a_rdata,
q_b => b_rdata );
wren_a <= a_we and a_en;
wren_b <= b_we and b_en;
end architecture;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.coregen_comp_defs.all;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
use proc_common_v3_00_a.family_support.all;
-- synopsys translate_off
library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V5_AND_EARLIER
--
-- If Generate Description:
-- This IfGen implements the fifo using FIFO Generator 4.3
-- when the designated FPGA Family is Spartan3, Virtex4, or
-- Virtex5.
--
------------------------------------------------------------
V5_AND_EARLIER: if(FAM_IS_S3_V4_V5) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : fifo_generator_v4_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1
)
port map (
CLK => Clk, -- : IN std_logic := '0';
BACKUP => '0', -- : IN std_logic := '0';
BACKUP_MARKER => '0', -- : IN std_logic := '0';
DIN => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK => '0', -- : IN std_logic := '0';
RD_EN => Rd_en, -- : IN std_logic := '0';
RD_RST => '0', -- : IN std_logic := '0';
RST => '0', -- : IN std_logic := '0';
SRST => Sinit, -- : IN std_logic := '0';
WR_CLK => '0', -- : IN std_logic := '0';
WR_EN => Wr_en, -- : IN std_logic := '0';
WR_RST => '0', -- : IN std_logic := '0';
INT_CLK => '0', -- : IN std_logic := '0';
ALMOST_EMPTY => open, -- : OUT std_logic;
ALMOST_FULL => Almost_full, -- : OUT std_logic;
DATA_COUNT => sig_prim_fg_datacnt, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY => Empty, -- : OUT std_logic;
FULL => sig_full, -- : OUT std_logic;
OVERFLOW => Wr_err, -- : OUT std_logic;
PROG_EMPTY => open, -- : OUT std_logic;
PROG_FULL => open, -- : OUT std_logic;
VALID => Rd_ack, -- : OUT std_logic;
RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW => Rd_err, -- : OUT std_logic;
WR_ACK => Wr_ack, -- : OUT std_logic;
WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR => open, -- : OUT std_logic;
DBITERR => open -- : OUT std_logic
);
end generate V5_AND_EARLIER;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
V6_S6_AND_LATER: if(FAM_IS_NOT_S3_V4_V5) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : fifo_generator_v9_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => Clk,
RST => '0',
SRST => Sinit,
WR_CLK => '0',
WR_RST => '0',
RD_CLK => '0',
RD_RST => '0',
DIN => Din,
WR_EN => Wr_en,
RD_EN => Rd_en,
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0', -- new FG 5.1/5.2
INJECTSBITERR => '0', -- new FG 5.1/5.2
DOUT => Dout,
FULL => sig_full,
ALMOST_FULL => Almost_full,
WR_ACK => Wr_ack,
OVERFLOW => Wr_err,
EMPTY => Empty,
ALMOST_EMPTY => open,
VALID => Rd_ack,
UNDERFLOW => Rd_err,
DATA_COUNT => sig_prim_fg_datacnt,
RD_DATA_COUNT => open,
WR_DATA_COUNT => open,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end implementation;
|
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 20:52:31 01/31/2010
-- Design Name: SPI
-- Module Name: tb_SPIShifter
-- Description: VHDL Test Bench for module: SPIShifter
--
-- Revision:
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_SPIShifter is
end tb_SPIShifter;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_1_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_1_0;
ARCHITECTURE system_inverter_1_0_arch OF system_inverter_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_1_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_1_0_arch : ARCHITECTURE IS "system_inverter_1_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_1_0_arch;
|
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