content stringlengths 1 1.04M ⌀ |
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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_1_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_1_0;
ARCHITECTURE system_inverter_1_0_arch OF system_inverter_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_1_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_1_0_arch : ARCHITECTURE IS "system_inverter_1_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_1_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_1_0;
ARCHITECTURE system_inverter_1_0_arch OF system_inverter_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_1_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_1_0_arch : ARCHITECTURE IS "system_inverter_1_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_1_0_arch;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration computer_structure of computer_system is
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
port map ( s0 => in0, s1 => in1, s2 => '0',
enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
-- . . .
end for;
end configuration computer_structure;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration computer_structure of computer_system is
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
port map ( s0 => in0, s1 => in1, s2 => '0',
enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
-- . . .
end for;
end configuration computer_structure;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration computer_structure of computer_system is
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
port map ( s0 => in0, s1 => in1, s2 => '0',
enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
-- . . .
end for;
end configuration computer_structure;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN8 module
entity EPROC_IN8_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (7 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8_DEC8b10b;
architecture Behavioral of EPROC_IN8_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (47 downto 0) := (others=>'0'); -- 48 bit (8 x 5 = 40, plus 8 more)
signal word10bx4_align_array, word10bx4_align_array_r : word10b_4array_8array_type;
signal word10b_array, word10b_array_s : word10b_4array_type;
signal isk_array : isk_4array_type;
signal comma_valid_bits_or, word10bx4_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1, realignment_ena : std_logic;
signal align_select : std_logic_vector (2 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (7 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 48 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(47 downto 8);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 7 generate -- 4 10bit-words per alignment, 8 possible alignments
--word10bx4_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx4_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(2) <= EDATAbitstreamSREG((I+29) downto (I+20)); -- 3rd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(3) <= EDATAbitstreamSREG((I+39) downto (I+30)); -- 4th 10 bit word, alligned to bit I
word10bx4_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx4_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
word10bx4_align_array(I)(2) <= EDATAbitstreamSREG(I+20)&EDATAbitstreamSREG(I+21)&EDATAbitstreamSREG(I+22)&EDATAbitstreamSREG(I+23)&EDATAbitstreamSREG(I+24)&
EDATAbitstreamSREG(I+25)&EDATAbitstreamSREG(I+26)&EDATAbitstreamSREG(I+27)&EDATAbitstreamSREG(I+28)&EDATAbitstreamSREG(I+29); -- 3rd 10 bit word, alligned to bit I
word10bx4_align_array(I)(3) <= EDATAbitstreamSREG(I+30)&EDATAbitstreamSREG(I+31)&EDATAbitstreamSREG(I+32)&EDATAbitstreamSREG(I+33)&EDATAbitstreamSREG(I+34)&
EDATAbitstreamSREG(I+35)&EDATAbitstreamSREG(I+36)&EDATAbitstreamSREG(I+37)&EDATAbitstreamSREG(I+38)&EDATAbitstreamSREG(I+39); -- 4th 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 7 generate -- 4 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx4_align_array(I)(0) = COMMAp or word10bx4_align_array(I)(0) = COMMAn) and
(word10bx4_align_array(I)(1) = COMMAp or word10bx4_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(7) or comma_valid_bits(6) or comma_valid_bits(5) or comma_valid_bits(4) or
comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx4_align_array_r <= word10bx4_align_array;
end if;
end process;
--
word10bx4_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3) or ( (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (
comma_valid_bits(5) or ( (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (
comma_valid_bits(7)
)))))));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
((comma_valid_bits(2) or comma_valid_bits(3)) or (
(not comma_valid_bits(2)) and (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (not comma_valid_bits(5)) and (
comma_valid_bits(6) or comma_valid_bits(7))));
align_select(2) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (not comma_valid_bits(3)) and
(comma_valid_bits(4) or comma_valid_bits(5) or comma_valid_bits(6) or comma_valid_bits(7));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx4_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "000" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx4_align_array_r(0);
when "001" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx4_align_array_r(1);
when "010" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx4_align_array_r(2);
when "011" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx4_align_array_r(3);
when "100" => -- bit4 word got comma => align to bit4
word10b_array <= word10bx4_align_array_r(4);
when "101" => -- bit5 word got comma => align to bit5
word10b_array <= word10bx4_align_array_r(5);
when "110" => -- bit6 word got comma => align to bit6
word10b_array <= word10bx4_align_array_r(6);
when "111" => -- bit7 word got comma => align to bit7
word10b_array <= word10bx4_align_array_r(7);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 3 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-- if more that 2 commas, will repeat itself next clock
realignment_ena <= '0' when (isk_array(0) = "11" and isk_array(1) = "11" and isk_array(2) = "11") else '1';
word10b_array_rdy_s1 <= word10b_array_rdy_s and realignment_ena;
-------------------------------------------------------------------------------------------
-- 4 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN8_ALIGN_BLOCK_inst: entity work.EPROC_IN8_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN8 module
entity EPROC_IN8_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (7 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8_DEC8b10b;
architecture Behavioral of EPROC_IN8_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (47 downto 0) := (others=>'0'); -- 48 bit (8 x 5 = 40, plus 8 more)
signal word10bx4_align_array, word10bx4_align_array_r : word10b_4array_8array_type;
signal word10b_array, word10b_array_s : word10b_4array_type;
signal isk_array : isk_4array_type;
signal comma_valid_bits_or, word10bx4_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1, realignment_ena : std_logic;
signal align_select : std_logic_vector (2 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (7 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 48 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(47 downto 8);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 7 generate -- 4 10bit-words per alignment, 8 possible alignments
--word10bx4_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx4_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(2) <= EDATAbitstreamSREG((I+29) downto (I+20)); -- 3rd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(3) <= EDATAbitstreamSREG((I+39) downto (I+30)); -- 4th 10 bit word, alligned to bit I
word10bx4_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx4_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
word10bx4_align_array(I)(2) <= EDATAbitstreamSREG(I+20)&EDATAbitstreamSREG(I+21)&EDATAbitstreamSREG(I+22)&EDATAbitstreamSREG(I+23)&EDATAbitstreamSREG(I+24)&
EDATAbitstreamSREG(I+25)&EDATAbitstreamSREG(I+26)&EDATAbitstreamSREG(I+27)&EDATAbitstreamSREG(I+28)&EDATAbitstreamSREG(I+29); -- 3rd 10 bit word, alligned to bit I
word10bx4_align_array(I)(3) <= EDATAbitstreamSREG(I+30)&EDATAbitstreamSREG(I+31)&EDATAbitstreamSREG(I+32)&EDATAbitstreamSREG(I+33)&EDATAbitstreamSREG(I+34)&
EDATAbitstreamSREG(I+35)&EDATAbitstreamSREG(I+36)&EDATAbitstreamSREG(I+37)&EDATAbitstreamSREG(I+38)&EDATAbitstreamSREG(I+39); -- 4th 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 7 generate -- 4 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx4_align_array(I)(0) = COMMAp or word10bx4_align_array(I)(0) = COMMAn) and
(word10bx4_align_array(I)(1) = COMMAp or word10bx4_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(7) or comma_valid_bits(6) or comma_valid_bits(5) or comma_valid_bits(4) or
comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx4_align_array_r <= word10bx4_align_array;
end if;
end process;
--
word10bx4_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3) or ( (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (
comma_valid_bits(5) or ( (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (
comma_valid_bits(7)
)))))));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
((comma_valid_bits(2) or comma_valid_bits(3)) or (
(not comma_valid_bits(2)) and (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (not comma_valid_bits(5)) and (
comma_valid_bits(6) or comma_valid_bits(7))));
align_select(2) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (not comma_valid_bits(3)) and
(comma_valid_bits(4) or comma_valid_bits(5) or comma_valid_bits(6) or comma_valid_bits(7));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx4_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "000" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx4_align_array_r(0);
when "001" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx4_align_array_r(1);
when "010" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx4_align_array_r(2);
when "011" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx4_align_array_r(3);
when "100" => -- bit4 word got comma => align to bit4
word10b_array <= word10bx4_align_array_r(4);
when "101" => -- bit5 word got comma => align to bit5
word10b_array <= word10bx4_align_array_r(5);
when "110" => -- bit6 word got comma => align to bit6
word10b_array <= word10bx4_align_array_r(6);
when "111" => -- bit7 word got comma => align to bit7
word10b_array <= word10bx4_align_array_r(7);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 3 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-- if more that 2 commas, will repeat itself next clock
realignment_ena <= '0' when (isk_array(0) = "11" and isk_array(1) = "11" and isk_array(2) = "11") else '1';
word10b_array_rdy_s1 <= word10b_array_rdy_s and realignment_ena;
-------------------------------------------------------------------------------------------
-- 4 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN8_ALIGN_BLOCK_inst: entity work.EPROC_IN8_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_nov;
architecture behaviour of train4_nov is
constant st0: std_logic_vector(1 downto 0) := "00";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cordic_tb is
end entity;
architecture cordic_tb_arq of cordic_tb is
signal x_in: std_logic_vector(31 downto 0) := (others => '0');
signal y_in: std_logic_vector(31 downto 0) := (others => '0');
signal angle : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
component cordic is
generic(TOTAL_BITS: integer := 32; STEPS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for cordic_0 : cordic use entity work.cordic;
begin
cordic_0 : cordic
port map(
x_in => x_in,
y_in => y_in,
angle => angle,
x_out => x_out,
y_out => y_out
);
process
type pattern_type is record
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
a : std_logic_vector(31 downto 0);
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000001011010000000000000000",
"00000000000000000000000000000000",
"00000000000000010110101000001010"),
("00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000010110100000000000000000",
"11111111111111110000000000000001",
"00000000000000001111111111111100")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
angle <= patterns(i).a;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, EXPECTED: " & integer'image(to_integer(signed(patterns(i).xo))) & " GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- mi32_async_arch.vhd: Envelope for mi_32_async_arch_norec.vhd using t_mi32
-- inout record
-- Copyright (C) 2008 CESNET
-- Author(s): Jiri Matousek <xmatou06@stud.fit.vutbr.cz>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi32_async_arch.vhd 6110 2008-10-26 22:48:24Z xmatou06 $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- library with MI_32 interface definition
use work.lb_pkg.all;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture full of MI32_ASYNC is
begin
-- -------------------------------------------------------------------------
-- Instantiation of mi32_async_norec
-- -------------------------------------------------------------------------
mi32_async_norec_i: entity work.MI32_ASYNC_NOREC
port map(
RESET => RESET,
-- Master interface
CLK_M => CLK_M,
MI_M_DWR => MI_M.DWR, -- Input Data
MI_M_ADDR => MI_M.ADDR, -- Address
MI_M_RD => MI_M.RD, -- Read Request
MI_M_WR => MI_M.WR, -- Write Request
MI_M_BE => MI_M.BE, -- Byte Enable
MI_M_DRD => MI_M.DRD, -- Output Data
MI_M_ARDY => MI_M.ARDY, -- Address Ready
MI_M_DRDY => MI_M.DRDY, -- Data Ready
-- Slave interface
CLK_S => CLK_S,
MI_S_DWR => MI_S.DWR, -- Input Data
MI_S_ADDR => MI_S.ADDR, -- Address
MI_S_RD => MI_S.RD, -- Read Request
MI_S_WR => MI_S.WR, -- Write Request
MI_S_BE => MI_S.BE, -- Byte Enable
MI_S_DRD => MI_S.DRD, -- Output Data
MI_S_ARDY => MI_S.ARDY, -- Address Ready
MI_S_DRDY => MI_S.DRDY -- Data Ready
);
end architecture full;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : JPEG_PKG
-- Design : JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : JPEG_PKG.VHD
-- Created : Sat Mar 7 2009
--
--------------------------------------------------------------------------------
--
-- Description : Package for JPEG core
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package JPEG_PKG is
-- do not change, constant
constant C_HDR_SIZE : integer := 623;
-- warning! this parameter heavily affects memory size required
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 640;
-- memory/performance tradeoff
-- 8 extra lines highest performance
-- 0 extra lines lowest area
--constant C_EXTRA_LINES : integer := 0; -- from 0 to 8
-- 24 bit format RGB/YCbCr 888 bits
-- 16 bit format RGB/YCbCr 565 bits
constant C_PIXEL_BITS : integer := 24;
-- 0 = RGB
-- 1 = YUV/YCbCr
constant C_YUV_INPUT : std_logic := '0';
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);
y_cnt : unsigned(15 downto 0);
cmp_idx : unsigned(2 downto 0);
end record;
constant C_SM_SETTINGS : T_SM_SETTINGS :=
(
(others => '0'),
(others => '0'),
(others => '0')
);
function log2(n : natural) return natural;
end package JPEG_PKG;
package body JPEG_PKG is
-----------------------------------------------------------------------------
function log2(n : natural)
return natural is
begin
for i in 0 to 31 loop
if (2**i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
-----------------------------------------------------------------------------
end package body JPEG_PKG; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: ft245uart.vhd
-- Authors: Jan Schirok - TU Dresden
-- Description: UART via USB FTDI FT245BL FIFO interface
-- interface: APB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ft245 is
type ft245_in_type is record
rddata : std_logic_vector(7 downto 0); -- data read from ft245
rxfn : std_logic; -- data avail (low active)
txen : std_logic; -- transmit possible (low active)
pwrenn : std_logic; -- dev is active (low active)
end record;
type ft245_out_type is record
wrdata : std_logic_vector(7 downto 0); -- data to ft245
oen : std_logic; -- output enable pad (low active)
rdn : std_logic; -- read enable (low active)
wr : std_logic; -- write enable (high active)
end record;
component ft245uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
use work.ft245.all;
entity ft245uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end;
architecture rtl of ft245uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- CYCLE DEFINITIONS FOR FT245 COMMUNICATION
--number of counter bits for cycles
constant CYC_WIDTH : integer := 6;
--minimum length of ft245o.rdn pulse
constant RDPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(2, CYC_WIDTH);
--number of clk periods until rddata is valid
constant RDTODATA : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(6, CYC_WIDTH);
--minimum length of ft245o.wr pulse in clk periods
constant WRPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(8, CYC_WIDTH);
--timeout for rdwait/wrwait (cycles to wait for rxfn/txen => '1')
constant TIMEOUT : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(63, CYC_WIDTH);
--zero definition
constant CYNULL : std_logic_vector(CYC_WIDTH-1 downto 0)
:= (CYC_WIDTH-1 downto 0 => '0');
type rxtxfsmtype is (idle, rdact, rddata, rdwait, wrdata, wrwait);
type ft245regs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
loopb : std_ulogic; -- loop back mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
break : std_ulogic; -- break detected (data==0x0, reset in SW)
irq : std_ulogic; -- tx/rx interrupt (internal)
ft245i : ft245_in_type; -- input register
ft245o : ft245_out_type; -- output register
rxtxstate : rxtxfsmtype; -- recv/transmit fsm
-- rcnt : std_logic_vector(0 downto 0);
-- tcnt : std_logic_vector(0 downto 0);
rhold : std_logic_vector(7 downto 0);
thold : std_logic_vector(7 downto 0);
cyclecnt : std_logic_vector(CYC_WIDTH-1 downto 0);
end record;
signal r, rin : ft245regs;
begin
uartop : process(rst, r, apbi )
variable rdata : std_logic_vector(31 downto 0);
-- variable scaler : std_logic_vector(11 downto 0);
-- variable rxclk, txclk : std_logic_vector(2 downto 0);
-- variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddr : std_logic_vector(7 downto 2);
variable v : ft245regs;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- dready := '0'; thempty := '1';
-- dready := r.rcnt(0); --rfull := dready; tfull := r.tcnt(0);
-- thempty := not r.tcnt(0);
--thempty := not tfull;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddr(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold;
v.rsempty := '1';
-- v.rcnt(0) := '0';
when "000001" =>
rdata(3 downto 0) := r.break & r.tsempty & r.tsempty & not(r.rsempty); --fifo==shiftreg
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
--no fifo => rdata(31)='0'
rdata(7) := r.loopb;
rdata(3 downto 0) := r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
-- no scaler
null;
when "000100" =>
-- no debug
null;
when others =>
null;
end case;
end if;
paddr := "000000"; paddr(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(7 downto 2) is
when "000000" =>
v.thold := apbi.pwdata(7 downto 0);
v.tsempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when "000001" =>
v.break := apbi.pwdata(3);
when "000010" =>
v.loopb := apbi.pwdata(7);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
when "000100" =>
when others =>
null;
end case;
end if;
-- FSM
case r.rxtxstate is
when idle =>
-- loopback mode, rx/tx active, recv buf empty, send buf full
if r.loopb = '1' and r.rxen = '1' and r.txen = '1' and
r.rsempty = '1' and r.tsempty = '0' then
v.rxtxstate := idle; -- loop back in one cycle
v.rhold := r.thold; -- copy transmit byte in recv buf
v.rsempty := '0';
v.tsempty := '1';
-- something to recv, recv enabled, recv hold reg empty
elsif r.ft245i.rxfn = '0' and r.rxen = '1' and r.rsempty = '1' then
v.rxtxstate := rdact;
v.cyclecnt := RDTODATA;
v.ft245o.oen := '1'; -- pad oen deact
v.ft245o.rdn := '0'; -- read enable
-- external send fifo not full, send enabled, send reg not empty
elsif r.ft245i.txen = '0' and r.txen = '1' and r.tsempty = '0' then
v.rxtxstate := wrdata;
v.cyclecnt := WRPULSE;
v.ft245o.wr := '1';
v.ft245o.oen := '0'; -- pad oen act
v.ft245o.wrdata := r.thold;
v.tsempty := '1';
if r.tirqen = '1' then
v.irq := '1';
end if;
end if;
when rdact =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rddata;
--rdn stays low
v.cyclecnt := RDPULSE;
end if;
when rddata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rdwait;
v.rsempty := '0';
if r.rirqen = '1' then
v.irq := '1'; -- irq if enabled
end if;
v.rhold := r.ft245i.rddata;
if r.ft245i.rddata = "00000000" then
v.break := '1';
end if;
v.ft245o.rdn := '1'; -- deactivate
v.cyclecnt := TIMEOUT;
end if;
when rdwait =>
v.cyclecnt := r.cyclecnt - 1;
-- value read or timeout
if v.ft245i.rxfn = '1' or v.cyclecnt = CYNULL then
v.rxtxstate := idle;
end if;
when wrdata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := wrwait;
v.cyclecnt := TIMEOUT;
v.ft245o.wr := '0';
end if;
when wrwait =>
v.cyclecnt := r.cyclecnt - 1;
--either tx byte accepted or timeout
if r.ft245i.txen = '1' or r.cyclecnt = CYNULL then
v.rxtxstate := idle;
v.ft245o.oen := '1'; -- output pad deact
v.tsempty := '1';
end if;
end case;
-- reset if no power enable at ft245
if r.ft245i.pwrenn = '1' then
v.rxtxstate := idle;
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rsempty := '1'; v.tsempty := '1';
v.irq := '0';
end if;
-- reset operation
if rst = '0' then
v.rxen := '0'; v.txen := '0';
v.rirqen := '0'; v.tirqen := '0';
v.loopb := '0';
v.rsempty := '1'; v.tsempty := '1';
v.break := '0';
v.irq := '0';
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rxtxstate := idle;
v.rhold := (others => '0');
v.thold := (others => '0');
v.cyclecnt := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
ft245o <= r.ft245o;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
r.ft245i <= ft245i;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": FT245 UART rev " & tost(REVISION) & ", no fifo " &
", irq " & tost(pirq));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: ft245uart.vhd
-- Authors: Jan Schirok - TU Dresden
-- Description: UART via USB FTDI FT245BL FIFO interface
-- interface: APB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ft245 is
type ft245_in_type is record
rddata : std_logic_vector(7 downto 0); -- data read from ft245
rxfn : std_logic; -- data avail (low active)
txen : std_logic; -- transmit possible (low active)
pwrenn : std_logic; -- dev is active (low active)
end record;
type ft245_out_type is record
wrdata : std_logic_vector(7 downto 0); -- data to ft245
oen : std_logic; -- output enable pad (low active)
rdn : std_logic; -- read enable (low active)
wr : std_logic; -- write enable (high active)
end record;
component ft245uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
use work.ft245.all;
entity ft245uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end;
architecture rtl of ft245uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- CYCLE DEFINITIONS FOR FT245 COMMUNICATION
--number of counter bits for cycles
constant CYC_WIDTH : integer := 6;
--minimum length of ft245o.rdn pulse
constant RDPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(2, CYC_WIDTH);
--number of clk periods until rddata is valid
constant RDTODATA : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(6, CYC_WIDTH);
--minimum length of ft245o.wr pulse in clk periods
constant WRPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(8, CYC_WIDTH);
--timeout for rdwait/wrwait (cycles to wait for rxfn/txen => '1')
constant TIMEOUT : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(63, CYC_WIDTH);
--zero definition
constant CYNULL : std_logic_vector(CYC_WIDTH-1 downto 0)
:= (CYC_WIDTH-1 downto 0 => '0');
type rxtxfsmtype is (idle, rdact, rddata, rdwait, wrdata, wrwait);
type ft245regs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
loopb : std_ulogic; -- loop back mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
break : std_ulogic; -- break detected (data==0x0, reset in SW)
irq : std_ulogic; -- tx/rx interrupt (internal)
ft245i : ft245_in_type; -- input register
ft245o : ft245_out_type; -- output register
rxtxstate : rxtxfsmtype; -- recv/transmit fsm
-- rcnt : std_logic_vector(0 downto 0);
-- tcnt : std_logic_vector(0 downto 0);
rhold : std_logic_vector(7 downto 0);
thold : std_logic_vector(7 downto 0);
cyclecnt : std_logic_vector(CYC_WIDTH-1 downto 0);
end record;
signal r, rin : ft245regs;
begin
uartop : process(rst, r, apbi )
variable rdata : std_logic_vector(31 downto 0);
-- variable scaler : std_logic_vector(11 downto 0);
-- variable rxclk, txclk : std_logic_vector(2 downto 0);
-- variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddr : std_logic_vector(7 downto 2);
variable v : ft245regs;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- dready := '0'; thempty := '1';
-- dready := r.rcnt(0); --rfull := dready; tfull := r.tcnt(0);
-- thempty := not r.tcnt(0);
--thempty := not tfull;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddr(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold;
v.rsempty := '1';
-- v.rcnt(0) := '0';
when "000001" =>
rdata(3 downto 0) := r.break & r.tsempty & r.tsempty & not(r.rsempty); --fifo==shiftreg
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
--no fifo => rdata(31)='0'
rdata(7) := r.loopb;
rdata(3 downto 0) := r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
-- no scaler
null;
when "000100" =>
-- no debug
null;
when others =>
null;
end case;
end if;
paddr := "000000"; paddr(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(7 downto 2) is
when "000000" =>
v.thold := apbi.pwdata(7 downto 0);
v.tsempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when "000001" =>
v.break := apbi.pwdata(3);
when "000010" =>
v.loopb := apbi.pwdata(7);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
when "000100" =>
when others =>
null;
end case;
end if;
-- FSM
case r.rxtxstate is
when idle =>
-- loopback mode, rx/tx active, recv buf empty, send buf full
if r.loopb = '1' and r.rxen = '1' and r.txen = '1' and
r.rsempty = '1' and r.tsempty = '0' then
v.rxtxstate := idle; -- loop back in one cycle
v.rhold := r.thold; -- copy transmit byte in recv buf
v.rsempty := '0';
v.tsempty := '1';
-- something to recv, recv enabled, recv hold reg empty
elsif r.ft245i.rxfn = '0' and r.rxen = '1' and r.rsempty = '1' then
v.rxtxstate := rdact;
v.cyclecnt := RDTODATA;
v.ft245o.oen := '1'; -- pad oen deact
v.ft245o.rdn := '0'; -- read enable
-- external send fifo not full, send enabled, send reg not empty
elsif r.ft245i.txen = '0' and r.txen = '1' and r.tsempty = '0' then
v.rxtxstate := wrdata;
v.cyclecnt := WRPULSE;
v.ft245o.wr := '1';
v.ft245o.oen := '0'; -- pad oen act
v.ft245o.wrdata := r.thold;
v.tsempty := '1';
if r.tirqen = '1' then
v.irq := '1';
end if;
end if;
when rdact =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rddata;
--rdn stays low
v.cyclecnt := RDPULSE;
end if;
when rddata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rdwait;
v.rsempty := '0';
if r.rirqen = '1' then
v.irq := '1'; -- irq if enabled
end if;
v.rhold := r.ft245i.rddata;
if r.ft245i.rddata = "00000000" then
v.break := '1';
end if;
v.ft245o.rdn := '1'; -- deactivate
v.cyclecnt := TIMEOUT;
end if;
when rdwait =>
v.cyclecnt := r.cyclecnt - 1;
-- value read or timeout
if v.ft245i.rxfn = '1' or v.cyclecnt = CYNULL then
v.rxtxstate := idle;
end if;
when wrdata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := wrwait;
v.cyclecnt := TIMEOUT;
v.ft245o.wr := '0';
end if;
when wrwait =>
v.cyclecnt := r.cyclecnt - 1;
--either tx byte accepted or timeout
if r.ft245i.txen = '1' or r.cyclecnt = CYNULL then
v.rxtxstate := idle;
v.ft245o.oen := '1'; -- output pad deact
v.tsempty := '1';
end if;
end case;
-- reset if no power enable at ft245
if r.ft245i.pwrenn = '1' then
v.rxtxstate := idle;
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rsempty := '1'; v.tsempty := '1';
v.irq := '0';
end if;
-- reset operation
if rst = '0' then
v.rxen := '0'; v.txen := '0';
v.rirqen := '0'; v.tirqen := '0';
v.loopb := '0';
v.rsempty := '1'; v.tsempty := '1';
v.break := '0';
v.irq := '0';
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rxtxstate := idle;
v.rhold := (others => '0');
v.thold := (others => '0');
v.cyclecnt := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
ft245o <= r.ft245o;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
r.ft245i <= ft245i;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": FT245 UART rev " & tost(REVISION) & ", no fifo " &
", irq " & tost(pirq));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: ft245uart.vhd
-- Authors: Jan Schirok - TU Dresden
-- Description: UART via USB FTDI FT245BL FIFO interface
-- interface: APB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ft245 is
type ft245_in_type is record
rddata : std_logic_vector(7 downto 0); -- data read from ft245
rxfn : std_logic; -- data avail (low active)
txen : std_logic; -- transmit possible (low active)
pwrenn : std_logic; -- dev is active (low active)
end record;
type ft245_out_type is record
wrdata : std_logic_vector(7 downto 0); -- data to ft245
oen : std_logic; -- output enable pad (low active)
rdn : std_logic; -- read enable (low active)
wr : std_logic; -- write enable (high active)
end record;
component ft245uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
use work.ft245.all;
entity ft245uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end;
architecture rtl of ft245uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- CYCLE DEFINITIONS FOR FT245 COMMUNICATION
--number of counter bits for cycles
constant CYC_WIDTH : integer := 6;
--minimum length of ft245o.rdn pulse
constant RDPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(2, CYC_WIDTH);
--number of clk periods until rddata is valid
constant RDTODATA : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(6, CYC_WIDTH);
--minimum length of ft245o.wr pulse in clk periods
constant WRPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(8, CYC_WIDTH);
--timeout for rdwait/wrwait (cycles to wait for rxfn/txen => '1')
constant TIMEOUT : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(63, CYC_WIDTH);
--zero definition
constant CYNULL : std_logic_vector(CYC_WIDTH-1 downto 0)
:= (CYC_WIDTH-1 downto 0 => '0');
type rxtxfsmtype is (idle, rdact, rddata, rdwait, wrdata, wrwait);
type ft245regs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
loopb : std_ulogic; -- loop back mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
break : std_ulogic; -- break detected (data==0x0, reset in SW)
irq : std_ulogic; -- tx/rx interrupt (internal)
ft245i : ft245_in_type; -- input register
ft245o : ft245_out_type; -- output register
rxtxstate : rxtxfsmtype; -- recv/transmit fsm
-- rcnt : std_logic_vector(0 downto 0);
-- tcnt : std_logic_vector(0 downto 0);
rhold : std_logic_vector(7 downto 0);
thold : std_logic_vector(7 downto 0);
cyclecnt : std_logic_vector(CYC_WIDTH-1 downto 0);
end record;
signal r, rin : ft245regs;
begin
uartop : process(rst, r, apbi )
variable rdata : std_logic_vector(31 downto 0);
-- variable scaler : std_logic_vector(11 downto 0);
-- variable rxclk, txclk : std_logic_vector(2 downto 0);
-- variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddr : std_logic_vector(7 downto 2);
variable v : ft245regs;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- dready := '0'; thempty := '1';
-- dready := r.rcnt(0); --rfull := dready; tfull := r.tcnt(0);
-- thempty := not r.tcnt(0);
--thempty := not tfull;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddr(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold;
v.rsempty := '1';
-- v.rcnt(0) := '0';
when "000001" =>
rdata(3 downto 0) := r.break & r.tsempty & r.tsempty & not(r.rsempty); --fifo==shiftreg
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
--no fifo => rdata(31)='0'
rdata(7) := r.loopb;
rdata(3 downto 0) := r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
-- no scaler
null;
when "000100" =>
-- no debug
null;
when others =>
null;
end case;
end if;
paddr := "000000"; paddr(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(7 downto 2) is
when "000000" =>
v.thold := apbi.pwdata(7 downto 0);
v.tsempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when "000001" =>
v.break := apbi.pwdata(3);
when "000010" =>
v.loopb := apbi.pwdata(7);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
when "000100" =>
when others =>
null;
end case;
end if;
-- FSM
case r.rxtxstate is
when idle =>
-- loopback mode, rx/tx active, recv buf empty, send buf full
if r.loopb = '1' and r.rxen = '1' and r.txen = '1' and
r.rsempty = '1' and r.tsempty = '0' then
v.rxtxstate := idle; -- loop back in one cycle
v.rhold := r.thold; -- copy transmit byte in recv buf
v.rsempty := '0';
v.tsempty := '1';
-- something to recv, recv enabled, recv hold reg empty
elsif r.ft245i.rxfn = '0' and r.rxen = '1' and r.rsempty = '1' then
v.rxtxstate := rdact;
v.cyclecnt := RDTODATA;
v.ft245o.oen := '1'; -- pad oen deact
v.ft245o.rdn := '0'; -- read enable
-- external send fifo not full, send enabled, send reg not empty
elsif r.ft245i.txen = '0' and r.txen = '1' and r.tsempty = '0' then
v.rxtxstate := wrdata;
v.cyclecnt := WRPULSE;
v.ft245o.wr := '1';
v.ft245o.oen := '0'; -- pad oen act
v.ft245o.wrdata := r.thold;
v.tsempty := '1';
if r.tirqen = '1' then
v.irq := '1';
end if;
end if;
when rdact =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rddata;
--rdn stays low
v.cyclecnt := RDPULSE;
end if;
when rddata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rdwait;
v.rsempty := '0';
if r.rirqen = '1' then
v.irq := '1'; -- irq if enabled
end if;
v.rhold := r.ft245i.rddata;
if r.ft245i.rddata = "00000000" then
v.break := '1';
end if;
v.ft245o.rdn := '1'; -- deactivate
v.cyclecnt := TIMEOUT;
end if;
when rdwait =>
v.cyclecnt := r.cyclecnt - 1;
-- value read or timeout
if v.ft245i.rxfn = '1' or v.cyclecnt = CYNULL then
v.rxtxstate := idle;
end if;
when wrdata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := wrwait;
v.cyclecnt := TIMEOUT;
v.ft245o.wr := '0';
end if;
when wrwait =>
v.cyclecnt := r.cyclecnt - 1;
--either tx byte accepted or timeout
if r.ft245i.txen = '1' or r.cyclecnt = CYNULL then
v.rxtxstate := idle;
v.ft245o.oen := '1'; -- output pad deact
v.tsempty := '1';
end if;
end case;
-- reset if no power enable at ft245
if r.ft245i.pwrenn = '1' then
v.rxtxstate := idle;
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rsempty := '1'; v.tsempty := '1';
v.irq := '0';
end if;
-- reset operation
if rst = '0' then
v.rxen := '0'; v.txen := '0';
v.rirqen := '0'; v.tirqen := '0';
v.loopb := '0';
v.rsempty := '1'; v.tsempty := '1';
v.break := '0';
v.irq := '0';
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rxtxstate := idle;
v.rhold := (others => '0');
v.thold := (others => '0');
v.cyclecnt := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
ft245o <= r.ft245o;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
r.ft245i <= ft245i;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": FT245 UART rev " & tost(REVISION) & ", no fifo " &
", irq " & tost(pirq));
-- pragma translate_on
end;
|
library verilog;
use verilog.vl_types.all;
entity rom_using_file is
port(
clock : in vl_logic;
address : in vl_logic_vector(7 downto 0);
data : out vl_logic_vector(12 downto 0)
);
end rom_using_file;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
entity usb_host_interface is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
usb_rx : out t_usb_rx;
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp;
-- low level ulpi interfacing
reg_read : in std_logic := '0';
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_rdata : out std_logic_vector(7 downto 0);
reg_ack : out std_logic;
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
status : out std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_dir : in std_logic;
ulpi_data : inout std_logic_vector(7 downto 0) );
end entity;
architecture structural of usb_host_interface is
signal status_i : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_register : std_logic := '0';
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal rx_crc_sync : std_logic;
signal rx_crc_dvalid : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal crc_dvalid : std_logic;
signal tx_data_to_crc: std_logic_vector(7 downto 0);
signal crc_data_in : std_logic_vector(7 downto 0);
signal data_crc : std_logic_vector(15 downto 0);
begin
i_ulpi: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ulpi_data,
ULPI_DIR => ulpi_dir,
ULPI_NXT => ulpi_nxt,
ULPI_STP => ulpi_stp,
-- status
status => status_i,
operational => '1',
-- chirp interface
do_chirp => do_chirp,
chirp_data => chirp_data,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store );
i_rx: entity work.ulpi_rx
generic map (
g_support_split => g_simulation,
g_support_token => g_simulation ) -- hosts do not receive tokens
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
status => status_i,
-- interface to DATA CRC (shared resource)
crc_sync => rx_crc_sync,
crc_dvalid => rx_crc_dvalid,
data_crc => data_crc,
usb_rx => usb_rx );
crc_sync <= rx_crc_sync or tx_crc_sync;
crc_dvalid <= rx_crc_dvalid or tx_crc_dvalid;
crc_data_in <= rx_data when rx_crc_dvalid='1' else tx_data_to_crc;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => crc_data_in,
crc => data_crc );
i_tx: entity work.ulpi_tx
generic map (
g_simulation => g_simulation,
g_support_split => true,
g_support_token => true ) -- hosts do send tokens
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_busy => rx_store,
-- interface to DATA CRC (shared resource)
crc_sync => tx_crc_sync,
crc_dvalid => tx_crc_dvalid,
data_crc => data_crc,
data_to_crc => tx_data_to_crc,
-- Status
status => status_i,
speed => speed,
-- Interface to send tokens and handshakes
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
status <= status_i;
reg_rdata <= rx_data;
end architecture;
|
--////////////////////// IIR_Biquad_I //////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_1.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
-- This biquad is set up for 18 bit input words with 32 bit coefficients
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad is
Port (
clk : in STD_LOGIC;
n_reset : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad;
architecture arch of IIR_Biquad is
-- -- Used Bilinear Z Transform
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients WORKED WITH HIGH SOUND
constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b0 ~ +0.2225548
constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0111_1100_1010_1100_1000_1110"; -- b1 ~ +0.4451095
constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b2 ~ +0.2225548
constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1010_0110_1001_1101_0101_0001_1011"; -- a1 ~ -0.3372905
constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_01_0011_1000_0011_1100_1110_1100_0001"; -- a2 ~ +0.3049199
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- define biquad coefficients -- DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT VERY LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients -- WORKED WITH AVERAGE SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529**
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875***
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT WITH LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118**
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 55 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector( 23 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk, n_reset, Y_out_double, sample_trig)
begin
if(n_reset = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk)) then
if(sample_trig = '1' and state_reg = idle)
then
ZFF_X0 <= X_in(23) & X_in(23 downto 1);
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, n_reset)
begin
if(n_reset = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk)) then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < "001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(55 downto 32);
pgZFF_X2 <= pgZFF_X2_quad(55 downto 32);
pgZFF_X1 <= pgZFF_X1_quad(55 downto 32);
pgZFF_Y1 <= pgZFF_Y1_quad(55 downto 32);
pgZFF_Y2 <= pgZFF_Y2_quad(55 downto 32);
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); --std_logic_vector((pgZFF_X0));--
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 23 downto 0);
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~ -1.9986306
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
--
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
|
--////////////////////// IIR_Biquad_I //////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_1.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
-- This biquad is set up for 18 bit input words with 32 bit coefficients
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad is
Port (
clk : in STD_LOGIC;
n_reset : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad;
architecture arch of IIR_Biquad is
-- -- Used Bilinear Z Transform
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients WORKED WITH HIGH SOUND
constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b0 ~ +0.2225548
constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0111_1100_1010_1100_1000_1110"; -- b1 ~ +0.4451095
constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b2 ~ +0.2225548
constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1010_0110_1001_1101_0101_0001_1011"; -- a1 ~ -0.3372905
constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_01_0011_1000_0011_1100_1110_1100_0001"; -- a2 ~ +0.3049199
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- define biquad coefficients -- DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT VERY LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients -- WORKED WITH AVERAGE SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529**
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875***
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT WITH LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118**
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 55 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector( 23 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk, n_reset, Y_out_double, sample_trig)
begin
if(n_reset = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk)) then
if(sample_trig = '1' and state_reg = idle)
then
ZFF_X0 <= X_in(23) & X_in(23 downto 1);
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, n_reset)
begin
if(n_reset = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk)) then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < "001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(55 downto 32);
pgZFF_X2 <= pgZFF_X2_quad(55 downto 32);
pgZFF_X1 <= pgZFF_X1_quad(55 downto 32);
pgZFF_Y1 <= pgZFF_Y1_quad(55 downto 32);
pgZFF_Y2 <= pgZFF_Y2_quad(55 downto 32);
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); --std_logic_vector((pgZFF_X0));--
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 23 downto 0);
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~ -1.9986306
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
--
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
|
--////////////////////// IIR_Biquad_I //////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_1.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
-- This biquad is set up for 18 bit input words with 32 bit coefficients
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad is
Port (
clk : in STD_LOGIC;
n_reset : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad;
architecture arch of IIR_Biquad is
-- -- Used Bilinear Z Transform
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients WORKED WITH HIGH SOUND
constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b0 ~ +0.2225548
constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0111_1100_1010_1100_1000_1110"; -- b1 ~ +0.4451095
constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b2 ~ +0.2225548
constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1010_0110_1001_1101_0101_0001_1011"; -- a1 ~ -0.3372905
constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_01_0011_1000_0011_1100_1110_1100_0001"; -- a2 ~ +0.3049199
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- define biquad coefficients -- DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT VERY LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients -- WORKED WITH AVERAGE SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529**
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875***
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT WITH LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118**
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 55 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector( 23 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk, n_reset, Y_out_double, sample_trig)
begin
if(n_reset = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk)) then
if(sample_trig = '1' and state_reg = idle)
then
ZFF_X0 <= X_in(23) & X_in(23 downto 1);
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, n_reset)
begin
if(n_reset = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk)) then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < "001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(55 downto 32);
pgZFF_X2 <= pgZFF_X2_quad(55 downto 32);
pgZFF_X1 <= pgZFF_X1_quad(55 downto 32);
pgZFF_Y1 <= pgZFF_Y1_quad(55 downto 32);
pgZFF_Y2 <= pgZFF_Y2_quad(55 downto 32);
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); --std_logic_vector((pgZFF_X0));--
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 23 downto 0);
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~ -1.9986306
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
--
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ROC_H_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
ROC_start_i : in std_logic;
serdat_i : in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end ROC_H_FSM;
architecture rtl of ROC_H_FSM is
type t_state is (waiting,
tick_RB3,
tick_RB2,
tick_RB1,
tick_RB0);
signal s_state : t_state;
--signal s_count : unsigned(3 downto 0);
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_RB3 =>
wen_o <= '0';
payload_o(3)<=serdat_i;
s_state <= tick_RB2;
-------------------------------------------------------------------------
when tick_RB2 =>
payload_o(2)<=serdat_i;
s_state <= tick_RB1;
-------------------------------------------------------------------------
when tick_RB1 =>
payload_o(1)<=serdat_i;
s_state <= tick_RB0;
-------------------------------------------------------------------------
when tick_RB0 =>
payload_o(0)<=serdat_i;
type_o <= "0111";
wen_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if ROC_start_i = '1' then
wen_o <= '0';
payload_o <= "0000";
s_state <= tick_RB3;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ROC_H_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
ROC_start_i : in std_logic;
serdat_i : in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end ROC_H_FSM;
architecture rtl of ROC_H_FSM is
type t_state is (waiting,
tick_RB3,
tick_RB2,
tick_RB1,
tick_RB0);
signal s_state : t_state;
--signal s_count : unsigned(3 downto 0);
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_RB3 =>
wen_o <= '0';
payload_o(3)<=serdat_i;
s_state <= tick_RB2;
-------------------------------------------------------------------------
when tick_RB2 =>
payload_o(2)<=serdat_i;
s_state <= tick_RB1;
-------------------------------------------------------------------------
when tick_RB1 =>
payload_o(1)<=serdat_i;
s_state <= tick_RB0;
-------------------------------------------------------------------------
when tick_RB0 =>
payload_o(0)<=serdat_i;
type_o <= "0111";
wen_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if ROC_start_i = '1' then
wen_o <= '0';
payload_o <= "0000";
s_state <= tick_RB3;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipeline4 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipeline4 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-----------------------------------
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WPAD : std_logic_vector(5 downto 0) := "011101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
----------------------------------------------------------------
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
signal w_80 : WORD_VECTOR(0 to 79);
-------------------------------------------------------------------
--constant K_TABLE : WORD_VECTOR(0 to 79) := (
-- 0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
-- 1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
-- 2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
-- 3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
-- 4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
-- 5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
-- 6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
-- 7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
-- 8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
-- 9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
-- 10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
-- 11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
-- 12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
-- 13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
-- 14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
-- 15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
-- 16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
-- 17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
-- 18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
-- 19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
-- 20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
-- 21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
-- 22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
-- 23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
-- 24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
-- 25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
-- 26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
-- 27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
-- 28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
-- 29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
-- 30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
-- 31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
-- 32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
-- 33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
-- 34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
-- 35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
-- 36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
-- 37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
-- 38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
-- 39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
-- 40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
-- 41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
-- 42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
-- 43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
-- 44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
-- 45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
-- 46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
-- 47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
-- 48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
-- 49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
-- 50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
-- 51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
-- 52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
-- 53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
-- 54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
-- 55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
-- 56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
-- 57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
-- 58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
-- 59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
-- 60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
-- 61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
-- 62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
-- 63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
-- 64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
-- 65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
-- 66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
-- 67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
-- 68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
-- 69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
-- 70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
-- 71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
-- 72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
-- 73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
-- 74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
-- 75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
-- 76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
-- 77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
-- 78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
-- 79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
-- );
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal message0 : std_logic_vector(63 downto 0);
signal message1 : std_logic_vector(63 downto 0);
signal message2 : std_logic_vector(63 downto 0);
signal message3 : std_logic_vector(63 downto 0);
signal message4 : std_logic_vector(63 downto 0);
signal message5 : std_logic_vector(63 downto 0);
signal message6 : std_logic_vector(63 downto 0);
signal message7 : std_logic_vector(63 downto 0);
signal message8 : std_logic_vector(63 downto 0);
signal message9 : std_logic_vector(63 downto 0);
signal message10 : std_logic_vector(63 downto 0);
signal message11 : std_logic_vector(63 downto 0);
signal message12 : std_logic_vector(63 downto 0);
signal message13 : std_logic_vector(63 downto 0);
signal message14 : std_logic_vector(63 downto 0);
signal message15 : std_logic_vector(63 downto 0);
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2=STM or Opcode2=STR or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
variable h0 : WORD_TYPE;
variable h1 : WORD_TYPE;
variable h2 : WORD_TYPE;
variable h3 : WORD_TYPE;
variable h4 : WORD_TYPE;
variable h5 : WORD_TYPE;
variable h6 : WORD_TYPE;
variable h7 : WORD_TYPE;
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2= MLOAD0) then
message0 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message1 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message2 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message3 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
message4 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message5 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message6 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message7 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
message8 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message9 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message10 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message11 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
message12 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))));
message13 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2)))));
message14 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2)))));
message15 <= std_logic_vector(unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = WPAD) then
w_80(0) <= message0;
w_80(1) <= message1;
w_80(2) <= message2;
w_80(3) <= message3;
w_80(4) <= message4;
w_80(5) <= message5;
w_80(6) <= message6;
w_80(7) <= message7;
w_80(8) <= message8;
w_80(9) <= message9;
w_80(10) <= message10;
w_80(11) <= message11;
w_80(12) <= message12;
w_80(13) <= message13;
w_80(14) <= message14;
w_80(15) <= message15;
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif(Opcode2 = ROUND1) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))))
);
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
elsif(opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = ROUND1) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
elsif (Opcode2 = WPAD) then
w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))) <=
std_logic_vector(
unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 19)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 61)) xor unsigned(shift_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-2)), 6)) +
unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-7)) +
unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 1)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 8)) xor unsigned(rotate_right(unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-15)), 7))+
unsigned(w_80(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))-16)));
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR ) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
stage3 <= S2;
end if;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
----
-- This file is part of etip-ss11-g07.
--
-- Copyright (C) 2011 Lukas Märdian <lukasmaerdian@gmail.com>
-- Copyright (C) 2011 M. S.
-- Copyright (C) 2011 Orest Tarasiuk <orest.tarasiuk@tum.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
ENTITY BINBCD IS
PORT(
clk : IN std_logic;
bin_input : IN std_logic_vector (16 DOWNTO 0);
einer, zehner, hunderter, tausender, zehntausender : OUT std_logic_vector (3 DOWNTO 0);
overflow : OUT std_logic
);
END BINBCD;
ARCHITECTURE DoubleDabbleV3 OF BINBCD IS
SIGNAL overflw : std_logic := '1';
BEGIN
PROCESS(clk)
VARIABLE int_input : integer := 0;
BEGIN
IF (rising_edge(clk)) THEN
int_input := to_integer(unsigned(bin_input));
IF (int_input <= 99999) THEN
overflow <= '0';
overflw <= '0';
ELSE
overflow <= '1';
overflw <= '1';
einer <= "0000";
zehner <= "0000";
hunderter <= "0000";
tausender <= "0000";
zehntausender <= "0000";
END IF;
END IF;
END PROCESS;
PROCESS(clk)
VARIABLE vector: std_logic_vector(36 DOWNTO 0) := "00000000000000000000" & bin_input;
VARIABLE int_bcd_seg : integer := 0;
BEGIN
IF (rising_edge(clk)) AND (overflw = '0') THEN
FOR i IN 0 TO 17 LOOP
-- Prüfen, ob größergleich 5; falls ja, dann 3 addieren für:
-- Zehntausender
int_bcd_seg := to_integer(unsigned(vector(3 DOWNTO 0)));
IF (int_bcd_seg >= 5) THEN
vector(3 DOWNTO 0) := std_logic_vector(unsigned(vector(3 DOWNTO 0)) + "0011");
END IF;
-- Tausender
int_bcd_seg := to_integer(unsigned(vector(7 DOWNTO 4)));
IF (int_bcd_seg >= 5) THEN
vector(7 DOWNTO 4) := std_logic_vector(unsigned(vector(7 DOWNTO 4)) + "0011");
END IF;
-- Hunderter
int_bcd_seg := to_integer(unsigned(vector(11 DOWNTO 8)));
IF (int_bcd_seg >= 5) THEN
vector(11 DOWNTO 8) := std_logic_vector(unsigned(vector(11 DOWNTO 8)) + "0011");
END IF;
-- Zehner
int_bcd_seg := to_integer(unsigned(vector(15 DOWNTO 12)));
IF (int_bcd_seg >= 5) THEN
vector(15 DOWNTO 12) := std_logic_vector(unsigned(vector(15 DOWNTO 12)) + "0011");
END IF;
-- Einer
int_bcd_seg := to_integer(unsigned(vector(19 DOWNTO 16)));
IF (int_bcd_seg >= 5) THEN
vector(19 DOWNTO 16) := std_logic_vector(unsigned(vector(19 DOWNTO 16)) + "0011");
END IF;
-- Shiften:
vector := vector(35 DOWNTO 0) & '0';
END LOOP;
-- Ergebnisse in die jeweiligen Stellen schreiben
zehntausender <= vector(3 DOWNTO 0);
tausender <= vector(7 DOWNTO 4);
hunderter <= vector(11 DOWNTO 8);
zehner <= vector(15 DOWNTO 12);
einer <= vector(19 DOWNTO 16);
END IF;
END PROCESS;
END DoubleDabbleV3;
|
entity simple is
end simple;
architecture behav of simple is
begin
assert false report "Hello";
end behav;
|
entity simple is
end simple;
architecture behav of simple is
begin
assert false report "Hello";
end behav;
|
----------------------------------------------------------------------------------------
-- Company: University of Washington
-- Engineer: Lev Kurilenko
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Lev Kurilenko
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.10.2016 15:47:35
-- Design Name:
-- Module Name: cktp_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: CKTP Generator
--
-- Dependencies:
--
-- Changelog:
-- 20.02.2017 Added dynamic CKBC input frequency and reset circuitry. Changed the input
-- clock frequency to 160 Mhz. (Christos Bakalis)
-- 27.02.2017 Added cktp_primary signal from flow_fsm. (Christos Bakalis)
-- 09.03.2017 Changed input bus widths and introduced integer range for logic and routing
-- optimization. (Christos Bakalis)
-- 14.03.2017 Added a cktp_start delay process. (Christos Bakalis)
--
----------------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cktp_gen is
port(
clk_160 : in std_logic;
cktp_start : in std_logic;
cktp_primary : in std_logic;
vmm_ckbc : in std_logic; -- CKBC clock currently dynamic
ckbc_mode : in std_logic;
ckbc_freq : in std_logic_vector(5 downto 0);
skew : in std_logic_vector(4 downto 0);
pulse_width : in std_logic_vector(11 downto 0);
period : in std_logic_vector(21 downto 0);
CKTP : out std_logic
);
end cktp_gen;
architecture Behavioral of cktp_gen is
--is_state <= "0101";
signal cktp_state : std_logic_vector(3 downto 0) := (others => '0');
signal cktp_cnt : integer range -2 to 2_100_000:= 0;
signal vmm_cktp : std_logic := '0';
signal cktp_start_i : std_logic := '0'; -- Internal connection to 2-Flip-Flop Synchronizer
signal cktp_start_sync : std_logic := '0'; -- Synchronized output from Synchronizer
signal cktp_start_final : std_logic := '0';
signal cktp_primary_i : std_logic := '0';
signal cktp_primary_sync : std_logic := '0';
signal cktp_start_aligned : std_logic := '0'; -- CKTP_start signal aligned to CKBC clock
signal align_cnt : unsigned(7 downto 0) := (others => '0'); -- Used for aligning with the CKBC
signal align_cnt_thresh : unsigned(7 downto 0) := (others => '0');
signal start_align_cnt : std_logic := '0'; --
signal cnt_delay : unsigned(3 downto 0) := (others => '0');
signal ckbc_mode_i : std_logic := '0';
signal ckbc_mode_sync : std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of cktp_start_i : signal is "TRUE";
attribute ASYNC_REG of cktp_start_sync : signal is "TRUE";
attribute ASYNC_REG of cktp_primary_i : signal is "TRUE";
attribute ASYNC_REG of cktp_primary_sync : signal is "TRUE";
attribute ASYNC_REG of ckbc_mode_i : signal is "TRUE";
attribute ASYNC_REG of ckbc_mode_sync : signal is "TRUE";
begin
--period <= x"43200"; -- Hardcode 320,000 cycles at 320 MHz to give a period of 1ms
CKTP <= vmm_cktp;
--testPulse_proc: process(clk_10_phase45) -- 10MHz/#states.
-- begin
-- if rising_edge(clk_10_phase45) then
-- if state = DAQ and trig_mode_int = '0' then
-- case cktp_state is
-- when 0 to 9979 =>
-- cktp_state <= cktp_state + 1;
-- vmm_cktp <= '0';
-- when 9980 to 10000 =>
-- cktp_state <= cktp_state + 1;
-- vmm_cktp <= '1';
-- when others =>
-- cktp_state <= 0;
-- end case;
-- else
-- vmm_cktp <= '0';
-- end if;
-- end if;
--end process;
synchronizer_proc: process(vmm_ckbc, cktp_start_final)
begin
if(cktp_start_final = '0')then
start_align_cnt <= '0';
elsif rising_edge(vmm_ckbc) then
start_align_cnt <= '1';
--if (cktp_start_sync = '1') then
-- cktp_start_aligned <= '1';
-- --if (unsigned(skew) = "00000") then -- Set CKTP signal as soon as rising edge of CKBC arrives if skew = 0
-- -- vmm_cktp <= '1';
-- --end if;
--else
-- cktp_start_aligned <= '0';
--end if;
end if;
end process;
sync160_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
cktp_start_i <= cktp_start;
cktp_start_sync <= cktp_start_i;
cktp_primary_i <= cktp_primary;
cktp_primary_sync <= cktp_primary_i;
ckbc_mode_i <= ckbc_mode;
ckbc_mode_sync <= ckbc_mode_i;
end if;
end process;
-- delay assertion of cktp start
cktpEnableDelayer: process(clk_160)
begin
if(rising_edge(clk_160))then
if(cktp_start_sync = '1')then
if(cnt_delay < "1110")then
cnt_delay <= cnt_delay + 1;
cktp_start_final <= '0';
else
cktp_start_final <= '1';
end if;
else
cnt_delay <= (others => '0');
cktp_start_final <= '0';
end if;
end if;
end process;
testPulse_proc: process(clk_160) -- 160 MHz
begin
if rising_edge(clk_160) then
if(cktp_start_final = '0' and cktp_primary_sync = '0')then
cktp_cnt <= 0;
vmm_cktp <= '0';
cktp_start_aligned <= '0';
align_cnt <= (others => '0');
cktp_state <= (others => '0');
elsif(cktp_primary_sync = '1')then -- from flow_fsm. keep cktp high for readout initialization
vmm_cktp <= '1';
else
if start_align_cnt = '1' or ckbc_mode_sync = '1' then -- Start alignment counter on rising edge of CKBC
if align_cnt < align_cnt_thresh then
align_cnt <= align_cnt + 1;
else
align_cnt <= (others => '0');
end if;
if ckbc_mode_sync = '1' then -- Just send periodic CKTPs if @ ckbc mode
cktp_start_aligned <= '1';
elsif cktp_start_final = '0' then -- Align CKTP generation to rising edge of CKBC if CKTPs are enabled @ top
cktp_start_aligned <= '0';
elsif (align_cnt = align_cnt_thresh) then
cktp_start_aligned <= '1';
if unsigned(skew) = "00000" then -- Set CKTP signal as soon as rising edge of CKBC arrives if skew = 0
vmm_cktp <= '1';
end if;
end if;
end if;
if cktp_start_aligned = '1' then
if (cktp_cnt < (to_integer(unsigned(skew)) - 1 ) and (cktp_cnt /= to_integer(unsigned(skew)))) then
cktp_state <= "0000";
vmm_cktp <= '0';
cktp_cnt <= cktp_cnt + 1;
elsif ( (cktp_cnt >= to_integer((unsigned(skew))) - 1) and (cktp_cnt <= (to_integer(unsigned(skew)) + to_integer(unsigned(pulse_width)) - 2) ) ) then
cktp_state <= "0001";
vmm_cktp <= '1';
cktp_cnt <= cktp_cnt + 1;
-- Uncomment if period needs to be hardcoded
--elsif ( (cktp_cnt > ( unsigned(skew) + unsigned(pulse_width) - 2) ) and (cktp_cnt <= 320000 - 2) ) then
elsif ( (cktp_cnt > ( to_integer(unsigned(skew)) + to_integer(unsigned(pulse_width)) - 2) ) and (cktp_cnt <= to_integer(unsigned(period)) - 2) ) then
cktp_state <= "0010";
vmm_cktp <= '0';
cktp_cnt <= cktp_cnt + 1;
else
cktp_state <= "0011";
cktp_cnt <= 0;
end if;
else
cktp_state <= "1111";
cktp_cnt <= 0;
end if;
end if;
end if;
end process;
ckbc_freq_proc: process(ckbc_freq)
begin
case ckbc_freq is
when "001010" => -- 10 Mhz
align_cnt_thresh <= "00001111"; -- (16 - 1)
when "010100" => -- 20 Mhz
align_cnt_thresh <= "00000111"; -- (8 - 1)
when "101000" => -- 40 Mhz
align_cnt_thresh <= "00000011"; -- (4 - 1)
when others =>
align_cnt_thresh <= "11111111";
end case;
end process;
end Behavioral; |
library ieee;
package body fifo_pkg is
end package body;
-- Violation below
package body fifo_pkg is
-- Comments could be allowed
end package body;
library ieee;
package body fifo_pkg is
constant a : std_logic;
end package body;
|
-- Simple wrapper of the eth_mac_1g_fifo
-- with helper attributes for Vivado to infer interfaces
library ieee;
use ieee.std_logic_1164.all;
entity eth_mac_1g_fifo_wrapper is
generic (
ENABLE_PADDING : natural := 1;
MIN_FRAME_LENGTH : natural := 64;
TX_FIFO_ADDR_WIDTH : natural := 12;
RX_FIFO_ADDR_WIDTH : natural := 12
);
port (
rx_clk : in std_logic;
rx_rst : in std_logic;
tx_clk : in std_logic;
tx_rst : in std_logic;
logic_clk : in std_logic;
logic_rst : in std_logic;
tx_axis_tdata : in std_logic_vector(7 downto 0);
tx_axis_tvalid : in std_logic;
tx_axis_tready : out std_logic;
tx_axis_tlast : in std_logic;
tx_axis_tuser : in std_logic;
rx_axis_tdata : out std_logic_vector(7 downto 0);
rx_axis_tvalid : out std_logic;
rx_axis_tready : in std_logic;
rx_axis_tlast : out std_logic;
rx_axis_tuser : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_bad_frame : out std_logic;
tx_fifo_good_frame : out std_logic;
rx_error_bad_frame : out std_logic;
rx_error_bad_fcs : out std_logic;
rx_fifo_overflow : out std_logic;
rx_fifo_bad_frame : out std_logic;
rx_fifo_good_frame : out std_logic;
ifg_delay : in std_logic_vector(7 downto 0) := x"0c" --interframe gap of 12 -standard is 96 bits (12 bytes) see https://en.wikipedia.org/wiki/Interpacket_gap
);
end entity;
architecture arch of eth_mac_1g_fifo_wrapper is
-- some helper attributes for Vivado to infer interfaces
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of gmii_txd : signal is "xilinx.com:interface:gmii:1.0 gmii TXD";
attribute X_INTERFACE_INFO of gmii_tx_en : signal is "xilinx.com:interface:gmii:1.0 gmii TX_EN";
attribute X_INTERFACE_INFO of gmii_tx_er : signal is "xilinx.com:interface:gmii:1.0 gmii TX_ER";
attribute X_INTERFACE_INFO of gmii_rxd : signal is "xilinx.com:interface:gmii:1.0 gmii RXD";
attribute X_INTERFACE_INFO of gmii_rx_dv : signal is "xilinx.com:interface:gmii:1.0 gmii RX_DV";
attribute X_INTERFACE_INFO of gmii_rx_er : signal is "xilinx.com:interface:gmii:1.0 gmii RX_ER";
attribute X_INTERFACE_INFO of tx_clk : signal is "xilinx.com:interface:gmii:1.0 gmii GTX_CLK";
attribute X_INTERFACE_INFO of rx_clk : signal is "xilinx.com:interface:gmii:1.0 gmii RX_CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of rx_rst : signal is "POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_PARAMETER of tx_rst : signal is "POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_PARAMETER of logic_rst : signal is "POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_PARAMETER of logic_clk : signal is
"ASSOCIATED_BUSIF rx_axis:tx_axis, ASSOCIATED_RESET logic_rst, FREQ_HZ 125000000";
component eth_mac_1g_fifo
generic (
ENABLE_PADDING : natural := 1;
MIN_FRAME_LENGTH : natural := 64;
TX_FIFO_ADDR_WIDTH : natural := 12;
RX_FIFO_ADDR_WIDTH : natural := 12
);
port (
rx_clk : in std_logic;
rx_rst : in std_logic;
tx_clk : in std_logic;
tx_rst : in std_logic;
logic_clk : in std_logic;
logic_rst : in std_logic;
tx_axis_tdata : in std_logic_vector(7 downto 0);
tx_axis_tvalid : in std_logic;
tx_axis_tready : out std_logic;
tx_axis_tlast : in std_logic;
tx_axis_tuser : in std_logic;
rx_axis_tdata : out std_logic_vector(7 downto 0);
rx_axis_tvalid : out std_logic;
rx_axis_tready : in std_logic;
rx_axis_tlast : out std_logic;
rx_axis_tuser : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_bad_frame : out std_logic;
tx_fifo_good_frame : out std_logic;
rx_error_bad_frame : out std_logic;
rx_error_bad_fcs : out std_logic;
rx_fifo_overflow : out std_logic;
rx_fifo_bad_frame : out std_logic;
rx_fifo_good_frame : out std_logic;
ifg_delay : in std_logic_vector(7 downto 0)
);
end component;
begin
eth_mac_1g_fifo_inst : eth_mac_1g_fifo
generic map (
ENABLE_PADDING => ENABLE_PADDING,
MIN_FRAME_LENGTH => MIN_FRAME_LENGTH,
TX_FIFO_ADDR_WIDTH => TX_FIFO_ADDR_WIDTH,
RX_FIFO_ADDR_WIDTH => RX_FIFO_ADDR_WIDTH
)
port map (
rx_clk => rx_clk,
rx_rst => rx_rst,
tx_clk => tx_clk,
tx_rst => tx_rst,
logic_clk => logic_clk,
logic_rst => logic_rst,
tx_axis_tdata => tx_axis_tdata,
tx_axis_tvalid => tx_axis_tvalid,
tx_axis_tready => tx_axis_tready,
tx_axis_tlast => tx_axis_tlast,
tx_axis_tuser => tx_axis_tuser,
rx_axis_tdata => rx_axis_tdata,
rx_axis_tvalid => rx_axis_tvalid,
rx_axis_tready => rx_axis_tready,
rx_axis_tlast => rx_axis_tlast,
rx_axis_tuser => rx_axis_tuser,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
tx_fifo_overflow => tx_fifo_overflow,
tx_fifo_bad_frame => tx_fifo_bad_frame,
tx_fifo_good_frame => tx_fifo_good_frame,
rx_error_bad_frame => rx_error_bad_frame,
rx_error_bad_fcs => rx_error_bad_fcs,
rx_fifo_overflow => rx_fifo_overflow,
rx_fifo_bad_frame => rx_fifo_bad_frame,
rx_fifo_good_frame => rx_fifo_good_frame,
ifg_delay => ifg_delay
);
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:00:14 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.vhdl
-- Design : fifo_generator_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_generator_0 is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
end fifo_generator_0;
architecture stub of fifo_generator_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[8:0],wr_data_count[9:0],prog_full,prog_empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3";
begin
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gr1553b_pkg
-- File: gr1553b_pkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Package for GR1553B top-level component and user-visible types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.ahb_mst_in_type;
use grlib.amba.ahb_mst_out_type;
use grlib.amba.apb_slv_in_type;
use grlib.amba.apb_slv_out_type;
library techmap;
use techmap.gencomp.all;
package gr1553b_pkg is
constant gr1553b_version: integer := 0;
constant gr1553b_cfgver: integer := 0;
-----------------------------------------------------------------------------
-- Types and top level component
type gr1553b_txout_type is record
busA_txP: std_logic;
busA_txN: std_logic;
busA_txen: std_logic;
busA_rxen: std_logic;
busB_txP: std_logic;
busB_txN: std_logic;
busB_txen: std_logic;
busB_rxen: std_logic;
-- For convenience, inverted versions of txen
busA_txin: std_logic;
busB_txin: std_logic;
end record;
type gr1553b_rxin_type is record
busA_rxP: std_logic;
busA_rxN: std_logic;
busB_rxP: std_logic;
busB_rxN: std_logic;
end record;
type gr1553b_auxin_type is record
extsync: std_logic;
rtaddr: std_logic_vector(4 downto 0);
rtpar: std_logic;
end record;
type gr1553b_auxout_type is record
rtsync: std_logic;
busreset: std_logic;
validcmdA: std_logic;
validcmdB: std_logic;
timedoutA: std_logic;
timedoutB: std_logic;
badreg: std_logic;
irqvec: std_logic_vector(7 downto 0);
end record;
constant gr1553b_rxin_zero: gr1553b_rxin_type :=
(busA_rxP=>'0', busA_rxN=>'0', busB_rxP=>'0', busB_rxN=>'0');
constant gr1553b_txout_zero: gr1553b_txout_type :=
('0','0','0','0','0','0','0','0','1','1');
constant gr1553b_auxin_zero: gr1553b_auxin_type :=
(extsync => '0', rtaddr => "11111", rtpar => '1');
constant gr1553b_auxout_zero: gr1553b_auxout_type :=
('0','0','0','0','0','0','0',x"00");
constant gr1553b_rxin_none: gr1553b_rxin_type := gr1553b_rxin_zero;
constant gr1553b_txout_none: gr1553b_txout_type := gr1553b_txout_zero;
constant gr1553b_auxin_none: gr1553b_auxin_type := gr1553b_auxin_zero;
constant gr1553b_auxout_none: gr1553b_auxout_type := gr1553b_auxout_zero;
component gr1553b is
generic(
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- Pads convenience component
component gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Wrappers for netlists etc.
component gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq: out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable: in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
component gr1553b_nlw is
generic(
tech: integer := 0;
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- APB Register definitions
constant REG_IRQSTATUS: std_logic_vector := x"00";
constant REG_IRQENABLE: std_logic_vector := x"04";
constant REG_BCSTATUS: std_logic_vector := x"40";
constant REG_BCACTION: std_logic_vector := x"44";
constant REG_BCSCHEMADDR: std_logic_vector := x"48";
constant REG_BCASYNCADDR: std_logic_vector := x"4C";
constant REG_BCTIME: std_logic_vector := x"50";
constant REG_BCWAKEUP: std_logic_vector := x"54";
constant REG_BCIRQSRC: std_logic_vector := x"58";
constant REG_BCRTBUSMASK: std_logic_vector := x"5C";
constant REG_BCSCHEMSLOT: std_logic_vector := x"68";
constant REG_BCASYNCSLOT: std_logic_vector := x"6C";
constant REG_RTSTATUS: std_logic_vector := x"80";
constant REG_RTCONFIG: std_logic_vector := x"84";
constant REG_RTBUSSTAT: std_logic_vector := x"88";
constant REG_RTBUSWORDS: std_logic_vector := x"8C";
constant REG_RTSYNC: std_logic_vector := x"90";
constant REG_RTTABLEADDR: std_logic_vector := x"94";
constant REG_RTMODECONFIG: std_logic_vector := x"98";
constant REG_RTTIMETAG: std_logic_vector := x"A4";
constant REG_RTLOGMASK: std_logic_vector := x"AC";
constant REG_RTLOGPOS: std_logic_vector := x"B0";
constant REG_RTIRQSRC: std_logic_vector := x"B4";
constant REG_BMSTATUS: std_logic_vector := x"C0";
constant REG_BMCONFIG: std_logic_vector := x"C4";
constant REG_BMADDRFILT: std_logic_vector := x"C8";
constant REG_BMSAFILT: std_logic_vector := x"CC";
constant REG_BMMCFILT: std_logic_vector := x"D0";
constant REG_BMBUFSTART: std_logic_vector := x"D4";
constant REG_BMBUFEND: std_logic_vector := x"D8";
constant REG_BMBUFPOS: std_logic_vector := x"DC";
constant REG_BMTIMETAG: std_logic_vector := x"E0";
-----------------------------------------------------------------------------
-- Embedded RT core
component grrt is
generic (
codecfreq: integer := 20;
sameclk : integer := 1;
syncrst : integer range 0 to 1 := 1
);
port (
-- Clock and reset
clk : in std_ulogic;
rst : in std_ulogic;
clk1553 : in std_ulogic;
rst1553 : in std_ulogic;
-- Control signals
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_ulogic;
rtstat : in std_logic_vector(3 downto 0); -- 3=SR, 2=busy 1=SSF 0=TF
ad31en : in std_ulogic; -- 1=RT31 is normal addr, 0=RT31 is broadcast
rtsync : out std_ulogic;
rtreset : out std_ulogic;
stamp : out std_ulogic;
-- Front-end interface
phase : out std_logic_vector(1 downto 0);
transfer : out std_logic_vector(11 downto 0);
resp : in std_logic_vector(1 downto 0);
tfrerror : out std_ulogic;
txdata : in std_logic_vector(15 downto 0);
rxdata : out std_logic_vector(15 downto 0);
datardy : in std_ulogic;
datarw : out std_ulogic;
-- 1553 transceiver interface
aoutin : out std_ulogic;
aoutp : out std_ulogic;
aoutn : out std_ulogic;
ainen : out std_ulogic;
ainp : in std_ulogic;
ainn : in std_ulogic;
boutin : out std_ulogic;
boutp : out std_ulogic;
boutn : out std_ulogic;
binen : out std_ulogic;
binp : in std_ulogic;
binn : in std_ulogic;
-- Fail-safe timer feedback
aoutp_fb : in std_logic;
aoutn_fb : in std_logic;
boutp_fb : in std_logic;
boutn_fb : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Test signal generators
component gr1553b_tgapb is
generic(
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
codecfreq: integer := 20;
extmodeen: integer range 0 to 1 := 0;
rawmodeen: integer range 0 to 1 := 0;
rawmemtech: integer := 0
);
port(
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
txout_core: in gr1553b_txout_type;
rxin_core: out gr1553b_rxin_type;
txout_bus: out gr1553b_txout_type;
rxin_bus: in gr1553b_rxin_type;
testing: out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Simulation types and components for test bench
-- U=Undefined, X=Unknown, 0=Zero, +=High, -=Low
type uwire1553 is ('U','X','0','+','-');
type uwire1553_array is array(natural range <>) of uwire1553;
function resolved (a: uwire1553_array) return uwire1553;
subtype wire1553 is resolved uwire1553;
component simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end component;
component simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end component;
component combine1553 is
port (
clk: in std_ulogic;
txin1,rxen1: in std_ulogic;
tx1P,tx1N: in std_ulogic;
rx1P,rx1N: out std_ulogic;
txin2,rxen2: in std_ulogic;
tx2P,tx2N: in std_ulogic;
rx2P,rx2N: out std_ulogic;
txin,rxen: out std_ulogic;
txP,txN: out std_ulogic;
rxP,rxN: in std_ulogic
);
end component;
end package;
package body gr1553b_pkg is
function resolved (a: uwire1553_array) return uwire1553 is
variable w,w2: uwire1553;
begin
w := a(a'left);
for q in a'range loop
w2 := a(q);
if w /= w2 then
case w is
when 'U' => w := 'X';
when 'X' => null;
when '0' => w := w2;
when '+' | '-' => if w2 /= '0' then w:='X'; end if;
end case;
end if;
end loop;
return w;
end;
end package body;
|
-------------------------------------------------------------------------------
-- xps_bram_if_cntlr_0_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_bram_if_cntlr_0_bram_elaborate_v1_00_a;
use xps_bram_if_cntlr_0_bram_elaborate_v1_00_a.all;
entity xps_bram_if_cntlr_0_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 7);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 63);
BRAM_Dout_A : in std_logic_vector(0 to 63);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 7);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 63);
BRAM_Dout_B : in std_logic_vector(0 to 63)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of xps_bram_if_cntlr_0_bram_wrapper : entity is "xps_bram_if_cntlr_0_bram_elaborate_v1_00_a";
attribute keep_hierarchy of xps_bram_if_cntlr_0_bram_wrapper : entity is "yes";
end xps_bram_if_cntlr_0_bram_wrapper;
architecture STRUCTURE of xps_bram_if_cntlr_0_bram_wrapper is
component xps_bram_if_cntlr_0_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
xps_bram_if_cntlr_0_bram : xps_bram_if_cntlr_0_bram_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 64,
C_PORT_AWIDTH => 32,
C_NUM_WE => 8,
C_FAMILY => "virtex5"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2058.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02058ent IS
END c07s02b04x00p01n01i02058ent;
ARCHITECTURE c07s02b04x00p01n01i02058arch OF c07s02b04x00p01n01i02058ent IS
BEGIN
TESTING: PROCESS
type FT is file of BIT;
file FILEV : FT is "input_file";
BEGIN
FILEV := FILEV - FILEV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02058 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02058arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2058.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02058ent IS
END c07s02b04x00p01n01i02058ent;
ARCHITECTURE c07s02b04x00p01n01i02058arch OF c07s02b04x00p01n01i02058ent IS
BEGIN
TESTING: PROCESS
type FT is file of BIT;
file FILEV : FT is "input_file";
BEGIN
FILEV := FILEV - FILEV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02058 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02058arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2058.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02058ent IS
END c07s02b04x00p01n01i02058ent;
ARCHITECTURE c07s02b04x00p01n01i02058arch OF c07s02b04x00p01n01i02058ent IS
BEGIN
TESTING: PROCESS
type FT is file of BIT;
file FILEV : FT is "input_file";
BEGIN
FILEV := FILEV - FILEV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02058 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02058arch;
|
-- $Id: ib_sres_or_4.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_4 - syn
-- Description: ibus: result or, 4 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_4;
architecture syn of ib_sres_or_4 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack or
IB_SRES_4.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy or
IB_SRES_4.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout or
IB_SRES_4.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4
);
-- synthesis translate_on
end syn;
|
-- $Id: ib_sres_or_4.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_4 - syn
-- Description: ibus: result or, 4 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_4;
architecture syn of ib_sres_or_4 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack or
IB_SRES_4.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy or
IB_SRES_4.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout or
IB_SRES_4.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4
);
-- synthesis translate_on
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien2 is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien2;
architecture generator of alien2 is
type states is (act, wait_clk);
signal state, state_next: states;
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 32;
constant FRAME_DELAY: integer := 5000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_x_next,
origin_y, origin_y_next: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
-- second level aliens need two hits to get killed
signal injured, injured_next: std_logic_vector(0 to 7);
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(22 downto 0);
signal alien_rgb, alien21_rgb, alien22_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
injured <= (others => '0');
state <= act;
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
injured <= injured_next;
state <= state_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, position_in_frame,
alive, injured, state, restart)
begin
state_next <= state;
destruction <= '0';
alive_next <= alive;
injured_next <= injured;
case state is
when act =>
if restart = '1' then
alive_next <= (others => '1');
injured_next <= (others => '0');
elsif missile_arrived = '1' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
if injured(conv_integer(attacked_alien)) = '0' then
state_next <= wait_clk;
destruction <= '1';
injured_next(conv_integer(attacked_alien)) <= '1';
else
state_next <= wait_clk;
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end if;
when wait_clk =>
state_next <= act;
end case;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien21_rgb when frame = '0' else
alien22_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_21:
entity work.alien21_rom(content)
port map(addr => addr, data => alien21_rgb);
alien_22:
entity work.alien22_rom(content)
port map(addr => addr, data => alien22_rgb);
end generator; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien2 is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien2;
architecture generator of alien2 is
type states is (act, wait_clk);
signal state, state_next: states;
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 32;
constant FRAME_DELAY: integer := 5000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_x_next,
origin_y, origin_y_next: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
-- second level aliens need two hits to get killed
signal injured, injured_next: std_logic_vector(0 to 7);
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(22 downto 0);
signal alien_rgb, alien21_rgb, alien22_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
injured <= (others => '0');
state <= act;
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
injured <= injured_next;
state <= state_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, position_in_frame,
alive, injured, state, restart)
begin
state_next <= state;
destruction <= '0';
alive_next <= alive;
injured_next <= injured;
case state is
when act =>
if restart = '1' then
alive_next <= (others => '1');
injured_next <= (others => '0');
elsif missile_arrived = '1' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
if injured(conv_integer(attacked_alien)) = '0' then
state_next <= wait_clk;
destruction <= '1';
injured_next(conv_integer(attacked_alien)) <= '1';
else
state_next <= wait_clk;
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end if;
when wait_clk =>
state_next <= act;
end case;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien21_rgb when frame = '0' else
alien22_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_21:
entity work.alien21_rom(content)
port map(addr => addr, data => alien21_rgb);
alien_22:
entity work.alien22_rom(content)
port map(addr => addr, data => alien22_rgb);
end generator; |
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_sync_manager_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_sync_manager_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Thu May 7 14:29:08 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_sync_manager_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_sync_manager_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_sync_manager_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_sync_manager_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_sync_manager_v1_00_a.plb_sync_manager
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY,
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P => C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS => C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => sig_dev_mderr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
|
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_sync_manager_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_sync_manager_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Thu May 7 14:29:08 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_sync_manager_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_sync_manager_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_sync_manager_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_sync_manager_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_sync_manager_v1_00_a.plb_sync_manager
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY,
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P => C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS => C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => sig_dev_mderr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
|
----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Transmitter. This transmitter is able
-- to transmit 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When transmit is complete o_TX_Done will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end UART_TX;
architecture RTL of UART_TX is
type t_SM_Main is (s_Idle, s_TX_Start_Bit, s_TX_Data_Bits,
s_TX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_TX_Data : std_logic_vector(7 downto 0) := (others => '0');
signal r_TX_Done : std_logic := '0';
begin
p_UART_TX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
o_TX_Active <= '0';
o_TX_Serial <= '1'; -- Drive Line High for Idle
r_TX_Done <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if i_TX_DV = '1' then
r_TX_Data <= i_TX_Byte;
r_SM_Main <= s_TX_Start_Bit;
o_TX_Active <= '1';
else
r_SM_Main <= s_Idle;
end if;
-- Send out Start Bit. Start bit = 0
when s_TX_Start_Bit =>
o_TX_Serial <= '0';
-- Wait g_CLKS_PER_BIT-1 clock cycles for start bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Start_Bit;
else
r_Clk_Count <= 0;
r_SM_Main <= s_TX_Data_Bits;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles for data bits to finish
when s_TX_Data_Bits =>
o_TX_Serial <= r_TX_Data(r_Bit_Index);
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Clk_Count <= 0;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_TX_Stop_Bit;
end if;
end if;
-- Send out Stop bit. Stop bit = 1
when s_TX_Stop_Bit =>
o_TX_Serial <= '1';
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Stop_Bit;
else
r_TX_Done <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
o_TX_Active <= '0';
r_TX_Done <= '1';
r_SM_Main <= s_Idle;
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_TX;
o_TX_Done <= r_TX_Done;
end RTL; |
----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Transmitter. This transmitter is able
-- to transmit 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When transmit is complete o_TX_Done will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end UART_TX;
architecture RTL of UART_TX is
type t_SM_Main is (s_Idle, s_TX_Start_Bit, s_TX_Data_Bits,
s_TX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_TX_Data : std_logic_vector(7 downto 0) := (others => '0');
signal r_TX_Done : std_logic := '0';
begin
p_UART_TX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
o_TX_Active <= '0';
o_TX_Serial <= '1'; -- Drive Line High for Idle
r_TX_Done <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if i_TX_DV = '1' then
r_TX_Data <= i_TX_Byte;
r_SM_Main <= s_TX_Start_Bit;
o_TX_Active <= '1';
else
r_SM_Main <= s_Idle;
end if;
-- Send out Start Bit. Start bit = 0
when s_TX_Start_Bit =>
o_TX_Serial <= '0';
-- Wait g_CLKS_PER_BIT-1 clock cycles for start bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Start_Bit;
else
r_Clk_Count <= 0;
r_SM_Main <= s_TX_Data_Bits;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles for data bits to finish
when s_TX_Data_Bits =>
o_TX_Serial <= r_TX_Data(r_Bit_Index);
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Clk_Count <= 0;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_TX_Stop_Bit;
end if;
end if;
-- Send out Stop bit. Stop bit = 1
when s_TX_Stop_Bit =>
o_TX_Serial <= '1';
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Stop_Bit;
else
r_TX_Done <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
o_TX_Active <= '0';
r_TX_Done <= '1';
r_SM_Main <= s_Idle;
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_TX;
o_TX_Done <= r_TX_Done;
end RTL; |
----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Transmitter. This transmitter is able
-- to transmit 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When transmit is complete o_TX_Done will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end UART_TX;
architecture RTL of UART_TX is
type t_SM_Main is (s_Idle, s_TX_Start_Bit, s_TX_Data_Bits,
s_TX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_TX_Data : std_logic_vector(7 downto 0) := (others => '0');
signal r_TX_Done : std_logic := '0';
begin
p_UART_TX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
o_TX_Active <= '0';
o_TX_Serial <= '1'; -- Drive Line High for Idle
r_TX_Done <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if i_TX_DV = '1' then
r_TX_Data <= i_TX_Byte;
r_SM_Main <= s_TX_Start_Bit;
o_TX_Active <= '1';
else
r_SM_Main <= s_Idle;
end if;
-- Send out Start Bit. Start bit = 0
when s_TX_Start_Bit =>
o_TX_Serial <= '0';
-- Wait g_CLKS_PER_BIT-1 clock cycles for start bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Start_Bit;
else
r_Clk_Count <= 0;
r_SM_Main <= s_TX_Data_Bits;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles for data bits to finish
when s_TX_Data_Bits =>
o_TX_Serial <= r_TX_Data(r_Bit_Index);
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Clk_Count <= 0;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_TX_Stop_Bit;
end if;
end if;
-- Send out Stop bit. Stop bit = 1
when s_TX_Stop_Bit =>
o_TX_Serial <= '1';
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Stop_Bit;
else
r_TX_Done <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
o_TX_Active <= '0';
r_TX_Done <= '1';
r_SM_Main <= s_Idle;
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_TX;
o_TX_Done <= r_TX_Done;
end RTL; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR_checkers;
architecture behavior of LBDR_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_in)
begin
if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and Requests_in /= "00100" and
Requests_in /= "01000" and Requests_in /= "10000") then
err_header_not_empty_Requests_in_onehot <= '1';
else
err_header_not_empty_Requests_in_onehot <= '0';
end if;
end process;
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, Requests_in)
begin
if (flit_type = "100" and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
process (flit_type, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
process (flit_type, empty, cur_addr, dst_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= (N1_out and not E1_out and not W1_out) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ((E1_out and not N1_out and not S1_out) or
(E1_out and N1_out) or (E1_out and S1_out)) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out) or (W1_out and S1_out)) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (S1_out and not E1_out and not W1_out) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
end behavior; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: opcodes
-- File: opcodes.vhd
-- Author: Jiri Gaisler
-- Description: Instruction definitions according to the SPARC V8 manual.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sparc is
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
constant CASA : op3_type := "111100";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FITOQ : fpop_type := "011001100";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FQTOI : fpop_type := "011010011";
constant FSTOD : fpop_type := "011001001";
constant FSTOQ : fpop_type := "011001101";
constant FDTOS : fpop_type := "011000110";
constant FDTOQ : fpop_type := "011001110";
constant FQTOS : fpop_type := "011000111";
constant FQTOD : fpop_type := "011001011";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FSQRTQ : fpop_type := "000101011";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FADDQ : fpop_type := "001000011";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FSUBQ : fpop_type := "001000111";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FMULQ : fpop_type := "001001011";
constant FSMULD : fpop_type := "001101001";
constant FDMULQ : fpop_type := "001101110";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
constant FDIVQ : fpop_type := "001001111";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPQ : fpop_type := "001010011";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
constant FCMPEQ : fpop_type := "001010111";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
-- Alternate address space identifiers
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
-- ASIs traditionally used by LEON for SRMMU
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
-- ASIs recommended in V8 specification, appendix I
constant ASI_MMUFLUSHPROBE_V8 : std_logic_vector(4 downto 0) := "00011"; -- 0x03 i/dtlb flush/(probe)
constant ASI_MMUREGS_V8 : std_logic_vector(4 downto 0) := "00100"; -- 0x04 mmu regs access
--constant ASI_MMU_BP_V8 : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
--constant ASI_MMU_DIAG_V8 : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPUNIMP_ERR : ftt_type := "011";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY circuitb IS
PORT (SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END circuitb;
ARCHITECTURE Behavior OF circuitb IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= SW;
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= '0';
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= '0';
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= SW;
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= SW;
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= SW;
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= '1';
END Behavior; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY circuitb IS
PORT (SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END circuitb;
ARCHITECTURE Behavior OF circuitb IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= SW;
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= '0';
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= '0';
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= SW;
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= SW;
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= SW;
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= '1';
END Behavior; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY circuitb IS
PORT (SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END circuitb;
ARCHITECTURE Behavior OF circuitb IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= SW;
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= '0';
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= '0';
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= SW;
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= SW;
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= SW;
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= '1';
END Behavior; |
--------------------------------------------------------------------------------
--! @file clk_fwd.vhd
--! @brief Clock forwarding
--! @author Yuan Mei
--!
--! Allow both single_ended and differential outputs.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY clk_fwd IS
GENERIC (
INV : boolean := false;
SLEW : string := "SLOW"
);
PORT (
R : IN std_logic;
I : IN std_logic;
O : OUT std_logic;
O_P : OUT std_logic;
O_N : OUT std_logic
);
END clk_fwd;
ARCHITECTURE Behavioral OF clk_fwd IS
SIGNAL d1 : std_logic := '1';
SIGNAL d2 : std_logic := '0';
SIGNAL os : std_logic;
BEGIN
d1 <= '1' WHEN INV = false ELSE '0';
d2 <= '0' WHEN INV = false ELSE '1';
ODDR_inst : ODDR
GENERIC MAP (
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
PORT MAP (
Q => os,
C => I,
CE => '1',
D1 => d1,
D2 => d2,
R => R,
S => '0'
);
clk_fwd_obufds_inst : OBUFDS
GENERIC MAP(
IOSTANDARD => "DEFAULT",
SLEW => SLEW
)
PORT MAP (
O => O_P,
OB => O_N,
I => os
);
O <= os;
END Behavioral;
|
--Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Manejo display 7-SEGMENTOS.
--Desarrollada por Héctor Gutiérrez Palancarejo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity switch2display7seg is
port(
a : in std_logic_vector(3 downto 0);
b : out std_logic_vector(6 downto 0)
);
end switch2display7seg;
architecture rtl of switch2display7seg is
constant zero : std_logic_vector(6 downto 0) := "0000001"; -- 0
constant one : std_logic_vector(6 downto 0) := "1001111";
constant two : std_logic_vector(6 downto 0) := "0010010";
constant three : std_logic_vector(6 downto 0) := "0000110";
constant four : std_logic_vector(6 downto 0) := "1001100";
constant five : std_logic_vector(6 downto 0) := "0100100";
constant six : std_logic_vector(6 downto 0) := "0100000";
constant seven : std_logic_vector(6 downto 0) := "0001111";
constant eight : std_logic_vector(6 downto 0) := "0000000";
constant nine : std_logic_vector(6 downto 0) := "0001100";
constant ten : std_logic_vector(6 downto 0) := "0001000";
constant eleven : std_logic_vector(6 downto 0) := "1100000";
constant twelve : std_logic_vector(6 downto 0) := "0110001";
constant thirteen : std_logic_vector(6 downto 0) := "1000010";
constant fourteen : std_logic_vector(6 downto 0) := "0110000";
constant fiveteen : std_logic_vector(6 downto 0) := "0111000"; -- 15
begin
b <= not(zero) when a = "0000" else
not(one) when a = "0001" else
not(two) when a = "0010" else
not(three) when a = "0011" else
not(four) when a = "0100" else
not(five) when a = "0101" else
not(six) when a = "0110" else
not(seven) when a = "0111" else
not(eight) when a = "1000" else
not(nine) when a = "1001" else
not(ten) when a = "1010" else
not(eleven) when a = "1011" else
not(twelve) when a = "1100" else
not(thirteen) when a = "1101" else
not(fourteen) when a = "1110" else
not(fiveteen);
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity imemory is
port(
address : in vl_logic_vector(31 downto 0);
data : out vl_logic_vector(127 downto 0);
read : in vl_logic
);
end imemory;
|
library verilog;
use verilog.vl_types.all;
entity imemory is
port(
address : in vl_logic_vector(31 downto 0);
data : out vl_logic_vector(127 downto 0);
read : in vl_logic
);
end imemory;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01960ent IS
END c07s02b01x00p02n02i01960ent;
ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01960"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01960arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01960ent IS
END c07s02b01x00p02n02i01960ent;
ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01960"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01960arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01960ent IS
END c07s02b01x00p02n02i01960ent;
ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01960"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01960arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter_Demo is
port( KEY : in std_logic_vector(3 downto 3);
SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(3 downto 0);
HEX7 : out std_logic_vector(7 downto 0));
end Counter_Demo;
architecture Structural of Counter_Demo is
signal s_count : std_logic_vector(3 downto 0);
begin
-- CounterUpDown: entity work.CounterUpDown4(Behavioral)
-- port map(clk => KEY(3),
-- updown => SW(0),
-- reset => SW(1),
-- count => s_count);
--
--LEDR(3 downto 0) <= s_count;
--
-- bin7seg_core : entity work.Bin7SegDecoder(Behavioral)
-- port map(enable => not SW(1),
-- binInput => s_count,
-- decOut_n => HEX7(6 downto 0));
counterloadupdown4: entity work.CounterLoadupdown4(Behavioral)
port map(clk => KEY(3),
reset => SW(7),
enable => SW(6),
load => SW(5),
updown => SW(4),
dataIn => SW(3 downto 0),
count => s_count);
LEDR(3 downto 0) <= s_count;
bin7seg_core : entity work.Bin7SegDecoder(Behavioral)
port map(enable => not SW(6),
binInput => s_count,
decOut_n => HEX7(6 downto 0));
end Structural; |
--
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015: 2015.01 Initial revision
-- 01/2016: 2016.01 TranscriptOpen function now calls procedure of same name
-- 11/2016: 2016.l1 Added procedure BlankLine
--
--
-- Copyright (c) 2015-2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
------------------------------------------------------------
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; |
--
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015: 2015.01 Initial revision
-- 01/2016: 2016.01 TranscriptOpen function now calls procedure of same name
-- 11/2016: 2016.l1 Added procedure BlankLine
--
--
-- Copyright (c) 2015-2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
------------------------------------------------------------
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; |
--
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015: 2015.01 Initial revision
-- 01/2016: 2016.01 TranscriptOpen function now calls procedure of same name
-- 11/2016: 2016.l1 Added procedure BlankLine
--
--
-- Copyright (c) 2015-2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
------------------------------------------------------------
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1110.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01110ent IS
END c06s05b00x00p03n01i01110ent;
ARCHITECTURE c06s05b00x00p03n01i01110arch OF c06s05b00x00p03n01i01110ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01110 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01110arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1110.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01110ent IS
END c06s05b00x00p03n01i01110ent;
ARCHITECTURE c06s05b00x00p03n01i01110arch OF c06s05b00x00p03n01i01110ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01110 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01110arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1110.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01110ent IS
END c06s05b00x00p03n01i01110ent;
ARCHITECTURE c06s05b00x00p03n01i01110arch OF c06s05b00x00p03n01i01110ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01110 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01110arch;
|
library ieee;
use ieee.std_logic_ll64.all;
entity gen_ena is
port{
clk: in std_logic;
rst: in std_logic;
ena: out std_logic;
};
end;
architecture gen_ena_arq of gen_ena is
variable count: integer := 0;
begin
cont: process(clk)
begin
if rst = '1' then
ena := '0';
elsif rising_edge(clk) then
count := count + 1;
if count = '10' then
count := 0;
ena := '1';
else
ena := 0;
end if;
end if;
end; |
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clk100MhzTo40MHz.vhd
-- Megafunction Name(s):
-- altpll
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.1 Build 181 06/29/2004 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
ENTITY Clk100MhzTo40MHz IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
pllena : IN STD_LOGIC := '1';
areset : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clk100MhzTo40MHz;
ARCHITECTURE SYN OF clk100mhzto40mhz IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_duty_cycle : NATURAL;
lpm_type : STRING;
clk0_multiply_by : NATURAL;
invalid_lock_multiplier : NATURAL;
inclk0_input_frequency : NATURAL;
gate_lock_signal : STRING;
clk0_divide_by : NATURAL;
pll_type : STRING;
valid_lock_multiplier : NATURAL;
spread_frequency : NATURAL;
intended_device_family : STRING;
operation_mode : STRING;
compensate_clock : STRING;
clk0_phase_shift : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
pllena : IN STD_LOGIC ;
locked : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_duty_cycle => 50,
lpm_type => "altpll",
clk0_multiply_by => 2,
invalid_lock_multiplier => 5,
inclk0_input_frequency => 10000,
gate_lock_signal => "NO",
clk0_divide_by => 5,
pll_type => "AUTO",
valid_lock_multiplier => 1,
spread_frequency => 0,
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
compensate_clock => "CLK0",
clk0_phase_shift => "0"
)
PORT MAP (
inclk => sub_wire4,
pllena => pllena,
areset => areset,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "200.000"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix II"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz_inst.vhd FALSE FALSE
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clk100MhzTo40MHz.vhd
-- Megafunction Name(s):
-- altpll
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.1 Build 181 06/29/2004 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
ENTITY Clk100MhzTo40MHz IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
pllena : IN STD_LOGIC := '1';
areset : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clk100MhzTo40MHz;
ARCHITECTURE SYN OF clk100mhzto40mhz IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_duty_cycle : NATURAL;
lpm_type : STRING;
clk0_multiply_by : NATURAL;
invalid_lock_multiplier : NATURAL;
inclk0_input_frequency : NATURAL;
gate_lock_signal : STRING;
clk0_divide_by : NATURAL;
pll_type : STRING;
valid_lock_multiplier : NATURAL;
spread_frequency : NATURAL;
intended_device_family : STRING;
operation_mode : STRING;
compensate_clock : STRING;
clk0_phase_shift : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
pllena : IN STD_LOGIC ;
locked : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_duty_cycle => 50,
lpm_type => "altpll",
clk0_multiply_by => 2,
invalid_lock_multiplier => 5,
inclk0_input_frequency => 10000,
gate_lock_signal => "NO",
clk0_divide_by => 5,
pll_type => "AUTO",
valid_lock_multiplier => 1,
spread_frequency => 0,
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
compensate_clock => "CLK0",
clk0_phase_shift => "0"
)
PORT MAP (
inclk => sub_wire4,
pllena => pllena,
areset => areset,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "200.000"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix II"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz_inst.vhd FALSE FALSE
|
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <paulino@dte.us.es>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity port_switches_dig is port (
r : in std_logic;
clk : in std_logic;
enable : in std_logic;
port_out : out std_logic_vector (7 downto 0);
switches_in : in std_logic_vector (7 downto 0));
end port_switches_dig;
architecture behavioral of port_switches_dig is
begin
read_proc: process(clk,enable,r)
begin
if falling_edge(clk) and enable='1' and r='1' then
port_out <= switches_in;
end if;
end process;
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: arith
-- File: arith.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Declaration of mul/div components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package arith is
type div32_in_type is record
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident)
op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector(39 downto 0);
--y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
--asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
component div32
generic (scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
divi : in div32_in_type;
divo : out div32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
component mul32
generic (
tech : integer := 0;
multype : integer := 0;
pipe : integer := 0;
mac : integer := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
function smult ( a, b : in std_logic_vector) return std_logic_vector;
function umult ( a, b : in std_logic_vector) return std_logic_vector;
end;
package body arith is
function smult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : signed (a'length-1 downto 0);
variable sb : signed (b'length-1 downto 0);
variable sc : signed ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := signed(a); sb := signed(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
function umult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : unsigned (a'length-1 downto 0);
variable sb : unsigned (b'length-1 downto 0);
variable sc : unsigned ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := unsigned(a); sb := unsigned(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
end;
|
architecture rtl of fifo is
begin
process begin
wr_data <=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
end process;
end architecture rtl;
|
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4256)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4256)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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5i3mF/BDg5iCfywPaW7/PgqN5mDptLpuGf7qUQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4256)
`protect data_block
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wkEAC1PoL03sRUhXGEryma25vR7BZinD9pfRnHiwSd/Lydh6xaU=
`protect end_protected
|
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