content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc705.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:43 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:46 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00705ent IS
END c03s04b01x00p23n01i00705ent;
ARCHITECTURE c03s04b01x00p23n01i00705arch OF c03s04b01x00p23n01i00705ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
type FT is file of BIT_VECTOR5;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.57";
-- Declare a variable into which we will read.
constant CON : BIT_VECTOR5 := B"10101";
variable VAR : BIT_VECTOR5;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00705"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00705 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00705arch;
|
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity tbShifter is
end tbShifter;
architecture tb_shifter_arch of tbShifter is
constant N: integer:=32;
signal a, b : std_logic_vector(N-1 downto 0):=x"00000000";
signal o_sll, o_srl, o_sla, o_sra, o_slr_0, o_srr_0, o_slr_1, o_srr_1: std_logic_vector(N-1 downto 0):=x"00000000";
component Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0);
b : in std_logic_vector(DATA_SIZE-1 downto 0);
o : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
begin
SH0 : Shifter
generic map(N)
port map('0', '0', '0', a, b, o_sll);
SH1 : Shifter
generic map(N)
port map('1', '0', '0', a, b, o_srl);
SH2 : Shifter
generic map(N)
port map('0', '1', '0', a, b, o_sla);
SH3 : Shifter
generic map(N)
port map('1', '1', '0', a, b, o_sra);
SH4 : Shifter
generic map(N)
port map('0', '0', '1', a, b, o_slr_0);
SH5 : Shifter
generic map(N)
port map('1', '0', '1', a, b, o_srr_0);
SH6 : Shifter
generic map(N)
port map('0', '1', '1', a, b, o_slr_1);
SH7 : Shifter
generic map(N)
port map('1', '1', '1', a, b, o_srr_1);
a <= x"ffffffff", x"04532434" after 1 ns, x"2234e826" after 2 ns, x"a323f443" after 3 ns, x"8b651a8b" after 4 ns, x"ffffffff" after 5 ns;
b <= x"00000001", x"05335f28" after 1.5 ns, x"23323424" after 2.5 ns, x"11645030" after 3.5 ns, x"030035a6" after 4.5 ns, x"00000001" after 5.5 ns, x"12334224" after 7 ns;
end tb_shifter_arch;
configuration tb_shifter_cfg of tbShifter is
for tb_shifter_arch
end for;
end tb_shifter_cfg;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:55:53 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.vhdl
-- Design : system_xlconstant_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_0 : entity is "yes";
end system_xlconstant_0_0;
architecture STRUCTURE of system_xlconstant_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
dout(0) <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mips_constants is
constant ZERO : std_logic_vector(31 downto 0):=
"00000000000000000000000000000000";
constant LINK_RET : integer := 1;
constant REG_DEST : integer := 11;
constant REG2OPERATION : integer := 2;
constant ALUSRC : integer := 4;
constant MEM_TO_REG : integer := 7;
constant MEM_READ : integer := 8;
constant MEM_WRITE : integer := 5;
constant REG_WRITE : integer := 3;
constant BRANCH_BIT : integer := 9;
constant JUMP_BIT : integer := 10;
constant JUMPTOREG_BIT : integer := 0;
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
end mips_constants;
package body mips_constants is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
end;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.net.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000; -- frequency of main clock (used for PLLs)
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clk125 : in std_ulogic;
errorn : out std_ulogic;
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
--rxd1 : in std_logic;
--txd1 : out std_logic;
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
-- flash/ssram bus
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 0);
rstoutn : out std_ulogic;
sram_advn : out std_ulogic;
sram_csn : out std_logic;
sram_wen : out std_logic;
sram_ben : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_clk : out std_ulogic;
sram_psn : out std_ulogic;
sram_wait : in std_logic_vector(1 downto 0);
flash_clk : out std_ulogic;
flash_advn : out std_logic;
flash_cen : out std_logic;
flash_oen : out std_logic;
flash_resetn: out std_logic;
flash_wen : out std_logic;
max_csn : out std_logic;
-- sram_adsp_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (8 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (8 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (8 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (15 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (71 downto 0); -- ddr data
-- ddra_cke : out std_logic;
ddra_csb : out std_logic;
-- ddra_web : out std_ulogic; -- ddr write enable
-- ddra_rasb : out std_ulogic; -- ddr ras
-- ddra_casb : out std_ulogic; -- ddr cas
-- ddra_ad : out std_logic_vector (14 downto 0); -- ddr address
-- ddra_ba : out std_logic_vector (2 downto 0); -- ddr bank address
--
-- ddrb_cke : out std_logic;
ddrb_csb : out std_logic;
-- ddrb_web : out std_ulogic; -- ddr write enable
-- ddrb_rasb : out std_ulogic; -- ddr ras
-- ddrb_casb : out std_ulogic; -- ddr cas
-- ddrb_ad : out std_logic_vector (14 downto 0); -- ddr address
-- ddrb_ba : out std_logic_vector (2 downto 0); -- ddr bank address
--
-- ddrab_clk : inout std_logic_vector(1 downto 0);
-- ddrab_clkb : inout std_logic_vector(1 downto 0);
-- ddrab_odt : out std_logic_vector(1 downto 0);
-- ddrab_dqsp : inout std_logic_vector(1 downto 0); -- ddr dqs
-- ddrab_dqsn : inout std_logic_vector(1 downto 0); -- ddr dqs
-- ddrab_dm : out std_logic_vector(1 downto 0); -- ddr dm
-- ddrab_dq : inout std_logic_vector (15 downto 0);-- ddr data
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ddr_clk_fb : std_ulogic;
-- -- DDR2 Device A&B
-- signal ddrab_clkv : std_logic_vector(2 downto 0);
-- signal ddrab_clkbv : std_logic_vector(2 downto 0);
-- signal ddra_ckev : std_logic_vector(1 downto 0);
-- signal ddra_csbv : std_logic_vector(1 downto 0);
-- signal ddrb_ckev : std_logic_vector(1 downto 0);
-- signal ddrb_csbv : std_logic_vector(1 downto 0);
-- signal lockab : std_logic;
-- signal clkmlab : std_logic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sram_clkl : std_ulogic;
signal cgi,cgi2 : clkgen_in_type;
signal cgo,cgo2 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal lclk, lclkout, lclk125, clkm125 : std_ulogic;
signal dsubre : std_ulogic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
cgi2.pllctrl <= "00"; cgi2.pllrst <= not resetn; cgi2.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clk125_pad : clkpad generic map (tech => padtech) port map (clk125, lclk125);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
clkm125 <= lclk125;
phy_gtx_clk <= lclk125;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, sram_clkl);
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, sram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0 : ahbuart -- Debug UART
-- generic map (hindex => NCPU, pindex => 4, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#a00#, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
srams_pad : outpad generic map ( tech => padtech)
port map (sram_csn, vcc(0));
flash_cen_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
srams_pad : outpad generic map ( tech => padtech)
port map (sram_csn, memo.ramsn(0));
sram_oen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.oen);
sram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_ben, memo.wrn);
sram_wri_pad : outpad generic map (tech => padtech)
port map (sram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
sram_advn_pad : outpad generic map (tech => padtech)
port map (sram_advn, gnd(0));
sram_psn_pad : outpad generic map (tech => padtech)
port map (sram_psn, vcc(0));
flash_advn_pad : outpad generic map (tech => padtech)
port map (flash_advn, gnd(0));
flash_cen_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
flash_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
flash_reset_pad : outpad generic map (tech => padtech)
port map (flash_resetn, resetn);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
end generate;
max_csn_pad : outpad generic map (tech => padtech)
port map (max_csn, vcc(0));
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech,
memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => 125000/1000, rskew => 0, TRFC => CFG_DDR2SP_TRFC,
clkmul => (CFG_DDR2SP_FREQ*5)/125, clkdiv => 5, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => dbits,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
odten => 3, octen => 1, readdly => 1)
port map ( resetn, rstn, clkm125, clkm, clkm125, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, ddr_clk_fb, ddr_clk_fb, ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm(dbits/8-1 downto 0), ddr_dqsp(dbits/8-1 downto 0), ddr_dqsn(dbits/8-1 downto 0),
ddr_ad(13 downto 0), ddr_ba(1 downto 0), ddr_dq(dbits-1 downto 0), ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
ddr_ad(15 downto 14) <= (others => '0');
ddr_ba(2) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
-- Disable DDR2 Device A and B
ddra_csb <= '1';
ddrb_csb <= '1';
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
-- loopback
u1i.rxd <= u1o.txd;
--upads : if CFG_AHB_UART = 0 generate
-- u1i.rxd <= rxd1; txd1 <= u1o.txd;
--end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
gpioi.din(i) <= gpio(i);
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP3SL150 PSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity main is
port(
clk, not_reset: in std_logic;
nes_data_1: in std_logic;
nes_data_2: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0);
buzzer: out std_logic;
nes_clk_out: out std_logic;
nes_ps_control: out std_logic
);
end main;
architecture behaviour of main is
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal px_x, px_y: std_logic_vector(9 downto 0);
signal video_on: std_logic;
signal menu_rgb, plong_rgb, fpgalaxy_rgb: std_logic_vector(2 downto 0);
signal plong_buzzer, fpgalaxy_buzzer: std_logic;
signal nes1_a, nes1_b, nes1_select, nes1_start,
nes1_up, nes1_down, nes1_left, nes1_right: std_logic;
signal nes2_a, nes2_b, nes2_select, nes2_start,
nes2_up, nes2_down, nes2_left, nes2_right: std_logic;
-- signals that go into graphics logic
signal f_nes1_a, f_nes1_b, f_nes1_left, f_nes1_right: std_logic;
signal p_nes1_up, p_nes1_down, p_nes1_start,
p_nes2_up, p_nes2_down, p_nes2_start: std_logic;
-- game selection: 0 - plong, 1 - fpgalaxy
signal selected_menu: std_logic;
-- which stream is enabled:
-- 00: menu
-- 01: fpgalaxy
-- 10: plong
-- 11: don't care
signal enable, enable_next: std_logic_vector(1 downto 0);
-- sound events
signal shot, destroyed,
ball_bounced, ball_missed: std_logic;
signal buzzer1, buzzer2: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
rgb_reg <= (others => '0');
enable <= (others => '0');
elsif falling_edge(clk) then
rgb_reg <= rgb_next;
enable <= enable_next;
end if;
end process;
rgb_next <= plong_rgb when enable = "01" else
fpgalaxy_rgb when enable = "10" else
menu_rgb;
enable_next <= "01" when (enable = "00" and
selected_menu = '0' and
nes1_select = '1') else
"10" when (enable = "00" and
selected_menu = '1' and
nes1_select = '1') else
enable;
f_nes1_a <= nes1_a when enable = "10" else '0';
f_nes1_b <= nes1_a when enable = "10" else '0';
f_nes1_left <= nes1_left when enable = "10" else '0';
f_nes1_right <= nes1_right when enable = "10" else '0';
p_nes1_up <= nes1_up when enable = "01" else '0';
p_nes1_down <= nes1_down when enable = "01" else '0';
p_nes1_start <= nes1_start when enable = "01" else '0';
p_nes2_up <= nes2_up when enable = "01" else '0';
p_nes2_down <= nes2_down when enable = "01" else '0';
p_nes2_start <= nes2_start when enable = "01" else '0';
vga:
entity work.vga(sync)
port map(
clk => clk, not_reset => not_reset,
hsync => hsync, vsync => vsync,
video_on => video_on, p_tick => open,
pixel_x => px_x, pixel_y => px_y
);
menu:
entity work.menu(behaviour)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
nes_up => nes1_up, nes_down => nes1_down,
selection => selected_menu,
rgb_pixel => menu_rgb
);
fpgalaxy:
entity work.fpgalaxy_graphics(dispatcher)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
video_on => video_on,
nes_a => f_nes1_a, nes_b => f_nes1_b,
nes_left => f_nes1_left, nes_right => f_nes1_right,
rgb_stream => fpgalaxy_rgb,
shooting_sound => shot, destruction_sound => destroyed
);
plong:
entity work.plong_graphics(dispatcher)
port map(
clk => clk, not_reset => not_reset,
nes1_up => p_nes1_up, nes1_down => p_nes1_down,
nes2_up => p_nes2_up, nes2_down => p_nes2_down,
nes1_start => p_nes1_start,
nes2_start => p_nes2_start,
px_x => px_x, px_y => px_y,
video_on => video_on,
rgb_stream => plong_rgb,
ball_bounced => ball_bounced,
ball_missed => ball_missed
);
sound1:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
bump_sound => ball_bounced, miss_sound => ball_missed,
shooting_sound => shot, explosion_sound => '0',
buzzer => buzzer2
);
-- two units needed for fpgalaxy due to one sound canceling the other
buzzer <= buzzer1 or buzzer2;
sound2:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
bump_sound => ball_bounced, miss_sound => ball_missed,
shooting_sound => '0', explosion_sound => destroyed,
buzzer => buzzer1
);
NES_controller1:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data_1,
clk_out => nes_clk_out,
ps_control => nes_ps_control,
gamepad(0) => nes1_a, gamepad(1) => nes1_b,
gamepad(2) => nes1_select, gamepad(3) => nes1_start,
gamepad(4) => nes1_up, gamepad(5) => nes1_down,
gamepad(6) => nes1_left, gamepad(7) => nes1_right
);
NES_controller2:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data_2,
clk_out => open,
ps_control => open,
gamepad(0) => nes2_a, gamepad(1) => nes2_b,
gamepad(2) => nes2_select, gamepad(3) => nes2_start,
gamepad(4) => nes2_up, gamepad(5) => nes2_down,
gamepad(6) => nes2_left, gamepad(7) => nes2_right
);
rgb <= rgb_reg;
end behaviour; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc943.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p08n01i00943ent IS
END c06s01b00x00p08n01i00943ent;
ARCHITECTURE c06s01b00x00p08n01i00943arch OF c06s01b00x00p08n01i00943ent IS
BEGIN
TESTING: PROCESS
variable V1 : BIT_VECTOR(0 to 5); -- No_failure_here
BEGIN
assert NOT( V1="000000" )
report "***PASSED TEST: c06s01b00x00p08n01i00943"
severity NOTE;
assert ( V1="000000" )
report "***FAILED TEST: c06s01b00x00p08n01i00943 - The name must be a simple name, an operator symbol, a selected name, an indexed name, a slice name, or an attribute name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p08n01i00943arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc943.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p08n01i00943ent IS
END c06s01b00x00p08n01i00943ent;
ARCHITECTURE c06s01b00x00p08n01i00943arch OF c06s01b00x00p08n01i00943ent IS
BEGIN
TESTING: PROCESS
variable V1 : BIT_VECTOR(0 to 5); -- No_failure_here
BEGIN
assert NOT( V1="000000" )
report "***PASSED TEST: c06s01b00x00p08n01i00943"
severity NOTE;
assert ( V1="000000" )
report "***FAILED TEST: c06s01b00x00p08n01i00943 - The name must be a simple name, an operator symbol, a selected name, an indexed name, a slice name, or an attribute name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p08n01i00943arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc943.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p08n01i00943ent IS
END c06s01b00x00p08n01i00943ent;
ARCHITECTURE c06s01b00x00p08n01i00943arch OF c06s01b00x00p08n01i00943ent IS
BEGIN
TESTING: PROCESS
variable V1 : BIT_VECTOR(0 to 5); -- No_failure_here
BEGIN
assert NOT( V1="000000" )
report "***PASSED TEST: c06s01b00x00p08n01i00943"
severity NOTE;
assert ( V1="000000" )
report "***FAILED TEST: c06s01b00x00p08n01i00943 - The name must be a simple name, an operator symbol, a selected name, an indexed name, a slice name, or an attribute name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p08n01i00943arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
i : in bit;
o : out bit
);
end;
architecture a of ent is
signal test : std_logic_vector(7 downto 0);
alias a : std_logic_vector(3 downto 0) is test(7 downto 4);
begin
process(i)
begin
case a(1 downto 0) is
when others =>
end case;
o <= i;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clock_counter is
Port ( enable : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (31 downto 0);
done : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end clock_counter;
architecture Behavioral of clock_counter is
type state_type is (RESET,COUNT_CLOCK,COUNT_DONE);
signal state : state_type;
signal temp_count : std_logic_vector (31 downto 0);
begin
count <= temp_count;
process(clk,rst)
begin
if rst = '1' then
state <= RESET;
temp_count <= (temp_count'range => '0');
elsif rising_edge(clk) then
case state is
when RESET =>
state <= RESET;
if enable = '1' then
state <= COUNT_CLOCK;
end if;
when COUNT_CLOCK =>
if done = '1' then
temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32));
state <= COUNT_DONE;
elsif done ='0' then
temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32));
state <= COUNT_CLOCK;
else
temp_count <= temp_count;
state <= COUNT_CLOCK;
end if;
when COUNT_DONE =>
temp_count <= temp_count;
state <= COUNT_DONE;
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clock_counter is
Port ( enable : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (31 downto 0);
done : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end clock_counter;
architecture Behavioral of clock_counter is
type state_type is (RESET,COUNT_CLOCK,COUNT_DONE);
signal state : state_type;
signal temp_count : std_logic_vector (31 downto 0);
begin
count <= temp_count;
process(clk,rst)
begin
if rst = '1' then
state <= RESET;
temp_count <= (temp_count'range => '0');
elsif rising_edge(clk) then
case state is
when RESET =>
state <= RESET;
if enable = '1' then
state <= COUNT_CLOCK;
end if;
when COUNT_CLOCK =>
if done = '1' then
temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32));
state <= COUNT_DONE;
elsif done ='0' then
temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32));
state <= COUNT_CLOCK;
else
temp_count <= temp_count;
state <= COUNT_CLOCK;
end if;
when COUNT_DONE =>
temp_count <= temp_count;
state <= COUNT_DONE;
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clock_counter is
Port ( enable : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (31 downto 0);
done : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end clock_counter;
architecture Behavioral of clock_counter is
type state_type is (RESET,COUNT_CLOCK,COUNT_DONE);
signal state : state_type;
signal temp_count : std_logic_vector (31 downto 0);
begin
count <= temp_count;
process(clk,rst)
begin
if rst = '1' then
state <= RESET;
temp_count <= (temp_count'range => '0');
elsif rising_edge(clk) then
case state is
when RESET =>
state <= RESET;
if enable = '1' then
state <= COUNT_CLOCK;
end if;
when COUNT_CLOCK =>
if done = '1' then
temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32));
state <= COUNT_DONE;
elsif done ='0' then
temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32));
state <= COUNT_CLOCK;
else
temp_count <= temp_count;
state <= COUNT_CLOCK;
end if;
when COUNT_DONE =>
temp_count <= temp_count;
state <= COUNT_DONE;
end case;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_test is
end tb_test;
architecture test of tb_test is
signal clk : std_logic := '0';
signal clr : std_logic := '1';
signal bcnt, lcnt : unsigned(3 downto 0);
signal btop, ltop : std_logic;
component cntr is
port (
clk : in std_logic;
clr : in std_logic;
count : out unsigned(3 downto 0);
top : out std_logic
);
end component;
component lfsr is
port (
clk : in std_logic;
clr : in std_logic;
count : out unsigned(3 downto 0);
top : out std_logic
);
end component;
begin
bcntr : cntr port map (
clk => clk, clr => clr, count => bcnt, top => btop);
lcntr : lfsr port map (
clk => clk, clr => clr, count => lcnt, top => ltop);
clk <= not clk after 5 ns;
process
begin
wait for 20 ns;
clr <= '1';
wait for 10 ns;
clr <= '0';
wait;
end process;
end test;
|
entity submodule is
port (
sig : in bit);
end entity;
architecture a of submodule is
begin
main : process
begin
wait for 1 ns;
assert sig = '1';
report "Success";
wait;
end process;
end;
entity issue340 is
end entity;
architecture a of issue340 is
signal sig_vector : bit_vector(0 to 1) := "00";
alias sig_bit_alias : bit is sig_vector(0);
signal sig : bit := '0';
alias sig_alias : bit is sig;
procedure drive(signal value : out bit) is
begin
value <= '1';
end;
begin
main : process
begin
drive(sig_alias);
drive(sig_bit_alias);
wait for 1 ns;
assert sig_vector(0) = '1';
assert sig = '1';
assert sig_alias = '1';
assert sig_bit_alias = '1';
report "Success";
wait;
end process;
submodule0_inst : entity work.submodule
port map (
sig => sig_alias);
submodule1_inst : entity work.submodule
port map (
sig => sig_bit_alias);
submodule2_inst : entity work.submodule
port map (
sig => sig);
submodule3_inst : entity work.submodule
port map (
sig => sig_vector(0));
end;
|
entity submodule is
port (
sig : in bit);
end entity;
architecture a of submodule is
begin
main : process
begin
wait for 1 ns;
assert sig = '1';
report "Success";
wait;
end process;
end;
entity issue340 is
end entity;
architecture a of issue340 is
signal sig_vector : bit_vector(0 to 1) := "00";
alias sig_bit_alias : bit is sig_vector(0);
signal sig : bit := '0';
alias sig_alias : bit is sig;
procedure drive(signal value : out bit) is
begin
value <= '1';
end;
begin
main : process
begin
drive(sig_alias);
drive(sig_bit_alias);
wait for 1 ns;
assert sig_vector(0) = '1';
assert sig = '1';
assert sig_alias = '1';
assert sig_bit_alias = '1';
report "Success";
wait;
end process;
submodule0_inst : entity work.submodule
port map (
sig => sig_alias);
submodule1_inst : entity work.submodule
port map (
sig => sig_bit_alias);
submodule2_inst : entity work.submodule
port map (
sig => sig);
submodule3_inst : entity work.submodule
port map (
sig => sig_vector(0));
end;
|
-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_xfirst_gen_unisim - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_xfirst_gen_unisim;
architecture syn of ram_1swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => O"000000000000",
SRVAL => O"000000000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(36*i+31 downto 36*i),
DOP => L_DO(36*i+35 downto 36*i+32),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(36*i+31 downto 36*i),
DIP => L_DI(36*i+35 downto 36*i+32),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => X"00000000",
SRVAL => X"00000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(32*i+31 downto 32*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(32*i+31 downto 32*i),
DIP => "0000",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => O"000000",
SRVAL => O"000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(18*i+15 downto 18*i),
DOP => L_DO(18*i+17 downto 18*i+16),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(18*i+15 downto 18*i),
DIP => L_DI(18*i+17 downto 18*i+16),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => X"0000",
SRVAL => X"0000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(16*i+15 downto 16*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(16*i+15 downto 16*i),
DIP => "00",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => O"000",
SRVAL => O"000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(9*i+7 downto 9*i),
DOP => L_DO(9*i+8 downto 9*i+8),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(9*i+7 downto 9*i),
DIP => L_DI(9*i+8 downto 9*i+8),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => X"00",
SRVAL => X"00",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(8*i+7 downto 8*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(8*i+7 downto 8*i),
DIP => "0",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4
generic map (
INIT => X"0",
SRVAL => X"0",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(4*i+3 downto 4*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(4*i+3 downto 4*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2
generic map (
INIT => "00",
SRVAL => "00",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(2*i+1 downto 2*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(2*i+1 downto 2*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1
generic map (
INIT => "0",
SRVAL => "0",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(i downto i),
ADDR => ADDR,
CLK => CLK,
DI => DI(i downto i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FSM_clock is
port( clock, reset: in std_logic;
c1, c2: out std_logic
);
end FSM_clock;
architecture bhv of FSM_clock is
signal contador_1, contador_2 : integer := 0;--definido signal como inteiro para os valores da frequência de entrada e 1/4 dela.
begin
P1: process(clock, reset)--process que vai definir o clock de 1hz para o contador ascendente do tempo.
begin
if reset= '0' then
contador_1 <= 0;
elsif clock'event and clock= '1' then
contador_1 <= contador_1 + 1;
if contador_1 >= 50000000 then
contador_1 <= 0;
c1 <= '1';
else
c1 <= '0';
end if;
end if;
end process;
P2: process(clock, reset)--vai definir o clock de 4hz para a contagem decrescente dos créditos.
begin
if reset= '0' then
contador_2 <= 0;
elsif clock'event and clock= '1' then
contador_2 <= contador_2 + 1;
if contador_2 >= 12500000 then
contador_2 <= 0;
c2 <= '1';
else
c2 <= '0';
end if;
end if;
end process;
end bhv;
|
entity tb_my_entity is
end tb_my_entity;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_my_entity is
signal a : std_logic_vector(0 downto 0);
begin
dut: entity work.my_entity
port map (a);
process
begin
wait for 1 ns;
assert a = "0" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tdc_application_pkg is
type tdc_events_t is
record
cnt_ov: std_logic;
d1_risings: std_logic_vector(3 downto 0);
d2_risings: std_logic_vector(3 downto 0);
a_maximum: std_logic_vector(1 downto 0);
end record;
function tdc_event(x: adc_sample_t) return std_logic_vector;
function to_adc_sample_t(x: std_logic_vector) return adc_sample_t;
end tdc_application_pkg;
package body tdc_application_pkg is
function to_std_logic_vector(x: adc_sample_t) return std_logic_vector is
variable result: std_logic_vector(ADC_SAMPLE_BITS downto 0);
begin
result(ADC_SAMPLE_BITS) := x.ovfl;
result(ADC_SAMPLE_BITS-1 downto 0) := std_logic_vector(x.data);
return result;
end to_std_logic_vector;
function to_adc_sample_t(x: std_logic_vector) return adc_sample_t is
variable result: adc_sample_t;
begin
result.ovfl := x(x'low + ADC_SAMPLE_BITS);
result.data := std_logic_vector(x(x'low + ADC_SAMPLE_BITS-1 downto x'low));
return result;
end to_adc_sample_t;
end tdc_application_pkg;
|
use std.textio.all;entity testing is end;architecture s of testing is
begin
write(output,"pong");end; |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00490
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (3)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00490(ARCH00490)
-- ENT00490_Test_Bench(ARCH00490_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00490 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - g_r1 to g_r1 ;
-- f2 : rec_arr (-g_r1 to g_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-g_r1 to g_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range g_a11 to g_a12 ;
subtype arange2 is integer range g_a21 to g_a22 ;
subtype brange1 is integer range g_b11 to g_b12 ;
subtype brange2 is integer range g_b21 to g_b22 ;
subtype crange is integer range g_c1 to g_c2 ;
subtype drange is integer range g_d1 to g_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00490 ;
--
architecture ARCH00490 of ENT00490 is
begin
B1 :
block
generic ( g_arr_1 : st_arr_1 ;
g_time_matrix : st_time_matrix ;
g_bit_vector : st_bit_vector ;
g_string : st_string ;
g_rec_1 : rec_1 ) ;
generic map ( ( others => (others => c_rec_1_1) ) ,
( others => (others => 15ms) ) ,
( others => '0' ) ,
( others => 'a' ) ,
-- ( f2 => (others => false), others => 0) ) ;
( others => 0) ) ;
--
procedure p3
is
variable bool : boolean := true ;
begin
for i in 1 to 5 loop
bool := bool and g_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and g_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and g_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and g_bit_vector = B"00000" ;
--
bool := bool and g_string = "aaa" ;
--
bool := bool and g_rec_1.f1 = 0 and g_rec_1.f4 = 0
and g_rec_1.f3 = 0 ;
-- bool := bool and g_rec_1.f2(1) = false
-- and g_rec_1.f2(0) = false and
-- g_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00490" ,
"Aggregates with others choice associated with formal"
& " generic (generic and dynamic)" ,
bool ) ;
--
end p3;
procedure p2 (
constant d_a11 : boolean := false ;
constant d_a12 : boolean := true ;
constant d_a21 : integer := 1 ;
constant d_a22 : integer := 5 ;
constant d_b11 : integer := 0 ;
constant d_b12 : integer := 0 ;
constant d_b21 : integer := -5 ;
constant d_b22 : integer := -3 ;
constant d_c1 : integer := 0 ;
constant d_c2 : integer := 4 ;
constant d_d1 : integer := 3 ;
constant d_d2 : integer := 5 ;
constant d_r1 : integer := 1
)
is
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - d_r1 to d_r1 ;
-- f2 : rec_arr (-d_r1 to d_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-d_r1 to d_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range d_a11 to d_a12 ;
subtype arange2 is integer range d_a21 to d_a22 ;
subtype brange1 is integer range d_b11 to d_b12 ;
subtype brange2 is integer range d_b21 to d_b22 ;
subtype crange is integer range d_c1 to d_c2 ;
subtype drange is integer range d_d1 to d_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
procedure p1 ( p_arr_1 : st_arr_1 ;
p_time_matrix : st_time_matrix ;
p_bit_vector : st_bit_vector ;
p_string : st_string ;
p_rec_1 : rec_1 ) is
variable bool : boolean := true ;
begin
for i in 1 to 5 loop
bool := bool and p_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and p_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and p_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and p_bit_vector = B"00000" ;
--
bool := bool and p_string = "aaa" ;
--
bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0
and p_rec_1.f3 = 0 ;
-- bool := bool and p_rec_1.f2(1) = false
-- and p_rec_1.f2(0) = false and
-- p_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00490" ,
"Aggregates with others choice associated with formal"
& " parameter (generic and dynamic)" ,
bool ) ;
end p1 ;
begin
p1 ( ( others => (others => c_rec_1_1) ) ,
( others => (others => 15ms) ) ,
( others => '0' ) ,
( others => 'a' ) ,
-- ( f2 => (others => false), others => 0) ) ;
( others => 0) ) ;
p3 ;
end p2 ;
begin
process
begin
p2( open, open, open, open, open, open, open, open,
open, open, open, open, open ) ;
wait ;
end process ;
end block B1 ;
end ARCH00490 ;
--
entity ENT00490_Test_Bench is
end ENT00490_Test_Bench ;
--
architecture ARCH00490_Test_Bench of ENT00490_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00490 ( ARCH00490 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00490_Test_Bench ;
|
architecture rtl of fifo is
ALIAS designator is name;
ALIAS designator is name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram05 is
port (
rst : std_logic;
clk_i : std_logic;
addr_i : std_logic_vector(3 downto 0);
data_i : std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
wen_i : std_logic);
end sram05;
architecture behav of sram05 is
begin
process (clk_i, addr_i)
type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
variable mem : mem_type;
variable addr : natural range mem_type'range;
begin
if rising_edge(clk_i) then
if rst = '1' then
null;
else
addr := to_integer (unsigned (addr_i));
if wen_i = '1' then
mem (addr) := data_i;
end if;
data_o <= mem (addr);
end if;
end if;
end process;
end behav;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The BitwiseNorInstructionExecutor entity
entity BitwiseNorInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end BitwiseNorInstructionExecutor;
architecture BitwiseNorInstructionExecutorImpl of BitwiseNorInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
result <= arg0 nor arg1;
state <= store_result;
when store_result =>
register_address <= AccumulatorRegister;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end BitwiseNorInstructionExecutorImpl;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
variable x : std_logic;
begin -- process
assert std_logic'pos('U') = 0 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('X') = 1 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('0') = 2 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('1') = 3 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('Z') = 4 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('W') = 5 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('L') = 6 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('H') = 7 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('-') = 8 report "TEST FAILED" severity FAILURE;
assert x'left = 'U' report "TEST FAILED" severity FAILURE;
assert x'right = '-' report "TEST FAILED" severity FAILURE;
assert x'high = '-' report "TEST FAILED" severity FAILURE;
assert x'low = 'U' report "TEST FAILED" severity FAILURE;
assert x'ascending = true report "TEST FAILED" severity FAILURE;
assert std_logic'image('U') = "'U'" report "TEST FAILED" severity FAILURE;
assert std_logic'value("'U'") = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'val(0) = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'succ('U') = 'X' report "TEST FAILED" severity FAILURE;
assert std_logic'pred('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'leftof('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'rightof('U') = 'X' report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
variable x : std_logic;
begin -- process
assert std_logic'pos('U') = 0 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('X') = 1 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('0') = 2 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('1') = 3 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('Z') = 4 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('W') = 5 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('L') = 6 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('H') = 7 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('-') = 8 report "TEST FAILED" severity FAILURE;
assert x'left = 'U' report "TEST FAILED" severity FAILURE;
assert x'right = '-' report "TEST FAILED" severity FAILURE;
assert x'high = '-' report "TEST FAILED" severity FAILURE;
assert x'low = 'U' report "TEST FAILED" severity FAILURE;
assert x'ascending = true report "TEST FAILED" severity FAILURE;
assert std_logic'image('U') = "'U'" report "TEST FAILED" severity FAILURE;
assert std_logic'value("'U'") = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'val(0) = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'succ('U') = 'X' report "TEST FAILED" severity FAILURE;
assert std_logic'pred('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'leftof('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'rightof('U') = 'X' report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
variable x : std_logic;
begin -- process
assert std_logic'pos('U') = 0 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('X') = 1 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('0') = 2 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('1') = 3 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('Z') = 4 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('W') = 5 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('L') = 6 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('H') = 7 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('-') = 8 report "TEST FAILED" severity FAILURE;
assert x'left = 'U' report "TEST FAILED" severity FAILURE;
assert x'right = '-' report "TEST FAILED" severity FAILURE;
assert x'high = '-' report "TEST FAILED" severity FAILURE;
assert x'low = 'U' report "TEST FAILED" severity FAILURE;
assert x'ascending = true report "TEST FAILED" severity FAILURE;
assert std_logic'image('U') = "'U'" report "TEST FAILED" severity FAILURE;
assert std_logic'value("'U'") = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'val(0) = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'succ('U') = 'X' report "TEST FAILED" severity FAILURE;
assert std_logic'pred('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'leftof('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'rightof('U') = 'X' report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity note;
wait;
end process;
end only;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_tb is
end entity uart_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tb is
-- component ports
signal txd : std_logic := '1';
signal rxd : std_logic := '1';
signal rxd_combined : std_logic := '1';
signal din : std_logic_vector(7 downto 0) := (others => '0');
signal dout : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic := '0';
signal we : std_logic := '0';
signal error : std_logic := '0';
signal full : std_logic := '0';
signal clk_en : std_logic := '0';
signal clk : std_logic := '0';
begin
rxd_combined <= rxd and txd;
-- component instantiation
dut : uart
port map (
txd_p => txd,
rxd_p => rxd_combined,
din_p => din,
empty_p => empty,
re_p => re,
dout_p => dout,
we_p => we,
error_p => error,
full_p => full,
clk_en => clk_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_en <= '1';
wait until rising_edge(clk);
clk_en <= '0';
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
-- transmission from extern
uart_transmit(rxd, "001111100", 5000000);
wait for 10 us;
uart_transmit(rxd, "101011100", 5000000);
wait for 1 us;
uart_transmit(rxd, "101011101", 5000000);
wait;
end process waveform;
fifo : process
begin
wait for 3 us;
empty <= '0';
din <= "00000000";
wait until falling_edge(re);
din <= "11001010";
wait until falling_edge(re);
din <= "00001011";
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
wait;
end process fifo;
end architecture behavourial;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_tb is
end entity uart_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tb is
-- component ports
signal txd : std_logic := '1';
signal rxd : std_logic := '1';
signal rxd_combined : std_logic := '1';
signal din : std_logic_vector(7 downto 0) := (others => '0');
signal dout : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic := '0';
signal we : std_logic := '0';
signal error : std_logic := '0';
signal full : std_logic := '0';
signal clk_en : std_logic := '0';
signal clk : std_logic := '0';
begin
rxd_combined <= rxd and txd;
-- component instantiation
dut : uart
port map (
txd_p => txd,
rxd_p => rxd_combined,
din_p => din,
empty_p => empty,
re_p => re,
dout_p => dout,
we_p => we,
error_p => error,
full_p => full,
clk_en => clk_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_en <= '1';
wait until rising_edge(clk);
clk_en <= '0';
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
-- transmission from extern
uart_transmit(rxd, "001111100", 5000000);
wait for 10 us;
uart_transmit(rxd, "101011100", 5000000);
wait for 1 us;
uart_transmit(rxd, "101011101", 5000000);
wait;
end process waveform;
fifo : process
begin
wait for 3 us;
empty <= '0';
din <= "00000000";
wait until falling_edge(re);
din <= "11001010";
wait until falling_edge(re);
din <= "00001011";
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
wait;
end process fifo;
end architecture behavourial;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.ALL;
package memory_pack is
constant CPU_MEM_RANGE : natural := 25;
constant CPU_MEM_SIZE : std_logic_vector(CPU_MEM_RANGE - 1 downto 0) := '1' & x"a2_0014";
constant CPU_MEM_SIZE_RANGE : natural := to_integer(unsigned(CPU_MEM_SIZE));
type t_cpu_memory is array(CPU_MEM_SIZE_RANGE - 1 downto 0) of t_cpu_mem_word;
subtype t_prog_addr is std_logic_vector(CPU_MEM_RANGE - 1 downto 0);
subtype t_data_addr is std_logic_vector(CPU_MEM_RANGE - 1 downto 0);
component memory is
port(
clk : in std_logic;
rst : in std_logic;
wr_mask : in t_cpu_mask;
rd_mask : in t_cpu_mask;
instr_stall : out std_logic;
data_stall : out std_logic;
prog_addr : in t_cpu_word;
data_addr : in t_cpu_word;
prog_out : out t_cpu_word;
data_in : in t_cpu_word;
data_out : out t_cpu_word
);
end component memory;
procedure read_instr( signal instr : out t_cpu_word;
addr : in t_prog_addr;
memory : t_cpu_memory );
procedure read_heap( signal data : out t_cpu_word;
signal data_in : in t_cpu_word;
addr : in t_data_addr;
mask : in t_cpu_mask;
memory : t_cpu_memory );
procedure write_heap(signal data : in t_cpu_word;
addr : in t_data_addr;
mask : in t_cpu_mask;
variable memory : out t_cpu_memory );
end package memory_pack;
package body memory_pack is
procedure read_instr( signal instr : out t_cpu_word;
addr : in t_prog_addr;
memory : t_cpu_memory ) is
variable i_addr : natural := 0;
begin
i_addr := to_integer(unsigned(addr));
instr(31 downto 24) <= memory(i_addr );
instr(23 downto 16) <= memory(i_addr + 1);
instr(15 downto 8) <= memory(i_addr + 2);
instr( 7 downto 0) <= memory(i_addr + 3);
end procedure read_instr;
procedure read_heap( signal data : out t_cpu_word;
signal data_in : in t_cpu_word;
addr : in t_data_addr;
mask : in t_cpu_mask;
memory : t_cpu_memory ) is
variable i_addr : natural := 0;
begin
i_addr := to_integer(unsigned(addr));
case mask is
when CPU_MASK_READ8 =>
data(31 downto 24) <= memory(i_addr );
data(23 downto 16) <= memory(i_addr );
data(15 downto 8) <= memory(i_addr );
data( 7 downto 0) <= memory(i_addr );
when CPU_MASK_READ16 =>
data(31 downto 24) <= memory(i_addr );
data(23 downto 16) <= memory(i_addr + 1);
data(15 downto 8) <= memory(i_addr );
data( 7 downto 0) <= memory(i_addr + 1);
when CPU_MASK_READ32 =>
data(31 downto 24) <= memory(i_addr );
data(23 downto 16) <= memory(i_addr + 1);
data(15 downto 8) <= memory(i_addr + 2);
data( 7 downto 0) <= memory(i_addr + 3);
when others =>
data <= (others => '0');
end case;
end procedure read_heap;
procedure write_heap(signal data : in t_cpu_word;
addr : in t_data_addr;
mask : in t_cpu_mask;
variable memory : out t_cpu_memory ) is
variable i_addr : natural := 0;
begin
i_addr := to_integer(unsigned(addr));
case mask is
when CPU_MASK_WRITE8 =>
memory(i_addr ) := data( 7 downto 0);
when CPU_MASK_WRITE16 =>
memory(i_addr + 1) := data( 7 downto 0);
memory(i_addr ) := data(15 downto 8);
when CPU_MASK_WRITE32 =>
memory(i_addr + 3) := data( 7 downto 0);
memory(i_addr + 2) := data(15 downto 8);
memory(i_addr + 1) := data(23 downto 16);
memory(i_addr ) := data(31 downto 24);
when others =>
end case;
end procedure write_heap;
end package body memory_pack;
library IEEE;
use IEEE.std_logic_1164.ALL;
library WORK;
use WORK.cpu_pack.t_cpu_mask;
use WORK.cpu_pack.t_cpu_word;
library WORK;
use WORK.memory_pack.ALL;
entity memory is
port(
clk : in std_logic;
rst : in std_logic;
wr_mask : in t_cpu_mask;
rd_mask : in t_cpu_mask;
instr_stall : out std_logic;
data_stall : out std_logic;
prog_addr : in t_cpu_word;
data_addr : in t_cpu_word;
prog_out : out t_cpu_word;
data_in : in t_cpu_word;
data_out : out t_cpu_word
);
end entity memory;
architecture behav_memory of memory is
shared variable ram : t_cpu_memory;
alias inst_addr : t_prog_addr is prog_addr(CPU_MEM_RANGE - 1 downto 0);
alias heap_addr : t_data_addr is data_addr(CPU_MEM_RANGE - 1 downto 0);
begin
memory_access:
process( clk )
begin
if falling_edge( clk ) then
-- ########### READ INSTRUCTION ###################
read_instr( prog_out, inst_addr, ram );
-- ########### READ HEAP ##########################
read_heap( data_out, data_in, heap_addr, rd_mask, ram );
-- ########### WRITE HEAP #########################
write_heap( data_in, heap_addr, wr_mask, ram );
end if;
end process;
instr_stall <= '0';
data_stall <= '0';
end behav_memory;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rec2 is
port (
clk : in std_logic;
sl_in : in std_logic;
slv_in : in std_logic_vector(7 downto 0);
int_in : in integer range 0 to 15;
usig_in : in unsigned(7 downto 0);
sl_out : out std_logic;
slv_out : out std_logic_vector(7 downto 0);
int_out : out integer range 0 to 15;
usig_out : out unsigned(7 downto 0)
);
end rec2;
architecture rtl of rec2 is
type t_record is record
sl : std_logic;
slv : std_logic_vector(7 downto 0);
int : integer range 0 to 15;
usig : unsigned(7 downto 0);
end record t_record;
signal sample_record : t_record;
begin
process(clk)
begin
if rising_edge(clk) then
sample_record.sl <= sl_in;
sample_record.slv <= slv_in;
sample_record.int <= int_in;
sample_record.usig <= usig_in;
end if;
end process;
sl_out <= sample_record.sl;
slv_out <= sample_record.slv;
int_out <= sample_record.int;
usig_out <= sample_record.usig;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Syndrome_Computing
-- Module Name: Controller_Polynomial_Syndrome_Computing
-- Project Name: McEliece Goppa decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Decoding.
--
-- This circuit is the state machine for polynomial_syndrome_computing_n_v2.
-- This state machine is for both during syndrome computation and polynomial sigma
-- evaluation and roots search.
--
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_polynomial_syndrome_computing is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_syndrome_ce : out STD_LOGIC;
ctr_address_polynomial_syndrome_load : out STD_LOGIC;
ctr_address_polynomial_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_polynomial_syndrome_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_mode_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
computation_finalized : out STD_LOGIC
);
end controller_polynomial_syndrome_computing;
architecture Behavioral of controller_polynomial_syndrome_computing is
type State is (reset, poly_load_counter, poly_load_first_polynomial_coefficient, poly_reset_first_polynomial_coefficient, poly_prepare_load_polynomial_coefficient, poly_load_polynomial_coefficient, poly_reset_polynomial_coefficient, poly_load_x, poly_load_x_write_x, poly_last_load_x_write_x, poly_write_x, poly_final,
synd_load_counter, synd_load_L_syndrome_values, synd_prepare_write_load_L_values, synd_write_load_L_values, synd_prepare_write_L_values, synd_write_L_values, synd_write_syndrome_values, synd_last_write_syndrome_values, synd_final_write_syndrome_values, synd_final_last_write_syndrome_values, synd_final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
end if;
when poly_prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
end if;
when poly_load_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '1';
when synd_load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_load_L_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_prepare_write_load_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_load_L_values =>
if(last_load_x_values = '1') then
ctr_load_x_address_ce <= '0';
else
ctr_load_x_address_ce <= '1';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_prepare_write_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_L_values =>
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_ce <= '1';
else
reg_final_syndrome_evaluation_ce <= '0';
end if;
if(last_store_x_values = '1') then
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
reg_store_temporary_syndrome_ce <= '1';
shift_polynomial_ce_rst <= '1';
else
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
reg_store_temporary_syndrome_ce <= '0';
shift_polynomial_ce_rst <= '0';
end if;
evaluation_data_in <= '1';
ctr_load_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '0';
shift_polynomial_ce_ce <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_last_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final_write_syndrome_values =>
if(final_syndrome_evaluation = '1' and last_syndrome_value = '0') then
write_enable_new_value_syndrome <= '0';
else
write_enable_new_value_syndrome <= '1';
end if;
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_rst <= '1';
else
reg_final_syndrome_evaluation_rst <= '0';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final_last_write_syndrome_values =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, mode_polynomial_syndrome, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
if(mode_polynomial_syndrome = '1') then
next_state <= synd_load_counter;
else
next_state <= poly_load_counter;
end if;
when poly_load_counter =>
next_state <= poly_load_first_polynomial_coefficient;
when poly_load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= poly_reset_first_polynomial_coefficient;
else
next_state <= poly_load_first_polynomial_coefficient;
end if;
when poly_reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
else
next_state <= poly_reset_first_polynomial_coefficient;
end if;
when poly_prepare_load_polynomial_coefficient =>
next_state <= poly_load_polynomial_coefficient;
when poly_load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= poly_reset_polynomial_coefficient;
else
next_state <= poly_load_polynomial_coefficient;
end if;
when poly_reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
else
next_state <= poly_reset_polynomial_coefficient;
end if;
when poly_load_x =>
next_state <= poly_load_x_write_x;
when poly_load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= poly_last_load_x_write_x;
else
next_state <= poly_prepare_load_polynomial_coefficient;
end if;
else
next_state <= poly_load_x_write_x;
end if;
when poly_last_load_x_write_x =>
next_state <= poly_write_x;
when poly_write_x =>
if(last_store_x_values = '1') then
next_state <= poly_final;
else
next_state <= poly_write_x;
end if;
when poly_final =>
next_state <= poly_final;
when synd_load_counter =>
next_state <= synd_load_L_syndrome_values;
when synd_load_L_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_prepare_write_load_L_values;
else
next_state <= synd_load_L_syndrome_values;
end if;
when synd_prepare_write_load_L_values =>
next_state <= synd_write_load_L_values;
when synd_write_load_L_values =>
if(last_load_x_values = '1') then
next_state <= synd_prepare_write_L_values;
else
next_state <= synd_write_load_L_values;
end if;
when synd_prepare_write_L_values =>
next_state <= synd_write_L_values;
when synd_write_L_values =>
if(last_store_x_values = '1') then
if(final_syndrome_evaluation = '1' or last_syndrome_value = '1') then
next_state <= synd_final_write_syndrome_values;
else
next_state <= synd_write_syndrome_values;
end if;
else
next_state <= synd_write_L_values;
end if;
when synd_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_last_write_syndrome_values;
else
next_state <= synd_write_syndrome_values;
end if;
when synd_last_write_syndrome_values =>
next_state <= synd_write_load_L_values;
when synd_final_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_final_last_write_syndrome_values;
else
next_state <= synd_final_write_syndrome_values;
end if;
when synd_final_last_write_syndrome_values =>
next_state <= synd_final;
when synd_final =>
next_state <= synd_final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: game_over_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY game_over_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE game_over_synth_ARCH OF game_over_synth IS
COMPONENT game_over_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: game_over_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity raw_uvc is
port (
-- raw signals
raw_en : in std_logic;
raw_bytes : in std_logic_vector(23 downto 0);
raw_fifo_full : out std_logic;
error : out std_logic;
raw_clk : in std_logic;
raw_enable : in std_logic;
-- USB signals
slwr : out std_logic;
pktend : out std_logic;
fdata : out std_logic_vector(7 downto 0);
flag_full : in std_logic;
ifclk : in std_logic;
faddr : in std_logic_vector(1 downto 0);
uvcin : in std_logic_vector(1 downto 0);
header : in std_logic;
to_send : in std_logic_vector(23 downto 0);
-- others
uvc_in_free : out std_logic;
uvc_rst : in std_logic
);
end entity raw_uvc;
architecture rtl of raw_uvc is
COMPONENT rawUVCfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
signal fid : std_logic;
signal eof : std_logic;
signal total_send: std_logic_vector(23 downto 0);
signal dout: std_logic_vector(23 downto 0);
signal wrightcount: std_logic_vector(11 downto 0);
signal watchdog: std_logic_vector(5 downto 0);
signal count: std_logic_vector(1 downto 0);
signal raw_en_i : std_logic;
signal full,empty,almost_empty,valid,rd_en : std_logic;
type states is (wait_for_uvc,uvc_wait,uvc_in_pktend,uvc_send_data,s_reset,free_uvc,s_skip);
signal ps : states;
begin
syncProc: process(uvc_rst,ifclk)
begin
if uvc_rst = '1' then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
wrightcount <= (others => '0');
watchdog <= (others => '0');
ps <= s_reset;
eof <= '0';
elsif falling_edge(ifclk) then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
case ps is
when s_reset =>
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
ps <= wait_for_uvc;
fdata <= (others => '0');
watchdog <= (others => '0');
wrightcount <= (others => '0');
total_send <= (others => '0');
count <= (others => '0');
when wait_for_uvc =>
if faddr = uvcin and raw_enable = '1' then
ps <= uvc_wait;
uvc_in_free <= '0';
end if;
when uvc_send_data =>
if empty = '0' and flag_full = '1' then
wrightcount <= wrightcount +1;
if header = '1' then
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
elsif wrightcount = X"000" then
slwr <= '0';
fdata <= X"0C"; -- header length
elsif wrightcount = X"001" then
slwr <= '0';
fdata <= ( "100000" & eof & fid ); -- EOH ERR STI RES SCR PTS EOF FID
eof <= '0';
elsif wrightcount = X"002" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"003" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"004" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"005" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"006" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"007" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"008" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"009" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00A" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00B" then
slwr <= '0';
fdata <= X"00";
else -- header sent
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
if (total_send = to_send - 1012) then
eof <= '1';
end if;
end if;
else -- if header not send
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
else
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
end if; -- end if header
end if; -- end if empty
-- else
-- ps <= uvc_wait;
end if;
when uvc_wait =>
watchdog <= watchdog + 1;
if empty = '0' and flag_full = '1' then
ps <= uvc_send_data;
watchdog <= (others => '0');
elsif watchdog(watchdog'range) = (watchdog'range => '1') then
ps <= free_uvc;
watchdog <= (others => '0');
end if;
when uvc_in_pktend =>
pktend <= '0';
ps <= free_uvc;
when free_uvc =>
uvc_in_free <= '1';
ps <= s_skip;
when s_skip =>
ps <= wait_for_uvc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
raw_en_i <= (raw_en and raw_enable);
rawUVCfifo_Comp : rawUVCfifo
PORT MAP (
rst => uvc_rst,
wr_clk => raw_clk,
rd_clk => ifclk,
din => raw_bytes,
wr_en => raw_en_i,
rd_en => rd_en,
dout => dout,
full => full,
-- almost_full => raw_fifo_full,
prog_full => raw_fifo_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
end rtl; |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity raw_uvc is
port (
-- raw signals
raw_en : in std_logic;
raw_bytes : in std_logic_vector(23 downto 0);
raw_fifo_full : out std_logic;
error : out std_logic;
raw_clk : in std_logic;
raw_enable : in std_logic;
-- USB signals
slwr : out std_logic;
pktend : out std_logic;
fdata : out std_logic_vector(7 downto 0);
flag_full : in std_logic;
ifclk : in std_logic;
faddr : in std_logic_vector(1 downto 0);
uvcin : in std_logic_vector(1 downto 0);
header : in std_logic;
to_send : in std_logic_vector(23 downto 0);
-- others
uvc_in_free : out std_logic;
uvc_rst : in std_logic
);
end entity raw_uvc;
architecture rtl of raw_uvc is
COMPONENT rawUVCfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
signal fid : std_logic;
signal eof : std_logic;
signal total_send: std_logic_vector(23 downto 0);
signal dout: std_logic_vector(23 downto 0);
signal wrightcount: std_logic_vector(11 downto 0);
signal watchdog: std_logic_vector(5 downto 0);
signal count: std_logic_vector(1 downto 0);
signal raw_en_i : std_logic;
signal full,empty,almost_empty,valid,rd_en : std_logic;
type states is (wait_for_uvc,uvc_wait,uvc_in_pktend,uvc_send_data,s_reset,free_uvc,s_skip);
signal ps : states;
begin
syncProc: process(uvc_rst,ifclk)
begin
if uvc_rst = '1' then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
wrightcount <= (others => '0');
watchdog <= (others => '0');
ps <= s_reset;
eof <= '0';
elsif falling_edge(ifclk) then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
case ps is
when s_reset =>
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
ps <= wait_for_uvc;
fdata <= (others => '0');
watchdog <= (others => '0');
wrightcount <= (others => '0');
total_send <= (others => '0');
count <= (others => '0');
when wait_for_uvc =>
if faddr = uvcin and raw_enable = '1' then
ps <= uvc_wait;
uvc_in_free <= '0';
end if;
when uvc_send_data =>
if empty = '0' and flag_full = '1' then
wrightcount <= wrightcount +1;
if header = '1' then
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
elsif wrightcount = X"000" then
slwr <= '0';
fdata <= X"0C"; -- header length
elsif wrightcount = X"001" then
slwr <= '0';
fdata <= ( "100000" & eof & fid ); -- EOH ERR STI RES SCR PTS EOF FID
eof <= '0';
elsif wrightcount = X"002" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"003" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"004" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"005" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"006" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"007" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"008" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"009" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00A" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00B" then
slwr <= '0';
fdata <= X"00";
else -- header sent
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
if (total_send = to_send - 1012) then
eof <= '1';
end if;
end if;
else -- if header not send
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
else
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
end if; -- end if header
end if; -- end if empty
-- else
-- ps <= uvc_wait;
end if;
when uvc_wait =>
watchdog <= watchdog + 1;
if empty = '0' and flag_full = '1' then
ps <= uvc_send_data;
watchdog <= (others => '0');
elsif watchdog(watchdog'range) = (watchdog'range => '1') then
ps <= free_uvc;
watchdog <= (others => '0');
end if;
when uvc_in_pktend =>
pktend <= '0';
ps <= free_uvc;
when free_uvc =>
uvc_in_free <= '1';
ps <= s_skip;
when s_skip =>
ps <= wait_for_uvc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
raw_en_i <= (raw_en and raw_enable);
rawUVCfifo_Comp : rawUVCfifo
PORT MAP (
rst => uvc_rst,
wr_clk => raw_clk,
rd_clk => ifclk,
din => raw_bytes,
wr_en => raw_en_i,
rd_en => rd_en,
dout => dout,
full => full,
-- almost_full => raw_fifo_full,
prog_full => raw_fifo_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
end rtl; |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity raw_uvc is
port (
-- raw signals
raw_en : in std_logic;
raw_bytes : in std_logic_vector(23 downto 0);
raw_fifo_full : out std_logic;
error : out std_logic;
raw_clk : in std_logic;
raw_enable : in std_logic;
-- USB signals
slwr : out std_logic;
pktend : out std_logic;
fdata : out std_logic_vector(7 downto 0);
flag_full : in std_logic;
ifclk : in std_logic;
faddr : in std_logic_vector(1 downto 0);
uvcin : in std_logic_vector(1 downto 0);
header : in std_logic;
to_send : in std_logic_vector(23 downto 0);
-- others
uvc_in_free : out std_logic;
uvc_rst : in std_logic
);
end entity raw_uvc;
architecture rtl of raw_uvc is
COMPONENT rawUVCfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
signal fid : std_logic;
signal eof : std_logic;
signal total_send: std_logic_vector(23 downto 0);
signal dout: std_logic_vector(23 downto 0);
signal wrightcount: std_logic_vector(11 downto 0);
signal watchdog: std_logic_vector(5 downto 0);
signal count: std_logic_vector(1 downto 0);
signal raw_en_i : std_logic;
signal full,empty,almost_empty,valid,rd_en : std_logic;
type states is (wait_for_uvc,uvc_wait,uvc_in_pktend,uvc_send_data,s_reset,free_uvc,s_skip);
signal ps : states;
begin
syncProc: process(uvc_rst,ifclk)
begin
if uvc_rst = '1' then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
wrightcount <= (others => '0');
watchdog <= (others => '0');
ps <= s_reset;
eof <= '0';
elsif falling_edge(ifclk) then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
case ps is
when s_reset =>
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
ps <= wait_for_uvc;
fdata <= (others => '0');
watchdog <= (others => '0');
wrightcount <= (others => '0');
total_send <= (others => '0');
count <= (others => '0');
when wait_for_uvc =>
if faddr = uvcin and raw_enable = '1' then
ps <= uvc_wait;
uvc_in_free <= '0';
end if;
when uvc_send_data =>
if empty = '0' and flag_full = '1' then
wrightcount <= wrightcount +1;
if header = '1' then
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
elsif wrightcount = X"000" then
slwr <= '0';
fdata <= X"0C"; -- header length
elsif wrightcount = X"001" then
slwr <= '0';
fdata <= ( "100000" & eof & fid ); -- EOH ERR STI RES SCR PTS EOF FID
eof <= '0';
elsif wrightcount = X"002" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"003" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"004" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"005" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"006" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"007" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"008" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"009" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00A" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00B" then
slwr <= '0';
fdata <= X"00";
else -- header sent
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
if (total_send = to_send - 1012) then
eof <= '1';
end if;
end if;
else -- if header not send
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
else
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
end if; -- end if header
end if; -- end if empty
-- else
-- ps <= uvc_wait;
end if;
when uvc_wait =>
watchdog <= watchdog + 1;
if empty = '0' and flag_full = '1' then
ps <= uvc_send_data;
watchdog <= (others => '0');
elsif watchdog(watchdog'range) = (watchdog'range => '1') then
ps <= free_uvc;
watchdog <= (others => '0');
end if;
when uvc_in_pktend =>
pktend <= '0';
ps <= free_uvc;
when free_uvc =>
uvc_in_free <= '1';
ps <= s_skip;
when s_skip =>
ps <= wait_for_uvc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
raw_en_i <= (raw_en and raw_enable);
rawUVCfifo_Comp : rawUVCfifo
PORT MAP (
rst => uvc_rst,
wr_clk => raw_clk,
rd_clk => ifclk,
din => raw_bytes,
wr_en => raw_en_i,
rd_en => rd_en,
dout => dout,
full => full,
-- almost_full => raw_fifo_full,
prog_full => raw_fifo_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
end rtl; |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_d_latch IS END tb_d_latch;
ARCHITECTURE test OF tb_d_latch IS
COMPONENT d_latch IS
PORT(d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL d, clk, q: STD_LOGIC;
BEGIN
T1: d_latch PORT MAP(d, clk, q);
d<='1',
'0' AFTER 7.5 ns,
'1' AFTER 15 ns,
'0' AFTER 22.5 ns,
'1' AFTER 30 ns,
'0' AFTER 37.5 ns;
clk<='0',
'1' AFTER 5 ns,
'0' AFTER 10 ns,
'1' AFTER 15 ns,
'0' AFTER 20 ns,
'1' AFTER 25 ns,
'0' AFTER 30 ns,
'1' AFTER 35 ns,
'0' AFTER 40 ns,
'0' AFTER 45 ns;
end test; |
--
-- This file is part of bit_delay
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity single_delay is
port (
clk : in std_logic; -- clock
rst : in std_logic; --rst
input : in std_logic; -- input
output : out std_logic); -- output
end single_delay;
architecture behavourial of single_delay is
begin -- behavourial
-- purpose: create delay
-- type : sequential
-- inputs : clk, rst
-- outputs: sig1
gen_output: process (clk,rst)
begin -- process gen_output
if rising_edge(clk) then -- rising clock edge
if rst = '1' then -- asynchronous reset (active low)
output <= '0';
else
output <= input;
end if;
end if;
end process gen_output;
end behavourial;
|
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`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity AhbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
lastCycle : in vl_logic;
hRegReq : out vl_logic;
hFMInvalidXfer : out vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
hRegSize : out vl_logic_vector(1 downto 0);
hRegMastLock : out vl_logic;
hRegWrite : out vl_logic;
regAddr : out vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
F_FM_HMASTLOCK : in vl_logic;
F_FM_HSIZE : in vl_logic_vector(1 downto 0);
F_FM_HTRANS1 : in vl_logic;
F_FM_HWRITE : in vl_logic;
F_FM_HSEL : in vl_logic;
F_FM_HREADY : in vl_logic;
F_FM_HREADYOUT : out vl_logic;
F_FM_HRESP : out vl_logic
);
end AhbWrapper_FM;
|
library verilog;
use verilog.vl_types.all;
entity AhbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
lastCycle : in vl_logic;
hRegReq : out vl_logic;
hFMInvalidXfer : out vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
hRegSize : out vl_logic_vector(1 downto 0);
hRegMastLock : out vl_logic;
hRegWrite : out vl_logic;
regAddr : out vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
F_FM_HMASTLOCK : in vl_logic;
F_FM_HSIZE : in vl_logic_vector(1 downto 0);
F_FM_HTRANS1 : in vl_logic;
F_FM_HWRITE : in vl_logic;
F_FM_HSEL : in vl_logic;
F_FM_HREADY : in vl_logic;
F_FM_HREADYOUT : out vl_logic;
F_FM_HRESP : out vl_logic
);
end AhbWrapper_FM;
|
library verilog;
use verilog.vl_types.all;
entity AhbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
lastCycle : in vl_logic;
hRegReq : out vl_logic;
hFMInvalidXfer : out vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
hRegSize : out vl_logic_vector(1 downto 0);
hRegMastLock : out vl_logic;
hRegWrite : out vl_logic;
regAddr : out vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
F_FM_HMASTLOCK : in vl_logic;
F_FM_HSIZE : in vl_logic_vector(1 downto 0);
F_FM_HTRANS1 : in vl_logic;
F_FM_HWRITE : in vl_logic;
F_FM_HSEL : in vl_logic;
F_FM_HREADY : in vl_logic;
F_FM_HREADYOUT : out vl_logic;
F_FM_HRESP : out vl_logic
);
end AhbWrapper_FM;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1170.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01170ent IS
END c06s06b00x00p06n01i01170ent;
ARCHITECTURE c06s06b00x00p06n01i01170arch OF c06s06b00x00p06n01i01170ent IS
BEGIN
TESTING: PROCESS
type II is range 1 to 1000;
type RR is range 0.0001 to 10000.01;
function F1 (A:II;B:RR) return BOOLEAN is
variable G1 : II;
variable G2 : RR;
begin
if (A'LEFT(0) /= 0) then -- ERROR: attribute does not have a
-- generic expression assoc. with it.
return FALSE;
end if;
end F1;
BEGIN
assert FALSE
report "***FAILED TEST: c06s06b00x00p06n01i01170 - Arrtribute does not have generic expression associated with it."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01170arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1170.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01170ent IS
END c06s06b00x00p06n01i01170ent;
ARCHITECTURE c06s06b00x00p06n01i01170arch OF c06s06b00x00p06n01i01170ent IS
BEGIN
TESTING: PROCESS
type II is range 1 to 1000;
type RR is range 0.0001 to 10000.01;
function F1 (A:II;B:RR) return BOOLEAN is
variable G1 : II;
variable G2 : RR;
begin
if (A'LEFT(0) /= 0) then -- ERROR: attribute does not have a
-- generic expression assoc. with it.
return FALSE;
end if;
end F1;
BEGIN
assert FALSE
report "***FAILED TEST: c06s06b00x00p06n01i01170 - Arrtribute does not have generic expression associated with it."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01170arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1170.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01170ent IS
END c06s06b00x00p06n01i01170ent;
ARCHITECTURE c06s06b00x00p06n01i01170arch OF c06s06b00x00p06n01i01170ent IS
BEGIN
TESTING: PROCESS
type II is range 1 to 1000;
type RR is range 0.0001 to 10000.01;
function F1 (A:II;B:RR) return BOOLEAN is
variable G1 : II;
variable G2 : RR;
begin
if (A'LEFT(0) /= 0) then -- ERROR: attribute does not have a
-- generic expression assoc. with it.
return FALSE;
end if;
end F1;
BEGIN
assert FALSE
report "***FAILED TEST: c06s06b00x00p06n01i01170 - Arrtribute does not have generic expression associated with it."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01170arch;
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis (christos.bakalis@cern.ch)
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 28.04.2017 12:39:23
-- Design Name: VMM Readout Wrapper
-- Module Name: vmm_readout_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Wrapper that contains the two main components that implement the
-- VMM3 readout, namely vmm_readout (old continouous mode) and L0_wrapper (level-0)
-- mode.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use UNISIM.VComponents.all;
entity vmm_readout_wrapper is
generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
Port(
------------------------------------
--- Continuous Readout Interface ---
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Main clock
--
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0); -- Max number of CKTKs
--
dt_state_o : out std_logic_vector(3 downto 0); -- for debugging
dt_cntr_st_o : out std_logic_vector(3 downto 0); -- for debugging
------------------------------------
---- Level-0 Readout Interface -----
clk_ckdt : in std_logic; -- will be forwarded to the VMM
rst_buff : in std_logic; -- reset the level-0 buffer
rst_intf_proc : in std_logic; -- reset the pf interface
--
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
--
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_ena_buff : in std_logic; -- read the readout buffer (level0 or continuous)
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
linkHealth_bmsk : out std_logic_vector(8 downto 1); -- status of comma alignment links
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_glbl : out std_logic; -- Strobe to VMM CKDT
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end vmm_readout_wrapper;
architecture RTL of vmm_readout_wrapper is
component vmm_readout is
Port(
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Used for fast switching between processes
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM CKTK
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0);
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
ethernet_fifo_wr_en : out std_logic; -- To be used for reading out seperate FIFOs in VMMx8 parallel readout
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_en : in std_logic;
dt_state_o : out std_logic_vector(3 downto 0);
dt_cntr_st_o : out std_logic_vector(3 downto 0)
);
end component;
component level0_wrapper is
Generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
clk : in std_logic; -- buffer read domain
rst_buff : in std_logic; -- reset buffer
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic; -- reset the pf interface
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
linkHealth_bmsk : out std_logic_vector(8 downto 1);
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end component;
signal data0_in_vec_cont : std_logic_vector(8 downto 1) := (others => '0');
signal data1_in_vec_cont : std_logic_vector(8 downto 1) := (others => '0');
signal cktk_out_vec_cont : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_ckdt_enable_cont : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWord_cont : std_logic_vector(15 downto 0) := (others => '0');
signal rd_en_cont : std_logic := '0';
signal vmmWordReady_cont : std_logic := '0';
signal vmmEventDone_cont : std_logic := '0';
signal vmm_ckdt_cont : std_logic := '0';
signal data0_in_vec_l0 : std_logic_vector(8 downto 1) := (others => '0');
signal data1_in_vec_l0 : std_logic_vector(8 downto 1) := (others => '0');
signal cktk_out_vec_l0 : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWord_l0 : std_logic_vector(15 downto 0) := (others => '0');
signal rd_en_l0 : std_logic := '0';
signal vmmWordReady_l0 : std_logic := '0';
signal vmmEventDone_l0 : std_logic := '0';
signal vmm_ckdt_glbl_i : std_logic := '0';
begin
-- continuous mode module instantiation
continuousReadoutMode: if vmmReadoutMode = '0' generate
readout_vmm_cont: vmm_readout
port map(
clkTkProc => clkTkProc,
clkDtProc => clkDtProc,
clk => clk,
vmm_data0_vec => data0_in_vec_cont,
vmm_data1_vec => data1_in_vec_cont,
vmm_ckdt_enable => vmm_ckdt_enable_cont,
vmm_cktk_vec => cktk_out_vec_cont,
vmm_ckdt => vmm_ckdt_cont,
daq_enable => daq_enable,
trigger_pulse => trigger_pulse,
cktk_max => cktk_max,
vmmId => vmmId,
ethernet_fifo_wr_en => open,
vmm_data_buf => open,
rd_en => rd_en_cont,
vmmWordReady => vmmWordReady_cont,
vmmWord => vmmWord_cont,
vmmEventDone => vmmEventDone_cont,
dt_state_o => dt_state_o,
dt_cntr_st_o => dt_cntr_st_o
);
end generate continuousReadoutMode;
level0_readout_case : if vmmReadoutMode = '1' generate
readout_vmm_l0: level0_wrapper
generic map(is_mmfe8 => is_mmfe8, vmmReadoutMode => vmmReadoutMode)
port map(
------------------------------------
------- General Interface ----------
clk_ckdt => clk_ckdt, -- vmm_ckdt_glbl_i ??
clk => clk,
rst_buff => rst_buff,
level_0 => level_0,
wr_accept => wr_accept,
vmm_conf => vmm_conf,
daq_on_inhib => daq_on_inhib,
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff => rd_ena_buff,
rst_intf_proc => rst_intf_proc,
vmmId => vmmId,
vmmWordReady => vmmWordReady_l0,
vmmWord => vmmWord_l0,
vmmEventDone => vmmEventDone_l0,
linkHealth_bmsk => linkHealth_bmsk,
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec => data0_in_vec_l0,
vmm_data1_vec => data1_in_vec_l0,
vmm_cktk_vec => cktk_out_vec_l0
);
end generate level0_readout_case;
-- multiplexer/demultiplexer for different mode cases
vmm_io_muxDemux: process(vmmWordReady_cont, vmmEventDone_cont, vmmWord_cont, vmm_ckdt_enable_cont, cktk_out_vec_cont, rd_ena_buff,
vmmWordReady_l0, vmmEventDone_l0, vmmWord_l0, cktk_out_vec_l0, vmm_data0_vec, vmm_data1_vec)
begin
case vmmReadoutMode is
when '0' =>
-- outputs
vmmWordReady <= vmmWordReady_cont;
vmmEventDone <= vmmEventDone_cont;
vmmWord <= vmmWord_cont;
vmm_ckdt_enable <= vmm_ckdt_enable_cont;
vmm_cktk_vec <= cktk_out_vec_cont;
-- inputs
rd_en_cont <= rd_ena_buff;
rd_en_l0 <= '0';
data0_in_vec_cont <= vmm_data0_vec;
data1_in_vec_cont <= vmm_data1_vec;
data0_in_vec_l0 <= (others => '0');
data1_in_vec_l0 <= (others => '0');
when '1' =>
-- outputs
vmmWordReady <= vmmWordReady_l0;
vmmEventDone <= vmmEventDone_l0;
vmmWord <= vmmWord_l0;
vmm_ckdt_enable <= x"FF";
vmm_cktk_vec <= cktk_out_vec_l0;
-- inputs
rd_en_cont <= '0';
rd_en_l0 <= rd_ena_buff;
data0_in_vec_cont <= (others => '0');
data1_in_vec_cont <= (others => '0');
data0_in_vec_l0 <= vmm_data0_vec;
data1_in_vec_l0 <= vmm_data1_vec;
when others =>
-- outputs
vmmWordReady <= '0';
vmmEventDone <= '0';
vmmWord <= (others => '0');
vmm_ckdt_enable <= (others => '0');
vmm_cktk_vec <= (others => '0');
-- inputs
data0_in_vec_cont <= (others => '0');
data1_in_vec_cont <= (others => '0');
data0_in_vec_l0 <= (others => '0');
data1_in_vec_l0 <= (others => '0');
end case;
end process;
CKDT_BUFGMUX: BUFGMUX
port map(O => vmm_ckdt_glbl_i, I0 => vmm_ckdt_cont, I1 => clk_ckdt, S => vmmReadoutMode);
vmm_ckdt_glbl <= vmm_ckdt_glbl_i;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram1_n is
generic( addr : natural := 8;
data : natural := 4);
port( clk : in std_logic;
writeEnable : in std_logic;
address : in std_logic_vector(addr-1 downto 0);
writeData : in std_logic_vector(data-1 downto 0);
readData : out std_logic_vector(data-1 downto 0));
end Ram1_N;
architecture Behavioral of Ram1_n is
type ram is array(0 to (2**addr-1)) of std_logic_vector(0 to (data-1));
signal memory : ram;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(writeEnable='1') then
memory(to_integer(unsigned(address))) <= writeData;
end if;
end if;
end process;
readData <= memory(to_integer(unsigned(address)));
end Behavioral; |
-- $Id: pdp11_mem70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mem70 - syn
-- Description: pdp11: 11/70 memory system registers
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mem70;
architecture syn of pdp11_mem70 is
constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16));
constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16));
constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16));
constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16));
constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16));
constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16));
constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16));
constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16));
subtype cntl_ibf_frep is integer range 5 downto 4;
subtype cntl_ibf_fmiss is integer range 3 downto 2;
constant cntl_ibf_disutrap : integer := 1;
constant cntl_ibf_distrap : integer := 0;
type regs_type is record -- state registers
ibsel_cr : slbit; -- ibus select cntl
ibsel_hm : slbit; -- ibus select hitmiss
ibsel_ls : slbit; -- ibus select losize
ibsel_nn : slbit; -- ibus select others
hm_data : slv6; -- hit/miss: data
cr_frep : slv2; -- cntl: force replacement bits
cr_fmiss : slv2; -- cntl: force miss bits
cr_disutrap: slbit; -- cntl: disable unibus trap
cr_distrap: slbit; -- cntl: disable traps
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- ibsel_*
(others=>'0'), -- hm_data
"00","00", -- cr_frep,_fmiss
'0','0' -- dis(u)trap
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel_cr := '0';
n.ibsel_hm := '0';
n.ibsel_ls := '0';
n.ibsel_nn := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
n.ibsel_cr := '1';
end if;
if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
n.ibsel_hm := '1';
end if;
if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
n.ibsel_ls := '1';
end if;
if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
IB_MREQ.addr=ibaddr_maint(12 downto 1) or
IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
n.ibsel_nn := '1';
end if;
end if;
-- ibus transactions
if r.ibsel_cr = '1' then
idout(cntl_ibf_frep) := r.cr_frep;
idout(cntl_ibf_fmiss) := r.cr_fmiss;
idout(cntl_ibf_disutrap) := r.cr_disutrap;
idout(cntl_ibf_distrap) := r.cr_distrap;
end if;
if r.ibsel_hm = '1' then
idout(r.hm_data'range) := r.hm_data;
end if;
if r.ibsel_ls = '1' then
idout := slv(to_unsigned(sys_conf_mem_losize,16));
end if;
if r.ibsel_cr='1' and ibw0='1' then
n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
end if;
if HM_ENA = '1' then
n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
r.ibsel_ls or r.ibsel_nn) and ibreq;
IB_SRES.busy <= '0';
end process proc_next;
CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
end syn;
|
-- Copyright (c) 2009 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
use work.YaGraphConPackage.all;
entity Framebuffer is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural
);
port(
clock: in std_logic;
-- 1st RAM port for read-only access
readAddress1: in unsigned(ADDRESS_WIDTH-1 downto 0);
q1: out unsigned(BIT_DEPTH-1 downto 0);
-- 2nd RAM port for read-only access
readAddress2: in unsigned(ADDRESS_WIDTH-1 downto 0);
q2: out unsigned(BIT_DEPTH-1 downto 0);
-- 3rd RAM port for write access
writeAddress: in unsigned(ADDRESS_WIDTH-1 downto 0);
data: in unsigned(BIT_DEPTH-1 downto 0);
writeEnable: in std_logic
);
end entity Framebuffer;
architecture rtl of Framebuffer is
-- infering template for Xilinx block RAM
constant ADDR_WIDTH : integer := ADDRESS_WIDTH;
constant DATA_WIDTH : integer := BIT_DEPTH;
type framebufferType is array (2**ADDR_WIDTH-1 downto 0) of unsigned(DATA_WIDTH-1 downto 0);
signal framebufferRam1: framebufferType;
signal framebufferRam2: framebufferType;
begin
-- infering template for Xilinx block RAM
ram1: process(clock)
begin
if rising_edge(clock) then
--if (clock'event and clock = '1') then
if writeEnable = '1' then
framebufferRam1(to_integer(writeAddress)) <= data;
end if;
q1 <= framebufferRam1(to_integer(readAddress1));
end if;
end process;
-- infering template for Xilinx block RAM
ram2: process(clock)
begin
if rising_edge(clock) then
--if (clock'event and clock = '1') then
if writeEnable = '1' then
framebufferRam2(to_integer(writeAddress)) <= data;
end if;
q2 <= framebufferRam2(to_integer(readAddress2));
end if;
end process;
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Entity: align_read_to_bram
-- Date:2015-03-14
-- Author: Gideon
--
-- Description: This module aligns 32 bit reads from memory to writes to BRAM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity align_read_to_bram is
port (
clock : in std_logic;
rdata : in std_logic_vector(31 downto 0);
rdata_valid : in std_logic;
first_word : in std_logic;
last_word : in std_logic;
offset : in unsigned(1 downto 0);
wdata : out std_logic_vector(31 downto 0);
wmask : out std_logic_vector(3 downto 0);
wnext : out std_logic );
end align_read_to_bram;
-- two possibilities.
-- 1) read from memory with lower address bits on zero. word from memory is aligned.
-- first byte in the word that needs to be written to BRAM depends on the offset,
-- so the word itself needs to be rotated, to get the right byte at the right 'lane'.
--
-- 2) read from memory with lower address set to the actual offset. Depending on the
-- burst size of the memory, the bytes in the word are actually shifted. Example:
-- Read from 0001 => 01.02.03.00 MSB first in this example.
-- ** ** ** -- Write these bytes to BRAM address 0
-- Read from 0005 => 05.06.07.04 MSB first
-- ** Write these bytes to BRAM address 0
-- ** ** ** -- Write these bytes to BRAM address 1
-- Read from 0009 => 09.0A.0B.09
-- ** Write these bytes to BRAM address 1
-- ** ** ** -- Write these bytes to BRAM address 2
-- ...
-- Read from 00FD => FD.FE.FF.FC
-- ** Write these bytes to BRAM address 62
-- ** ** ** -- Write these bytes to BRAM address 63
-- Read from 0101 => 01.02.03.00
-- ** Write these bytes to BRAM address 63
-- END.
-- So in this way we only need to generate the correct write strobes and address advance.
--
-- Note on count generation:
-- Bytes Offset | Words
-- 1 x | 1
-- 2 0 | 1
-- 2 1 | 1
-- 2 2 | 1
-- 2 3 | 2
-- 3 0 | 1
-- 3 1 | 1
-- 3 2 | 2
-- 3 3 | 2
-- 4 0 | 1
-- 4 1 | 2
-- 4 2 | 2
-- 4 3 | 2
-- (bytes + 3 + offset) and ~3
--
architecture arch of align_read_to_bram is
signal need_second : std_logic;
signal second_cycle : std_logic;
signal byte_en : std_logic_vector(3 downto 0);
signal advance : std_logic;
begin
process(offset, rdata_valid, first_word, last_word, second_cycle)
begin
need_second <= '0';
advance <= '0';
byte_en <= "0000";
if rdata_valid='1' then
case offset is
when "00" => -- direct fit
byte_en <= "1111";
advance <= '1';
when "01" =>
if first_word='1' then
byte_en <= "0111";
else
byte_en <= "1000";
advance <= '1';
need_second <= '1';
end if;
when "10" =>
if first_word='1' then
byte_en <= "0011";
else
byte_en <= "1100";
advance <= '1';
need_second <= '1';
end if;
when "11" =>
if first_word='1' then
byte_en <= "0001";
else
byte_en <= "1110";
advance <= '1';
need_second <= '1';
end if;
when others =>
null;
end case;
if last_word='1' then
need_second <= '0';
end if;
elsif second_cycle='1' then
case offset is
when "01" =>
byte_en <= "0111";
when "10" =>
byte_en <= "0011";
when "11" =>
byte_en <= "0001";
when others =>
null;
end case;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
second_cycle <= need_second;
if rdata_valid = '1' then
wdata <= rdata;
end if;
wmask <= byte_en;
wnext <= advance;
end if;
end process;
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity or00 is
port(
Ao: in std_logic ;
Bo: in std_logic ;
Yo: out std_logic );
end;
architecture or0 of or00 is
begin
Yo <= Ao or Bo;
end or0;
|
-- Ethernet DSU
constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
|
-- Ethernet DSU
constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I1",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I1"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_axcelerator_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel AX rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library axcelerator;
use axcelerator.RAM64K36;
-- pragma translate_on
entity axcel_ssram is
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end;
architecture rtl of axcel_ssram is
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
signal gnd : std_ulogic;
signal depth : std_logic_vector(4 downto 0);
signal d, q : std_logic_vector(36 downto 0);
begin
depth <= "00000";
do <= q(dbits-1 downto 0);
d(dbits-1 downto 0) <= di;
d(36 downto dbits) <= (others => '0');
u0 : RAM64K36
port map (
WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3),
WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7),
WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11),
WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15),
WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4),
WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9),
WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14),
WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19),
WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24),
WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29),
WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34),
WD35 => d(35), WEN => wen, DEPTH0 => depth(0),
DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3),
WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk,
RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3),
RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7),
RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11),
RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15),
REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2),
RCLK => rclk,
RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4),
RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9),
RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14),
RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19),
RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24),
RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29),
RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34),
RD35 => q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity axcel_syncram_2p is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of axcel_syncram_2p is
component axcel_ssram
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end component;
type dwtype is array (1 to 24) of integer;
constant dwmap : dwtype := (36, 36, 36, 36, 36, 36, 36, 18, 9, 4, 2, others => 1);
constant xbits : integer := dwmap(abits);
constant dw : integer := dbits + 36;
signal wen, gnd : std_ulogic;
signal ra, wa : std_logic_vector(31 downto 0);
signal d, q : std_logic_vector(dw downto 0);
signal ren : std_ulogic;
signal width : std_logic_vector(2 downto 0);
constant READFAST : std_ulogic := '0';
begin
width <= "101" when abits <= 7 else
"100" when abits = 8 else
"011" when abits = 9 else
"010" when abits = 10 else
"001" when abits = 11 else
"000";
wen <= write; ren <= rena or READFAST; gnd <= '0';
ra(31 downto abits) <= (others =>'0'); wa(31 downto abits) <= (others =>'0');
ra(abits-1 downto 0) <= raddr(abits-1 downto 0);
wa(abits-1 downto 0) <= waddr(abits-1 downto 0);
d(dw downto dbits) <= (others =>'0');
d(dbits-1 downto 0) <= din(dbits-1 downto 0);
dout <= q(dbits-1 downto 0);
a7 : if abits <= 7 generate
agen : for i in 0 to (dbits-1)/xbits generate
u0 : axcel_ssram
generic map (abits => 7, dbits => xbits)
port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
wclk => wclk, ren => ren, rclk => rclk,
do => q(xbits*(i+1)-1 downto xbits*i));
end generate;
end generate;
a8to12 : if (abits > 7) and (abits <= 12) generate
agen : for i in 0 to (dbits-1)/xbits generate
u0 : axcel_ssram
generic map (abits => abits, dbits => xbits)
port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
wclk => wclk, ren => ren, rclk => rclk,
do => q(xbits*(i+1)-1 downto xbits*i));
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for AX rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axcel_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of axcel_syncram is
component axcel_syncram_2p
generic ( abits : integer := 10; dbits : integer := 8 );
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component axcel_ssram
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end component;
type d_type is array (0 to 3) of std_logic_vector(35 downto 0);
signal wen : std_logic_vector(3 downto 0);
signal q : d_type;
signal addr : std_logic_vector(15 downto 0);
signal addrreg : std_logic_vector(1 downto 0);
begin
a : if not ((abits = 10 or abits = 11) and dbits = 36) generate
u0 : axcel_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end generate;
-- Special case for 4 or 8 KB cache with FT: 36x1024 or 2048: 2 or 4 banks of 4*9*512
a10to11d36 : if (abits = 10 or abits = 11) and dbits = 36 generate
addr_reg : process (clk)
begin
if rising_edge(clk) then addrreg(abits-10 downto 0) <= address(abits-1 downto 9); end if;
end process;
addr(15 downto 9) <= (others => '0');
addr(8 downto 0) <= address(8 downto 0);
decode : process (address, write)
variable vwen : std_logic_vector(3 downto 0);
begin
vwen := (others => '0');
if write = '1' then
vwen( to_integer(unsigned(address(abits-1 downto 9))) ) := '1';
end if;
wen <= vwen;
end process;
loop0 : for b in 0 to 2*(abits-9)-1 generate
agen0 : for i in 0 to 3 generate
u0 : axcel_ssram
generic map (abits => 9, dbits => 9)
port map (ra => addr, wa => addr,
di => datain(9*(i+1)-1 downto 9*i), wen => wen(b), width => "011",
wclk => clk, ren => enable, rclk => clk,
do => q(b)(9*(i+1)-1 downto 9*i));
end generate;
end generate;
dout10: if abits = 10 generate
dataout <= q(0) when addrreg(0)='0' else q(1);
end generate;
dout11: if abits = 11 generate
dataout <= q(0) when addrreg(1 downto 0)="00" else q(1) when addrreg(1 downto 0)="01" else
q(2) when addrreg(1 downto 0)="10" else q(3);
end generate;
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_axcelerator_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel AX rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library axcelerator;
use axcelerator.RAM64K36;
-- pragma translate_on
entity axcel_ssram is
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end;
architecture rtl of axcel_ssram is
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
signal gnd : std_ulogic;
signal depth : std_logic_vector(4 downto 0);
signal d, q : std_logic_vector(36 downto 0);
begin
depth <= "00000";
do <= q(dbits-1 downto 0);
d(dbits-1 downto 0) <= di;
d(36 downto dbits) <= (others => '0');
u0 : RAM64K36
port map (
WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3),
WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7),
WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11),
WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15),
WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4),
WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9),
WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14),
WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19),
WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24),
WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29),
WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34),
WD35 => d(35), WEN => wen, DEPTH0 => depth(0),
DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3),
WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk,
RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3),
RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7),
RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11),
RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15),
REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2),
RCLK => rclk,
RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4),
RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9),
RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14),
RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19),
RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24),
RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29),
RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34),
RD35 => q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity axcel_syncram_2p is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of axcel_syncram_2p is
component axcel_ssram
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end component;
type dwtype is array (1 to 24) of integer;
constant dwmap : dwtype := (36, 36, 36, 36, 36, 36, 36, 18, 9, 4, 2, others => 1);
constant xbits : integer := dwmap(abits);
constant dw : integer := dbits + 36;
signal wen, gnd : std_ulogic;
signal ra, wa : std_logic_vector(31 downto 0);
signal d, q : std_logic_vector(dw downto 0);
signal ren : std_ulogic;
signal width : std_logic_vector(2 downto 0);
constant READFAST : std_ulogic := '0';
begin
width <= "101" when abits <= 7 else
"100" when abits = 8 else
"011" when abits = 9 else
"010" when abits = 10 else
"001" when abits = 11 else
"000";
wen <= write; ren <= rena or READFAST; gnd <= '0';
ra(31 downto abits) <= (others =>'0'); wa(31 downto abits) <= (others =>'0');
ra(abits-1 downto 0) <= raddr(abits-1 downto 0);
wa(abits-1 downto 0) <= waddr(abits-1 downto 0);
d(dw downto dbits) <= (others =>'0');
d(dbits-1 downto 0) <= din(dbits-1 downto 0);
dout <= q(dbits-1 downto 0);
a7 : if abits <= 7 generate
agen : for i in 0 to (dbits-1)/xbits generate
u0 : axcel_ssram
generic map (abits => 7, dbits => xbits)
port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
wclk => wclk, ren => ren, rclk => rclk,
do => q(xbits*(i+1)-1 downto xbits*i));
end generate;
end generate;
a8to12 : if (abits > 7) and (abits <= 12) generate
agen : for i in 0 to (dbits-1)/xbits generate
u0 : axcel_ssram
generic map (abits => abits, dbits => xbits)
port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
wclk => wclk, ren => ren, rclk => rclk,
do => q(xbits*(i+1)-1 downto xbits*i));
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for AX rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axcel_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of axcel_syncram is
component axcel_syncram_2p
generic ( abits : integer := 10; dbits : integer := 8 );
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component axcel_ssram
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end component;
type d_type is array (0 to 3) of std_logic_vector(35 downto 0);
signal wen : std_logic_vector(3 downto 0);
signal q : d_type;
signal addr : std_logic_vector(15 downto 0);
signal addrreg : std_logic_vector(1 downto 0);
begin
a : if not ((abits = 10 or abits = 11) and dbits = 36) generate
u0 : axcel_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end generate;
-- Special case for 4 or 8 KB cache with FT: 36x1024 or 2048: 2 or 4 banks of 4*9*512
a10to11d36 : if (abits = 10 or abits = 11) and dbits = 36 generate
addr_reg : process (clk)
begin
if rising_edge(clk) then addrreg(abits-10 downto 0) <= address(abits-1 downto 9); end if;
end process;
addr(15 downto 9) <= (others => '0');
addr(8 downto 0) <= address(8 downto 0);
decode : process (address, write)
variable vwen : std_logic_vector(3 downto 0);
begin
vwen := (others => '0');
if write = '1' then
vwen( to_integer(unsigned(address(abits-1 downto 9))) ) := '1';
end if;
wen <= vwen;
end process;
loop0 : for b in 0 to 2*(abits-9)-1 generate
agen0 : for i in 0 to 3 generate
u0 : axcel_ssram
generic map (abits => 9, dbits => 9)
port map (ra => addr, wa => addr,
di => datain(9*(i+1)-1 downto 9*i), wen => wen(b), width => "011",
wclk => clk, ren => enable, rclk => clk,
do => q(b)(9*(i+1)-1 downto 9*i));
end generate;
end generate;
dout10: if abits = 10 generate
dataout <= q(0) when addrreg(0)='0' else q(1);
end generate;
dout11: if abits = 11 generate
dataout <= q(0) when addrreg(1 downto 0)="00" else q(1) when addrreg(1 downto 0)="01" else
q(2) when addrreg(1 downto 0)="10" else q(3);
end generate;
end generate;
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_20_0 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_20_0;
ARCHITECTURE sys_axi_nic_20_0_arch OF sys_axi_nic_20_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_20_0_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_20_0_arch;
|
entity elab6 is
end entity;
architecture test of elab6 is
type int_vec is array (integer range <>) of integer;
signal s : int_vec(1 to 10);
begin
test_g: for i in s'range generate
signal tmp : integer;
begin
tmp <= i * 2;
s(i) <= tmp;
end generate;
process is
begin
wait for 1 ns;
for i in s'range loop
assert s(i) = i * 2;
end loop;
wait;
end process;
end architecture;
|
entity elab6 is
end entity;
architecture test of elab6 is
type int_vec is array (integer range <>) of integer;
signal s : int_vec(1 to 10);
begin
test_g: for i in s'range generate
signal tmp : integer;
begin
tmp <= i * 2;
s(i) <= tmp;
end generate;
process is
begin
wait for 1 ns;
for i in s'range loop
assert s(i) = i * 2;
end loop;
wait;
end process;
end architecture;
|
entity elab6 is
end entity;
architecture test of elab6 is
type int_vec is array (integer range <>) of integer;
signal s : int_vec(1 to 10);
begin
test_g: for i in s'range generate
signal tmp : integer;
begin
tmp <= i * 2;
s(i) <= tmp;
end generate;
process is
begin
wait for 1 ns;
for i in s'range loop
assert s(i) = i * 2;
end loop;
wait;
end process;
end architecture;
|
entity elab6 is
end entity;
architecture test of elab6 is
type int_vec is array (integer range <>) of integer;
signal s : int_vec(1 to 10);
begin
test_g: for i in s'range generate
signal tmp : integer;
begin
tmp <= i * 2;
s(i) <= tmp;
end generate;
process is
begin
wait for 1 ns;
for i in s'range loop
assert s(i) = i * 2;
end loop;
wait;
end process;
end architecture;
|
entity elab6 is
end entity;
architecture test of elab6 is
type int_vec is array (integer range <>) of integer;
signal s : int_vec(1 to 10);
begin
test_g: for i in s'range generate
signal tmp : integer;
begin
tmp <= i * 2;
s(i) <= tmp;
end generate;
process is
begin
wait for 1 ns;
for i in s'range loop
assert s(i) = i * 2;
end loop;
wait;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
COMPONENT top
PORT(
addr : IN std_logic_vector(8 downto 0);
cmd_data : IN std_logic;
wen : IN std_logic;
ren : IN std_logic;
rdy : OUT std_logic;
usb_data : INOUT std_logic_vector(7 downto 0);
adc_data : IN std_logic_vector(7 downto 0);
dac_data : OUT std_logic_vector(7 downto 0);
dac_clk : OUT std_logic;
led : OUT std_logic_vector(7 downto 0);
sw0 : IN std_logic;
sw1 : IN std_logic;
sw2 : IN std_logic;
sw3 : IN std_logic;
crystal_clk : IN std_logic
);
END COMPONENT;
--Inputs
signal addr : std_logic_vector(8 downto 0) := (others => '0');
signal cmd_data : std_logic := '0';
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal adc_data : std_logic_vector(7 downto 0) := (others => '0');
signal sw0 : std_logic := '0';
signal sw1 : std_logic := '0';
signal sw2 : std_logic := '0';
signal sw3 : std_logic := '0';
signal crystal_clk : std_logic := '0';
--BiDirs
signal usb_data : std_logic_vector(7 downto 0);
--Outputs
signal rdy : std_logic;
signal dac_data : std_logic_vector(7 downto 0);
signal dac_clk : std_logic;
signal led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant crystal_clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
addr => addr,
cmd_data => cmd_data,
wen => wen,
ren => ren,
rdy => rdy,
usb_data => usb_data,
adc_data => adc_data,
dac_data => dac_data,
dac_clk => dac_clk,
led => led,
sw0 => sw0,
sw1 => sw1,
sw2 => sw2,
sw3 => sw3,
crystal_clk => crystal_clk
);
-- Clock process definitions
crystal_clk_process :process
begin
crystal_clk <= '0';
wait for crystal_clk_period/2;
crystal_clk <= '1';
wait for crystal_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
cmd_data <= '1';
addr <= "110000000";
wait for crystal_clk_period*10;
cmd_data <= '0';
addr <= "000000000";
wait for crystal_clk_period*10;
addr <= "110000010";
cmd_data <= '1';
usb_data <= "10001000";
wait for crystal_clk_period*10;
cmd_data <= '0';
wen <= '1';
wait for crystal_clk_period*10;
wen <= '0';
wait for crystal_clk_period*10;
cmd_data <= '1';
usb_data <= "01110111";
wait for crystal_clk_period*10;
cmd_data <= '0';
wen <= '1';
wait for crystal_clk_period*10;
wen <= '0';
wait for crystal_clk_period*10;
cmd_data <= '1';
usb_data <= "01100110";
wait for crystal_clk_period*10;
cmd_data <= '0';
wen <= '1';
wait for crystal_clk_period*10;
wen <= '0';
wait for crystal_clk_period*10;
cmd_data <= '1';
usb_data <= "01010101";
wait for crystal_clk_period*10;
cmd_data <= '0';
wen <= '1';
wait for crystal_clk_period*10;
wen <= '0';
wait for crystal_clk_period*10;
cmd_data <= '1';
addr <= "101100000";
wait for crystal_clk_period*10;
cmd_data <= '0';
wait for crystal_clk_period*10;
addr <= "110000100";
cmd_data <= '1';
wait for crystal_clk_period*10;
ren <= '1';
wait for crystal_clk_period*10;
ren <= '0';
cmd_data <= '0';
wait for crystal_clk_period*20;
addr <= "101100010";
cmd_data <= '1';
wait for crystal_clk_period*10;
ren <= '1';
wait for crystal_clk_period*10;
ren <= '0';
wait for crystal_clk_period*10;
cmd_data <= '0';
wait for crystal_clk_period*50;
addr <= "101100100";
cmd_data <= '1';
wait for crystal_clk_period*10;
cmd_data <= '0';
wait;
end process;
END;
|
-- This block set the putput to 1 if the input (result of the subtraction of the two operand) match the relation applied to the control input, 0 otherwise.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
use work.reduce_pack.all;
entity COMPARATOR_GENERIC is
generic(N: integer);
port( SUB: in std_logic_vector(N-1 downto 0);
CARRY: in std_logic;
EQUAL: in std_logic;
NOT_EQUAL: in std_logic;
GREATER: in std_logic;
GREATER_EQUAL: in std_logic;
LOWER: in std_logic;
LOWER_EQUAL: in std_logic;
COMPARATOR_OUT: out std_logic_vector(N-1 downto 0);
ZERO: out std_logic);
end entity COMPARATOR_GENERIC;
architecture BEHAVIORAL of COMPARATOR_GENERIC is
signal ZERO_INT: std_logic;
signal EQUAL_INT: std_logic;
signal NOT_EQUAL_INT: std_logic;
signal GREATER_INT: std_logic;
signal GREATER_EQUAL_INT: std_logic;
signal LOWER_INT: std_logic;
signal LOWER_EQUAL_INT: std_logic;
signal EQUAL_AND: std_logic;
signal NOT_EQUAL_AND: std_logic;
signal GREATER_AND: std_logic;
signal GREATER_EQUAL_AND: std_logic;
signal LOWER_AND: std_logic;
signal LOWER_EQUAL_AND: std_logic;
begin
ZERO_INT<= reduce_pack.nor_reduce(SUB);
ZERO <= ZERO_INT;
EQUAL_INT <= ZERO_INT;
NOT_EQUAL_INT <= not ZERO_INT;
GREATER_INT <= NOT_EQUAL_INT and GREATER_EQUAL_INT;
GREATER_EQUAL_INT <= CARRY;
LOWER_INT <= not GREATER_EQUAL_INT;
LOWER_EQUAL_INT <= EQUAL_INT or LOWER_INT;
EQUAL_AND <= EQUAL_INT and EQUAL;
NOT_EQUAL_AND <= NOT_EQUAL_INT and NOT_EQUAL;
GREATER_AND <= GREATER_INT and GREATER;
GREATER_EQUAL_AND <= GREATER_EQUAL_INT and GREATER_EQUAL;
LOWER_AND <= LOWER_INT and LOWER;
LOWER_EQUAL_AND <= LOWER_EQUAL_INT and LOWER_EQUAL;
COMPARATOR_OUT(0) <= EQUAL_AND or NOT_EQUAL_AND or GREATER_AND or GREATER_EQUAL_AND or LOWER_AND or LOWER_EQUAL_AND;
COMPARATOR_OUT(N-1 downto 1) <= (others => '0');
end architecture BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
entity function_test is
generic (
g : std_logic := '1'
);
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0)
);
end function_test;
architecture rtl of function_test is
function assign_value(value : in std_logic_vector(7 downto 0);
invert : in std_logic)
return std_logic_vector is
variable slv_out : std_logic_vector(7 downto 0);
begin
if invert = '0' then
slv_out := value;
elsif invert = '1' then
slv_out := not value;
end if;
return slv_out;
end;
begin
o <= assign_value(i, g);
end rtl;
|
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
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`protect end_protected
|
-- UART RX/TX with clock
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rxtx_clock is
port(
clk, reset: in std_logic; -- Clock and reset
--
rx: in std_logic; -- UART RX (Receive) pin
tx: out std_logic; -- UART TX (Send) pin
data_rx: out std_logic_vector(7 downto 0); -- Data byte to send
data_tx: in std_logic_vector(7 downto 0); -- Received data byte
rx_done_tick: out std_logic; -- Sent done tick
tx_done_tick: out std_logic; -- Receive done tick
tx_start: in std_logic -- Start transmission tick
);
end uart_rxtx_clock;
architecture uart_rxtx_clock_arch of uart_rxtx_clock is
signal baud16_tick: std_logic;
begin
uart_clock: entity work.counter_mod_m
generic map(N => 10, M => 54) -- 115200 bauds from 100Mhz clock (16x oversampling)
port map(clk => clk, reset => reset, max_tick => baud16_tick);
receiver: entity work.uart_rx
port map(clk => clk, reset => reset,
rx => rx, baud16_tick => baud16_tick,
data_out => data_rx, rx_done_tick => rx_done_tick);
transmitter: entity work.uart_tx
port map(clk => clk, reset => reset,
tx => tx, baud16_tick => baud16_tick,
data_in => data_tx, tx_done_tick => tx_done_tick,
tx_start => tx_start);
end uart_rxtx_clock_arch; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2474.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n02i02474ent IS
END c07s03b02x02p13n02i02474ent;
ARCHITECTURE c07s03b02x02p13n02i02474arch OF c07s03b02x02p13n02i02474ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
BEGIN
TESTING: PROCESS
variable k : CA_DOWN;
BEGIN
k := CA_DOWN'((10 downto 1 => 'B'));
assert NOT(k="BBBBBBBBBB")
report "***PASSED TEST: c07s03b02x02p13n02i02474"
severity NOTE;
assert (k="BBBBBBBBBB")
report "***FAILED TEST: c07s03b02x02p13n02i02474 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n02i02474arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2474.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n02i02474ent IS
END c07s03b02x02p13n02i02474ent;
ARCHITECTURE c07s03b02x02p13n02i02474arch OF c07s03b02x02p13n02i02474ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
BEGIN
TESTING: PROCESS
variable k : CA_DOWN;
BEGIN
k := CA_DOWN'((10 downto 1 => 'B'));
assert NOT(k="BBBBBBBBBB")
report "***PASSED TEST: c07s03b02x02p13n02i02474"
severity NOTE;
assert (k="BBBBBBBBBB")
report "***FAILED TEST: c07s03b02x02p13n02i02474 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n02i02474arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2474.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n02i02474ent IS
END c07s03b02x02p13n02i02474ent;
ARCHITECTURE c07s03b02x02p13n02i02474arch OF c07s03b02x02p13n02i02474ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
BEGIN
TESTING: PROCESS
variable k : CA_DOWN;
BEGIN
k := CA_DOWN'((10 downto 1 => 'B'));
assert NOT(k="BBBBBBBBBB")
report "***PASSED TEST: c07s03b02x02p13n02i02474"
severity NOTE;
assert (k="BBBBBBBBBB")
report "***FAILED TEST: c07s03b02x02p13n02i02474 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n02i02474arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity keyboard is
port (
clk : in std_logic;
rst_n : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
col : out std_logic_vector(3 downto 0);
row : in std_logic_vector(13 downto 0);
break : out std_logic;
turbo : out std_logic_vector(1 downto 0)
);
end entity;
architecture rtl of keyboard is
type key_matrix is array(0 to 13) of std_logic_vector(3 downto 0);
signal keys : key_matrix;
signal release : std_logic;
signal extended : std_logic;
signal keyb_data : std_logic_vector(7 downto 0);
signal keyb_valid : std_logic;
signal keyb_error : std_logic;
begin
ps2 : entity work.ps2_intf port map (
CLK => clk,
nRESET => rst_n,
PS2_CLK => ps2_clk,
PS2_DATA => ps2_data,
DATA => keyb_data,
VALID => keyb_valid,
error => keyb_error
);
process(keys, row)
variable i : integer;
variable tmp : std_logic_vector(3 downto 0);
begin
tmp := "1111";
for i in 0 to 13 loop
if (row(i) = '0') then
tmp := tmp and keys(i);
end if;
end loop;
col <= tmp;
end process;
process(clk, rst_n)
begin
if rst_n = '0' then
release <= '0';
extended <= '0';
turbo <= "01"; -- 2MHz
break <= '1';
keys( 0) <= (others => '1');
keys( 1) <= (others => '1');
keys( 2) <= (others => '1');
keys( 3) <= (others => '1');
keys( 4) <= (others => '1');
keys( 5) <= (others => '1');
keys( 6) <= (others => '1');
keys( 7) <= (others => '1');
keys( 8) <= (others => '1');
keys( 9) <= (others => '1');
keys(10) <= (others => '1');
keys(11) <= (others => '1');
keys(12) <= (others => '1');
keys(13) <= (others => '1');
elsif rising_edge(clk) then
if keyb_valid = '1' then
if keyb_data = X"e0" then
extended <= '1';
elsif keyb_data = X"f0" then
release <= '1';
else
release <= '0';
extended <= '0';
case keyb_data is
-- Special keys
when X"05" => turbo <= "00"; -- F1 (1MHz)
when X"06" => turbo <= "01"; -- F2 (2MMz)
when X"04" => turbo <= "10"; -- F3 (4MHz)
when X"0C" => turbo <= "11"; -- F4 (8MHz)
when X"09" => break <= release; -- F10 (BREAK)
-- Key Matrix
when X"74" => keys( 0)(0) <= release; -- RIGHT
when X"69" => keys( 0)(1) <= release; -- END (COPY)
-- keys( 0)(2) -- NC
when X"29" => keys( 0)(3) <= release; -- SPACE
when X"6B" => keys( 1)(0) <= release; -- LEFT
when X"72" => keys( 1)(1) <= release; -- DOWN
when X"5B" => keys( 1)(1) <= release; -- ]
when X"5A" => keys( 1)(2) <= release; -- RETURN
when X"66" => keys( 1)(3) <= release; -- BACKSPACE (DELETE)
when X"4E" => keys( 2)(0) <= release; -- -
when X"75" => keys( 2)(1) <= release; -- UP
when X"54" => keys( 2)(1) <= release; -- [
when X"52" => keys( 2)(2) <= release; -- ' full colon substitute
-- keys( 2)(3) -- NC
when X"45" => keys( 3)(0) <= release; -- 0
when X"4D" => keys( 3)(1) <= release; -- P
when X"4C" => keys( 3)(2) <= release; -- ;
when X"4A" => keys( 3)(3) <= release; -- /
when X"46" => keys( 4)(0) <= release; -- 9
when X"44" => keys( 4)(1) <= release; -- O
when X"4B" => keys( 4)(2) <= release; -- L
when X"49" => keys( 4)(3) <= release; -- .
when X"3E" => keys( 5)(0) <= release; -- 8
when X"43" => keys( 5)(1) <= release; -- I
when X"42" => keys( 5)(2) <= release; -- K
when X"41" => keys( 5)(3) <= release; -- ,
when X"3D" => keys( 6)(0) <= release; -- 7
when X"3C" => keys( 6)(1) <= release; -- U
when X"3B" => keys( 6)(2) <= release; -- J
when X"3A" => keys( 6)(3) <= release; -- M
when X"36" => keys( 7)(0) <= release; -- 6
when X"35" => keys( 7)(1) <= release; -- Y
when X"33" => keys( 7)(2) <= release; -- H
when X"31" => keys( 7)(3) <= release; -- N
when X"2E" => keys( 8)(0) <= release; -- 5
when X"2C" => keys( 8)(1) <= release; -- T
when X"34" => keys( 8)(2) <= release; -- G
when X"32" => keys( 8)(3) <= release; -- B
when X"25" => keys( 9)(0) <= release; -- 4
when X"2D" => keys( 9)(1) <= release; -- R
when X"2B" => keys( 9)(2) <= release; -- F
when X"2A" => keys( 9)(3) <= release; -- V
when X"26" => keys(10)(0) <= release; -- 3
when X"24" => keys(10)(1) <= release; -- E
when X"23" => keys(10)(2) <= release; -- D
when X"21" => keys(10)(3) <= release; -- C
when X"1E" => keys(11)(0) <= release; -- 2
when X"1D" => keys(11)(1) <= release; -- W
when X"1B" => keys(11)(2) <= release; -- S
when X"22" => keys(11)(3) <= release; -- X
when X"16" => keys(12)(0) <= release; -- 1
when X"15" => keys(12)(1) <= release; -- Q
when X"1C" => keys(12)(2) <= release; -- A
when X"1A" => keys(12)(3) <= release; -- Z
when X"76" => keys(13)(0) <= release; -- ESCAPE
when X"58" => keys(13)(1) <= release; -- CAPS LOCK
when X"14" => keys(13)(2) <= release; -- LEFT/RIGHT CTRL (CTRL)
when X"12" | X"59" =>
if (extended = '0') then -- Ignore fake shifts
keys(13)(3) <= release; -- Left SHIFT -- Right SHIFT
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_ALU IS
END tb_ALU;
ARCHITECTURE behavior OF tb_ALU IS
--Inputs
SIGNAL tb_a1 : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_a2 : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_alu_control : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_alu_result : std_logic_vector(31 DOWNTO 0);
SIGNAL tb_zero : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : ENTITY work.ALU(Behavioral)
PORT MAP(
a1 => tb_a1,
a2 => tb_a2,
alu_control => tb_alu_control,
alu_result => tb_alu_result,
zero => tb_zero
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
tb_a1 <= x"00000003";
tb_a2 <= x"FFFFFFFF";
tb_alu_control <= "0000"; --bitwise and
WAIT FOR 50 ns;
tb_alu_control <= "0001"; --bitwise or
WAIT FOR 50 ns;
tb_alu_control <= "0010"; --bitwise addition
WAIT FOR 50 ns;
tb_alu_control <= "0110"; --bitwise substraction
WAIT FOR 50 ns;
tb_alu_control <= "0111"; --set les than
WAIT FOR 50 ns;
tb_alu_control <= "1100"; --bitwise nor
WAIT FOR 50 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity debounce is
generic(timeOut: integer:=2000000);
port(
input: in std_logic;
clk: in std_logic;
output: out std_logic;
reset: in std_logic
);
end debounce;
architecture Behavioral of debounce is
signal capture: std_logic;
begin
count: process(input,clk)
variable count: integer range 0 to timeOut*2:=0;
variable inputCapture: std_logic;
begin
if(reset = '1') then
count := 0;
inputCapture <= '0';
output <= '0';
elsif(rising_edge(clk)) then
if(count = 0) then
inputCapture := input;
capture <= '1';
else
capture <= '0';
inputCapture := inputCapture;
end if;
if(capture = '1' AND count = timeOut AND input = inputCapture) then
output <= inputCapture;
count := 0;
capture <= '0';
elsif (capture = '1' and count = timeOut and not(input = inputCapture)) then
count := 0;
capture <= '0';
output <= input;
elsif(capture = '1') then
capture <= capture;
count := count+1;
output <= '0';
else
count := count;
output <= ;
capture <= '0';
end if;
end if;
end process;
end Behavioral;
|
---------------------------------------------------------------------
-- LXP32 CPU Core
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_cpu is
generic(
DBUS_RMW: boolean;
DIVIDER_EN: boolean;
MUL_ARCH: string;
START_ADDR: std_logic_vector(31 downto 0)
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic;
dbus_cyc_o: out std_logic;
dbus_stb_o: out std_logic;
dbus_we_o: out std_logic;
dbus_sel_o: out std_logic_vector(3 downto 0);
dbus_ack_i: in std_logic;
dbus_adr_o: out std_logic_vector(31 downto 2);
dbus_dat_o: out std_logic_vector(31 downto 0);
dbus_dat_i: in std_logic_vector(31 downto 0);
irq_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of lxp32_cpu is
signal fetch_word: std_logic_vector(31 downto 0);
signal fetch_next_ip: std_logic_vector(29 downto 0);
signal fetch_current_ip: std_logic_vector(29 downto 0);
signal fetch_valid: std_logic;
signal fetch_jump_ready: std_logic;
signal decode_ready: std_logic;
signal decode_valid: std_logic;
signal decode_cmd_loadop3: std_logic;
signal decode_cmd_signed: std_logic;
signal decode_cmd_dbus: std_logic;
signal decode_cmd_dbus_store: std_logic;
signal decode_cmd_dbus_byte: std_logic;
signal decode_cmd_addsub: std_logic;
signal decode_cmd_mul: std_logic;
signal decode_cmd_div: std_logic;
signal decode_cmd_div_mod: std_logic;
signal decode_cmd_cmp: std_logic;
signal decode_cmd_jump: std_logic;
signal decode_cmd_negate_op2: std_logic;
signal decode_cmd_and: std_logic;
signal decode_cmd_xor: std_logic;
signal decode_cmd_shift: std_logic;
signal decode_cmd_shift_right: std_logic;
signal decode_jump_type: std_logic_vector(3 downto 0);
signal decode_op1: std_logic_vector(31 downto 0);
signal decode_op2: std_logic_vector(31 downto 0);
signal decode_op3: std_logic_vector(31 downto 0);
signal decode_dst: std_logic_vector(7 downto 0);
signal execute_ready: std_logic;
signal execute_jump_valid: std_logic;
signal execute_jump_dst: std_logic_vector(29 downto 0);
signal sp_raddr1: std_logic_vector(7 downto 0);
signal sp_rdata1: std_logic_vector(31 downto 0);
signal sp_raddr2: std_logic_vector(7 downto 0);
signal sp_rdata2: std_logic_vector(31 downto 0);
signal sp_waddr: std_logic_vector(7 downto 0);
signal sp_we: std_logic;
signal sp_wdata: std_logic_vector(31 downto 0);
signal interrupt_valid: std_logic;
signal interrupt_vector: std_logic_vector(2 downto 0);
signal interrupt_ready: std_logic;
signal interrupt_return: std_logic;
signal interrupt_wakeup: std_logic;
begin
fetch_inst: entity work.lxp32_fetch(rtl)
generic map(
START_ADDR=>START_ADDR
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_o=>lli_re_o,
lli_adr_o=>lli_adr_o,
lli_dat_i=>lli_dat_i,
lli_busy_i=>lli_busy_i,
word_o=>fetch_word,
next_ip_o=>fetch_next_ip,
current_ip_o=>fetch_current_ip,
valid_o=>fetch_valid,
ready_i=>decode_ready,
jump_valid_i=>execute_jump_valid,
jump_dst_i=>execute_jump_dst,
jump_ready_o=>fetch_jump_ready
);
decode_inst: entity work.lxp32_decode(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
word_i=>fetch_word,
next_ip_i=>fetch_next_ip,
current_ip_i=>fetch_current_ip,
valid_i=>fetch_valid,
jump_valid_i=>execute_jump_valid,
ready_o=>decode_ready,
interrupt_valid_i=>interrupt_valid,
interrupt_vector_i=>interrupt_vector,
interrupt_ready_o=>interrupt_ready,
wakeup_i=>interrupt_wakeup,
sp_raddr1_o=>sp_raddr1,
sp_rdata1_i=>sp_rdata1,
sp_raddr2_o=>sp_raddr2,
sp_rdata2_i=>sp_rdata2,
ready_i=>execute_ready,
valid_o=>decode_valid,
cmd_loadop3_o=>decode_cmd_loadop3,
cmd_signed_o=>decode_cmd_signed,
cmd_dbus_o=>decode_cmd_dbus,
cmd_dbus_store_o=>decode_cmd_dbus_store,
cmd_dbus_byte_o=>decode_cmd_dbus_byte,
cmd_addsub_o=>decode_cmd_addsub,
cmd_mul_o=>decode_cmd_mul,
cmd_div_o=>decode_cmd_div,
cmd_div_mod_o=>decode_cmd_div_mod,
cmd_cmp_o=>decode_cmd_cmp,
cmd_jump_o=>decode_cmd_jump,
cmd_negate_op2_o=>decode_cmd_negate_op2,
cmd_and_o=>decode_cmd_and,
cmd_xor_o=>decode_cmd_xor,
cmd_shift_o=>decode_cmd_shift,
cmd_shift_right_o=>decode_cmd_shift_right,
jump_type_o=>decode_jump_type,
op1_o=>decode_op1,
op2_o=>decode_op2,
op3_o=>decode_op3,
dst_o=>decode_dst
);
execute_inst: entity work.lxp32_execute(rtl)
generic map(
DBUS_RMW=>DBUS_RMW,
DIVIDER_EN=>DIVIDER_EN,
MUL_ARCH=>MUL_ARCH
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
cmd_loadop3_i=>decode_cmd_loadop3,
cmd_signed_i=>decode_cmd_signed,
cmd_dbus_i=>decode_cmd_dbus,
cmd_dbus_store_i=>decode_cmd_dbus_store,
cmd_dbus_byte_i=>decode_cmd_dbus_byte,
cmd_addsub_i=>decode_cmd_addsub,
cmd_mul_i=>decode_cmd_mul,
cmd_div_i=>decode_cmd_div,
cmd_div_mod_i=>decode_cmd_div_mod,
cmd_cmp_i=>decode_cmd_cmp,
cmd_jump_i=>decode_cmd_jump,
cmd_negate_op2_i=>decode_cmd_negate_op2,
cmd_and_i=>decode_cmd_and,
cmd_xor_i=>decode_cmd_xor,
cmd_shift_i=>decode_cmd_shift,
cmd_shift_right_i=>decode_cmd_shift_right,
jump_type_i=>decode_jump_type,
op1_i=>decode_op1,
op2_i=>decode_op2,
op3_i=>decode_op3,
dst_i=>decode_dst,
sp_waddr_o=>sp_waddr,
sp_we_o=>sp_we,
sp_wdata_o=>sp_wdata,
valid_i=>decode_valid,
ready_o=>execute_ready,
dbus_cyc_o=>dbus_cyc_o,
dbus_stb_o=>dbus_stb_o,
dbus_we_o=>dbus_we_o,
dbus_sel_o=>dbus_sel_o,
dbus_ack_i=>dbus_ack_i,
dbus_adr_o=>dbus_adr_o,
dbus_dat_o=>dbus_dat_o,
dbus_dat_i=>dbus_dat_i,
jump_valid_o=>execute_jump_valid,
jump_dst_o=>execute_jump_dst,
jump_ready_i=>fetch_jump_ready,
interrupt_return_o=>interrupt_return
);
scratchpad_inst: entity work.lxp32_scratchpad(rtl)
port map(
clk_i=>clk_i,
raddr1_i=>sp_raddr1,
rdata1_o=>sp_rdata1,
raddr2_i=>sp_raddr2,
rdata2_o=>sp_rdata2,
waddr_i=>sp_waddr,
we_i=>sp_we,
wdata_i=>sp_wdata
);
interrupt_mux_inst: entity work.lxp32_interrupt_mux(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
irq_i=>irq_i,
interrupt_valid_o=>interrupt_valid,
interrupt_vector_o=>interrupt_vector,
interrupt_ready_i=>interrupt_ready,
interrupt_return_i=>interrupt_return,
wakeup_o=>interrupt_wakeup,
sp_waddr_i=>sp_waddr,
sp_we_i=>sp_we,
sp_wdata_i=>sp_wdata
);
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity reg4 is
port ( clk, clr, d0, d1, d2, d3 : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
architecture struct of reg4 is
begin
bit0 : entity work.edge_triggered_Dff(behavioral)
port map (d0, clk, clr, q0);
bit1 : entity work.edge_triggered_Dff(behavioral)
port map (d1, clk, clr, q1);
bit2 : entity work.edge_triggered_Dff(behavioral)
port map (d2, clk, clr, q2);
bit3 : entity work.edge_triggered_Dff(behavioral)
port map (d3, clk, clr, q3);
end architecture struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity reg4 is
port ( clk, clr, d0, d1, d2, d3 : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
architecture struct of reg4 is
begin
bit0 : entity work.edge_triggered_Dff(behavioral)
port map (d0, clk, clr, q0);
bit1 : entity work.edge_triggered_Dff(behavioral)
port map (d1, clk, clr, q1);
bit2 : entity work.edge_triggered_Dff(behavioral)
port map (d2, clk, clr, q2);
bit3 : entity work.edge_triggered_Dff(behavioral)
port map (d3, clk, clr, q3);
end architecture struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity reg4 is
port ( clk, clr, d0, d1, d2, d3 : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
architecture struct of reg4 is
begin
bit0 : entity work.edge_triggered_Dff(behavioral)
port map (d0, clk, clr, q0);
bit1 : entity work.edge_triggered_Dff(behavioral)
port map (d1, clk, clr, q1);
bit2 : entity work.edge_triggered_Dff(behavioral)
port map (d2, clk, clr, q2);
bit3 : entity work.edge_triggered_Dff(behavioral)
port map (d3, clk, clr, q3);
end architecture struct;
|
--------------------------------------------
-- Author: Mike Field <hamster@snap.net.nz>
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gps_capture is
port (
clk : in std_logic;
---------------------------------------
-- From the GPS front end
---------------------------------------
gps_mag : in std_logic;
gps_sgn : in std_logic;
gps_clk : in std_logic;
---------------------------------------
-- To the FIFO for transfer to the host
---------------------------------------
fifo_data : out std_logic_vector(7 downto 0) := (others => '0');
fifo_we : out std_logic;
fifo_full : in std_logic;
fifo_empty : in std_logic;
---------------------------------------
-- status for user
---------------------------------------
led : OUT std_logic_vector(7 downto 0);
overrun : out std_logic);
end gps_capture;
architecture Behavioral of gps_capture is
signal sync_mag : std_logic_vector(3 downto 0) := "0000";
signal sync_sgn : std_logic_vector(3 downto 0) := "0000";
signal sync_clk : std_logic_vector(3 downto 0) := "0000";
signal overrun_counter : unsigned(26 downto 0) := (others => '1');
signal data : std_logic_vector(7 downto 0) := x"00";
signal fifo_active : std_logic := '0';
signal one_in_six : std_logic_vector(2 downto 0) := "001";
signal gap_count : unsigned(7 downto 0) := (others => '0');
signal max_gap : unsigned(7 downto 0) := (others => '0');
begin
fifo_data <= data;
led <= std_logic_vector(max_gap);
clk_proc: process(clk)
begin
if rising_edge(clk) then
fifo_we <= '0';
--------------------------------------------------
-- Capture the data on the rising edge of sync_clk
--------------------------------------------------
if sync_clk(1) = '1' and sync_clk(0) = '0' then
-- The upper two bits form a sequence counter to enable the
-- detection dropped data in the transfer to the host.
if one_in_six(0) = '1' then
data(7 downto 6) <= std_logic_vector(unsigned(data(7 downto 6))+1);
end if;
data(5 downto 0) <= sync_sgn(0) & data(5 downto 1);
fifo_we <= fifo_active and one_in_six(0);
one_in_six <= one_in_six(0) & one_in_six(5 downto 1);
if max_gap < gap_count then
max_gap <= gap_count;
end if;
gap_count <= (others => '0');
else
if gap_count /= x"FF" then
gap_count <= gap_count+1;
end if;
end if;
--------------------------------------------------------
-- Displaying to the user when the FIFO is stalled.
-- This stretches the pulse on overrun for at least
-- 2^(overrun_counter'high) cycles if fifo_full gets set
--------------------------------------------------------
overrun <= std_logic(overrun_counter(overrun_counter'high));
if fifo_full = '1' then
overrun_counter <= (others => '1');
else
overrun_counter <= overrun_counter - overrun_counter(overrun_counter'high downto overrun_counter'high);
end if;
-----------------------------------------------------------
-- If the fifo becomes full, then assume that the host is
-- no longer reading new data. However, if the fifo becomes
-- empty, then assume that the host is pulling data.
-----------------------------------------------------------
if fifo_empty = '1' then
fifo_active <= '1';
elsif fifo_full = '1' then
fifo_active <= '0';
overrun_counter <= (others => '1');
end if;
-----------------------------------------
-- Synchronise the incoming signals
-----------------------------------------
sync_mag <= gps_mag & sync_mag(3 downto 1);
sync_sgn <= gps_sgn & sync_sgn(3 downto 1);
sync_clk <= gps_clk & sync_clk(3 downto 1);
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc731.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00731ent IS
-- A basic entity with a port
port ( signal s : bit);
END c01s01b01x00p04n01i00731ent;
ARCHITECTURE c01s01b01x00p04n01i00731arch OF c01s01b01x00p04n01i00731ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x00p04n01i00731"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00731arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc731.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00731ent IS
-- A basic entity with a port
port ( signal s : bit);
END c01s01b01x00p04n01i00731ent;
ARCHITECTURE c01s01b01x00p04n01i00731arch OF c01s01b01x00p04n01i00731ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x00p04n01i00731"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00731arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc731.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00731ent IS
-- A basic entity with a port
port ( signal s : bit);
END c01s01b01x00p04n01i00731ent;
ARCHITECTURE c01s01b01x00p04n01i00731arch OF c01s01b01x00p04n01i00731ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x00p04n01i00731"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00731arch;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT20.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut20 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
END dp_explut20;
ARCHITECTURE rtl OF dp_explut20 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16,24);
manlo <= conv_std_logic_vector(2048,28);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32,24);
manlo <= conv_std_logic_vector(8192,28);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(48,24);
manlo <= conv_std_logic_vector(18432,28);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(64,24);
manlo <= conv_std_logic_vector(32768,28);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(80,24);
manlo <= conv_std_logic_vector(51200,28);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(96,24);
manlo <= conv_std_logic_vector(73728,28);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(112,24);
manlo <= conv_std_logic_vector(100352,28);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(128,24);
manlo <= conv_std_logic_vector(131072,28);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(144,24);
manlo <= conv_std_logic_vector(165888,28);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(160,24);
manlo <= conv_std_logic_vector(204801,28);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(176,24);
manlo <= conv_std_logic_vector(247809,28);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(192,24);
manlo <= conv_std_logic_vector(294913,28);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(208,24);
manlo <= conv_std_logic_vector(346113,28);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(224,24);
manlo <= conv_std_logic_vector(401410,28);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(240,24);
manlo <= conv_std_logic_vector(460802,28);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(256,24);
manlo <= conv_std_logic_vector(524291,28);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(272,24);
manlo <= conv_std_logic_vector(591875,28);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(288,24);
manlo <= conv_std_logic_vector(663556,28);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(304,24);
manlo <= conv_std_logic_vector(739332,28);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(320,24);
manlo <= conv_std_logic_vector(819205,28);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(336,24);
manlo <= conv_std_logic_vector(903174,28);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(352,24);
manlo <= conv_std_logic_vector(991239,28);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(368,24);
manlo <= conv_std_logic_vector(1083400,28);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(384,24);
manlo <= conv_std_logic_vector(1179657,28);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(400,24);
manlo <= conv_std_logic_vector(1280010,28);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(416,24);
manlo <= conv_std_logic_vector(1384459,28);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(432,24);
manlo <= conv_std_logic_vector(1493005,28);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(448,24);
manlo <= conv_std_logic_vector(1605646,28);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(464,24);
manlo <= conv_std_logic_vector(1722384,28);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(480,24);
manlo <= conv_std_logic_vector(1843218,28);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(496,24);
manlo <= conv_std_logic_vector(1968147,28);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(512,24);
manlo <= conv_std_logic_vector(2097173,28);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(528,24);
manlo <= conv_std_logic_vector(2230295,28);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(544,24);
manlo <= conv_std_logic_vector(2367514,28);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(560,24);
manlo <= conv_std_logic_vector(2508828,28);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(576,24);
manlo <= conv_std_logic_vector(2654238,28);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(592,24);
manlo <= conv_std_logic_vector(2803745,28);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(608,24);
manlo <= conv_std_logic_vector(2957348,28);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(624,24);
manlo <= conv_std_logic_vector(3115047,28);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(640,24);
manlo <= conv_std_logic_vector(3276842,28);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(656,24);
manlo <= conv_std_logic_vector(3442733,28);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(672,24);
manlo <= conv_std_logic_vector(3612720,28);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(688,24);
manlo <= conv_std_logic_vector(3786804,28);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(704,24);
manlo <= conv_std_logic_vector(3964983,28);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(720,24);
manlo <= conv_std_logic_vector(4147259,28);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(736,24);
manlo <= conv_std_logic_vector(4333631,28);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(752,24);
manlo <= conv_std_logic_vector(4524100,28);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(768,24);
manlo <= conv_std_logic_vector(4718664,28);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(784,24);
manlo <= conv_std_logic_vector(4917325,28);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(800,24);
manlo <= conv_std_logic_vector(5120081,28);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(816,24);
manlo <= conv_std_logic_vector(5326934,28);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(832,24);
manlo <= conv_std_logic_vector(5537884,28);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(848,24);
manlo <= conv_std_logic_vector(5752929,28);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(864,24);
manlo <= conv_std_logic_vector(5972071,28);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(880,24);
manlo <= conv_std_logic_vector(6195308,28);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(896,24);
manlo <= conv_std_logic_vector(6422642,28);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(912,24);
manlo <= conv_std_logic_vector(6654073,28);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(928,24);
manlo <= conv_std_logic_vector(6889599,28);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(944,24);
manlo <= conv_std_logic_vector(7129222,28);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(960,24);
manlo <= conv_std_logic_vector(7372941,28);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(976,24);
manlo <= conv_std_logic_vector(7620756,28);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(992,24);
manlo <= conv_std_logic_vector(7872667,28);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1008,24);
manlo <= conv_std_logic_vector(8128675,28);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1024,24);
manlo <= conv_std_logic_vector(8388779,28);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1040,24);
manlo <= conv_std_logic_vector(8652979,28);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1056,24);
manlo <= conv_std_logic_vector(8921275,28);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1072,24);
manlo <= conv_std_logic_vector(9193668,28);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1088,24);
manlo <= conv_std_logic_vector(9470157,28);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1104,24);
manlo <= conv_std_logic_vector(9750742,28);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1120,24);
manlo <= conv_std_logic_vector(10035423,28);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1136,24);
manlo <= conv_std_logic_vector(10324201,28);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1152,24);
manlo <= conv_std_logic_vector(10617075,28);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1168,24);
manlo <= conv_std_logic_vector(10914045,28);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1184,24);
manlo <= conv_std_logic_vector(11215112,28);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1200,24);
manlo <= conv_std_logic_vector(11520275,28);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1216,24);
manlo <= conv_std_logic_vector(11829534,28);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1232,24);
manlo <= conv_std_logic_vector(12142889,28);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1248,24);
manlo <= conv_std_logic_vector(12460341,28);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1264,24);
manlo <= conv_std_logic_vector(12781889,28);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1280,24);
manlo <= conv_std_logic_vector(13107533,28);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1296,24);
manlo <= conv_std_logic_vector(13437274,28);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1312,24);
manlo <= conv_std_logic_vector(13771111,28);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1328,24);
manlo <= conv_std_logic_vector(14109044,28);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1344,24);
manlo <= conv_std_logic_vector(14451074,28);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1360,24);
manlo <= conv_std_logic_vector(14797200,28);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1376,24);
manlo <= conv_std_logic_vector(15147422,28);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1392,24);
manlo <= conv_std_logic_vector(15501741,28);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1408,24);
manlo <= conv_std_logic_vector(15860156,28);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1424,24);
manlo <= conv_std_logic_vector(16222667,28);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1440,24);
manlo <= conv_std_logic_vector(16589275,28);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1456,24);
manlo <= conv_std_logic_vector(16959979,28);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1472,24);
manlo <= conv_std_logic_vector(17334779,28);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1488,24);
manlo <= conv_std_logic_vector(17713676,28);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1504,24);
manlo <= conv_std_logic_vector(18096669,28);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1520,24);
manlo <= conv_std_logic_vector(18483758,28);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1536,24);
manlo <= conv_std_logic_vector(18874944,28);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1552,24);
manlo <= conv_std_logic_vector(19270226,28);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1568,24);
manlo <= conv_std_logic_vector(19669605,28);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1584,24);
manlo <= conv_std_logic_vector(20073080,28);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1600,24);
manlo <= conv_std_logic_vector(20480651,28);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1616,24);
manlo <= conv_std_logic_vector(20892319,28);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1632,24);
manlo <= conv_std_logic_vector(21308083,28);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1648,24);
manlo <= conv_std_logic_vector(21727943,28);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1664,24);
manlo <= conv_std_logic_vector(22151900,28);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1680,24);
manlo <= conv_std_logic_vector(22579954,28);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1696,24);
manlo <= conv_std_logic_vector(23012103,28);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1712,24);
manlo <= conv_std_logic_vector(23448350,28);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1728,24);
manlo <= conv_std_logic_vector(23888692,28);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1744,24);
manlo <= conv_std_logic_vector(24333131,28);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1760,24);
manlo <= conv_std_logic_vector(24781667,28);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1776,24);
manlo <= conv_std_logic_vector(25234298,28);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1792,24);
manlo <= conv_std_logic_vector(25691027,28);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1808,24);
manlo <= conv_std_logic_vector(26151851,28);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1824,24);
manlo <= conv_std_logic_vector(26616773,28);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1840,24);
manlo <= conv_std_logic_vector(27085790,28);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(1856,24);
manlo <= conv_std_logic_vector(27558904,28);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(1872,24);
manlo <= conv_std_logic_vector(28036115,28);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(1888,24);
manlo <= conv_std_logic_vector(28517422,28);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(1904,24);
manlo <= conv_std_logic_vector(29002825,28);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(1920,24);
manlo <= conv_std_logic_vector(29492325,28);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(1936,24);
manlo <= conv_std_logic_vector(29985921,28);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(1952,24);
manlo <= conv_std_logic_vector(30483614,28);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(1968,24);
manlo <= conv_std_logic_vector(30985404,28);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1984,24);
manlo <= conv_std_logic_vector(31491289,28);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2000,24);
manlo <= conv_std_logic_vector(32001272,28);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2016,24);
manlo <= conv_std_logic_vector(32515350,28);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2032,24);
manlo <= conv_std_logic_vector(33033526,28);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2048,24);
manlo <= conv_std_logic_vector(33555797,28);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2064,24);
manlo <= conv_std_logic_vector(34082166,28);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2080,24);
manlo <= conv_std_logic_vector(34612630,28);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2096,24);
manlo <= conv_std_logic_vector(35147192,28);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2112,24);
manlo <= conv_std_logic_vector(35685849,28);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2128,24);
manlo <= conv_std_logic_vector(36228604,28);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2144,24);
manlo <= conv_std_logic_vector(36775455,28);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2160,24);
manlo <= conv_std_logic_vector(37326402,28);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2176,24);
manlo <= conv_std_logic_vector(37881446,28);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2192,24);
manlo <= conv_std_logic_vector(38440586,28);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2208,24);
manlo <= conv_std_logic_vector(39003823,28);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2224,24);
manlo <= conv_std_logic_vector(39571157,28);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2240,24);
manlo <= conv_std_logic_vector(40142587,28);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2256,24);
manlo <= conv_std_logic_vector(40718113,28);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2272,24);
manlo <= conv_std_logic_vector(41297736,28);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2288,24);
manlo <= conv_std_logic_vector(41881456,28);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2304,24);
manlo <= conv_std_logic_vector(42469272,28);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2320,24);
manlo <= conv_std_logic_vector(43061185,28);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2336,24);
manlo <= conv_std_logic_vector(43657194,28);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2352,24);
manlo <= conv_std_logic_vector(44257300,28);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2368,24);
manlo <= conv_std_logic_vector(44861503,28);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2384,24);
manlo <= conv_std_logic_vector(45469802,28);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2400,24);
manlo <= conv_std_logic_vector(46082197,28);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2416,24);
manlo <= conv_std_logic_vector(46698690,28);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2432,24);
manlo <= conv_std_logic_vector(47319278,28);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2448,24);
manlo <= conv_std_logic_vector(47943964,28);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2464,24);
manlo <= conv_std_logic_vector(48572746,28);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2480,24);
manlo <= conv_std_logic_vector(49205624,28);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2496,24);
manlo <= conv_std_logic_vector(49842600,28);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2512,24);
manlo <= conv_std_logic_vector(50483672,28);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2528,24);
manlo <= conv_std_logic_vector(51128840,28);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2544,24);
manlo <= conv_std_logic_vector(51778105,28);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2560,24);
manlo <= conv_std_logic_vector(52431467,28);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2576,24);
manlo <= conv_std_logic_vector(53088925,28);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2592,24);
manlo <= conv_std_logic_vector(53750480,28);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2608,24);
manlo <= conv_std_logic_vector(54416132,28);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2624,24);
manlo <= conv_std_logic_vector(55085880,28);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2640,24);
manlo <= conv_std_logic_vector(55759725,28);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2656,24);
manlo <= conv_std_logic_vector(56437666,28);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2672,24);
manlo <= conv_std_logic_vector(57119704,28);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2688,24);
manlo <= conv_std_logic_vector(57805839,28);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2704,24);
manlo <= conv_std_logic_vector(58496071,28);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(2720,24);
manlo <= conv_std_logic_vector(59190399,28);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(2736,24);
manlo <= conv_std_logic_vector(59888823,28);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(2752,24);
manlo <= conv_std_logic_vector(60591345,28);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(2768,24);
manlo <= conv_std_logic_vector(61297963,28);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(2784,24);
manlo <= conv_std_logic_vector(62008678,28);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(2800,24);
manlo <= conv_std_logic_vector(62723489,28);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(2816,24);
manlo <= conv_std_logic_vector(63442397,28);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(2832,24);
manlo <= conv_std_logic_vector(64165402,28);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2848,24);
manlo <= conv_std_logic_vector(64892504,28);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(2864,24);
manlo <= conv_std_logic_vector(65623702,28);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(2880,24);
manlo <= conv_std_logic_vector(66358997,28);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(2896,24);
manlo <= conv_std_logic_vector(67098389,28);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(2912,24);
manlo <= conv_std_logic_vector(67841877,28);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(2928,24);
manlo <= conv_std_logic_vector(68589462,28);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(2944,24);
manlo <= conv_std_logic_vector(69341144,28);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(2960,24);
manlo <= conv_std_logic_vector(70096922,28);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(2976,24);
manlo <= conv_std_logic_vector(70856798,28);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2992,24);
manlo <= conv_std_logic_vector(71620769,28);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3008,24);
manlo <= conv_std_logic_vector(72388838,28);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3024,24);
manlo <= conv_std_logic_vector(73161004,28);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3040,24);
manlo <= conv_std_logic_vector(73937266,28);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3056,24);
manlo <= conv_std_logic_vector(74717625,28);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3072,24);
manlo <= conv_std_logic_vector(75502080,28);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3088,24);
manlo <= conv_std_logic_vector(76290633,28);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3104,24);
manlo <= conv_std_logic_vector(77083282,28);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3120,24);
manlo <= conv_std_logic_vector(77880028,28);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3136,24);
manlo <= conv_std_logic_vector(78680870,28);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3152,24);
manlo <= conv_std_logic_vector(79485810,28);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3168,24);
manlo <= conv_std_logic_vector(80294846,28);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3184,24);
manlo <= conv_std_logic_vector(81107979,28);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3200,24);
manlo <= conv_std_logic_vector(81925209,28);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3216,24);
manlo <= conv_std_logic_vector(82746535,28);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3232,24);
manlo <= conv_std_logic_vector(83571958,28);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3248,24);
manlo <= conv_std_logic_vector(84401479,28);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3264,24);
manlo <= conv_std_logic_vector(85235095,28);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3280,24);
manlo <= conv_std_logic_vector(86072809,28);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3296,24);
manlo <= conv_std_logic_vector(86914620,28);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3312,24);
manlo <= conv_std_logic_vector(87760527,28);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3328,24);
manlo <= conv_std_logic_vector(88610531,28);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3344,24);
manlo <= conv_std_logic_vector(89464632,28);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3360,24);
manlo <= conv_std_logic_vector(90322830,28);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3376,24);
manlo <= conv_std_logic_vector(91185124,28);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3392,24);
manlo <= conv_std_logic_vector(92051516,28);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3408,24);
manlo <= conv_std_logic_vector(92922004,28);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3424,24);
manlo <= conv_std_logic_vector(93796589,28);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3440,24);
manlo <= conv_std_logic_vector(94675271,28);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3456,24);
manlo <= conv_std_logic_vector(95558049,28);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3472,24);
manlo <= conv_std_logic_vector(96444925,28);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3488,24);
manlo <= conv_std_logic_vector(97335897,28);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(3504,24);
manlo <= conv_std_logic_vector(98230967,28);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(3520,24);
manlo <= conv_std_logic_vector(99130133,28);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(3536,24);
manlo <= conv_std_logic_vector(100033396,28);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(3552,24);
manlo <= conv_std_logic_vector(100940755,28);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3568,24);
manlo <= conv_std_logic_vector(101852212,28);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(3584,24);
manlo <= conv_std_logic_vector(102767766,28);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(3600,24);
manlo <= conv_std_logic_vector(103687416,28);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(3616,24);
manlo <= conv_std_logic_vector(104611163,28);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(3632,24);
manlo <= conv_std_logic_vector(105539008,28);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(3648,24);
manlo <= conv_std_logic_vector(106470949,28);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(3664,24);
manlo <= conv_std_logic_vector(107406987,28);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(3680,24);
manlo <= conv_std_logic_vector(108347122,28);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(3696,24);
manlo <= conv_std_logic_vector(109291353,28);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3712,24);
manlo <= conv_std_logic_vector(110239682,28);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(3728,24);
manlo <= conv_std_logic_vector(111192108,28);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(3744,24);
manlo <= conv_std_logic_vector(112148630,28);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(3760,24);
manlo <= conv_std_logic_vector(113109250,28);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(3776,24);
manlo <= conv_std_logic_vector(114073966,28);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(3792,24);
manlo <= conv_std_logic_vector(115042779,28);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(3808,24);
manlo <= conv_std_logic_vector(116015689,28);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(3824,24);
manlo <= conv_std_logic_vector(116992696,28);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(3840,24);
manlo <= conv_std_logic_vector(117973801,28);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(3856,24);
manlo <= conv_std_logic_vector(118959001,28);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(3872,24);
manlo <= conv_std_logic_vector(119948299,28);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(3888,24);
manlo <= conv_std_logic_vector(120941694,28);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(3904,24);
manlo <= conv_std_logic_vector(121939186,28);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(3920,24);
manlo <= conv_std_logic_vector(122940775,28);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(3936,24);
manlo <= conv_std_logic_vector(123946461,28);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(3952,24);
manlo <= conv_std_logic_vector(124956243,28);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(3968,24);
manlo <= conv_std_logic_vector(125970123,28);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(3984,24);
manlo <= conv_std_logic_vector(126988100,28);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4000,24);
manlo <= conv_std_logic_vector(128010173,28);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4016,24);
manlo <= conv_std_logic_vector(129036344,28);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4032,24);
manlo <= conv_std_logic_vector(130066611,28);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4048,24);
manlo <= conv_std_logic_vector(131100976,28);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4064,24);
manlo <= conv_std_logic_vector(132139437,28);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4080,24);
manlo <= conv_std_logic_vector(133181996,28);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4096,24);
manlo <= conv_std_logic_vector(134228651,28);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4112,24);
manlo <= conv_std_logic_vector(135279404,28);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4128,24);
manlo <= conv_std_logic_vector(136334253,28);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4144,24);
manlo <= conv_std_logic_vector(137393200,28);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4160,24);
manlo <= conv_std_logic_vector(138456243,28);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4176,24);
manlo <= conv_std_logic_vector(139523384,28);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4192,24);
manlo <= conv_std_logic_vector(140594622,28);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4208,24);
manlo <= conv_std_logic_vector(141669956,28);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4224,24);
manlo <= conv_std_logic_vector(142749388,28);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4240,24);
manlo <= conv_std_logic_vector(143832916,28);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4256,24);
manlo <= conv_std_logic_vector(144920542,28);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4272,24);
manlo <= conv_std_logic_vector(146012265,28);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4288,24);
manlo <= conv_std_logic_vector(147108085,28);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(4304,24);
manlo <= conv_std_logic_vector(148208001,28);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(4320,24);
manlo <= conv_std_logic_vector(149312015,28);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(4336,24);
manlo <= conv_std_logic_vector(150420126,28);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(4352,24);
manlo <= conv_std_logic_vector(151532334,28);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(4368,24);
manlo <= conv_std_logic_vector(152648639,28);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(4384,24);
manlo <= conv_std_logic_vector(153769041,28);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(4400,24);
manlo <= conv_std_logic_vector(154893541,28);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(4416,24);
manlo <= conv_std_logic_vector(156022137,28);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4432,24);
manlo <= conv_std_logic_vector(157154830,28);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(4448,24);
manlo <= conv_std_logic_vector(158291621,28);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(4464,24);
manlo <= conv_std_logic_vector(159432508,28);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(4480,24);
manlo <= conv_std_logic_vector(160577493,28);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(4496,24);
manlo <= conv_std_logic_vector(161726574,28);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(4512,24);
manlo <= conv_std_logic_vector(162879753,28);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(4528,24);
manlo <= conv_std_logic_vector(164037029,28);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(4544,24);
manlo <= conv_std_logic_vector(165198402,28);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(4560,24);
manlo <= conv_std_logic_vector(166363872,28);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(4576,24);
manlo <= conv_std_logic_vector(167533439,28);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(4592,24);
manlo <= conv_std_logic_vector(168707104,28);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(4608,24);
manlo <= conv_std_logic_vector(169884865,28);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(4624,24);
manlo <= conv_std_logic_vector(171066724,28);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(4640,24);
manlo <= conv_std_logic_vector(172252679,28);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(4656,24);
manlo <= conv_std_logic_vector(173442732,28);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(4672,24);
manlo <= conv_std_logic_vector(174636882,28);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(4688,24);
manlo <= conv_std_logic_vector(175835129,28);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(4704,24);
manlo <= conv_std_logic_vector(177037474,28);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(4720,24);
manlo <= conv_std_logic_vector(178243915,28);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(4736,24);
manlo <= conv_std_logic_vector(179454454,28);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(4752,24);
manlo <= conv_std_logic_vector(180669089,28);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(4768,24);
manlo <= conv_std_logic_vector(181887822,28);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(4784,24);
manlo <= conv_std_logic_vector(183110652,28);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(4800,24);
manlo <= conv_std_logic_vector(184337579,28);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(4816,24);
manlo <= conv_std_logic_vector(185568604,28);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(4832,24);
manlo <= conv_std_logic_vector(186803725,28);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(4848,24);
manlo <= conv_std_logic_vector(188042944,28);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(4864,24);
manlo <= conv_std_logic_vector(189286260,28);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(4880,24);
manlo <= conv_std_logic_vector(190533673,28);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(4896,24);
manlo <= conv_std_logic_vector(191785183,28);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(4912,24);
manlo <= conv_std_logic_vector(193040791,28);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(4928,24);
manlo <= conv_std_logic_vector(194300496,28);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(4944,24);
manlo <= conv_std_logic_vector(195564298,28);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(4960,24);
manlo <= conv_std_logic_vector(196832197,28);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4976,24);
manlo <= conv_std_logic_vector(198104193,28);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(4992,24);
manlo <= conv_std_logic_vector(199380286,28);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5008,24);
manlo <= conv_std_logic_vector(200660477,28);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(5024,24);
manlo <= conv_std_logic_vector(201944765,28);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(5040,24);
manlo <= conv_std_logic_vector(203233150,28);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(5056,24);
manlo <= conv_std_logic_vector(204525633,28);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(5072,24);
manlo <= conv_std_logic_vector(205822213,28);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(5088,24);
manlo <= conv_std_logic_vector(207122889,28);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(5104,24);
manlo <= conv_std_logic_vector(208427664,28);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(5120,24);
manlo <= conv_std_logic_vector(209736535,28);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(5136,24);
manlo <= conv_std_logic_vector(211049504,28);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(5152,24);
manlo <= conv_std_logic_vector(212366570,28);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(5168,24);
manlo <= conv_std_logic_vector(213687733,28);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(5184,24);
manlo <= conv_std_logic_vector(215012993,28);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(5200,24);
manlo <= conv_std_logic_vector(216342351,28);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(5216,24);
manlo <= conv_std_logic_vector(217675806,28);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(5232,24);
manlo <= conv_std_logic_vector(219013358,28);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(5248,24);
manlo <= conv_std_logic_vector(220355007,28);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(5264,24);
manlo <= conv_std_logic_vector(221700754,28);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(5280,24);
manlo <= conv_std_logic_vector(223050598,28);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(5296,24);
manlo <= conv_std_logic_vector(224404540,28);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(5312,24);
manlo <= conv_std_logic_vector(225762578,28);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(5328,24);
manlo <= conv_std_logic_vector(227124714,28);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(5344,24);
manlo <= conv_std_logic_vector(228490948,28);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(5360,24);
manlo <= conv_std_logic_vector(229861278,28);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(5376,24);
manlo <= conv_std_logic_vector(231235706,28);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(5392,24);
manlo <= conv_std_logic_vector(232614231,28);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(5408,24);
manlo <= conv_std_logic_vector(233996854,28);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(5424,24);
manlo <= conv_std_logic_vector(235383573,28);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(5440,24);
manlo <= conv_std_logic_vector(236774391,28);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(5456,24);
manlo <= conv_std_logic_vector(238169305,28);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(5472,24);
manlo <= conv_std_logic_vector(239568317,28);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(5488,24);
manlo <= conv_std_logic_vector(240971426,28);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(5504,24);
manlo <= conv_std_logic_vector(242378633,28);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(5520,24);
manlo <= conv_std_logic_vector(243789936,28);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(5536,24);
manlo <= conv_std_logic_vector(245205338,28);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5552,24);
manlo <= conv_std_logic_vector(246624836,28);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(5568,24);
manlo <= conv_std_logic_vector(248048432,28);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(5584,24);
manlo <= conv_std_logic_vector(249476125,28);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(5600,24);
manlo <= conv_std_logic_vector(250907916,28);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(5616,24);
manlo <= conv_std_logic_vector(252343804,28);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(5632,24);
manlo <= conv_std_logic_vector(253783789,28);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(5648,24);
manlo <= conv_std_logic_vector(255227872,28);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(5664,24);
manlo <= conv_std_logic_vector(256676052,28);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(5680,24);
manlo <= conv_std_logic_vector(258128329,28);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5696,24);
manlo <= conv_std_logic_vector(259584704,28);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(5712,24);
manlo <= conv_std_logic_vector(261045176,28);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(5728,24);
manlo <= conv_std_logic_vector(262509746,28);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(5744,24);
manlo <= conv_std_logic_vector(263978413,28);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(5760,24);
manlo <= conv_std_logic_vector(265451178,28);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(5776,24);
manlo <= conv_std_logic_vector(266928039,28);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(5792,24);
manlo <= conv_std_logic_vector(268408999,28);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(5809,24);
manlo <= conv_std_logic_vector(1458599,28);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(5825,24);
manlo <= conv_std_logic_vector(2947754,28);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5841,24);
manlo <= conv_std_logic_vector(4441005,28);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(5857,24);
manlo <= conv_std_logic_vector(5938354,28);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(5873,24);
manlo <= conv_std_logic_vector(7439800,28);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(5889,24);
manlo <= conv_std_logic_vector(8945344,28);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(5905,24);
manlo <= conv_std_logic_vector(10454985,28);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(5921,24);
manlo <= conv_std_logic_vector(11968724,28);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(5937,24);
manlo <= conv_std_logic_vector(13486560,28);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(5953,24);
manlo <= conv_std_logic_vector(15008494,28);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(5969,24);
manlo <= conv_std_logic_vector(16534525,28);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5985,24);
manlo <= conv_std_logic_vector(18064653,28);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(6001,24);
manlo <= conv_std_logic_vector(19598879,28);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(6017,24);
manlo <= conv_std_logic_vector(21137203,28);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(6033,24);
manlo <= conv_std_logic_vector(22679624,28);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(6049,24);
manlo <= conv_std_logic_vector(24226142,28);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(6065,24);
manlo <= conv_std_logic_vector(25776758,28);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(6081,24);
manlo <= conv_std_logic_vector(27331471,28);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(6097,24);
manlo <= conv_std_logic_vector(28890282,28);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(6113,24);
manlo <= conv_std_logic_vector(30453190,28);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6129,24);
manlo <= conv_std_logic_vector(32020196,28);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(6145,24);
manlo <= conv_std_logic_vector(33591299,28);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(6161,24);
manlo <= conv_std_logic_vector(35166500,28);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(6177,24);
manlo <= conv_std_logic_vector(36745798,28);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(6193,24);
manlo <= conv_std_logic_vector(38329194,28);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(6209,24);
manlo <= conv_std_logic_vector(39916688,28);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(6225,24);
manlo <= conv_std_logic_vector(41508278,28);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(6241,24);
manlo <= conv_std_logic_vector(43103967,28);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(6257,24);
manlo <= conv_std_logic_vector(44703753,28);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6273,24);
manlo <= conv_std_logic_vector(46307636,28);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(6289,24);
manlo <= conv_std_logic_vector(47915617,28);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(6305,24);
manlo <= conv_std_logic_vector(49527695,28);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(6321,24);
manlo <= conv_std_logic_vector(51143871,28);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(6337,24);
manlo <= conv_std_logic_vector(52764145,28);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(6353,24);
manlo <= conv_std_logic_vector(54388516,28);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(6369,24);
manlo <= conv_std_logic_vector(56016985,28);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(6385,24);
manlo <= conv_std_logic_vector(57649551,28);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(6401,24);
manlo <= conv_std_logic_vector(59286215,28);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6417,24);
manlo <= conv_std_logic_vector(60926976,28);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(6433,24);
manlo <= conv_std_logic_vector(62571835,28);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(6449,24);
manlo <= conv_std_logic_vector(64220791,28);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(6465,24);
manlo <= conv_std_logic_vector(65873845,28);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(6481,24);
manlo <= conv_std_logic_vector(67530997,28);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(6497,24);
manlo <= conv_std_logic_vector(69192246,28);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(6513,24);
manlo <= conv_std_logic_vector(70857593,28);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(6529,24);
manlo <= conv_std_logic_vector(72527037,28);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(6545,24);
manlo <= conv_std_logic_vector(74200579,28);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6561,24);
manlo <= conv_std_logic_vector(75878219,28);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(6577,24);
manlo <= conv_std_logic_vector(77559956,28);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(6593,24);
manlo <= conv_std_logic_vector(79245791,28);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(6609,24);
manlo <= conv_std_logic_vector(80935723,28);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(6625,24);
manlo <= conv_std_logic_vector(82629753,28);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(6641,24);
manlo <= conv_std_logic_vector(84327881,28);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(6657,24);
manlo <= conv_std_logic_vector(86030106,28);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(6673,24);
manlo <= conv_std_logic_vector(87736429,28);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(6689,24);
manlo <= conv_std_logic_vector(89446849,28);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(6705,24);
manlo <= conv_std_logic_vector(91161367,28);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(6721,24);
manlo <= conv_std_logic_vector(92879983,28);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(6737,24);
manlo <= conv_std_logic_vector(94602697,28);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(6753,24);
manlo <= conv_std_logic_vector(96329508,28);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(6769,24);
manlo <= conv_std_logic_vector(98060416,28);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(6785,24);
manlo <= conv_std_logic_vector(99795423,28);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(6801,24);
manlo <= conv_std_logic_vector(101534527,28);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(6817,24);
manlo <= conv_std_logic_vector(103277728,28);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(6833,24);
manlo <= conv_std_logic_vector(105025028,28);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(6849,24);
manlo <= conv_std_logic_vector(106776425,28);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(6865,24);
manlo <= conv_std_logic_vector(108531919,28);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(6881,24);
manlo <= conv_std_logic_vector(110291512,28);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(6897,24);
manlo <= conv_std_logic_vector(112055202,28);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(6913,24);
manlo <= conv_std_logic_vector(113822989,28);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(6929,24);
manlo <= conv_std_logic_vector(115594875,28);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(6945,24);
manlo <= conv_std_logic_vector(117370858,28);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(6961,24);
manlo <= conv_std_logic_vector(119150939,28);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(6977,24);
manlo <= conv_std_logic_vector(120935117,28);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(6993,24);
manlo <= conv_std_logic_vector(122723393,28);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(7009,24);
manlo <= conv_std_logic_vector(124515767,28);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(7025,24);
manlo <= conv_std_logic_vector(126312239,28);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(7041,24);
manlo <= conv_std_logic_vector(128112808,28);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(7057,24);
manlo <= conv_std_logic_vector(129917475,28);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(7073,24);
manlo <= conv_std_logic_vector(131726240,28);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(7089,24);
manlo <= conv_std_logic_vector(133539102,28);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(7105,24);
manlo <= conv_std_logic_vector(135356063,28);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(7121,24);
manlo <= conv_std_logic_vector(137177121,28);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7137,24);
manlo <= conv_std_logic_vector(139002276,28);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(7153,24);
manlo <= conv_std_logic_vector(140831530,28);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(7169,24);
manlo <= conv_std_logic_vector(142664881,28);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(7185,24);
manlo <= conv_std_logic_vector(144502330,28);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(7201,24);
manlo <= conv_std_logic_vector(146343877,28);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(7217,24);
manlo <= conv_std_logic_vector(148189521,28);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(7233,24);
manlo <= conv_std_logic_vector(150039263,28);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(7249,24);
manlo <= conv_std_logic_vector(151893103,28);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(7265,24);
manlo <= conv_std_logic_vector(153751041,28);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(7281,24);
manlo <= conv_std_logic_vector(155613076,28);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(7297,24);
manlo <= conv_std_logic_vector(157479210,28);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(7313,24);
manlo <= conv_std_logic_vector(159349441,28);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(7329,24);
manlo <= conv_std_logic_vector(161223770,28);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(7345,24);
manlo <= conv_std_logic_vector(163102196,28);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(7361,24);
manlo <= conv_std_logic_vector(164984721,28);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(7377,24);
manlo <= conv_std_logic_vector(166871343,28);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(7393,24);
manlo <= conv_std_logic_vector(168762063,28);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(7409,24);
manlo <= conv_std_logic_vector(170656881,28);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(7425,24);
manlo <= conv_std_logic_vector(172555797,28);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(7441,24);
manlo <= conv_std_logic_vector(174458810,28);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(7457,24);
manlo <= conv_std_logic_vector(176365921,28);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(7473,24);
manlo <= conv_std_logic_vector(178277130,28);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(7489,24);
manlo <= conv_std_logic_vector(180192437,28);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(7505,24);
manlo <= conv_std_logic_vector(182111842,28);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(7521,24);
manlo <= conv_std_logic_vector(184035345,28);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(7537,24);
manlo <= conv_std_logic_vector(185962945,28);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(7553,24);
manlo <= conv_std_logic_vector(187894643,28);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(7569,24);
manlo <= conv_std_logic_vector(189830439,28);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(7585,24);
manlo <= conv_std_logic_vector(191770333,28);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(7601,24);
manlo <= conv_std_logic_vector(193714325,28);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(7617,24);
manlo <= conv_std_logic_vector(195662415,28);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(7633,24);
manlo <= conv_std_logic_vector(197614602,28);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(7649,24);
manlo <= conv_std_logic_vector(199570888,28);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(7665,24);
manlo <= conv_std_logic_vector(201531271,28);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7681,24);
manlo <= conv_std_logic_vector(203495752,28);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(7697,24);
manlo <= conv_std_logic_vector(205464331,28);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(7713,24);
manlo <= conv_std_logic_vector(207437008,28);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(7729,24);
manlo <= conv_std_logic_vector(209413783,28);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(7745,24);
manlo <= conv_std_logic_vector(211394656,28);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(7761,24);
manlo <= conv_std_logic_vector(213379626,28);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(7777,24);
manlo <= conv_std_logic_vector(215368695,28);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(7793,24);
manlo <= conv_std_logic_vector(217361861,28);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(7809,24);
manlo <= conv_std_logic_vector(219359125,28);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7825,24);
manlo <= conv_std_logic_vector(221360487,28);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(7841,24);
manlo <= conv_std_logic_vector(223365947,28);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(7857,24);
manlo <= conv_std_logic_vector(225375505,28);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(7873,24);
manlo <= conv_std_logic_vector(227389161,28);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(7889,24);
manlo <= conv_std_logic_vector(229406915,28);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(7905,24);
manlo <= conv_std_logic_vector(231428767,28);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(7921,24);
manlo <= conv_std_logic_vector(233454716,28);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(7937,24);
manlo <= conv_std_logic_vector(235484764,28);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(7953,24);
manlo <= conv_std_logic_vector(237518910,28);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7969,24);
manlo <= conv_std_logic_vector(239557153,28);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(7985,24);
manlo <= conv_std_logic_vector(241599495,28);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(8001,24);
manlo <= conv_std_logic_vector(243645934,28);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(8017,24);
manlo <= conv_std_logic_vector(245696471,28);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(8033,24);
manlo <= conv_std_logic_vector(247751107,28);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(8049,24);
manlo <= conv_std_logic_vector(249809840,28);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(8065,24);
manlo <= conv_std_logic_vector(251872671,28);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(8081,24);
manlo <= conv_std_logic_vector(253939600,28);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(8097,24);
manlo <= conv_std_logic_vector(256010627,28);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(8113,24);
manlo <= conv_std_logic_vector(258085753,28);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(8129,24);
manlo <= conv_std_logic_vector(260164976,28);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(8145,24);
manlo <= conv_std_logic_vector(262248297,28);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(8161,24);
manlo <= conv_std_logic_vector(264335716,28);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(8177,24);
manlo <= conv_std_logic_vector(266427233,28);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(8194,24);
manlo <= conv_std_logic_vector(87392,28);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(8210,24);
manlo <= conv_std_logic_vector(2187105,28);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(8226,24);
manlo <= conv_std_logic_vector(4290916,28);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(8242,24);
manlo <= conv_std_logic_vector(6398825,28);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8258,24);
manlo <= conv_std_logic_vector(8510832,28);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(8274,24);
manlo <= conv_std_logic_vector(10626938,28);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(8290,24);
manlo <= conv_std_logic_vector(12747141,28);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(8306,24);
manlo <= conv_std_logic_vector(14871442,28);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(8322,24);
manlo <= conv_std_logic_vector(16999841,28);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(8338,24);
manlo <= conv_std_logic_vector(19132338,28);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(8354,24);
manlo <= conv_std_logic_vector(21268934,28);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(8370,24);
manlo <= conv_std_logic_vector(23409627,28);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(8386,24);
manlo <= conv_std_logic_vector(25554418,28);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8402,24);
manlo <= conv_std_logic_vector(27703308,28);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(8418,24);
manlo <= conv_std_logic_vector(29856295,28);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(8434,24);
manlo <= conv_std_logic_vector(32013381,28);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(8450,24);
manlo <= conv_std_logic_vector(34174564,28);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(8466,24);
manlo <= conv_std_logic_vector(36339846,28);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(8482,24);
manlo <= conv_std_logic_vector(38509225,28);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(8498,24);
manlo <= conv_std_logic_vector(40682703,28);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(8514,24);
manlo <= conv_std_logic_vector(42860279,28);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(8530,24);
manlo <= conv_std_logic_vector(45041953,28);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8546,24);
manlo <= conv_std_logic_vector(47227725,28);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(8562,24);
manlo <= conv_std_logic_vector(49417595,28);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(8578,24);
manlo <= conv_std_logic_vector(51611563,28);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(8594,24);
manlo <= conv_std_logic_vector(53809629,28);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(8610,24);
manlo <= conv_std_logic_vector(56011794,28);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(8626,24);
manlo <= conv_std_logic_vector(58218056,28);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(8642,24);
manlo <= conv_std_logic_vector(60428417,28);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(8658,24);
manlo <= conv_std_logic_vector(62642876,28);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(8674,24);
manlo <= conv_std_logic_vector(64861432,28);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8690,24);
manlo <= conv_std_logic_vector(67084087,28);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(8706,24);
manlo <= conv_std_logic_vector(69310840,28);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(8722,24);
manlo <= conv_std_logic_vector(71541691,28);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(8738,24);
manlo <= conv_std_logic_vector(73776641,28);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(8754,24);
manlo <= conv_std_logic_vector(76015688,28);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(8770,24);
manlo <= conv_std_logic_vector(78258834,28);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(8786,24);
manlo <= conv_std_logic_vector(80506077,28);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(8802,24);
manlo <= conv_std_logic_vector(82757419,28);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(8818,24);
manlo <= conv_std_logic_vector(85012859,28);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(8834,24);
manlo <= conv_std_logic_vector(87272397,28);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(8850,24);
manlo <= conv_std_logic_vector(89536034,28);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(8866,24);
manlo <= conv_std_logic_vector(91803768,28);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(8882,24);
manlo <= conv_std_logic_vector(94075601,28);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(8898,24);
manlo <= conv_std_logic_vector(96351532,28);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(8914,24);
manlo <= conv_std_logic_vector(98631561,28);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(8930,24);
manlo <= conv_std_logic_vector(100915688,28);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(8946,24);
manlo <= conv_std_logic_vector(103203913,28);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(8962,24);
manlo <= conv_std_logic_vector(105496237,28);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(8978,24);
manlo <= conv_std_logic_vector(107792658,28);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(8994,24);
manlo <= conv_std_logic_vector(110093178,28);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(9010,24);
manlo <= conv_std_logic_vector(112397796,28);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(9026,24);
manlo <= conv_std_logic_vector(114706513,28);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(9042,24);
manlo <= conv_std_logic_vector(117019327,28);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(9058,24);
manlo <= conv_std_logic_vector(119336240,28);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(9074,24);
manlo <= conv_std_logic_vector(121657251,28);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(9090,24);
manlo <= conv_std_logic_vector(123982360,28);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(9106,24);
manlo <= conv_std_logic_vector(126311567,28);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9122,24);
manlo <= conv_std_logic_vector(128644873,28);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(9138,24);
manlo <= conv_std_logic_vector(130982277,28);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(9154,24);
manlo <= conv_std_logic_vector(133323779,28);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(9170,24);
manlo <= conv_std_logic_vector(135669379,28);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(9186,24);
manlo <= conv_std_logic_vector(138019077,28);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(9202,24);
manlo <= conv_std_logic_vector(140372874,28);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(9218,24);
manlo <= conv_std_logic_vector(142730769,28);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(9234,24);
manlo <= conv_std_logic_vector(145092762,28);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(9250,24);
manlo <= conv_std_logic_vector(147458854,28);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(9266,24);
manlo <= conv_std_logic_vector(149829044,28);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(9282,24);
manlo <= conv_std_logic_vector(152203332,28);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(9298,24);
manlo <= conv_std_logic_vector(154581718,28);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(9314,24);
manlo <= conv_std_logic_vector(156964202,28);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(9330,24);
manlo <= conv_std_logic_vector(159350785,28);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(9346,24);
manlo <= conv_std_logic_vector(161741466,28);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(9362,24);
manlo <= conv_std_logic_vector(164136246,28);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(9378,24);
manlo <= conv_std_logic_vector(166535123,28);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(9394,24);
manlo <= conv_std_logic_vector(168938099,28);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(9410,24);
manlo <= conv_std_logic_vector(171345174,28);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(9426,24);
manlo <= conv_std_logic_vector(173756346,28);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(9442,24);
manlo <= conv_std_logic_vector(176171617,28);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(9458,24);
manlo <= conv_std_logic_vector(178590986,28);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(9474,24);
manlo <= conv_std_logic_vector(181014454,28);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(9490,24);
manlo <= conv_std_logic_vector(183442020,28);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(9506,24);
manlo <= conv_std_logic_vector(185873684,28);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(9522,24);
manlo <= conv_std_logic_vector(188309446,28);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(9538,24);
manlo <= conv_std_logic_vector(190749307,28);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(9554,24);
manlo <= conv_std_logic_vector(193193266,28);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(9570,24);
manlo <= conv_std_logic_vector(195641323,28);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(9586,24);
manlo <= conv_std_logic_vector(198093479,28);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(9602,24);
manlo <= conv_std_logic_vector(200549733,28);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(9618,24);
manlo <= conv_std_logic_vector(203010086,28);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(9634,24);
manlo <= conv_std_logic_vector(205474536,28);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(9650,24);
manlo <= conv_std_logic_vector(207943085,28);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(9666,24);
manlo <= conv_std_logic_vector(210415733,28);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(9682,24);
manlo <= conv_std_logic_vector(212892479,28);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(9698,24);
manlo <= conv_std_logic_vector(215373323,28);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(9714,24);
manlo <= conv_std_logic_vector(217858266,28);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(9730,24);
manlo <= conv_std_logic_vector(220347307,28);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(9746,24);
manlo <= conv_std_logic_vector(222840446,28);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(9762,24);
manlo <= conv_std_logic_vector(225337684,28);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(9778,24);
manlo <= conv_std_logic_vector(227839020,28);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(9794,24);
manlo <= conv_std_logic_vector(230344454,28);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9810,24);
manlo <= conv_std_logic_vector(232853987,28);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(9826,24);
manlo <= conv_std_logic_vector(235367618,28);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(9842,24);
manlo <= conv_std_logic_vector(237885348,28);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(9858,24);
manlo <= conv_std_logic_vector(240407176,28);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(9874,24);
manlo <= conv_std_logic_vector(242933102,28);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(9890,24);
manlo <= conv_std_logic_vector(245463127,28);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(9906,24);
manlo <= conv_std_logic_vector(247997251,28);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(9922,24);
manlo <= conv_std_logic_vector(250535472,28);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(9938,24);
manlo <= conv_std_logic_vector(253077793,28);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9954,24);
manlo <= conv_std_logic_vector(255624211,28);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(9970,24);
manlo <= conv_std_logic_vector(258174728,28);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(9986,24);
manlo <= conv_std_logic_vector(260729344,28);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(10002,24);
manlo <= conv_std_logic_vector(263288057,28);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(10018,24);
manlo <= conv_std_logic_vector(265850870,28);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(10034,24);
manlo <= conv_std_logic_vector(268417780,28);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(10051,24);
manlo <= conv_std_logic_vector(2553334,28);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(10067,24);
manlo <= conv_std_logic_vector(5128441,28);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(10083,24);
manlo <= conv_std_logic_vector(7707647,28);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(10099,24);
manlo <= conv_std_logic_vector(10290952,28);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(10115,24);
manlo <= conv_std_logic_vector(12878355,28);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(10131,24);
manlo <= conv_std_logic_vector(15469857,28);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(10147,24);
manlo <= conv_std_logic_vector(18065457,28);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(10163,24);
manlo <= conv_std_logic_vector(20665155,28);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(10179,24);
manlo <= conv_std_logic_vector(23268952,28);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(10195,24);
manlo <= conv_std_logic_vector(25876847,28);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(10211,24);
manlo <= conv_std_logic_vector(28488841,28);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(10227,24);
manlo <= conv_std_logic_vector(31104934,28);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10243,24);
manlo <= conv_std_logic_vector(33725125,28);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(10259,24);
manlo <= conv_std_logic_vector(36349414,28);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(10275,24);
manlo <= conv_std_logic_vector(38977802,28);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(10291,24);
manlo <= conv_std_logic_vector(41610288,28);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(10307,24);
manlo <= conv_std_logic_vector(44246873,28);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(10323,24);
manlo <= conv_std_logic_vector(46887557,28);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(10339,24);
manlo <= conv_std_logic_vector(49532339,28);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(10355,24);
manlo <= conv_std_logic_vector(52181219,28);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(10371,24);
manlo <= conv_std_logic_vector(54834198,28);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10387,24);
manlo <= conv_std_logic_vector(57491276,28);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(10403,24);
manlo <= conv_std_logic_vector(60152452,28);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(10419,24);
manlo <= conv_std_logic_vector(62817727,28);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(10435,24);
manlo <= conv_std_logic_vector(65487100,28);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(10451,24);
manlo <= conv_std_logic_vector(68160572,28);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(10467,24);
manlo <= conv_std_logic_vector(70838142,28);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(10483,24);
manlo <= conv_std_logic_vector(73519811,28);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(10499,24);
manlo <= conv_std_logic_vector(76205578,28);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(10515,24);
manlo <= conv_std_logic_vector(78895444,28);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10531,24);
manlo <= conv_std_logic_vector(81589409,28);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(10547,24);
manlo <= conv_std_logic_vector(84287472,28);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(10563,24);
manlo <= conv_std_logic_vector(86989633,28);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(10579,24);
manlo <= conv_std_logic_vector(89695894,28);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(10595,24);
manlo <= conv_std_logic_vector(92406252,28);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(10611,24);
manlo <= conv_std_logic_vector(95120710,28);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(10627,24);
manlo <= conv_std_logic_vector(97839266,28);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(10643,24);
manlo <= conv_std_logic_vector(100561920,28);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(10659,24);
manlo <= conv_std_logic_vector(103288674,28);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10675,24);
manlo <= conv_std_logic_vector(106019525,28);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(10691,24);
manlo <= conv_std_logic_vector(108754476,28);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(10707,24);
manlo <= conv_std_logic_vector(111493525,28);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(10723,24);
manlo <= conv_std_logic_vector(114236673,28);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(10739,24);
manlo <= conv_std_logic_vector(116983919,28);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(10755,24);
manlo <= conv_std_logic_vector(119735264,28);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(10771,24);
manlo <= conv_std_logic_vector(122490707,28);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(10787,24);
manlo <= conv_std_logic_vector(125250249,28);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(10803,24);
manlo <= conv_std_logic_vector(128013890,28);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(10819,24);
manlo <= conv_std_logic_vector(130781629,28);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(10835,24);
manlo <= conv_std_logic_vector(133553468,28);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(10851,24);
manlo <= conv_std_logic_vector(136329404,28);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(10867,24);
manlo <= conv_std_logic_vector(139109440,28);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(10883,24);
manlo <= conv_std_logic_vector(141893574,28);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(10899,24);
manlo <= conv_std_logic_vector(144681806,28);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(10915,24);
manlo <= conv_std_logic_vector(147474137,28);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(10931,24);
manlo <= conv_std_logic_vector(150270567,28);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(10947,24);
manlo <= conv_std_logic_vector(153071096,28);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(10963,24);
manlo <= conv_std_logic_vector(155875723,28);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(10979,24);
manlo <= conv_std_logic_vector(158684449,28);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(10995,24);
manlo <= conv_std_logic_vector(161497274,28);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(11011,24);
manlo <= conv_std_logic_vector(164314197,28);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(11027,24);
manlo <= conv_std_logic_vector(167135219,28);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(11043,24);
manlo <= conv_std_logic_vector(169960340,28);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(11059,24);
manlo <= conv_std_logic_vector(172789560,28);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(11075,24);
manlo <= conv_std_logic_vector(175622878,28);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(11091,24);
manlo <= conv_std_logic_vector(178460295,28);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11107,24);
manlo <= conv_std_logic_vector(181301810,28);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(11123,24);
manlo <= conv_std_logic_vector(184147424,28);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(11139,24);
manlo <= conv_std_logic_vector(186997137,28);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(11155,24);
manlo <= conv_std_logic_vector(189850949,28);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(11171,24);
manlo <= conv_std_logic_vector(192708860,28);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(11187,24);
manlo <= conv_std_logic_vector(195570869,28);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(11203,24);
manlo <= conv_std_logic_vector(198436977,28);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(11219,24);
manlo <= conv_std_logic_vector(201307183,28);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(11235,24);
manlo <= conv_std_logic_vector(204181489,28);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(11251,24);
manlo <= conv_std_logic_vector(207059893,28);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(11267,24);
manlo <= conv_std_logic_vector(209942395,28);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(11283,24);
manlo <= conv_std_logic_vector(212828997,28);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(11299,24);
manlo <= conv_std_logic_vector(215719697,28);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(11315,24);
manlo <= conv_std_logic_vector(218614497,28);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(11331,24);
manlo <= conv_std_logic_vector(221513394,28);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(11347,24);
manlo <= conv_std_logic_vector(224416391,28);
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(11363,24);
manlo <= conv_std_logic_vector(227323486,28);
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(11379,24);
manlo <= conv_std_logic_vector(230234681,28);
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(11395,24);
manlo <= conv_std_logic_vector(233149974,28);
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(11411,24);
manlo <= conv_std_logic_vector(236069365,28);
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(11427,24);
manlo <= conv_std_logic_vector(238992856,28);
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(11443,24);
manlo <= conv_std_logic_vector(241920445,28);
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(11459,24);
manlo <= conv_std_logic_vector(244852133,28);
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(11475,24);
manlo <= conv_std_logic_vector(247787920,28);
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(11491,24);
manlo <= conv_std_logic_vector(250727806,28);
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(11507,24);
manlo <= conv_std_logic_vector(253671790,28);
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(11523,24);
manlo <= conv_std_logic_vector(256619874,28);
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(11539,24);
manlo <= conv_std_logic_vector(259572056,28);
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(11555,24);
manlo <= conv_std_logic_vector(262528337,28);
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(11571,24);
manlo <= conv_std_logic_vector(265488717,28);
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(11588,24);
manlo <= conv_std_logic_vector(17739,28);
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(11604,24);
manlo <= conv_std_logic_vector(2986317,28);
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(11620,24);
manlo <= conv_std_logic_vector(5958993,28);
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(11636,24);
manlo <= conv_std_logic_vector(8935768,28);
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(11652,24);
manlo <= conv_std_logic_vector(11916642,28);
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(11668,24);
manlo <= conv_std_logic_vector(14901615,28);
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(11684,24);
manlo <= conv_std_logic_vector(17890686,28);
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(11700,24);
manlo <= conv_std_logic_vector(20883857,28);
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(11716,24);
manlo <= conv_std_logic_vector(23881126,28);
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(11732,24);
manlo <= conv_std_logic_vector(26882494,28);
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(11748,24);
manlo <= conv_std_logic_vector(29887961,28);
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(11764,24);
manlo <= conv_std_logic_vector(32897527,28);
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(11780,24);
manlo <= conv_std_logic_vector(35911192,28);
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(11796,24);
manlo <= conv_std_logic_vector(38928956,28);
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(11812,24);
manlo <= conv_std_logic_vector(41950818,28);
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(11828,24);
manlo <= conv_std_logic_vector(44976780,28);
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(11844,24);
manlo <= conv_std_logic_vector(48006840,28);
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(11860,24);
manlo <= conv_std_logic_vector(51040999,28);
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(11876,24);
manlo <= conv_std_logic_vector(54079258,28);
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(11892,24);
manlo <= conv_std_logic_vector(57121615,28);
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(11908,24);
manlo <= conv_std_logic_vector(60168071,28);
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(11924,24);
manlo <= conv_std_logic_vector(63218625,28);
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(11940,24);
manlo <= conv_std_logic_vector(66273279,28);
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(11956,24);
manlo <= conv_std_logic_vector(69332032,28);
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(11972,24);
manlo <= conv_std_logic_vector(72394883,28);
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(11988,24);
manlo <= conv_std_logic_vector(75461834,28);
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(12004,24);
manlo <= conv_std_logic_vector(78532883,28);
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(12020,24);
manlo <= conv_std_logic_vector(81608032,28);
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(12036,24);
manlo <= conv_std_logic_vector(84687279,28);
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(12052,24);
manlo <= conv_std_logic_vector(87770625,28);
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(12068,24);
manlo <= conv_std_logic_vector(90858070,28);
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(12084,24);
manlo <= conv_std_logic_vector(93949615,28);
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(12100,24);
manlo <= conv_std_logic_vector(97045258,28);
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(12116,24);
manlo <= conv_std_logic_vector(100145000,28);
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(12132,24);
manlo <= conv_std_logic_vector(103248841,28);
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(12148,24);
manlo <= conv_std_logic_vector(106356781,28);
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(12164,24);
manlo <= conv_std_logic_vector(109468819,28);
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(12180,24);
manlo <= conv_std_logic_vector(112584957,28);
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(12196,24);
manlo <= conv_std_logic_vector(115705194,28);
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(12212,24);
manlo <= conv_std_logic_vector(118829530,28);
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(12228,24);
manlo <= conv_std_logic_vector(121957965,28);
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(12244,24);
manlo <= conv_std_logic_vector(125090499,28);
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(12260,24);
manlo <= conv_std_logic_vector(128227131,28);
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(12276,24);
manlo <= conv_std_logic_vector(131367863,28);
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(12292,24);
manlo <= conv_std_logic_vector(134512694,28);
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(12308,24);
manlo <= conv_std_logic_vector(137661624,28);
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(12324,24);
manlo <= conv_std_logic_vector(140814653,28);
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(12340,24);
manlo <= conv_std_logic_vector(143971780,28);
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(12356,24);
manlo <= conv_std_logic_vector(147133007,28);
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(12372,24);
manlo <= conv_std_logic_vector(150298333,28);
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(12388,24);
manlo <= conv_std_logic_vector(153467758,28);
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(12404,24);
manlo <= conv_std_logic_vector(156641282,28);
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(12420,24);
manlo <= conv_std_logic_vector(159818905,28);
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(12436,24);
manlo <= conv_std_logic_vector(163000627,28);
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(12452,24);
manlo <= conv_std_logic_vector(166186448,28);
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(12468,24);
manlo <= conv_std_logic_vector(169376368,28);
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(12484,24);
manlo <= conv_std_logic_vector(172570387,28);
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(12500,24);
manlo <= conv_std_logic_vector(175768505,28);
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(12516,24);
manlo <= conv_std_logic_vector(178970722,28);
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(12532,24);
manlo <= conv_std_logic_vector(182177038,28);
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(12548,24);
manlo <= conv_std_logic_vector(185387453,28);
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(12564,24);
manlo <= conv_std_logic_vector(188601968,28);
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(12580,24);
manlo <= conv_std_logic_vector(191820581,28);
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(12596,24);
manlo <= conv_std_logic_vector(195043294,28);
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(12612,24);
manlo <= conv_std_logic_vector(198270105,28);
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(12628,24);
manlo <= conv_std_logic_vector(201501016,28);
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(12644,24);
manlo <= conv_std_logic_vector(204736025,28);
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(12660,24);
manlo <= conv_std_logic_vector(207975134,28);
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(12676,24);
manlo <= conv_std_logic_vector(211218342,28);
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(12692,24);
manlo <= conv_std_logic_vector(214465649,28);
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(12708,24);
manlo <= conv_std_logic_vector(217717055,28);
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(12724,24);
manlo <= conv_std_logic_vector(220972560,28);
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(12740,24);
manlo <= conv_std_logic_vector(224232165,28);
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(12756,24);
manlo <= conv_std_logic_vector(227495868,28);
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(12772,24);
manlo <= conv_std_logic_vector(230763671,28);
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(12788,24);
manlo <= conv_std_logic_vector(234035572,28);
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(12804,24);
manlo <= conv_std_logic_vector(237311573,28);
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(12820,24);
manlo <= conv_std_logic_vector(240591673,28);
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(12836,24);
manlo <= conv_std_logic_vector(243875872,28);
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(12852,24);
manlo <= conv_std_logic_vector(247164170,28);
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(12868,24);
manlo <= conv_std_logic_vector(250456567,28);
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(12884,24);
manlo <= conv_std_logic_vector(253753064,28);
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(12900,24);
manlo <= conv_std_logic_vector(257053659,28);
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(12916,24);
manlo <= conv_std_logic_vector(260358354,28);
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(12932,24);
manlo <= conv_std_logic_vector(263667148,28);
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(12948,24);
manlo <= conv_std_logic_vector(266980041,28);
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(12965,24);
manlo <= conv_std_logic_vector(1861577,28);
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(12981,24);
manlo <= conv_std_logic_vector(5182668,28);
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(12997,24);
manlo <= conv_std_logic_vector(8507859,28);
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(13013,24);
manlo <= conv_std_logic_vector(11837149,28);
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(13029,24);
manlo <= conv_std_logic_vector(15170538,28);
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(13045,24);
manlo <= conv_std_logic_vector(18508026,28);
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(13061,24);
manlo <= conv_std_logic_vector(21849613,28);
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(13077,24);
manlo <= conv_std_logic_vector(25195299,28);
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(13093,24);
manlo <= conv_std_logic_vector(28545085,28);
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(13109,24);
manlo <= conv_std_logic_vector(31898970,28);
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(13125,24);
manlo <= conv_std_logic_vector(35256954,28);
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(13141,24);
manlo <= conv_std_logic_vector(38619037,28);
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(13157,24);
manlo <= conv_std_logic_vector(41985219,28);
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(13173,24);
manlo <= conv_std_logic_vector(45355501,28);
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(13189,24);
manlo <= conv_std_logic_vector(48729882,28);
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(13205,24);
manlo <= conv_std_logic_vector(52108362,28);
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(13221,24);
manlo <= conv_std_logic_vector(55490941,28);
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(13237,24);
manlo <= conv_std_logic_vector(58877620,28);
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(13253,24);
manlo <= conv_std_logic_vector(62268398,28);
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(13269,24);
manlo <= conv_std_logic_vector(65663275,28);
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(13285,24);
manlo <= conv_std_logic_vector(69062251,28);
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(13301,24);
manlo <= conv_std_logic_vector(72465326,28);
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(13317,24);
manlo <= conv_std_logic_vector(75872501,28);
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(13333,24);
manlo <= conv_std_logic_vector(79283775,28);
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(13349,24);
manlo <= conv_std_logic_vector(82699148,28);
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(13365,24);
manlo <= conv_std_logic_vector(86118621,28);
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(13381,24);
manlo <= conv_std_logic_vector(89542193,28);
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(13397,24);
manlo <= conv_std_logic_vector(92969864,28);
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(13413,24);
manlo <= conv_std_logic_vector(96401634,28);
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(13429,24);
manlo <= conv_std_logic_vector(99837503,28);
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(13445,24);
manlo <= conv_std_logic_vector(103277472,28);
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(13461,24);
manlo <= conv_std_logic_vector(106721540,28);
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(13477,24);
manlo <= conv_std_logic_vector(110169708,28);
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(13493,24);
manlo <= conv_std_logic_vector(113621975,28);
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(13509,24);
manlo <= conv_std_logic_vector(117078341,28);
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(13525,24);
manlo <= conv_std_logic_vector(120538806,28);
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(13541,24);
manlo <= conv_std_logic_vector(124003370,28);
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(13557,24);
manlo <= conv_std_logic_vector(127472034,28);
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(13573,24);
manlo <= conv_std_logic_vector(130944798,28);
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(13589,24);
manlo <= conv_std_logic_vector(134421660,28);
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(13605,24);
manlo <= conv_std_logic_vector(137902622,28);
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(13621,24);
manlo <= conv_std_logic_vector(141387683,28);
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(13637,24);
manlo <= conv_std_logic_vector(144876844,28);
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(13653,24);
manlo <= conv_std_logic_vector(148370104,28);
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(13669,24);
manlo <= conv_std_logic_vector(151867463,28);
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(13685,24);
manlo <= conv_std_logic_vector(155368921,28);
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(13701,24);
manlo <= conv_std_logic_vector(158874479,28);
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(13717,24);
manlo <= conv_std_logic_vector(162384136,28);
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(13733,24);
manlo <= conv_std_logic_vector(165897893,28);
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(13749,24);
manlo <= conv_std_logic_vector(169415749,28);
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(13765,24);
manlo <= conv_std_logic_vector(172937704,28);
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(13781,24);
manlo <= conv_std_logic_vector(176463758,28);
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(13797,24);
manlo <= conv_std_logic_vector(179993912,28);
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(13813,24);
manlo <= conv_std_logic_vector(183528166,28);
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(13829,24);
manlo <= conv_std_logic_vector(187066519,28);
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(13845,24);
manlo <= conv_std_logic_vector(190608971,28);
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(13861,24);
manlo <= conv_std_logic_vector(194155522,28);
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(13877,24);
manlo <= conv_std_logic_vector(197706173,28);
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(13893,24);
manlo <= conv_std_logic_vector(201260923,28);
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(13909,24);
manlo <= conv_std_logic_vector(204819773,28);
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(13925,24);
manlo <= conv_std_logic_vector(208382722,28);
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(13941,24);
manlo <= conv_std_logic_vector(211949770,28);
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(13957,24);
manlo <= conv_std_logic_vector(215520918,28);
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(13973,24);
manlo <= conv_std_logic_vector(219096165,28);
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(13989,24);
manlo <= conv_std_logic_vector(222675512,28);
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(14005,24);
manlo <= conv_std_logic_vector(226258958,28);
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(14021,24);
manlo <= conv_std_logic_vector(229846504,28);
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(14037,24);
manlo <= conv_std_logic_vector(233438148,28);
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(14053,24);
manlo <= conv_std_logic_vector(237033893,28);
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(14069,24);
manlo <= conv_std_logic_vector(240633737,28);
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(14085,24);
manlo <= conv_std_logic_vector(244237680,28);
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(14101,24);
manlo <= conv_std_logic_vector(247845722,28);
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(14117,24);
manlo <= conv_std_logic_vector(251457864,28);
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(14133,24);
manlo <= conv_std_logic_vector(255074106,28);
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(14149,24);
manlo <= conv_std_logic_vector(258694447,28);
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(14165,24);
manlo <= conv_std_logic_vector(262318887,28);
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(14181,24);
manlo <= conv_std_logic_vector(265947427,28);
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(14198,24);
manlo <= conv_std_logic_vector(1144611,28);
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(14214,24);
manlo <= conv_std_logic_vector(4781350,28);
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(14230,24);
manlo <= conv_std_logic_vector(8422188,28);
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(14246,24);
manlo <= conv_std_logic_vector(12067126,28);
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(14262,24);
manlo <= conv_std_logic_vector(15716163,28);
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(14278,24);
manlo <= conv_std_logic_vector(19369300,28);
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(14294,24);
manlo <= conv_std_logic_vector(23026536,28);
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(14310,24);
manlo <= conv_std_logic_vector(26687871,28);
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(14326,24);
manlo <= conv_std_logic_vector(30353307,28);
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(14342,24);
manlo <= conv_std_logic_vector(34022841,28);
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(14358,24);
manlo <= conv_std_logic_vector(37696476,28);
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(14374,24);
manlo <= conv_std_logic_vector(41374209,28);
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(14390,24);
manlo <= conv_std_logic_vector(45056043,28);
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(14406,24);
manlo <= conv_std_logic_vector(48741975,28);
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(14422,24);
manlo <= conv_std_logic_vector(52432007,28);
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(14438,24);
manlo <= conv_std_logic_vector(56126139,28);
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(14454,24);
manlo <= conv_std_logic_vector(59824371,28);
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(14470,24);
manlo <= conv_std_logic_vector(63526701,28);
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(14486,24);
manlo <= conv_std_logic_vector(67233132,28);
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(14502,24);
manlo <= conv_std_logic_vector(70943662,28);
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(14518,24);
manlo <= conv_std_logic_vector(74658291,28);
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(14534,24);
manlo <= conv_std_logic_vector(78377020,28);
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(14550,24);
manlo <= conv_std_logic_vector(82099849,28);
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(14566,24);
manlo <= conv_std_logic_vector(85826777,28);
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(14582,24);
manlo <= conv_std_logic_vector(89557804,28);
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(14598,24);
manlo <= conv_std_logic_vector(93292931,28);
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(14614,24);
manlo <= conv_std_logic_vector(97032158,28);
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(14630,24);
manlo <= conv_std_logic_vector(100775484,28);
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(14646,24);
manlo <= conv_std_logic_vector(104522910,28);
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(14662,24);
manlo <= conv_std_logic_vector(108274436,28);
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(14678,24);
manlo <= conv_std_logic_vector(112030061,28);
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(14694,24);
manlo <= conv_std_logic_vector(115789786,28);
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(14710,24);
manlo <= conv_std_logic_vector(119553610,28);
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(14726,24);
manlo <= conv_std_logic_vector(123321534,28);
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(14742,24);
manlo <= conv_std_logic_vector(127093557,28);
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(14758,24);
manlo <= conv_std_logic_vector(130869680,28);
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(14774,24);
manlo <= conv_std_logic_vector(134649903,28);
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(14790,24);
manlo <= conv_std_logic_vector(138434225,28);
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(14806,24);
manlo <= conv_std_logic_vector(142222647,28);
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(14822,24);
manlo <= conv_std_logic_vector(146015168,28);
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(14838,24);
manlo <= conv_std_logic_vector(149811789,28);
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(14854,24);
manlo <= conv_std_logic_vector(153612510,28);
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(14870,24);
manlo <= conv_std_logic_vector(157417330,28);
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(14886,24);
manlo <= conv_std_logic_vector(161226250,28);
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(14902,24);
manlo <= conv_std_logic_vector(165039270,28);
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(14918,24);
manlo <= conv_std_logic_vector(168856389,28);
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(14934,24);
manlo <= conv_std_logic_vector(172677608,28);
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(14950,24);
manlo <= conv_std_logic_vector(176502926,28);
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(14966,24);
manlo <= conv_std_logic_vector(180332344,28);
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(14982,24);
manlo <= conv_std_logic_vector(184165862,28);
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(14998,24);
manlo <= conv_std_logic_vector(188003480,28);
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(15014,24);
manlo <= conv_std_logic_vector(191845197,28);
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(15030,24);
manlo <= conv_std_logic_vector(195691014,28);
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(15046,24);
manlo <= conv_std_logic_vector(199540930,28);
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(15062,24);
manlo <= conv_std_logic_vector(203394946,28);
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(15078,24);
manlo <= conv_std_logic_vector(207253062,28);
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(15094,24);
manlo <= conv_std_logic_vector(211115277,28);
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(15110,24);
manlo <= conv_std_logic_vector(214981593,28);
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(15126,24);
manlo <= conv_std_logic_vector(218852007,28);
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(15142,24);
manlo <= conv_std_logic_vector(222726522,28);
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(15158,24);
manlo <= conv_std_logic_vector(226605136,28);
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(15174,24);
manlo <= conv_std_logic_vector(230487850,28);
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(15190,24);
manlo <= conv_std_logic_vector(234374664,28);
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(15206,24);
manlo <= conv_std_logic_vector(238265577,28);
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(15222,24);
manlo <= conv_std_logic_vector(242160590,28);
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(15238,24);
manlo <= conv_std_logic_vector(246059703,28);
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(15254,24);
manlo <= conv_std_logic_vector(249962916,28);
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(15270,24);
manlo <= conv_std_logic_vector(253870228,28);
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(15286,24);
manlo <= conv_std_logic_vector(257781640,28);
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(15302,24);
manlo <= conv_std_logic_vector(261697152,28);
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(15318,24);
manlo <= conv_std_logic_vector(265616763,28);
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(15335,24);
manlo <= conv_std_logic_vector(1105018,28);
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(15351,24);
manlo <= conv_std_logic_vector(5032829,28);
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(15367,24);
manlo <= conv_std_logic_vector(8964740,28);
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(15383,24);
manlo <= conv_std_logic_vector(12900750,28);
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(15399,24);
manlo <= conv_std_logic_vector(16840860,28);
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(15415,24);
manlo <= conv_std_logic_vector(20785070,28);
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(15431,24);
manlo <= conv_std_logic_vector(24733380,28);
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(15447,24);
manlo <= conv_std_logic_vector(28685790,28);
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(15463,24);
manlo <= conv_std_logic_vector(32642299,28);
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(15479,24);
manlo <= conv_std_logic_vector(36602908,28);
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(15495,24);
manlo <= conv_std_logic_vector(40567617,28);
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(15511,24);
manlo <= conv_std_logic_vector(44536425,28);
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(15527,24);
manlo <= conv_std_logic_vector(48509334,28);
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(15543,24);
manlo <= conv_std_logic_vector(52486342,28);
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(15559,24);
manlo <= conv_std_logic_vector(56467450,28);
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(15575,24);
manlo <= conv_std_logic_vector(60452657,28);
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(15591,24);
manlo <= conv_std_logic_vector(64441965,28);
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(15607,24);
manlo <= conv_std_logic_vector(68435372,28);
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(15623,24);
manlo <= conv_std_logic_vector(72432880,28);
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(15639,24);
manlo <= conv_std_logic_vector(76434487,28);
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(15655,24);
manlo <= conv_std_logic_vector(80440193,28);
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(15671,24);
manlo <= conv_std_logic_vector(84450000,28);
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(15687,24);
manlo <= conv_std_logic_vector(88463906,28);
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(15703,24);
manlo <= conv_std_logic_vector(92481913,28);
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(15719,24);
manlo <= conv_std_logic_vector(96504019,28);
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(15735,24);
manlo <= conv_std_logic_vector(100530225,28);
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(15751,24);
manlo <= conv_std_logic_vector(104560531,28);
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(15767,24);
manlo <= conv_std_logic_vector(108594936,28);
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(15783,24);
manlo <= conv_std_logic_vector(112633442,28);
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(15799,24);
manlo <= conv_std_logic_vector(116676047,28);
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(15815,24);
manlo <= conv_std_logic_vector(120722752,28);
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(15831,24);
manlo <= conv_std_logic_vector(124773557,28);
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(15847,24);
manlo <= conv_std_logic_vector(128828462,28);
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(15863,24);
manlo <= conv_std_logic_vector(132887467,28);
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(15879,24);
manlo <= conv_std_logic_vector(136950572,28);
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(15895,24);
manlo <= conv_std_logic_vector(141017776,28);
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(15911,24);
manlo <= conv_std_logic_vector(145089081,28);
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(15927,24);
manlo <= conv_std_logic_vector(149164485,28);
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(15943,24);
manlo <= conv_std_logic_vector(153243989,28);
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(15959,24);
manlo <= conv_std_logic_vector(157327593,28);
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(15975,24);
manlo <= conv_std_logic_vector(161415297,28);
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(15991,24);
manlo <= conv_std_logic_vector(165507101,28);
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(16007,24);
manlo <= conv_std_logic_vector(169603005,28);
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(16023,24);
manlo <= conv_std_logic_vector(173703009,28);
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(16039,24);
manlo <= conv_std_logic_vector(177807112,28);
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(16055,24);
manlo <= conv_std_logic_vector(181915316,28);
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(16071,24);
manlo <= conv_std_logic_vector(186027619,28);
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(16087,24);
manlo <= conv_std_logic_vector(190144023,28);
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(16103,24);
manlo <= conv_std_logic_vector(194264526,28);
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(16119,24);
manlo <= conv_std_logic_vector(198389129,28);
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(16135,24);
manlo <= conv_std_logic_vector(202517832,28);
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(16151,24);
manlo <= conv_std_logic_vector(206650635,28);
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(16167,24);
manlo <= conv_std_logic_vector(210787538,28);
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(16183,24);
manlo <= conv_std_logic_vector(214928541,28);
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(16199,24);
manlo <= conv_std_logic_vector(219073644,28);
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(16215,24);
manlo <= conv_std_logic_vector(223222847,28);
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(16231,24);
manlo <= conv_std_logic_vector(227376150,28);
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(16247,24);
manlo <= conv_std_logic_vector(231533553,28);
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(16263,24);
manlo <= conv_std_logic_vector(235695056,28);
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(16279,24);
manlo <= conv_std_logic_vector(239860659,28);
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(16295,24);
manlo <= conv_std_logic_vector(244030361,28);
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(16311,24);
manlo <= conv_std_logic_vector(248204164,28);
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(16327,24);
manlo <= conv_std_logic_vector(252382067,28);
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(16343,24);
manlo <= conv_std_logic_vector(256564069,28);
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(16359,24);
manlo <= conv_std_logic_vector(260750172,28);
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(16375,24);
manlo <= conv_std_logic_vector(264940375,28);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT20.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut20 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
END dp_explut20;
ARCHITECTURE rtl OF dp_explut20 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16,24);
manlo <= conv_std_logic_vector(2048,28);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32,24);
manlo <= conv_std_logic_vector(8192,28);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(48,24);
manlo <= conv_std_logic_vector(18432,28);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(64,24);
manlo <= conv_std_logic_vector(32768,28);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(80,24);
manlo <= conv_std_logic_vector(51200,28);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(96,24);
manlo <= conv_std_logic_vector(73728,28);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(112,24);
manlo <= conv_std_logic_vector(100352,28);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(128,24);
manlo <= conv_std_logic_vector(131072,28);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(144,24);
manlo <= conv_std_logic_vector(165888,28);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(160,24);
manlo <= conv_std_logic_vector(204801,28);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(176,24);
manlo <= conv_std_logic_vector(247809,28);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(192,24);
manlo <= conv_std_logic_vector(294913,28);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(208,24);
manlo <= conv_std_logic_vector(346113,28);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(224,24);
manlo <= conv_std_logic_vector(401410,28);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(240,24);
manlo <= conv_std_logic_vector(460802,28);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(256,24);
manlo <= conv_std_logic_vector(524291,28);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(272,24);
manlo <= conv_std_logic_vector(591875,28);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(288,24);
manlo <= conv_std_logic_vector(663556,28);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(304,24);
manlo <= conv_std_logic_vector(739332,28);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(320,24);
manlo <= conv_std_logic_vector(819205,28);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(336,24);
manlo <= conv_std_logic_vector(903174,28);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(352,24);
manlo <= conv_std_logic_vector(991239,28);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(368,24);
manlo <= conv_std_logic_vector(1083400,28);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(384,24);
manlo <= conv_std_logic_vector(1179657,28);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(400,24);
manlo <= conv_std_logic_vector(1280010,28);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(416,24);
manlo <= conv_std_logic_vector(1384459,28);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(432,24);
manlo <= conv_std_logic_vector(1493005,28);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(448,24);
manlo <= conv_std_logic_vector(1605646,28);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(464,24);
manlo <= conv_std_logic_vector(1722384,28);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(480,24);
manlo <= conv_std_logic_vector(1843218,28);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(496,24);
manlo <= conv_std_logic_vector(1968147,28);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(512,24);
manlo <= conv_std_logic_vector(2097173,28);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(528,24);
manlo <= conv_std_logic_vector(2230295,28);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(544,24);
manlo <= conv_std_logic_vector(2367514,28);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(560,24);
manlo <= conv_std_logic_vector(2508828,28);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(576,24);
manlo <= conv_std_logic_vector(2654238,28);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(592,24);
manlo <= conv_std_logic_vector(2803745,28);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(608,24);
manlo <= conv_std_logic_vector(2957348,28);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(624,24);
manlo <= conv_std_logic_vector(3115047,28);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(640,24);
manlo <= conv_std_logic_vector(3276842,28);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(656,24);
manlo <= conv_std_logic_vector(3442733,28);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(672,24);
manlo <= conv_std_logic_vector(3612720,28);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(688,24);
manlo <= conv_std_logic_vector(3786804,28);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(704,24);
manlo <= conv_std_logic_vector(3964983,28);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(720,24);
manlo <= conv_std_logic_vector(4147259,28);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(736,24);
manlo <= conv_std_logic_vector(4333631,28);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(752,24);
manlo <= conv_std_logic_vector(4524100,28);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(768,24);
manlo <= conv_std_logic_vector(4718664,28);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(784,24);
manlo <= conv_std_logic_vector(4917325,28);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(800,24);
manlo <= conv_std_logic_vector(5120081,28);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(816,24);
manlo <= conv_std_logic_vector(5326934,28);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(832,24);
manlo <= conv_std_logic_vector(5537884,28);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(848,24);
manlo <= conv_std_logic_vector(5752929,28);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(864,24);
manlo <= conv_std_logic_vector(5972071,28);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(880,24);
manlo <= conv_std_logic_vector(6195308,28);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(896,24);
manlo <= conv_std_logic_vector(6422642,28);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(912,24);
manlo <= conv_std_logic_vector(6654073,28);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(928,24);
manlo <= conv_std_logic_vector(6889599,28);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(944,24);
manlo <= conv_std_logic_vector(7129222,28);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(960,24);
manlo <= conv_std_logic_vector(7372941,28);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(976,24);
manlo <= conv_std_logic_vector(7620756,28);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(992,24);
manlo <= conv_std_logic_vector(7872667,28);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1008,24);
manlo <= conv_std_logic_vector(8128675,28);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1024,24);
manlo <= conv_std_logic_vector(8388779,28);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1040,24);
manlo <= conv_std_logic_vector(8652979,28);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1056,24);
manlo <= conv_std_logic_vector(8921275,28);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1072,24);
manlo <= conv_std_logic_vector(9193668,28);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1088,24);
manlo <= conv_std_logic_vector(9470157,28);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1104,24);
manlo <= conv_std_logic_vector(9750742,28);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1120,24);
manlo <= conv_std_logic_vector(10035423,28);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1136,24);
manlo <= conv_std_logic_vector(10324201,28);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1152,24);
manlo <= conv_std_logic_vector(10617075,28);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1168,24);
manlo <= conv_std_logic_vector(10914045,28);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1184,24);
manlo <= conv_std_logic_vector(11215112,28);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1200,24);
manlo <= conv_std_logic_vector(11520275,28);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1216,24);
manlo <= conv_std_logic_vector(11829534,28);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1232,24);
manlo <= conv_std_logic_vector(12142889,28);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1248,24);
manlo <= conv_std_logic_vector(12460341,28);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1264,24);
manlo <= conv_std_logic_vector(12781889,28);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1280,24);
manlo <= conv_std_logic_vector(13107533,28);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1296,24);
manlo <= conv_std_logic_vector(13437274,28);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1312,24);
manlo <= conv_std_logic_vector(13771111,28);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1328,24);
manlo <= conv_std_logic_vector(14109044,28);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1344,24);
manlo <= conv_std_logic_vector(14451074,28);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1360,24);
manlo <= conv_std_logic_vector(14797200,28);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1376,24);
manlo <= conv_std_logic_vector(15147422,28);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1392,24);
manlo <= conv_std_logic_vector(15501741,28);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1408,24);
manlo <= conv_std_logic_vector(15860156,28);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1424,24);
manlo <= conv_std_logic_vector(16222667,28);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1440,24);
manlo <= conv_std_logic_vector(16589275,28);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1456,24);
manlo <= conv_std_logic_vector(16959979,28);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1472,24);
manlo <= conv_std_logic_vector(17334779,28);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1488,24);
manlo <= conv_std_logic_vector(17713676,28);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1504,24);
manlo <= conv_std_logic_vector(18096669,28);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1520,24);
manlo <= conv_std_logic_vector(18483758,28);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1536,24);
manlo <= conv_std_logic_vector(18874944,28);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1552,24);
manlo <= conv_std_logic_vector(19270226,28);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1568,24);
manlo <= conv_std_logic_vector(19669605,28);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1584,24);
manlo <= conv_std_logic_vector(20073080,28);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1600,24);
manlo <= conv_std_logic_vector(20480651,28);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1616,24);
manlo <= conv_std_logic_vector(20892319,28);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1632,24);
manlo <= conv_std_logic_vector(21308083,28);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1648,24);
manlo <= conv_std_logic_vector(21727943,28);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1664,24);
manlo <= conv_std_logic_vector(22151900,28);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1680,24);
manlo <= conv_std_logic_vector(22579954,28);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1696,24);
manlo <= conv_std_logic_vector(23012103,28);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1712,24);
manlo <= conv_std_logic_vector(23448350,28);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1728,24);
manlo <= conv_std_logic_vector(23888692,28);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1744,24);
manlo <= conv_std_logic_vector(24333131,28);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1760,24);
manlo <= conv_std_logic_vector(24781667,28);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1776,24);
manlo <= conv_std_logic_vector(25234298,28);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1792,24);
manlo <= conv_std_logic_vector(25691027,28);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1808,24);
manlo <= conv_std_logic_vector(26151851,28);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1824,24);
manlo <= conv_std_logic_vector(26616773,28);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1840,24);
manlo <= conv_std_logic_vector(27085790,28);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(1856,24);
manlo <= conv_std_logic_vector(27558904,28);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(1872,24);
manlo <= conv_std_logic_vector(28036115,28);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(1888,24);
manlo <= conv_std_logic_vector(28517422,28);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(1904,24);
manlo <= conv_std_logic_vector(29002825,28);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(1920,24);
manlo <= conv_std_logic_vector(29492325,28);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(1936,24);
manlo <= conv_std_logic_vector(29985921,28);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(1952,24);
manlo <= conv_std_logic_vector(30483614,28);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(1968,24);
manlo <= conv_std_logic_vector(30985404,28);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1984,24);
manlo <= conv_std_logic_vector(31491289,28);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2000,24);
manlo <= conv_std_logic_vector(32001272,28);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2016,24);
manlo <= conv_std_logic_vector(32515350,28);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2032,24);
manlo <= conv_std_logic_vector(33033526,28);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2048,24);
manlo <= conv_std_logic_vector(33555797,28);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2064,24);
manlo <= conv_std_logic_vector(34082166,28);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2080,24);
manlo <= conv_std_logic_vector(34612630,28);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2096,24);
manlo <= conv_std_logic_vector(35147192,28);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2112,24);
manlo <= conv_std_logic_vector(35685849,28);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2128,24);
manlo <= conv_std_logic_vector(36228604,28);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2144,24);
manlo <= conv_std_logic_vector(36775455,28);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2160,24);
manlo <= conv_std_logic_vector(37326402,28);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2176,24);
manlo <= conv_std_logic_vector(37881446,28);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2192,24);
manlo <= conv_std_logic_vector(38440586,28);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2208,24);
manlo <= conv_std_logic_vector(39003823,28);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2224,24);
manlo <= conv_std_logic_vector(39571157,28);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2240,24);
manlo <= conv_std_logic_vector(40142587,28);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2256,24);
manlo <= conv_std_logic_vector(40718113,28);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2272,24);
manlo <= conv_std_logic_vector(41297736,28);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2288,24);
manlo <= conv_std_logic_vector(41881456,28);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2304,24);
manlo <= conv_std_logic_vector(42469272,28);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2320,24);
manlo <= conv_std_logic_vector(43061185,28);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2336,24);
manlo <= conv_std_logic_vector(43657194,28);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2352,24);
manlo <= conv_std_logic_vector(44257300,28);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2368,24);
manlo <= conv_std_logic_vector(44861503,28);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2384,24);
manlo <= conv_std_logic_vector(45469802,28);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2400,24);
manlo <= conv_std_logic_vector(46082197,28);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2416,24);
manlo <= conv_std_logic_vector(46698690,28);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2432,24);
manlo <= conv_std_logic_vector(47319278,28);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2448,24);
manlo <= conv_std_logic_vector(47943964,28);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2464,24);
manlo <= conv_std_logic_vector(48572746,28);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2480,24);
manlo <= conv_std_logic_vector(49205624,28);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2496,24);
manlo <= conv_std_logic_vector(49842600,28);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2512,24);
manlo <= conv_std_logic_vector(50483672,28);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2528,24);
manlo <= conv_std_logic_vector(51128840,28);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2544,24);
manlo <= conv_std_logic_vector(51778105,28);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2560,24);
manlo <= conv_std_logic_vector(52431467,28);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2576,24);
manlo <= conv_std_logic_vector(53088925,28);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2592,24);
manlo <= conv_std_logic_vector(53750480,28);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2608,24);
manlo <= conv_std_logic_vector(54416132,28);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2624,24);
manlo <= conv_std_logic_vector(55085880,28);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2640,24);
manlo <= conv_std_logic_vector(55759725,28);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2656,24);
manlo <= conv_std_logic_vector(56437666,28);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2672,24);
manlo <= conv_std_logic_vector(57119704,28);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2688,24);
manlo <= conv_std_logic_vector(57805839,28);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2704,24);
manlo <= conv_std_logic_vector(58496071,28);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(2720,24);
manlo <= conv_std_logic_vector(59190399,28);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(2736,24);
manlo <= conv_std_logic_vector(59888823,28);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(2752,24);
manlo <= conv_std_logic_vector(60591345,28);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(2768,24);
manlo <= conv_std_logic_vector(61297963,28);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(2784,24);
manlo <= conv_std_logic_vector(62008678,28);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(2800,24);
manlo <= conv_std_logic_vector(62723489,28);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(2816,24);
manlo <= conv_std_logic_vector(63442397,28);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(2832,24);
manlo <= conv_std_logic_vector(64165402,28);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2848,24);
manlo <= conv_std_logic_vector(64892504,28);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(2864,24);
manlo <= conv_std_logic_vector(65623702,28);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(2880,24);
manlo <= conv_std_logic_vector(66358997,28);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(2896,24);
manlo <= conv_std_logic_vector(67098389,28);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(2912,24);
manlo <= conv_std_logic_vector(67841877,28);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(2928,24);
manlo <= conv_std_logic_vector(68589462,28);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(2944,24);
manlo <= conv_std_logic_vector(69341144,28);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(2960,24);
manlo <= conv_std_logic_vector(70096922,28);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(2976,24);
manlo <= conv_std_logic_vector(70856798,28);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2992,24);
manlo <= conv_std_logic_vector(71620769,28);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3008,24);
manlo <= conv_std_logic_vector(72388838,28);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3024,24);
manlo <= conv_std_logic_vector(73161004,28);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3040,24);
manlo <= conv_std_logic_vector(73937266,28);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3056,24);
manlo <= conv_std_logic_vector(74717625,28);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3072,24);
manlo <= conv_std_logic_vector(75502080,28);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3088,24);
manlo <= conv_std_logic_vector(76290633,28);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3104,24);
manlo <= conv_std_logic_vector(77083282,28);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3120,24);
manlo <= conv_std_logic_vector(77880028,28);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3136,24);
manlo <= conv_std_logic_vector(78680870,28);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3152,24);
manlo <= conv_std_logic_vector(79485810,28);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3168,24);
manlo <= conv_std_logic_vector(80294846,28);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3184,24);
manlo <= conv_std_logic_vector(81107979,28);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3200,24);
manlo <= conv_std_logic_vector(81925209,28);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3216,24);
manlo <= conv_std_logic_vector(82746535,28);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3232,24);
manlo <= conv_std_logic_vector(83571958,28);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3248,24);
manlo <= conv_std_logic_vector(84401479,28);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3264,24);
manlo <= conv_std_logic_vector(85235095,28);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3280,24);
manlo <= conv_std_logic_vector(86072809,28);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3296,24);
manlo <= conv_std_logic_vector(86914620,28);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3312,24);
manlo <= conv_std_logic_vector(87760527,28);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3328,24);
manlo <= conv_std_logic_vector(88610531,28);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3344,24);
manlo <= conv_std_logic_vector(89464632,28);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3360,24);
manlo <= conv_std_logic_vector(90322830,28);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3376,24);
manlo <= conv_std_logic_vector(91185124,28);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3392,24);
manlo <= conv_std_logic_vector(92051516,28);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3408,24);
manlo <= conv_std_logic_vector(92922004,28);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3424,24);
manlo <= conv_std_logic_vector(93796589,28);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3440,24);
manlo <= conv_std_logic_vector(94675271,28);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3456,24);
manlo <= conv_std_logic_vector(95558049,28);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3472,24);
manlo <= conv_std_logic_vector(96444925,28);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3488,24);
manlo <= conv_std_logic_vector(97335897,28);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(3504,24);
manlo <= conv_std_logic_vector(98230967,28);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(3520,24);
manlo <= conv_std_logic_vector(99130133,28);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(3536,24);
manlo <= conv_std_logic_vector(100033396,28);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(3552,24);
manlo <= conv_std_logic_vector(100940755,28);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3568,24);
manlo <= conv_std_logic_vector(101852212,28);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(3584,24);
manlo <= conv_std_logic_vector(102767766,28);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(3600,24);
manlo <= conv_std_logic_vector(103687416,28);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(3616,24);
manlo <= conv_std_logic_vector(104611163,28);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(3632,24);
manlo <= conv_std_logic_vector(105539008,28);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(3648,24);
manlo <= conv_std_logic_vector(106470949,28);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(3664,24);
manlo <= conv_std_logic_vector(107406987,28);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(3680,24);
manlo <= conv_std_logic_vector(108347122,28);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(3696,24);
manlo <= conv_std_logic_vector(109291353,28);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3712,24);
manlo <= conv_std_logic_vector(110239682,28);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(3728,24);
manlo <= conv_std_logic_vector(111192108,28);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(3744,24);
manlo <= conv_std_logic_vector(112148630,28);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(3760,24);
manlo <= conv_std_logic_vector(113109250,28);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(3776,24);
manlo <= conv_std_logic_vector(114073966,28);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(3792,24);
manlo <= conv_std_logic_vector(115042779,28);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(3808,24);
manlo <= conv_std_logic_vector(116015689,28);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(3824,24);
manlo <= conv_std_logic_vector(116992696,28);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(3840,24);
manlo <= conv_std_logic_vector(117973801,28);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(3856,24);
manlo <= conv_std_logic_vector(118959001,28);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(3872,24);
manlo <= conv_std_logic_vector(119948299,28);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(3888,24);
manlo <= conv_std_logic_vector(120941694,28);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(3904,24);
manlo <= conv_std_logic_vector(121939186,28);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(3920,24);
manlo <= conv_std_logic_vector(122940775,28);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(3936,24);
manlo <= conv_std_logic_vector(123946461,28);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(3952,24);
manlo <= conv_std_logic_vector(124956243,28);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(3968,24);
manlo <= conv_std_logic_vector(125970123,28);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(3984,24);
manlo <= conv_std_logic_vector(126988100,28);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4000,24);
manlo <= conv_std_logic_vector(128010173,28);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4016,24);
manlo <= conv_std_logic_vector(129036344,28);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4032,24);
manlo <= conv_std_logic_vector(130066611,28);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4048,24);
manlo <= conv_std_logic_vector(131100976,28);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4064,24);
manlo <= conv_std_logic_vector(132139437,28);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4080,24);
manlo <= conv_std_logic_vector(133181996,28);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4096,24);
manlo <= conv_std_logic_vector(134228651,28);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4112,24);
manlo <= conv_std_logic_vector(135279404,28);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4128,24);
manlo <= conv_std_logic_vector(136334253,28);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4144,24);
manlo <= conv_std_logic_vector(137393200,28);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4160,24);
manlo <= conv_std_logic_vector(138456243,28);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4176,24);
manlo <= conv_std_logic_vector(139523384,28);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4192,24);
manlo <= conv_std_logic_vector(140594622,28);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4208,24);
manlo <= conv_std_logic_vector(141669956,28);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4224,24);
manlo <= conv_std_logic_vector(142749388,28);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4240,24);
manlo <= conv_std_logic_vector(143832916,28);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4256,24);
manlo <= conv_std_logic_vector(144920542,28);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4272,24);
manlo <= conv_std_logic_vector(146012265,28);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4288,24);
manlo <= conv_std_logic_vector(147108085,28);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(4304,24);
manlo <= conv_std_logic_vector(148208001,28);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(4320,24);
manlo <= conv_std_logic_vector(149312015,28);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(4336,24);
manlo <= conv_std_logic_vector(150420126,28);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(4352,24);
manlo <= conv_std_logic_vector(151532334,28);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(4368,24);
manlo <= conv_std_logic_vector(152648639,28);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(4384,24);
manlo <= conv_std_logic_vector(153769041,28);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(4400,24);
manlo <= conv_std_logic_vector(154893541,28);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(4416,24);
manlo <= conv_std_logic_vector(156022137,28);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4432,24);
manlo <= conv_std_logic_vector(157154830,28);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(4448,24);
manlo <= conv_std_logic_vector(158291621,28);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(4464,24);
manlo <= conv_std_logic_vector(159432508,28);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(4480,24);
manlo <= conv_std_logic_vector(160577493,28);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(4496,24);
manlo <= conv_std_logic_vector(161726574,28);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(4512,24);
manlo <= conv_std_logic_vector(162879753,28);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(4528,24);
manlo <= conv_std_logic_vector(164037029,28);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(4544,24);
manlo <= conv_std_logic_vector(165198402,28);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(4560,24);
manlo <= conv_std_logic_vector(166363872,28);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(4576,24);
manlo <= conv_std_logic_vector(167533439,28);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(4592,24);
manlo <= conv_std_logic_vector(168707104,28);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(4608,24);
manlo <= conv_std_logic_vector(169884865,28);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(4624,24);
manlo <= conv_std_logic_vector(171066724,28);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(4640,24);
manlo <= conv_std_logic_vector(172252679,28);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(4656,24);
manlo <= conv_std_logic_vector(173442732,28);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(4672,24);
manlo <= conv_std_logic_vector(174636882,28);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(4688,24);
manlo <= conv_std_logic_vector(175835129,28);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(4704,24);
manlo <= conv_std_logic_vector(177037474,28);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(4720,24);
manlo <= conv_std_logic_vector(178243915,28);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(4736,24);
manlo <= conv_std_logic_vector(179454454,28);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(4752,24);
manlo <= conv_std_logic_vector(180669089,28);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(4768,24);
manlo <= conv_std_logic_vector(181887822,28);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(4784,24);
manlo <= conv_std_logic_vector(183110652,28);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(4800,24);
manlo <= conv_std_logic_vector(184337579,28);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(4816,24);
manlo <= conv_std_logic_vector(185568604,28);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(4832,24);
manlo <= conv_std_logic_vector(186803725,28);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(4848,24);
manlo <= conv_std_logic_vector(188042944,28);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(4864,24);
manlo <= conv_std_logic_vector(189286260,28);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(4880,24);
manlo <= conv_std_logic_vector(190533673,28);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(4896,24);
manlo <= conv_std_logic_vector(191785183,28);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(4912,24);
manlo <= conv_std_logic_vector(193040791,28);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(4928,24);
manlo <= conv_std_logic_vector(194300496,28);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(4944,24);
manlo <= conv_std_logic_vector(195564298,28);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(4960,24);
manlo <= conv_std_logic_vector(196832197,28);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4976,24);
manlo <= conv_std_logic_vector(198104193,28);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(4992,24);
manlo <= conv_std_logic_vector(199380286,28);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5008,24);
manlo <= conv_std_logic_vector(200660477,28);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(5024,24);
manlo <= conv_std_logic_vector(201944765,28);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(5040,24);
manlo <= conv_std_logic_vector(203233150,28);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(5056,24);
manlo <= conv_std_logic_vector(204525633,28);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(5072,24);
manlo <= conv_std_logic_vector(205822213,28);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(5088,24);
manlo <= conv_std_logic_vector(207122889,28);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(5104,24);
manlo <= conv_std_logic_vector(208427664,28);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(5120,24);
manlo <= conv_std_logic_vector(209736535,28);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(5136,24);
manlo <= conv_std_logic_vector(211049504,28);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(5152,24);
manlo <= conv_std_logic_vector(212366570,28);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(5168,24);
manlo <= conv_std_logic_vector(213687733,28);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(5184,24);
manlo <= conv_std_logic_vector(215012993,28);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(5200,24);
manlo <= conv_std_logic_vector(216342351,28);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(5216,24);
manlo <= conv_std_logic_vector(217675806,28);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(5232,24);
manlo <= conv_std_logic_vector(219013358,28);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(5248,24);
manlo <= conv_std_logic_vector(220355007,28);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(5264,24);
manlo <= conv_std_logic_vector(221700754,28);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(5280,24);
manlo <= conv_std_logic_vector(223050598,28);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(5296,24);
manlo <= conv_std_logic_vector(224404540,28);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(5312,24);
manlo <= conv_std_logic_vector(225762578,28);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(5328,24);
manlo <= conv_std_logic_vector(227124714,28);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(5344,24);
manlo <= conv_std_logic_vector(228490948,28);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(5360,24);
manlo <= conv_std_logic_vector(229861278,28);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(5376,24);
manlo <= conv_std_logic_vector(231235706,28);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(5392,24);
manlo <= conv_std_logic_vector(232614231,28);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(5408,24);
manlo <= conv_std_logic_vector(233996854,28);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(5424,24);
manlo <= conv_std_logic_vector(235383573,28);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(5440,24);
manlo <= conv_std_logic_vector(236774391,28);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(5456,24);
manlo <= conv_std_logic_vector(238169305,28);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(5472,24);
manlo <= conv_std_logic_vector(239568317,28);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(5488,24);
manlo <= conv_std_logic_vector(240971426,28);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(5504,24);
manlo <= conv_std_logic_vector(242378633,28);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(5520,24);
manlo <= conv_std_logic_vector(243789936,28);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(5536,24);
manlo <= conv_std_logic_vector(245205338,28);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5552,24);
manlo <= conv_std_logic_vector(246624836,28);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(5568,24);
manlo <= conv_std_logic_vector(248048432,28);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(5584,24);
manlo <= conv_std_logic_vector(249476125,28);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(5600,24);
manlo <= conv_std_logic_vector(250907916,28);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(5616,24);
manlo <= conv_std_logic_vector(252343804,28);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(5632,24);
manlo <= conv_std_logic_vector(253783789,28);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(5648,24);
manlo <= conv_std_logic_vector(255227872,28);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(5664,24);
manlo <= conv_std_logic_vector(256676052,28);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(5680,24);
manlo <= conv_std_logic_vector(258128329,28);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5696,24);
manlo <= conv_std_logic_vector(259584704,28);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(5712,24);
manlo <= conv_std_logic_vector(261045176,28);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(5728,24);
manlo <= conv_std_logic_vector(262509746,28);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(5744,24);
manlo <= conv_std_logic_vector(263978413,28);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(5760,24);
manlo <= conv_std_logic_vector(265451178,28);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(5776,24);
manlo <= conv_std_logic_vector(266928039,28);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(5792,24);
manlo <= conv_std_logic_vector(268408999,28);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(5809,24);
manlo <= conv_std_logic_vector(1458599,28);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(5825,24);
manlo <= conv_std_logic_vector(2947754,28);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5841,24);
manlo <= conv_std_logic_vector(4441005,28);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(5857,24);
manlo <= conv_std_logic_vector(5938354,28);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(5873,24);
manlo <= conv_std_logic_vector(7439800,28);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(5889,24);
manlo <= conv_std_logic_vector(8945344,28);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(5905,24);
manlo <= conv_std_logic_vector(10454985,28);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(5921,24);
manlo <= conv_std_logic_vector(11968724,28);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(5937,24);
manlo <= conv_std_logic_vector(13486560,28);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(5953,24);
manlo <= conv_std_logic_vector(15008494,28);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(5969,24);
manlo <= conv_std_logic_vector(16534525,28);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5985,24);
manlo <= conv_std_logic_vector(18064653,28);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(6001,24);
manlo <= conv_std_logic_vector(19598879,28);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(6017,24);
manlo <= conv_std_logic_vector(21137203,28);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(6033,24);
manlo <= conv_std_logic_vector(22679624,28);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(6049,24);
manlo <= conv_std_logic_vector(24226142,28);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(6065,24);
manlo <= conv_std_logic_vector(25776758,28);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(6081,24);
manlo <= conv_std_logic_vector(27331471,28);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(6097,24);
manlo <= conv_std_logic_vector(28890282,28);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(6113,24);
manlo <= conv_std_logic_vector(30453190,28);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6129,24);
manlo <= conv_std_logic_vector(32020196,28);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(6145,24);
manlo <= conv_std_logic_vector(33591299,28);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(6161,24);
manlo <= conv_std_logic_vector(35166500,28);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(6177,24);
manlo <= conv_std_logic_vector(36745798,28);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(6193,24);
manlo <= conv_std_logic_vector(38329194,28);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(6209,24);
manlo <= conv_std_logic_vector(39916688,28);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(6225,24);
manlo <= conv_std_logic_vector(41508278,28);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(6241,24);
manlo <= conv_std_logic_vector(43103967,28);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(6257,24);
manlo <= conv_std_logic_vector(44703753,28);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6273,24);
manlo <= conv_std_logic_vector(46307636,28);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(6289,24);
manlo <= conv_std_logic_vector(47915617,28);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(6305,24);
manlo <= conv_std_logic_vector(49527695,28);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(6321,24);
manlo <= conv_std_logic_vector(51143871,28);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(6337,24);
manlo <= conv_std_logic_vector(52764145,28);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(6353,24);
manlo <= conv_std_logic_vector(54388516,28);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(6369,24);
manlo <= conv_std_logic_vector(56016985,28);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(6385,24);
manlo <= conv_std_logic_vector(57649551,28);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(6401,24);
manlo <= conv_std_logic_vector(59286215,28);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6417,24);
manlo <= conv_std_logic_vector(60926976,28);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(6433,24);
manlo <= conv_std_logic_vector(62571835,28);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(6449,24);
manlo <= conv_std_logic_vector(64220791,28);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(6465,24);
manlo <= conv_std_logic_vector(65873845,28);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(6481,24);
manlo <= conv_std_logic_vector(67530997,28);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(6497,24);
manlo <= conv_std_logic_vector(69192246,28);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(6513,24);
manlo <= conv_std_logic_vector(70857593,28);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(6529,24);
manlo <= conv_std_logic_vector(72527037,28);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(6545,24);
manlo <= conv_std_logic_vector(74200579,28);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6561,24);
manlo <= conv_std_logic_vector(75878219,28);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(6577,24);
manlo <= conv_std_logic_vector(77559956,28);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(6593,24);
manlo <= conv_std_logic_vector(79245791,28);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(6609,24);
manlo <= conv_std_logic_vector(80935723,28);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(6625,24);
manlo <= conv_std_logic_vector(82629753,28);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(6641,24);
manlo <= conv_std_logic_vector(84327881,28);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(6657,24);
manlo <= conv_std_logic_vector(86030106,28);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(6673,24);
manlo <= conv_std_logic_vector(87736429,28);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(6689,24);
manlo <= conv_std_logic_vector(89446849,28);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(6705,24);
manlo <= conv_std_logic_vector(91161367,28);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(6721,24);
manlo <= conv_std_logic_vector(92879983,28);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(6737,24);
manlo <= conv_std_logic_vector(94602697,28);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(6753,24);
manlo <= conv_std_logic_vector(96329508,28);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(6769,24);
manlo <= conv_std_logic_vector(98060416,28);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(6785,24);
manlo <= conv_std_logic_vector(99795423,28);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(6801,24);
manlo <= conv_std_logic_vector(101534527,28);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(6817,24);
manlo <= conv_std_logic_vector(103277728,28);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(6833,24);
manlo <= conv_std_logic_vector(105025028,28);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(6849,24);
manlo <= conv_std_logic_vector(106776425,28);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(6865,24);
manlo <= conv_std_logic_vector(108531919,28);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(6881,24);
manlo <= conv_std_logic_vector(110291512,28);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(6897,24);
manlo <= conv_std_logic_vector(112055202,28);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(6913,24);
manlo <= conv_std_logic_vector(113822989,28);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(6929,24);
manlo <= conv_std_logic_vector(115594875,28);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(6945,24);
manlo <= conv_std_logic_vector(117370858,28);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(6961,24);
manlo <= conv_std_logic_vector(119150939,28);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(6977,24);
manlo <= conv_std_logic_vector(120935117,28);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(6993,24);
manlo <= conv_std_logic_vector(122723393,28);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(7009,24);
manlo <= conv_std_logic_vector(124515767,28);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(7025,24);
manlo <= conv_std_logic_vector(126312239,28);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(7041,24);
manlo <= conv_std_logic_vector(128112808,28);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(7057,24);
manlo <= conv_std_logic_vector(129917475,28);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(7073,24);
manlo <= conv_std_logic_vector(131726240,28);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(7089,24);
manlo <= conv_std_logic_vector(133539102,28);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(7105,24);
manlo <= conv_std_logic_vector(135356063,28);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(7121,24);
manlo <= conv_std_logic_vector(137177121,28);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7137,24);
manlo <= conv_std_logic_vector(139002276,28);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(7153,24);
manlo <= conv_std_logic_vector(140831530,28);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(7169,24);
manlo <= conv_std_logic_vector(142664881,28);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(7185,24);
manlo <= conv_std_logic_vector(144502330,28);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(7201,24);
manlo <= conv_std_logic_vector(146343877,28);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(7217,24);
manlo <= conv_std_logic_vector(148189521,28);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(7233,24);
manlo <= conv_std_logic_vector(150039263,28);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(7249,24);
manlo <= conv_std_logic_vector(151893103,28);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(7265,24);
manlo <= conv_std_logic_vector(153751041,28);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(7281,24);
manlo <= conv_std_logic_vector(155613076,28);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(7297,24);
manlo <= conv_std_logic_vector(157479210,28);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(7313,24);
manlo <= conv_std_logic_vector(159349441,28);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(7329,24);
manlo <= conv_std_logic_vector(161223770,28);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(7345,24);
manlo <= conv_std_logic_vector(163102196,28);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(7361,24);
manlo <= conv_std_logic_vector(164984721,28);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(7377,24);
manlo <= conv_std_logic_vector(166871343,28);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(7393,24);
manlo <= conv_std_logic_vector(168762063,28);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(7409,24);
manlo <= conv_std_logic_vector(170656881,28);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(7425,24);
manlo <= conv_std_logic_vector(172555797,28);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(7441,24);
manlo <= conv_std_logic_vector(174458810,28);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(7457,24);
manlo <= conv_std_logic_vector(176365921,28);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(7473,24);
manlo <= conv_std_logic_vector(178277130,28);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(7489,24);
manlo <= conv_std_logic_vector(180192437,28);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(7505,24);
manlo <= conv_std_logic_vector(182111842,28);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(7521,24);
manlo <= conv_std_logic_vector(184035345,28);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(7537,24);
manlo <= conv_std_logic_vector(185962945,28);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(7553,24);
manlo <= conv_std_logic_vector(187894643,28);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(7569,24);
manlo <= conv_std_logic_vector(189830439,28);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(7585,24);
manlo <= conv_std_logic_vector(191770333,28);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(7601,24);
manlo <= conv_std_logic_vector(193714325,28);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(7617,24);
manlo <= conv_std_logic_vector(195662415,28);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(7633,24);
manlo <= conv_std_logic_vector(197614602,28);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(7649,24);
manlo <= conv_std_logic_vector(199570888,28);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(7665,24);
manlo <= conv_std_logic_vector(201531271,28);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7681,24);
manlo <= conv_std_logic_vector(203495752,28);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(7697,24);
manlo <= conv_std_logic_vector(205464331,28);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(7713,24);
manlo <= conv_std_logic_vector(207437008,28);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(7729,24);
manlo <= conv_std_logic_vector(209413783,28);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(7745,24);
manlo <= conv_std_logic_vector(211394656,28);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(7761,24);
manlo <= conv_std_logic_vector(213379626,28);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(7777,24);
manlo <= conv_std_logic_vector(215368695,28);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(7793,24);
manlo <= conv_std_logic_vector(217361861,28);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(7809,24);
manlo <= conv_std_logic_vector(219359125,28);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7825,24);
manlo <= conv_std_logic_vector(221360487,28);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(7841,24);
manlo <= conv_std_logic_vector(223365947,28);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(7857,24);
manlo <= conv_std_logic_vector(225375505,28);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(7873,24);
manlo <= conv_std_logic_vector(227389161,28);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(7889,24);
manlo <= conv_std_logic_vector(229406915,28);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(7905,24);
manlo <= conv_std_logic_vector(231428767,28);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(7921,24);
manlo <= conv_std_logic_vector(233454716,28);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(7937,24);
manlo <= conv_std_logic_vector(235484764,28);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(7953,24);
manlo <= conv_std_logic_vector(237518910,28);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7969,24);
manlo <= conv_std_logic_vector(239557153,28);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(7985,24);
manlo <= conv_std_logic_vector(241599495,28);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(8001,24);
manlo <= conv_std_logic_vector(243645934,28);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(8017,24);
manlo <= conv_std_logic_vector(245696471,28);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(8033,24);
manlo <= conv_std_logic_vector(247751107,28);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(8049,24);
manlo <= conv_std_logic_vector(249809840,28);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(8065,24);
manlo <= conv_std_logic_vector(251872671,28);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(8081,24);
manlo <= conv_std_logic_vector(253939600,28);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(8097,24);
manlo <= conv_std_logic_vector(256010627,28);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(8113,24);
manlo <= conv_std_logic_vector(258085753,28);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(8129,24);
manlo <= conv_std_logic_vector(260164976,28);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(8145,24);
manlo <= conv_std_logic_vector(262248297,28);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(8161,24);
manlo <= conv_std_logic_vector(264335716,28);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(8177,24);
manlo <= conv_std_logic_vector(266427233,28);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(8194,24);
manlo <= conv_std_logic_vector(87392,28);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(8210,24);
manlo <= conv_std_logic_vector(2187105,28);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(8226,24);
manlo <= conv_std_logic_vector(4290916,28);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(8242,24);
manlo <= conv_std_logic_vector(6398825,28);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8258,24);
manlo <= conv_std_logic_vector(8510832,28);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(8274,24);
manlo <= conv_std_logic_vector(10626938,28);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(8290,24);
manlo <= conv_std_logic_vector(12747141,28);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(8306,24);
manlo <= conv_std_logic_vector(14871442,28);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(8322,24);
manlo <= conv_std_logic_vector(16999841,28);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(8338,24);
manlo <= conv_std_logic_vector(19132338,28);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(8354,24);
manlo <= conv_std_logic_vector(21268934,28);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(8370,24);
manlo <= conv_std_logic_vector(23409627,28);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(8386,24);
manlo <= conv_std_logic_vector(25554418,28);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8402,24);
manlo <= conv_std_logic_vector(27703308,28);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(8418,24);
manlo <= conv_std_logic_vector(29856295,28);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(8434,24);
manlo <= conv_std_logic_vector(32013381,28);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(8450,24);
manlo <= conv_std_logic_vector(34174564,28);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(8466,24);
manlo <= conv_std_logic_vector(36339846,28);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(8482,24);
manlo <= conv_std_logic_vector(38509225,28);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(8498,24);
manlo <= conv_std_logic_vector(40682703,28);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(8514,24);
manlo <= conv_std_logic_vector(42860279,28);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(8530,24);
manlo <= conv_std_logic_vector(45041953,28);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8546,24);
manlo <= conv_std_logic_vector(47227725,28);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(8562,24);
manlo <= conv_std_logic_vector(49417595,28);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(8578,24);
manlo <= conv_std_logic_vector(51611563,28);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(8594,24);
manlo <= conv_std_logic_vector(53809629,28);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(8610,24);
manlo <= conv_std_logic_vector(56011794,28);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(8626,24);
manlo <= conv_std_logic_vector(58218056,28);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(8642,24);
manlo <= conv_std_logic_vector(60428417,28);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(8658,24);
manlo <= conv_std_logic_vector(62642876,28);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(8674,24);
manlo <= conv_std_logic_vector(64861432,28);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8690,24);
manlo <= conv_std_logic_vector(67084087,28);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(8706,24);
manlo <= conv_std_logic_vector(69310840,28);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(8722,24);
manlo <= conv_std_logic_vector(71541691,28);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(8738,24);
manlo <= conv_std_logic_vector(73776641,28);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(8754,24);
manlo <= conv_std_logic_vector(76015688,28);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(8770,24);
manlo <= conv_std_logic_vector(78258834,28);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(8786,24);
manlo <= conv_std_logic_vector(80506077,28);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(8802,24);
manlo <= conv_std_logic_vector(82757419,28);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(8818,24);
manlo <= conv_std_logic_vector(85012859,28);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(8834,24);
manlo <= conv_std_logic_vector(87272397,28);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(8850,24);
manlo <= conv_std_logic_vector(89536034,28);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(8866,24);
manlo <= conv_std_logic_vector(91803768,28);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(8882,24);
manlo <= conv_std_logic_vector(94075601,28);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(8898,24);
manlo <= conv_std_logic_vector(96351532,28);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(8914,24);
manlo <= conv_std_logic_vector(98631561,28);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(8930,24);
manlo <= conv_std_logic_vector(100915688,28);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(8946,24);
manlo <= conv_std_logic_vector(103203913,28);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(8962,24);
manlo <= conv_std_logic_vector(105496237,28);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(8978,24);
manlo <= conv_std_logic_vector(107792658,28);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(8994,24);
manlo <= conv_std_logic_vector(110093178,28);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(9010,24);
manlo <= conv_std_logic_vector(112397796,28);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(9026,24);
manlo <= conv_std_logic_vector(114706513,28);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(9042,24);
manlo <= conv_std_logic_vector(117019327,28);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(9058,24);
manlo <= conv_std_logic_vector(119336240,28);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(9074,24);
manlo <= conv_std_logic_vector(121657251,28);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(9090,24);
manlo <= conv_std_logic_vector(123982360,28);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(9106,24);
manlo <= conv_std_logic_vector(126311567,28);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9122,24);
manlo <= conv_std_logic_vector(128644873,28);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(9138,24);
manlo <= conv_std_logic_vector(130982277,28);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(9154,24);
manlo <= conv_std_logic_vector(133323779,28);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(9170,24);
manlo <= conv_std_logic_vector(135669379,28);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(9186,24);
manlo <= conv_std_logic_vector(138019077,28);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(9202,24);
manlo <= conv_std_logic_vector(140372874,28);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(9218,24);
manlo <= conv_std_logic_vector(142730769,28);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(9234,24);
manlo <= conv_std_logic_vector(145092762,28);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(9250,24);
manlo <= conv_std_logic_vector(147458854,28);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(9266,24);
manlo <= conv_std_logic_vector(149829044,28);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(9282,24);
manlo <= conv_std_logic_vector(152203332,28);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(9298,24);
manlo <= conv_std_logic_vector(154581718,28);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(9314,24);
manlo <= conv_std_logic_vector(156964202,28);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(9330,24);
manlo <= conv_std_logic_vector(159350785,28);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(9346,24);
manlo <= conv_std_logic_vector(161741466,28);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(9362,24);
manlo <= conv_std_logic_vector(164136246,28);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(9378,24);
manlo <= conv_std_logic_vector(166535123,28);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(9394,24);
manlo <= conv_std_logic_vector(168938099,28);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(9410,24);
manlo <= conv_std_logic_vector(171345174,28);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(9426,24);
manlo <= conv_std_logic_vector(173756346,28);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(9442,24);
manlo <= conv_std_logic_vector(176171617,28);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(9458,24);
manlo <= conv_std_logic_vector(178590986,28);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(9474,24);
manlo <= conv_std_logic_vector(181014454,28);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(9490,24);
manlo <= conv_std_logic_vector(183442020,28);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(9506,24);
manlo <= conv_std_logic_vector(185873684,28);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(9522,24);
manlo <= conv_std_logic_vector(188309446,28);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(9538,24);
manlo <= conv_std_logic_vector(190749307,28);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(9554,24);
manlo <= conv_std_logic_vector(193193266,28);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(9570,24);
manlo <= conv_std_logic_vector(195641323,28);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(9586,24);
manlo <= conv_std_logic_vector(198093479,28);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(9602,24);
manlo <= conv_std_logic_vector(200549733,28);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(9618,24);
manlo <= conv_std_logic_vector(203010086,28);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(9634,24);
manlo <= conv_std_logic_vector(205474536,28);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(9650,24);
manlo <= conv_std_logic_vector(207943085,28);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(9666,24);
manlo <= conv_std_logic_vector(210415733,28);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(9682,24);
manlo <= conv_std_logic_vector(212892479,28);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(9698,24);
manlo <= conv_std_logic_vector(215373323,28);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(9714,24);
manlo <= conv_std_logic_vector(217858266,28);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(9730,24);
manlo <= conv_std_logic_vector(220347307,28);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(9746,24);
manlo <= conv_std_logic_vector(222840446,28);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(9762,24);
manlo <= conv_std_logic_vector(225337684,28);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(9778,24);
manlo <= conv_std_logic_vector(227839020,28);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(9794,24);
manlo <= conv_std_logic_vector(230344454,28);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9810,24);
manlo <= conv_std_logic_vector(232853987,28);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(9826,24);
manlo <= conv_std_logic_vector(235367618,28);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(9842,24);
manlo <= conv_std_logic_vector(237885348,28);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(9858,24);
manlo <= conv_std_logic_vector(240407176,28);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(9874,24);
manlo <= conv_std_logic_vector(242933102,28);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(9890,24);
manlo <= conv_std_logic_vector(245463127,28);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(9906,24);
manlo <= conv_std_logic_vector(247997251,28);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(9922,24);
manlo <= conv_std_logic_vector(250535472,28);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(9938,24);
manlo <= conv_std_logic_vector(253077793,28);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9954,24);
manlo <= conv_std_logic_vector(255624211,28);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(9970,24);
manlo <= conv_std_logic_vector(258174728,28);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(9986,24);
manlo <= conv_std_logic_vector(260729344,28);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(10002,24);
manlo <= conv_std_logic_vector(263288057,28);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(10018,24);
manlo <= conv_std_logic_vector(265850870,28);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(10034,24);
manlo <= conv_std_logic_vector(268417780,28);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(10051,24);
manlo <= conv_std_logic_vector(2553334,28);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(10067,24);
manlo <= conv_std_logic_vector(5128441,28);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(10083,24);
manlo <= conv_std_logic_vector(7707647,28);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(10099,24);
manlo <= conv_std_logic_vector(10290952,28);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(10115,24);
manlo <= conv_std_logic_vector(12878355,28);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(10131,24);
manlo <= conv_std_logic_vector(15469857,28);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(10147,24);
manlo <= conv_std_logic_vector(18065457,28);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(10163,24);
manlo <= conv_std_logic_vector(20665155,28);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(10179,24);
manlo <= conv_std_logic_vector(23268952,28);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(10195,24);
manlo <= conv_std_logic_vector(25876847,28);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(10211,24);
manlo <= conv_std_logic_vector(28488841,28);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(10227,24);
manlo <= conv_std_logic_vector(31104934,28);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10243,24);
manlo <= conv_std_logic_vector(33725125,28);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(10259,24);
manlo <= conv_std_logic_vector(36349414,28);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(10275,24);
manlo <= conv_std_logic_vector(38977802,28);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(10291,24);
manlo <= conv_std_logic_vector(41610288,28);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(10307,24);
manlo <= conv_std_logic_vector(44246873,28);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(10323,24);
manlo <= conv_std_logic_vector(46887557,28);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(10339,24);
manlo <= conv_std_logic_vector(49532339,28);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(10355,24);
manlo <= conv_std_logic_vector(52181219,28);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(10371,24);
manlo <= conv_std_logic_vector(54834198,28);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10387,24);
manlo <= conv_std_logic_vector(57491276,28);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(10403,24);
manlo <= conv_std_logic_vector(60152452,28);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(10419,24);
manlo <= conv_std_logic_vector(62817727,28);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(10435,24);
manlo <= conv_std_logic_vector(65487100,28);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(10451,24);
manlo <= conv_std_logic_vector(68160572,28);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(10467,24);
manlo <= conv_std_logic_vector(70838142,28);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(10483,24);
manlo <= conv_std_logic_vector(73519811,28);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(10499,24);
manlo <= conv_std_logic_vector(76205578,28);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(10515,24);
manlo <= conv_std_logic_vector(78895444,28);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10531,24);
manlo <= conv_std_logic_vector(81589409,28);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(10547,24);
manlo <= conv_std_logic_vector(84287472,28);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(10563,24);
manlo <= conv_std_logic_vector(86989633,28);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(10579,24);
manlo <= conv_std_logic_vector(89695894,28);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(10595,24);
manlo <= conv_std_logic_vector(92406252,28);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(10611,24);
manlo <= conv_std_logic_vector(95120710,28);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(10627,24);
manlo <= conv_std_logic_vector(97839266,28);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(10643,24);
manlo <= conv_std_logic_vector(100561920,28);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(10659,24);
manlo <= conv_std_logic_vector(103288674,28);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10675,24);
manlo <= conv_std_logic_vector(106019525,28);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(10691,24);
manlo <= conv_std_logic_vector(108754476,28);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(10707,24);
manlo <= conv_std_logic_vector(111493525,28);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(10723,24);
manlo <= conv_std_logic_vector(114236673,28);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(10739,24);
manlo <= conv_std_logic_vector(116983919,28);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(10755,24);
manlo <= conv_std_logic_vector(119735264,28);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(10771,24);
manlo <= conv_std_logic_vector(122490707,28);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(10787,24);
manlo <= conv_std_logic_vector(125250249,28);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(10803,24);
manlo <= conv_std_logic_vector(128013890,28);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(10819,24);
manlo <= conv_std_logic_vector(130781629,28);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(10835,24);
manlo <= conv_std_logic_vector(133553468,28);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(10851,24);
manlo <= conv_std_logic_vector(136329404,28);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(10867,24);
manlo <= conv_std_logic_vector(139109440,28);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(10883,24);
manlo <= conv_std_logic_vector(141893574,28);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(10899,24);
manlo <= conv_std_logic_vector(144681806,28);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(10915,24);
manlo <= conv_std_logic_vector(147474137,28);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(10931,24);
manlo <= conv_std_logic_vector(150270567,28);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(10947,24);
manlo <= conv_std_logic_vector(153071096,28);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(10963,24);
manlo <= conv_std_logic_vector(155875723,28);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(10979,24);
manlo <= conv_std_logic_vector(158684449,28);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(10995,24);
manlo <= conv_std_logic_vector(161497274,28);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(11011,24);
manlo <= conv_std_logic_vector(164314197,28);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(11027,24);
manlo <= conv_std_logic_vector(167135219,28);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(11043,24);
manlo <= conv_std_logic_vector(169960340,28);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(11059,24);
manlo <= conv_std_logic_vector(172789560,28);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(11075,24);
manlo <= conv_std_logic_vector(175622878,28);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(11091,24);
manlo <= conv_std_logic_vector(178460295,28);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11107,24);
manlo <= conv_std_logic_vector(181301810,28);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(11123,24);
manlo <= conv_std_logic_vector(184147424,28);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(11139,24);
manlo <= conv_std_logic_vector(186997137,28);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(11155,24);
manlo <= conv_std_logic_vector(189850949,28);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(11171,24);
manlo <= conv_std_logic_vector(192708860,28);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(11187,24);
manlo <= conv_std_logic_vector(195570869,28);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(11203,24);
manlo <= conv_std_logic_vector(198436977,28);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(11219,24);
manlo <= conv_std_logic_vector(201307183,28);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(11235,24);
manlo <= conv_std_logic_vector(204181489,28);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(11251,24);
manlo <= conv_std_logic_vector(207059893,28);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(11267,24);
manlo <= conv_std_logic_vector(209942395,28);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(11283,24);
manlo <= conv_std_logic_vector(212828997,28);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(11299,24);
manlo <= conv_std_logic_vector(215719697,28);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(11315,24);
manlo <= conv_std_logic_vector(218614497,28);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(11331,24);
manlo <= conv_std_logic_vector(221513394,28);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(11347,24);
manlo <= conv_std_logic_vector(224416391,28);
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(11363,24);
manlo <= conv_std_logic_vector(227323486,28);
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(11379,24);
manlo <= conv_std_logic_vector(230234681,28);
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(11395,24);
manlo <= conv_std_logic_vector(233149974,28);
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(11411,24);
manlo <= conv_std_logic_vector(236069365,28);
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(11427,24);
manlo <= conv_std_logic_vector(238992856,28);
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(11443,24);
manlo <= conv_std_logic_vector(241920445,28);
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(11459,24);
manlo <= conv_std_logic_vector(244852133,28);
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(11475,24);
manlo <= conv_std_logic_vector(247787920,28);
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(11491,24);
manlo <= conv_std_logic_vector(250727806,28);
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(11507,24);
manlo <= conv_std_logic_vector(253671790,28);
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(11523,24);
manlo <= conv_std_logic_vector(256619874,28);
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(11539,24);
manlo <= conv_std_logic_vector(259572056,28);
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(11555,24);
manlo <= conv_std_logic_vector(262528337,28);
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(11571,24);
manlo <= conv_std_logic_vector(265488717,28);
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(11588,24);
manlo <= conv_std_logic_vector(17739,28);
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(11604,24);
manlo <= conv_std_logic_vector(2986317,28);
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(11620,24);
manlo <= conv_std_logic_vector(5958993,28);
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(11636,24);
manlo <= conv_std_logic_vector(8935768,28);
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(11652,24);
manlo <= conv_std_logic_vector(11916642,28);
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(11668,24);
manlo <= conv_std_logic_vector(14901615,28);
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(11684,24);
manlo <= conv_std_logic_vector(17890686,28);
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(11700,24);
manlo <= conv_std_logic_vector(20883857,28);
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(11716,24);
manlo <= conv_std_logic_vector(23881126,28);
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(11732,24);
manlo <= conv_std_logic_vector(26882494,28);
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(11748,24);
manlo <= conv_std_logic_vector(29887961,28);
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(11764,24);
manlo <= conv_std_logic_vector(32897527,28);
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(11780,24);
manlo <= conv_std_logic_vector(35911192,28);
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(11796,24);
manlo <= conv_std_logic_vector(38928956,28);
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(11812,24);
manlo <= conv_std_logic_vector(41950818,28);
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(11828,24);
manlo <= conv_std_logic_vector(44976780,28);
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(11844,24);
manlo <= conv_std_logic_vector(48006840,28);
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(11860,24);
manlo <= conv_std_logic_vector(51040999,28);
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(11876,24);
manlo <= conv_std_logic_vector(54079258,28);
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(11892,24);
manlo <= conv_std_logic_vector(57121615,28);
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(11908,24);
manlo <= conv_std_logic_vector(60168071,28);
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(11924,24);
manlo <= conv_std_logic_vector(63218625,28);
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(11940,24);
manlo <= conv_std_logic_vector(66273279,28);
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(11956,24);
manlo <= conv_std_logic_vector(69332032,28);
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(11972,24);
manlo <= conv_std_logic_vector(72394883,28);
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(11988,24);
manlo <= conv_std_logic_vector(75461834,28);
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(12004,24);
manlo <= conv_std_logic_vector(78532883,28);
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(12020,24);
manlo <= conv_std_logic_vector(81608032,28);
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(12036,24);
manlo <= conv_std_logic_vector(84687279,28);
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(12052,24);
manlo <= conv_std_logic_vector(87770625,28);
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(12068,24);
manlo <= conv_std_logic_vector(90858070,28);
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(12084,24);
manlo <= conv_std_logic_vector(93949615,28);
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(12100,24);
manlo <= conv_std_logic_vector(97045258,28);
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(12116,24);
manlo <= conv_std_logic_vector(100145000,28);
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(12132,24);
manlo <= conv_std_logic_vector(103248841,28);
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(12148,24);
manlo <= conv_std_logic_vector(106356781,28);
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(12164,24);
manlo <= conv_std_logic_vector(109468819,28);
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(12180,24);
manlo <= conv_std_logic_vector(112584957,28);
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(12196,24);
manlo <= conv_std_logic_vector(115705194,28);
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(12212,24);
manlo <= conv_std_logic_vector(118829530,28);
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(12228,24);
manlo <= conv_std_logic_vector(121957965,28);
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(12244,24);
manlo <= conv_std_logic_vector(125090499,28);
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(12260,24);
manlo <= conv_std_logic_vector(128227131,28);
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(12276,24);
manlo <= conv_std_logic_vector(131367863,28);
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(12292,24);
manlo <= conv_std_logic_vector(134512694,28);
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(12308,24);
manlo <= conv_std_logic_vector(137661624,28);
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(12324,24);
manlo <= conv_std_logic_vector(140814653,28);
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(12340,24);
manlo <= conv_std_logic_vector(143971780,28);
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(12356,24);
manlo <= conv_std_logic_vector(147133007,28);
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(12372,24);
manlo <= conv_std_logic_vector(150298333,28);
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(12388,24);
manlo <= conv_std_logic_vector(153467758,28);
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(12404,24);
manlo <= conv_std_logic_vector(156641282,28);
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(12420,24);
manlo <= conv_std_logic_vector(159818905,28);
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(12436,24);
manlo <= conv_std_logic_vector(163000627,28);
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(12452,24);
manlo <= conv_std_logic_vector(166186448,28);
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(12468,24);
manlo <= conv_std_logic_vector(169376368,28);
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(12484,24);
manlo <= conv_std_logic_vector(172570387,28);
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(12500,24);
manlo <= conv_std_logic_vector(175768505,28);
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(12516,24);
manlo <= conv_std_logic_vector(178970722,28);
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(12532,24);
manlo <= conv_std_logic_vector(182177038,28);
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(12548,24);
manlo <= conv_std_logic_vector(185387453,28);
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(12564,24);
manlo <= conv_std_logic_vector(188601968,28);
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(12580,24);
manlo <= conv_std_logic_vector(191820581,28);
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(12596,24);
manlo <= conv_std_logic_vector(195043294,28);
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(12612,24);
manlo <= conv_std_logic_vector(198270105,28);
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(12628,24);
manlo <= conv_std_logic_vector(201501016,28);
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(12644,24);
manlo <= conv_std_logic_vector(204736025,28);
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(12660,24);
manlo <= conv_std_logic_vector(207975134,28);
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(12676,24);
manlo <= conv_std_logic_vector(211218342,28);
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(12692,24);
manlo <= conv_std_logic_vector(214465649,28);
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(12708,24);
manlo <= conv_std_logic_vector(217717055,28);
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(12724,24);
manlo <= conv_std_logic_vector(220972560,28);
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(12740,24);
manlo <= conv_std_logic_vector(224232165,28);
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(12756,24);
manlo <= conv_std_logic_vector(227495868,28);
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(12772,24);
manlo <= conv_std_logic_vector(230763671,28);
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(12788,24);
manlo <= conv_std_logic_vector(234035572,28);
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(12804,24);
manlo <= conv_std_logic_vector(237311573,28);
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(12820,24);
manlo <= conv_std_logic_vector(240591673,28);
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(12836,24);
manlo <= conv_std_logic_vector(243875872,28);
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(12852,24);
manlo <= conv_std_logic_vector(247164170,28);
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(12868,24);
manlo <= conv_std_logic_vector(250456567,28);
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(12884,24);
manlo <= conv_std_logic_vector(253753064,28);
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(12900,24);
manlo <= conv_std_logic_vector(257053659,28);
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(12916,24);
manlo <= conv_std_logic_vector(260358354,28);
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(12932,24);
manlo <= conv_std_logic_vector(263667148,28);
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(12948,24);
manlo <= conv_std_logic_vector(266980041,28);
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(12965,24);
manlo <= conv_std_logic_vector(1861577,28);
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(12981,24);
manlo <= conv_std_logic_vector(5182668,28);
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(12997,24);
manlo <= conv_std_logic_vector(8507859,28);
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(13013,24);
manlo <= conv_std_logic_vector(11837149,28);
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(13029,24);
manlo <= conv_std_logic_vector(15170538,28);
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(13045,24);
manlo <= conv_std_logic_vector(18508026,28);
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(13061,24);
manlo <= conv_std_logic_vector(21849613,28);
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(13077,24);
manlo <= conv_std_logic_vector(25195299,28);
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(13093,24);
manlo <= conv_std_logic_vector(28545085,28);
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(13109,24);
manlo <= conv_std_logic_vector(31898970,28);
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(13125,24);
manlo <= conv_std_logic_vector(35256954,28);
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(13141,24);
manlo <= conv_std_logic_vector(38619037,28);
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(13157,24);
manlo <= conv_std_logic_vector(41985219,28);
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(13173,24);
manlo <= conv_std_logic_vector(45355501,28);
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(13189,24);
manlo <= conv_std_logic_vector(48729882,28);
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(13205,24);
manlo <= conv_std_logic_vector(52108362,28);
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(13221,24);
manlo <= conv_std_logic_vector(55490941,28);
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(13237,24);
manlo <= conv_std_logic_vector(58877620,28);
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(13253,24);
manlo <= conv_std_logic_vector(62268398,28);
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(13269,24);
manlo <= conv_std_logic_vector(65663275,28);
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(13285,24);
manlo <= conv_std_logic_vector(69062251,28);
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(13301,24);
manlo <= conv_std_logic_vector(72465326,28);
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(13317,24);
manlo <= conv_std_logic_vector(75872501,28);
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(13333,24);
manlo <= conv_std_logic_vector(79283775,28);
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(13349,24);
manlo <= conv_std_logic_vector(82699148,28);
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(13365,24);
manlo <= conv_std_logic_vector(86118621,28);
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(13381,24);
manlo <= conv_std_logic_vector(89542193,28);
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(13397,24);
manlo <= conv_std_logic_vector(92969864,28);
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(13413,24);
manlo <= conv_std_logic_vector(96401634,28);
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(13429,24);
manlo <= conv_std_logic_vector(99837503,28);
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(13445,24);
manlo <= conv_std_logic_vector(103277472,28);
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(13461,24);
manlo <= conv_std_logic_vector(106721540,28);
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(13477,24);
manlo <= conv_std_logic_vector(110169708,28);
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(13493,24);
manlo <= conv_std_logic_vector(113621975,28);
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(13509,24);
manlo <= conv_std_logic_vector(117078341,28);
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(13525,24);
manlo <= conv_std_logic_vector(120538806,28);
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(13541,24);
manlo <= conv_std_logic_vector(124003370,28);
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(13557,24);
manlo <= conv_std_logic_vector(127472034,28);
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(13573,24);
manlo <= conv_std_logic_vector(130944798,28);
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(13589,24);
manlo <= conv_std_logic_vector(134421660,28);
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(13605,24);
manlo <= conv_std_logic_vector(137902622,28);
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(13621,24);
manlo <= conv_std_logic_vector(141387683,28);
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(13637,24);
manlo <= conv_std_logic_vector(144876844,28);
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(13653,24);
manlo <= conv_std_logic_vector(148370104,28);
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(13669,24);
manlo <= conv_std_logic_vector(151867463,28);
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(13685,24);
manlo <= conv_std_logic_vector(155368921,28);
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(13701,24);
manlo <= conv_std_logic_vector(158874479,28);
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(13717,24);
manlo <= conv_std_logic_vector(162384136,28);
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(13733,24);
manlo <= conv_std_logic_vector(165897893,28);
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(13749,24);
manlo <= conv_std_logic_vector(169415749,28);
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(13765,24);
manlo <= conv_std_logic_vector(172937704,28);
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(13781,24);
manlo <= conv_std_logic_vector(176463758,28);
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(13797,24);
manlo <= conv_std_logic_vector(179993912,28);
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(13813,24);
manlo <= conv_std_logic_vector(183528166,28);
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(13829,24);
manlo <= conv_std_logic_vector(187066519,28);
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(13845,24);
manlo <= conv_std_logic_vector(190608971,28);
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(13861,24);
manlo <= conv_std_logic_vector(194155522,28);
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(13877,24);
manlo <= conv_std_logic_vector(197706173,28);
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(13893,24);
manlo <= conv_std_logic_vector(201260923,28);
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(13909,24);
manlo <= conv_std_logic_vector(204819773,28);
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(13925,24);
manlo <= conv_std_logic_vector(208382722,28);
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(13941,24);
manlo <= conv_std_logic_vector(211949770,28);
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(13957,24);
manlo <= conv_std_logic_vector(215520918,28);
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(13973,24);
manlo <= conv_std_logic_vector(219096165,28);
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(13989,24);
manlo <= conv_std_logic_vector(222675512,28);
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(14005,24);
manlo <= conv_std_logic_vector(226258958,28);
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(14021,24);
manlo <= conv_std_logic_vector(229846504,28);
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(14037,24);
manlo <= conv_std_logic_vector(233438148,28);
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(14053,24);
manlo <= conv_std_logic_vector(237033893,28);
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(14069,24);
manlo <= conv_std_logic_vector(240633737,28);
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(14085,24);
manlo <= conv_std_logic_vector(244237680,28);
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(14101,24);
manlo <= conv_std_logic_vector(247845722,28);
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(14117,24);
manlo <= conv_std_logic_vector(251457864,28);
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(14133,24);
manlo <= conv_std_logic_vector(255074106,28);
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(14149,24);
manlo <= conv_std_logic_vector(258694447,28);
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(14165,24);
manlo <= conv_std_logic_vector(262318887,28);
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(14181,24);
manlo <= conv_std_logic_vector(265947427,28);
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(14198,24);
manlo <= conv_std_logic_vector(1144611,28);
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(14214,24);
manlo <= conv_std_logic_vector(4781350,28);
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(14230,24);
manlo <= conv_std_logic_vector(8422188,28);
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(14246,24);
manlo <= conv_std_logic_vector(12067126,28);
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(14262,24);
manlo <= conv_std_logic_vector(15716163,28);
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(14278,24);
manlo <= conv_std_logic_vector(19369300,28);
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(14294,24);
manlo <= conv_std_logic_vector(23026536,28);
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(14310,24);
manlo <= conv_std_logic_vector(26687871,28);
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(14326,24);
manlo <= conv_std_logic_vector(30353307,28);
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(14342,24);
manlo <= conv_std_logic_vector(34022841,28);
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(14358,24);
manlo <= conv_std_logic_vector(37696476,28);
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(14374,24);
manlo <= conv_std_logic_vector(41374209,28);
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(14390,24);
manlo <= conv_std_logic_vector(45056043,28);
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(14406,24);
manlo <= conv_std_logic_vector(48741975,28);
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(14422,24);
manlo <= conv_std_logic_vector(52432007,28);
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(14438,24);
manlo <= conv_std_logic_vector(56126139,28);
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(14454,24);
manlo <= conv_std_logic_vector(59824371,28);
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(14470,24);
manlo <= conv_std_logic_vector(63526701,28);
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(14486,24);
manlo <= conv_std_logic_vector(67233132,28);
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(14502,24);
manlo <= conv_std_logic_vector(70943662,28);
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(14518,24);
manlo <= conv_std_logic_vector(74658291,28);
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(14534,24);
manlo <= conv_std_logic_vector(78377020,28);
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(14550,24);
manlo <= conv_std_logic_vector(82099849,28);
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(14566,24);
manlo <= conv_std_logic_vector(85826777,28);
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(14582,24);
manlo <= conv_std_logic_vector(89557804,28);
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(14598,24);
manlo <= conv_std_logic_vector(93292931,28);
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(14614,24);
manlo <= conv_std_logic_vector(97032158,28);
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(14630,24);
manlo <= conv_std_logic_vector(100775484,28);
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(14646,24);
manlo <= conv_std_logic_vector(104522910,28);
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(14662,24);
manlo <= conv_std_logic_vector(108274436,28);
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(14678,24);
manlo <= conv_std_logic_vector(112030061,28);
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(14694,24);
manlo <= conv_std_logic_vector(115789786,28);
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(14710,24);
manlo <= conv_std_logic_vector(119553610,28);
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(14726,24);
manlo <= conv_std_logic_vector(123321534,28);
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(14742,24);
manlo <= conv_std_logic_vector(127093557,28);
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(14758,24);
manlo <= conv_std_logic_vector(130869680,28);
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(14774,24);
manlo <= conv_std_logic_vector(134649903,28);
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(14790,24);
manlo <= conv_std_logic_vector(138434225,28);
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(14806,24);
manlo <= conv_std_logic_vector(142222647,28);
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(14822,24);
manlo <= conv_std_logic_vector(146015168,28);
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(14838,24);
manlo <= conv_std_logic_vector(149811789,28);
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(14854,24);
manlo <= conv_std_logic_vector(153612510,28);
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(14870,24);
manlo <= conv_std_logic_vector(157417330,28);
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(14886,24);
manlo <= conv_std_logic_vector(161226250,28);
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(14902,24);
manlo <= conv_std_logic_vector(165039270,28);
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(14918,24);
manlo <= conv_std_logic_vector(168856389,28);
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(14934,24);
manlo <= conv_std_logic_vector(172677608,28);
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(14950,24);
manlo <= conv_std_logic_vector(176502926,28);
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(14966,24);
manlo <= conv_std_logic_vector(180332344,28);
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(14982,24);
manlo <= conv_std_logic_vector(184165862,28);
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(14998,24);
manlo <= conv_std_logic_vector(188003480,28);
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(15014,24);
manlo <= conv_std_logic_vector(191845197,28);
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(15030,24);
manlo <= conv_std_logic_vector(195691014,28);
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(15046,24);
manlo <= conv_std_logic_vector(199540930,28);
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(15062,24);
manlo <= conv_std_logic_vector(203394946,28);
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(15078,24);
manlo <= conv_std_logic_vector(207253062,28);
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(15094,24);
manlo <= conv_std_logic_vector(211115277,28);
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(15110,24);
manlo <= conv_std_logic_vector(214981593,28);
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(15126,24);
manlo <= conv_std_logic_vector(218852007,28);
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(15142,24);
manlo <= conv_std_logic_vector(222726522,28);
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(15158,24);
manlo <= conv_std_logic_vector(226605136,28);
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(15174,24);
manlo <= conv_std_logic_vector(230487850,28);
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(15190,24);
manlo <= conv_std_logic_vector(234374664,28);
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(15206,24);
manlo <= conv_std_logic_vector(238265577,28);
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(15222,24);
manlo <= conv_std_logic_vector(242160590,28);
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(15238,24);
manlo <= conv_std_logic_vector(246059703,28);
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(15254,24);
manlo <= conv_std_logic_vector(249962916,28);
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(15270,24);
manlo <= conv_std_logic_vector(253870228,28);
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(15286,24);
manlo <= conv_std_logic_vector(257781640,28);
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(15302,24);
manlo <= conv_std_logic_vector(261697152,28);
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(15318,24);
manlo <= conv_std_logic_vector(265616763,28);
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(15335,24);
manlo <= conv_std_logic_vector(1105018,28);
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(15351,24);
manlo <= conv_std_logic_vector(5032829,28);
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(15367,24);
manlo <= conv_std_logic_vector(8964740,28);
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(15383,24);
manlo <= conv_std_logic_vector(12900750,28);
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(15399,24);
manlo <= conv_std_logic_vector(16840860,28);
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(15415,24);
manlo <= conv_std_logic_vector(20785070,28);
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(15431,24);
manlo <= conv_std_logic_vector(24733380,28);
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(15447,24);
manlo <= conv_std_logic_vector(28685790,28);
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(15463,24);
manlo <= conv_std_logic_vector(32642299,28);
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(15479,24);
manlo <= conv_std_logic_vector(36602908,28);
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(15495,24);
manlo <= conv_std_logic_vector(40567617,28);
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(15511,24);
manlo <= conv_std_logic_vector(44536425,28);
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(15527,24);
manlo <= conv_std_logic_vector(48509334,28);
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(15543,24);
manlo <= conv_std_logic_vector(52486342,28);
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(15559,24);
manlo <= conv_std_logic_vector(56467450,28);
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(15575,24);
manlo <= conv_std_logic_vector(60452657,28);
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(15591,24);
manlo <= conv_std_logic_vector(64441965,28);
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(15607,24);
manlo <= conv_std_logic_vector(68435372,28);
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(15623,24);
manlo <= conv_std_logic_vector(72432880,28);
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(15639,24);
manlo <= conv_std_logic_vector(76434487,28);
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(15655,24);
manlo <= conv_std_logic_vector(80440193,28);
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(15671,24);
manlo <= conv_std_logic_vector(84450000,28);
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(15687,24);
manlo <= conv_std_logic_vector(88463906,28);
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(15703,24);
manlo <= conv_std_logic_vector(92481913,28);
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(15719,24);
manlo <= conv_std_logic_vector(96504019,28);
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(15735,24);
manlo <= conv_std_logic_vector(100530225,28);
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(15751,24);
manlo <= conv_std_logic_vector(104560531,28);
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(15767,24);
manlo <= conv_std_logic_vector(108594936,28);
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(15783,24);
manlo <= conv_std_logic_vector(112633442,28);
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(15799,24);
manlo <= conv_std_logic_vector(116676047,28);
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(15815,24);
manlo <= conv_std_logic_vector(120722752,28);
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(15831,24);
manlo <= conv_std_logic_vector(124773557,28);
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(15847,24);
manlo <= conv_std_logic_vector(128828462,28);
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(15863,24);
manlo <= conv_std_logic_vector(132887467,28);
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(15879,24);
manlo <= conv_std_logic_vector(136950572,28);
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(15895,24);
manlo <= conv_std_logic_vector(141017776,28);
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(15911,24);
manlo <= conv_std_logic_vector(145089081,28);
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(15927,24);
manlo <= conv_std_logic_vector(149164485,28);
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(15943,24);
manlo <= conv_std_logic_vector(153243989,28);
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(15959,24);
manlo <= conv_std_logic_vector(157327593,28);
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(15975,24);
manlo <= conv_std_logic_vector(161415297,28);
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(15991,24);
manlo <= conv_std_logic_vector(165507101,28);
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(16007,24);
manlo <= conv_std_logic_vector(169603005,28);
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(16023,24);
manlo <= conv_std_logic_vector(173703009,28);
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(16039,24);
manlo <= conv_std_logic_vector(177807112,28);
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(16055,24);
manlo <= conv_std_logic_vector(181915316,28);
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(16071,24);
manlo <= conv_std_logic_vector(186027619,28);
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(16087,24);
manlo <= conv_std_logic_vector(190144023,28);
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(16103,24);
manlo <= conv_std_logic_vector(194264526,28);
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(16119,24);
manlo <= conv_std_logic_vector(198389129,28);
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(16135,24);
manlo <= conv_std_logic_vector(202517832,28);
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(16151,24);
manlo <= conv_std_logic_vector(206650635,28);
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(16167,24);
manlo <= conv_std_logic_vector(210787538,28);
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(16183,24);
manlo <= conv_std_logic_vector(214928541,28);
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(16199,24);
manlo <= conv_std_logic_vector(219073644,28);
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(16215,24);
manlo <= conv_std_logic_vector(223222847,28);
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(16231,24);
manlo <= conv_std_logic_vector(227376150,28);
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(16247,24);
manlo <= conv_std_logic_vector(231533553,28);
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(16263,24);
manlo <= conv_std_logic_vector(235695056,28);
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(16279,24);
manlo <= conv_std_logic_vector(239860659,28);
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(16295,24);
manlo <= conv_std_logic_vector(244030361,28);
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(16311,24);
manlo <= conv_std_logic_vector(248204164,28);
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(16327,24);
manlo <= conv_std_logic_vector(252382067,28);
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(16343,24);
manlo <= conv_std_logic_vector(256564069,28);
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(16359,24);
manlo <= conv_std_logic_vector(260750172,28);
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(16375,24);
manlo <= conv_std_logic_vector(264940375,28);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT20.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut20 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
END dp_explut20;
ARCHITECTURE rtl OF dp_explut20 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16,24);
manlo <= conv_std_logic_vector(2048,28);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32,24);
manlo <= conv_std_logic_vector(8192,28);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(48,24);
manlo <= conv_std_logic_vector(18432,28);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(64,24);
manlo <= conv_std_logic_vector(32768,28);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(80,24);
manlo <= conv_std_logic_vector(51200,28);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(96,24);
manlo <= conv_std_logic_vector(73728,28);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(112,24);
manlo <= conv_std_logic_vector(100352,28);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(128,24);
manlo <= conv_std_logic_vector(131072,28);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(144,24);
manlo <= conv_std_logic_vector(165888,28);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(160,24);
manlo <= conv_std_logic_vector(204801,28);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(176,24);
manlo <= conv_std_logic_vector(247809,28);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(192,24);
manlo <= conv_std_logic_vector(294913,28);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(208,24);
manlo <= conv_std_logic_vector(346113,28);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(224,24);
manlo <= conv_std_logic_vector(401410,28);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(240,24);
manlo <= conv_std_logic_vector(460802,28);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(256,24);
manlo <= conv_std_logic_vector(524291,28);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(272,24);
manlo <= conv_std_logic_vector(591875,28);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(288,24);
manlo <= conv_std_logic_vector(663556,28);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(304,24);
manlo <= conv_std_logic_vector(739332,28);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(320,24);
manlo <= conv_std_logic_vector(819205,28);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(336,24);
manlo <= conv_std_logic_vector(903174,28);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(352,24);
manlo <= conv_std_logic_vector(991239,28);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(368,24);
manlo <= conv_std_logic_vector(1083400,28);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(384,24);
manlo <= conv_std_logic_vector(1179657,28);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(400,24);
manlo <= conv_std_logic_vector(1280010,28);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(416,24);
manlo <= conv_std_logic_vector(1384459,28);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(432,24);
manlo <= conv_std_logic_vector(1493005,28);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(448,24);
manlo <= conv_std_logic_vector(1605646,28);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(464,24);
manlo <= conv_std_logic_vector(1722384,28);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(480,24);
manlo <= conv_std_logic_vector(1843218,28);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(496,24);
manlo <= conv_std_logic_vector(1968147,28);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(512,24);
manlo <= conv_std_logic_vector(2097173,28);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(528,24);
manlo <= conv_std_logic_vector(2230295,28);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(544,24);
manlo <= conv_std_logic_vector(2367514,28);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(560,24);
manlo <= conv_std_logic_vector(2508828,28);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(576,24);
manlo <= conv_std_logic_vector(2654238,28);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(592,24);
manlo <= conv_std_logic_vector(2803745,28);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(608,24);
manlo <= conv_std_logic_vector(2957348,28);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(624,24);
manlo <= conv_std_logic_vector(3115047,28);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(640,24);
manlo <= conv_std_logic_vector(3276842,28);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(656,24);
manlo <= conv_std_logic_vector(3442733,28);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(672,24);
manlo <= conv_std_logic_vector(3612720,28);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(688,24);
manlo <= conv_std_logic_vector(3786804,28);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(704,24);
manlo <= conv_std_logic_vector(3964983,28);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(720,24);
manlo <= conv_std_logic_vector(4147259,28);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(736,24);
manlo <= conv_std_logic_vector(4333631,28);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(752,24);
manlo <= conv_std_logic_vector(4524100,28);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(768,24);
manlo <= conv_std_logic_vector(4718664,28);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(784,24);
manlo <= conv_std_logic_vector(4917325,28);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(800,24);
manlo <= conv_std_logic_vector(5120081,28);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(816,24);
manlo <= conv_std_logic_vector(5326934,28);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(832,24);
manlo <= conv_std_logic_vector(5537884,28);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(848,24);
manlo <= conv_std_logic_vector(5752929,28);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(864,24);
manlo <= conv_std_logic_vector(5972071,28);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(880,24);
manlo <= conv_std_logic_vector(6195308,28);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(896,24);
manlo <= conv_std_logic_vector(6422642,28);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(912,24);
manlo <= conv_std_logic_vector(6654073,28);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(928,24);
manlo <= conv_std_logic_vector(6889599,28);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(944,24);
manlo <= conv_std_logic_vector(7129222,28);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(960,24);
manlo <= conv_std_logic_vector(7372941,28);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(976,24);
manlo <= conv_std_logic_vector(7620756,28);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(992,24);
manlo <= conv_std_logic_vector(7872667,28);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1008,24);
manlo <= conv_std_logic_vector(8128675,28);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1024,24);
manlo <= conv_std_logic_vector(8388779,28);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1040,24);
manlo <= conv_std_logic_vector(8652979,28);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1056,24);
manlo <= conv_std_logic_vector(8921275,28);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1072,24);
manlo <= conv_std_logic_vector(9193668,28);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1088,24);
manlo <= conv_std_logic_vector(9470157,28);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1104,24);
manlo <= conv_std_logic_vector(9750742,28);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1120,24);
manlo <= conv_std_logic_vector(10035423,28);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1136,24);
manlo <= conv_std_logic_vector(10324201,28);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1152,24);
manlo <= conv_std_logic_vector(10617075,28);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1168,24);
manlo <= conv_std_logic_vector(10914045,28);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1184,24);
manlo <= conv_std_logic_vector(11215112,28);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1200,24);
manlo <= conv_std_logic_vector(11520275,28);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1216,24);
manlo <= conv_std_logic_vector(11829534,28);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1232,24);
manlo <= conv_std_logic_vector(12142889,28);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1248,24);
manlo <= conv_std_logic_vector(12460341,28);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1264,24);
manlo <= conv_std_logic_vector(12781889,28);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1280,24);
manlo <= conv_std_logic_vector(13107533,28);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1296,24);
manlo <= conv_std_logic_vector(13437274,28);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1312,24);
manlo <= conv_std_logic_vector(13771111,28);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1328,24);
manlo <= conv_std_logic_vector(14109044,28);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1344,24);
manlo <= conv_std_logic_vector(14451074,28);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1360,24);
manlo <= conv_std_logic_vector(14797200,28);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1376,24);
manlo <= conv_std_logic_vector(15147422,28);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1392,24);
manlo <= conv_std_logic_vector(15501741,28);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1408,24);
manlo <= conv_std_logic_vector(15860156,28);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1424,24);
manlo <= conv_std_logic_vector(16222667,28);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1440,24);
manlo <= conv_std_logic_vector(16589275,28);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1456,24);
manlo <= conv_std_logic_vector(16959979,28);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1472,24);
manlo <= conv_std_logic_vector(17334779,28);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1488,24);
manlo <= conv_std_logic_vector(17713676,28);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1504,24);
manlo <= conv_std_logic_vector(18096669,28);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1520,24);
manlo <= conv_std_logic_vector(18483758,28);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1536,24);
manlo <= conv_std_logic_vector(18874944,28);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1552,24);
manlo <= conv_std_logic_vector(19270226,28);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1568,24);
manlo <= conv_std_logic_vector(19669605,28);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1584,24);
manlo <= conv_std_logic_vector(20073080,28);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1600,24);
manlo <= conv_std_logic_vector(20480651,28);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1616,24);
manlo <= conv_std_logic_vector(20892319,28);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1632,24);
manlo <= conv_std_logic_vector(21308083,28);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1648,24);
manlo <= conv_std_logic_vector(21727943,28);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1664,24);
manlo <= conv_std_logic_vector(22151900,28);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1680,24);
manlo <= conv_std_logic_vector(22579954,28);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1696,24);
manlo <= conv_std_logic_vector(23012103,28);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1712,24);
manlo <= conv_std_logic_vector(23448350,28);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1728,24);
manlo <= conv_std_logic_vector(23888692,28);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1744,24);
manlo <= conv_std_logic_vector(24333131,28);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1760,24);
manlo <= conv_std_logic_vector(24781667,28);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1776,24);
manlo <= conv_std_logic_vector(25234298,28);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1792,24);
manlo <= conv_std_logic_vector(25691027,28);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1808,24);
manlo <= conv_std_logic_vector(26151851,28);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1824,24);
manlo <= conv_std_logic_vector(26616773,28);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1840,24);
manlo <= conv_std_logic_vector(27085790,28);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(1856,24);
manlo <= conv_std_logic_vector(27558904,28);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(1872,24);
manlo <= conv_std_logic_vector(28036115,28);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(1888,24);
manlo <= conv_std_logic_vector(28517422,28);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(1904,24);
manlo <= conv_std_logic_vector(29002825,28);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(1920,24);
manlo <= conv_std_logic_vector(29492325,28);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(1936,24);
manlo <= conv_std_logic_vector(29985921,28);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(1952,24);
manlo <= conv_std_logic_vector(30483614,28);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(1968,24);
manlo <= conv_std_logic_vector(30985404,28);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1984,24);
manlo <= conv_std_logic_vector(31491289,28);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2000,24);
manlo <= conv_std_logic_vector(32001272,28);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2016,24);
manlo <= conv_std_logic_vector(32515350,28);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2032,24);
manlo <= conv_std_logic_vector(33033526,28);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2048,24);
manlo <= conv_std_logic_vector(33555797,28);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2064,24);
manlo <= conv_std_logic_vector(34082166,28);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2080,24);
manlo <= conv_std_logic_vector(34612630,28);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2096,24);
manlo <= conv_std_logic_vector(35147192,28);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2112,24);
manlo <= conv_std_logic_vector(35685849,28);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2128,24);
manlo <= conv_std_logic_vector(36228604,28);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2144,24);
manlo <= conv_std_logic_vector(36775455,28);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2160,24);
manlo <= conv_std_logic_vector(37326402,28);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2176,24);
manlo <= conv_std_logic_vector(37881446,28);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2192,24);
manlo <= conv_std_logic_vector(38440586,28);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2208,24);
manlo <= conv_std_logic_vector(39003823,28);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2224,24);
manlo <= conv_std_logic_vector(39571157,28);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2240,24);
manlo <= conv_std_logic_vector(40142587,28);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2256,24);
manlo <= conv_std_logic_vector(40718113,28);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2272,24);
manlo <= conv_std_logic_vector(41297736,28);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2288,24);
manlo <= conv_std_logic_vector(41881456,28);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2304,24);
manlo <= conv_std_logic_vector(42469272,28);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2320,24);
manlo <= conv_std_logic_vector(43061185,28);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2336,24);
manlo <= conv_std_logic_vector(43657194,28);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2352,24);
manlo <= conv_std_logic_vector(44257300,28);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2368,24);
manlo <= conv_std_logic_vector(44861503,28);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2384,24);
manlo <= conv_std_logic_vector(45469802,28);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2400,24);
manlo <= conv_std_logic_vector(46082197,28);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2416,24);
manlo <= conv_std_logic_vector(46698690,28);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2432,24);
manlo <= conv_std_logic_vector(47319278,28);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2448,24);
manlo <= conv_std_logic_vector(47943964,28);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2464,24);
manlo <= conv_std_logic_vector(48572746,28);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2480,24);
manlo <= conv_std_logic_vector(49205624,28);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2496,24);
manlo <= conv_std_logic_vector(49842600,28);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2512,24);
manlo <= conv_std_logic_vector(50483672,28);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2528,24);
manlo <= conv_std_logic_vector(51128840,28);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2544,24);
manlo <= conv_std_logic_vector(51778105,28);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2560,24);
manlo <= conv_std_logic_vector(52431467,28);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2576,24);
manlo <= conv_std_logic_vector(53088925,28);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2592,24);
manlo <= conv_std_logic_vector(53750480,28);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2608,24);
manlo <= conv_std_logic_vector(54416132,28);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2624,24);
manlo <= conv_std_logic_vector(55085880,28);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2640,24);
manlo <= conv_std_logic_vector(55759725,28);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2656,24);
manlo <= conv_std_logic_vector(56437666,28);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2672,24);
manlo <= conv_std_logic_vector(57119704,28);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2688,24);
manlo <= conv_std_logic_vector(57805839,28);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2704,24);
manlo <= conv_std_logic_vector(58496071,28);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(2720,24);
manlo <= conv_std_logic_vector(59190399,28);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(2736,24);
manlo <= conv_std_logic_vector(59888823,28);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(2752,24);
manlo <= conv_std_logic_vector(60591345,28);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(2768,24);
manlo <= conv_std_logic_vector(61297963,28);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(2784,24);
manlo <= conv_std_logic_vector(62008678,28);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(2800,24);
manlo <= conv_std_logic_vector(62723489,28);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(2816,24);
manlo <= conv_std_logic_vector(63442397,28);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(2832,24);
manlo <= conv_std_logic_vector(64165402,28);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2848,24);
manlo <= conv_std_logic_vector(64892504,28);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(2864,24);
manlo <= conv_std_logic_vector(65623702,28);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(2880,24);
manlo <= conv_std_logic_vector(66358997,28);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(2896,24);
manlo <= conv_std_logic_vector(67098389,28);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(2912,24);
manlo <= conv_std_logic_vector(67841877,28);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(2928,24);
manlo <= conv_std_logic_vector(68589462,28);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(2944,24);
manlo <= conv_std_logic_vector(69341144,28);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(2960,24);
manlo <= conv_std_logic_vector(70096922,28);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(2976,24);
manlo <= conv_std_logic_vector(70856798,28);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2992,24);
manlo <= conv_std_logic_vector(71620769,28);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3008,24);
manlo <= conv_std_logic_vector(72388838,28);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3024,24);
manlo <= conv_std_logic_vector(73161004,28);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3040,24);
manlo <= conv_std_logic_vector(73937266,28);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3056,24);
manlo <= conv_std_logic_vector(74717625,28);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3072,24);
manlo <= conv_std_logic_vector(75502080,28);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3088,24);
manlo <= conv_std_logic_vector(76290633,28);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3104,24);
manlo <= conv_std_logic_vector(77083282,28);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3120,24);
manlo <= conv_std_logic_vector(77880028,28);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3136,24);
manlo <= conv_std_logic_vector(78680870,28);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3152,24);
manlo <= conv_std_logic_vector(79485810,28);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3168,24);
manlo <= conv_std_logic_vector(80294846,28);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3184,24);
manlo <= conv_std_logic_vector(81107979,28);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3200,24);
manlo <= conv_std_logic_vector(81925209,28);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3216,24);
manlo <= conv_std_logic_vector(82746535,28);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3232,24);
manlo <= conv_std_logic_vector(83571958,28);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3248,24);
manlo <= conv_std_logic_vector(84401479,28);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3264,24);
manlo <= conv_std_logic_vector(85235095,28);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3280,24);
manlo <= conv_std_logic_vector(86072809,28);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3296,24);
manlo <= conv_std_logic_vector(86914620,28);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3312,24);
manlo <= conv_std_logic_vector(87760527,28);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3328,24);
manlo <= conv_std_logic_vector(88610531,28);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3344,24);
manlo <= conv_std_logic_vector(89464632,28);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3360,24);
manlo <= conv_std_logic_vector(90322830,28);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3376,24);
manlo <= conv_std_logic_vector(91185124,28);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3392,24);
manlo <= conv_std_logic_vector(92051516,28);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3408,24);
manlo <= conv_std_logic_vector(92922004,28);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3424,24);
manlo <= conv_std_logic_vector(93796589,28);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3440,24);
manlo <= conv_std_logic_vector(94675271,28);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3456,24);
manlo <= conv_std_logic_vector(95558049,28);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3472,24);
manlo <= conv_std_logic_vector(96444925,28);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3488,24);
manlo <= conv_std_logic_vector(97335897,28);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(3504,24);
manlo <= conv_std_logic_vector(98230967,28);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(3520,24);
manlo <= conv_std_logic_vector(99130133,28);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(3536,24);
manlo <= conv_std_logic_vector(100033396,28);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(3552,24);
manlo <= conv_std_logic_vector(100940755,28);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3568,24);
manlo <= conv_std_logic_vector(101852212,28);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(3584,24);
manlo <= conv_std_logic_vector(102767766,28);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(3600,24);
manlo <= conv_std_logic_vector(103687416,28);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(3616,24);
manlo <= conv_std_logic_vector(104611163,28);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(3632,24);
manlo <= conv_std_logic_vector(105539008,28);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(3648,24);
manlo <= conv_std_logic_vector(106470949,28);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(3664,24);
manlo <= conv_std_logic_vector(107406987,28);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(3680,24);
manlo <= conv_std_logic_vector(108347122,28);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(3696,24);
manlo <= conv_std_logic_vector(109291353,28);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3712,24);
manlo <= conv_std_logic_vector(110239682,28);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(3728,24);
manlo <= conv_std_logic_vector(111192108,28);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(3744,24);
manlo <= conv_std_logic_vector(112148630,28);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(3760,24);
manlo <= conv_std_logic_vector(113109250,28);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(3776,24);
manlo <= conv_std_logic_vector(114073966,28);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(3792,24);
manlo <= conv_std_logic_vector(115042779,28);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(3808,24);
manlo <= conv_std_logic_vector(116015689,28);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(3824,24);
manlo <= conv_std_logic_vector(116992696,28);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(3840,24);
manlo <= conv_std_logic_vector(117973801,28);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(3856,24);
manlo <= conv_std_logic_vector(118959001,28);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(3872,24);
manlo <= conv_std_logic_vector(119948299,28);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(3888,24);
manlo <= conv_std_logic_vector(120941694,28);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(3904,24);
manlo <= conv_std_logic_vector(121939186,28);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(3920,24);
manlo <= conv_std_logic_vector(122940775,28);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(3936,24);
manlo <= conv_std_logic_vector(123946461,28);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(3952,24);
manlo <= conv_std_logic_vector(124956243,28);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(3968,24);
manlo <= conv_std_logic_vector(125970123,28);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(3984,24);
manlo <= conv_std_logic_vector(126988100,28);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4000,24);
manlo <= conv_std_logic_vector(128010173,28);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4016,24);
manlo <= conv_std_logic_vector(129036344,28);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4032,24);
manlo <= conv_std_logic_vector(130066611,28);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4048,24);
manlo <= conv_std_logic_vector(131100976,28);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4064,24);
manlo <= conv_std_logic_vector(132139437,28);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4080,24);
manlo <= conv_std_logic_vector(133181996,28);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4096,24);
manlo <= conv_std_logic_vector(134228651,28);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4112,24);
manlo <= conv_std_logic_vector(135279404,28);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4128,24);
manlo <= conv_std_logic_vector(136334253,28);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4144,24);
manlo <= conv_std_logic_vector(137393200,28);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4160,24);
manlo <= conv_std_logic_vector(138456243,28);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4176,24);
manlo <= conv_std_logic_vector(139523384,28);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4192,24);
manlo <= conv_std_logic_vector(140594622,28);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4208,24);
manlo <= conv_std_logic_vector(141669956,28);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4224,24);
manlo <= conv_std_logic_vector(142749388,28);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4240,24);
manlo <= conv_std_logic_vector(143832916,28);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4256,24);
manlo <= conv_std_logic_vector(144920542,28);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4272,24);
manlo <= conv_std_logic_vector(146012265,28);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4288,24);
manlo <= conv_std_logic_vector(147108085,28);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(4304,24);
manlo <= conv_std_logic_vector(148208001,28);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(4320,24);
manlo <= conv_std_logic_vector(149312015,28);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(4336,24);
manlo <= conv_std_logic_vector(150420126,28);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(4352,24);
manlo <= conv_std_logic_vector(151532334,28);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(4368,24);
manlo <= conv_std_logic_vector(152648639,28);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(4384,24);
manlo <= conv_std_logic_vector(153769041,28);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(4400,24);
manlo <= conv_std_logic_vector(154893541,28);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(4416,24);
manlo <= conv_std_logic_vector(156022137,28);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4432,24);
manlo <= conv_std_logic_vector(157154830,28);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(4448,24);
manlo <= conv_std_logic_vector(158291621,28);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(4464,24);
manlo <= conv_std_logic_vector(159432508,28);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(4480,24);
manlo <= conv_std_logic_vector(160577493,28);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(4496,24);
manlo <= conv_std_logic_vector(161726574,28);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(4512,24);
manlo <= conv_std_logic_vector(162879753,28);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(4528,24);
manlo <= conv_std_logic_vector(164037029,28);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(4544,24);
manlo <= conv_std_logic_vector(165198402,28);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(4560,24);
manlo <= conv_std_logic_vector(166363872,28);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(4576,24);
manlo <= conv_std_logic_vector(167533439,28);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(4592,24);
manlo <= conv_std_logic_vector(168707104,28);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(4608,24);
manlo <= conv_std_logic_vector(169884865,28);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(4624,24);
manlo <= conv_std_logic_vector(171066724,28);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(4640,24);
manlo <= conv_std_logic_vector(172252679,28);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(4656,24);
manlo <= conv_std_logic_vector(173442732,28);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(4672,24);
manlo <= conv_std_logic_vector(174636882,28);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(4688,24);
manlo <= conv_std_logic_vector(175835129,28);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(4704,24);
manlo <= conv_std_logic_vector(177037474,28);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(4720,24);
manlo <= conv_std_logic_vector(178243915,28);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(4736,24);
manlo <= conv_std_logic_vector(179454454,28);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(4752,24);
manlo <= conv_std_logic_vector(180669089,28);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(4768,24);
manlo <= conv_std_logic_vector(181887822,28);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(4784,24);
manlo <= conv_std_logic_vector(183110652,28);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(4800,24);
manlo <= conv_std_logic_vector(184337579,28);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(4816,24);
manlo <= conv_std_logic_vector(185568604,28);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(4832,24);
manlo <= conv_std_logic_vector(186803725,28);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(4848,24);
manlo <= conv_std_logic_vector(188042944,28);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(4864,24);
manlo <= conv_std_logic_vector(189286260,28);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(4880,24);
manlo <= conv_std_logic_vector(190533673,28);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(4896,24);
manlo <= conv_std_logic_vector(191785183,28);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(4912,24);
manlo <= conv_std_logic_vector(193040791,28);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(4928,24);
manlo <= conv_std_logic_vector(194300496,28);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(4944,24);
manlo <= conv_std_logic_vector(195564298,28);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(4960,24);
manlo <= conv_std_logic_vector(196832197,28);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4976,24);
manlo <= conv_std_logic_vector(198104193,28);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(4992,24);
manlo <= conv_std_logic_vector(199380286,28);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5008,24);
manlo <= conv_std_logic_vector(200660477,28);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(5024,24);
manlo <= conv_std_logic_vector(201944765,28);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(5040,24);
manlo <= conv_std_logic_vector(203233150,28);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(5056,24);
manlo <= conv_std_logic_vector(204525633,28);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(5072,24);
manlo <= conv_std_logic_vector(205822213,28);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(5088,24);
manlo <= conv_std_logic_vector(207122889,28);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(5104,24);
manlo <= conv_std_logic_vector(208427664,28);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(5120,24);
manlo <= conv_std_logic_vector(209736535,28);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(5136,24);
manlo <= conv_std_logic_vector(211049504,28);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(5152,24);
manlo <= conv_std_logic_vector(212366570,28);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(5168,24);
manlo <= conv_std_logic_vector(213687733,28);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(5184,24);
manlo <= conv_std_logic_vector(215012993,28);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(5200,24);
manlo <= conv_std_logic_vector(216342351,28);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(5216,24);
manlo <= conv_std_logic_vector(217675806,28);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(5232,24);
manlo <= conv_std_logic_vector(219013358,28);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(5248,24);
manlo <= conv_std_logic_vector(220355007,28);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(5264,24);
manlo <= conv_std_logic_vector(221700754,28);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(5280,24);
manlo <= conv_std_logic_vector(223050598,28);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(5296,24);
manlo <= conv_std_logic_vector(224404540,28);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(5312,24);
manlo <= conv_std_logic_vector(225762578,28);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(5328,24);
manlo <= conv_std_logic_vector(227124714,28);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(5344,24);
manlo <= conv_std_logic_vector(228490948,28);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(5360,24);
manlo <= conv_std_logic_vector(229861278,28);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(5376,24);
manlo <= conv_std_logic_vector(231235706,28);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(5392,24);
manlo <= conv_std_logic_vector(232614231,28);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(5408,24);
manlo <= conv_std_logic_vector(233996854,28);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(5424,24);
manlo <= conv_std_logic_vector(235383573,28);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(5440,24);
manlo <= conv_std_logic_vector(236774391,28);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(5456,24);
manlo <= conv_std_logic_vector(238169305,28);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(5472,24);
manlo <= conv_std_logic_vector(239568317,28);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(5488,24);
manlo <= conv_std_logic_vector(240971426,28);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(5504,24);
manlo <= conv_std_logic_vector(242378633,28);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(5520,24);
manlo <= conv_std_logic_vector(243789936,28);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(5536,24);
manlo <= conv_std_logic_vector(245205338,28);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5552,24);
manlo <= conv_std_logic_vector(246624836,28);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(5568,24);
manlo <= conv_std_logic_vector(248048432,28);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(5584,24);
manlo <= conv_std_logic_vector(249476125,28);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(5600,24);
manlo <= conv_std_logic_vector(250907916,28);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(5616,24);
manlo <= conv_std_logic_vector(252343804,28);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(5632,24);
manlo <= conv_std_logic_vector(253783789,28);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(5648,24);
manlo <= conv_std_logic_vector(255227872,28);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(5664,24);
manlo <= conv_std_logic_vector(256676052,28);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(5680,24);
manlo <= conv_std_logic_vector(258128329,28);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5696,24);
manlo <= conv_std_logic_vector(259584704,28);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(5712,24);
manlo <= conv_std_logic_vector(261045176,28);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(5728,24);
manlo <= conv_std_logic_vector(262509746,28);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(5744,24);
manlo <= conv_std_logic_vector(263978413,28);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(5760,24);
manlo <= conv_std_logic_vector(265451178,28);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(5776,24);
manlo <= conv_std_logic_vector(266928039,28);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(5792,24);
manlo <= conv_std_logic_vector(268408999,28);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(5809,24);
manlo <= conv_std_logic_vector(1458599,28);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(5825,24);
manlo <= conv_std_logic_vector(2947754,28);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5841,24);
manlo <= conv_std_logic_vector(4441005,28);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(5857,24);
manlo <= conv_std_logic_vector(5938354,28);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(5873,24);
manlo <= conv_std_logic_vector(7439800,28);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(5889,24);
manlo <= conv_std_logic_vector(8945344,28);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(5905,24);
manlo <= conv_std_logic_vector(10454985,28);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(5921,24);
manlo <= conv_std_logic_vector(11968724,28);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(5937,24);
manlo <= conv_std_logic_vector(13486560,28);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(5953,24);
manlo <= conv_std_logic_vector(15008494,28);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(5969,24);
manlo <= conv_std_logic_vector(16534525,28);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5985,24);
manlo <= conv_std_logic_vector(18064653,28);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(6001,24);
manlo <= conv_std_logic_vector(19598879,28);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(6017,24);
manlo <= conv_std_logic_vector(21137203,28);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(6033,24);
manlo <= conv_std_logic_vector(22679624,28);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(6049,24);
manlo <= conv_std_logic_vector(24226142,28);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(6065,24);
manlo <= conv_std_logic_vector(25776758,28);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(6081,24);
manlo <= conv_std_logic_vector(27331471,28);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(6097,24);
manlo <= conv_std_logic_vector(28890282,28);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(6113,24);
manlo <= conv_std_logic_vector(30453190,28);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6129,24);
manlo <= conv_std_logic_vector(32020196,28);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(6145,24);
manlo <= conv_std_logic_vector(33591299,28);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(6161,24);
manlo <= conv_std_logic_vector(35166500,28);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(6177,24);
manlo <= conv_std_logic_vector(36745798,28);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(6193,24);
manlo <= conv_std_logic_vector(38329194,28);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(6209,24);
manlo <= conv_std_logic_vector(39916688,28);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(6225,24);
manlo <= conv_std_logic_vector(41508278,28);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(6241,24);
manlo <= conv_std_logic_vector(43103967,28);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(6257,24);
manlo <= conv_std_logic_vector(44703753,28);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6273,24);
manlo <= conv_std_logic_vector(46307636,28);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(6289,24);
manlo <= conv_std_logic_vector(47915617,28);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(6305,24);
manlo <= conv_std_logic_vector(49527695,28);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(6321,24);
manlo <= conv_std_logic_vector(51143871,28);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(6337,24);
manlo <= conv_std_logic_vector(52764145,28);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(6353,24);
manlo <= conv_std_logic_vector(54388516,28);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(6369,24);
manlo <= conv_std_logic_vector(56016985,28);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(6385,24);
manlo <= conv_std_logic_vector(57649551,28);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(6401,24);
manlo <= conv_std_logic_vector(59286215,28);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6417,24);
manlo <= conv_std_logic_vector(60926976,28);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(6433,24);
manlo <= conv_std_logic_vector(62571835,28);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(6449,24);
manlo <= conv_std_logic_vector(64220791,28);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(6465,24);
manlo <= conv_std_logic_vector(65873845,28);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(6481,24);
manlo <= conv_std_logic_vector(67530997,28);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(6497,24);
manlo <= conv_std_logic_vector(69192246,28);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(6513,24);
manlo <= conv_std_logic_vector(70857593,28);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(6529,24);
manlo <= conv_std_logic_vector(72527037,28);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(6545,24);
manlo <= conv_std_logic_vector(74200579,28);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6561,24);
manlo <= conv_std_logic_vector(75878219,28);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(6577,24);
manlo <= conv_std_logic_vector(77559956,28);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(6593,24);
manlo <= conv_std_logic_vector(79245791,28);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(6609,24);
manlo <= conv_std_logic_vector(80935723,28);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(6625,24);
manlo <= conv_std_logic_vector(82629753,28);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(6641,24);
manlo <= conv_std_logic_vector(84327881,28);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(6657,24);
manlo <= conv_std_logic_vector(86030106,28);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(6673,24);
manlo <= conv_std_logic_vector(87736429,28);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(6689,24);
manlo <= conv_std_logic_vector(89446849,28);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(6705,24);
manlo <= conv_std_logic_vector(91161367,28);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(6721,24);
manlo <= conv_std_logic_vector(92879983,28);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(6737,24);
manlo <= conv_std_logic_vector(94602697,28);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(6753,24);
manlo <= conv_std_logic_vector(96329508,28);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(6769,24);
manlo <= conv_std_logic_vector(98060416,28);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(6785,24);
manlo <= conv_std_logic_vector(99795423,28);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(6801,24);
manlo <= conv_std_logic_vector(101534527,28);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(6817,24);
manlo <= conv_std_logic_vector(103277728,28);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(6833,24);
manlo <= conv_std_logic_vector(105025028,28);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(6849,24);
manlo <= conv_std_logic_vector(106776425,28);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(6865,24);
manlo <= conv_std_logic_vector(108531919,28);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(6881,24);
manlo <= conv_std_logic_vector(110291512,28);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(6897,24);
manlo <= conv_std_logic_vector(112055202,28);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(6913,24);
manlo <= conv_std_logic_vector(113822989,28);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(6929,24);
manlo <= conv_std_logic_vector(115594875,28);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(6945,24);
manlo <= conv_std_logic_vector(117370858,28);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(6961,24);
manlo <= conv_std_logic_vector(119150939,28);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(6977,24);
manlo <= conv_std_logic_vector(120935117,28);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(6993,24);
manlo <= conv_std_logic_vector(122723393,28);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(7009,24);
manlo <= conv_std_logic_vector(124515767,28);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(7025,24);
manlo <= conv_std_logic_vector(126312239,28);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(7041,24);
manlo <= conv_std_logic_vector(128112808,28);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(7057,24);
manlo <= conv_std_logic_vector(129917475,28);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(7073,24);
manlo <= conv_std_logic_vector(131726240,28);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(7089,24);
manlo <= conv_std_logic_vector(133539102,28);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(7105,24);
manlo <= conv_std_logic_vector(135356063,28);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(7121,24);
manlo <= conv_std_logic_vector(137177121,28);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7137,24);
manlo <= conv_std_logic_vector(139002276,28);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(7153,24);
manlo <= conv_std_logic_vector(140831530,28);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(7169,24);
manlo <= conv_std_logic_vector(142664881,28);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(7185,24);
manlo <= conv_std_logic_vector(144502330,28);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(7201,24);
manlo <= conv_std_logic_vector(146343877,28);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(7217,24);
manlo <= conv_std_logic_vector(148189521,28);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(7233,24);
manlo <= conv_std_logic_vector(150039263,28);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(7249,24);
manlo <= conv_std_logic_vector(151893103,28);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(7265,24);
manlo <= conv_std_logic_vector(153751041,28);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(7281,24);
manlo <= conv_std_logic_vector(155613076,28);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(7297,24);
manlo <= conv_std_logic_vector(157479210,28);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(7313,24);
manlo <= conv_std_logic_vector(159349441,28);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(7329,24);
manlo <= conv_std_logic_vector(161223770,28);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(7345,24);
manlo <= conv_std_logic_vector(163102196,28);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(7361,24);
manlo <= conv_std_logic_vector(164984721,28);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(7377,24);
manlo <= conv_std_logic_vector(166871343,28);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(7393,24);
manlo <= conv_std_logic_vector(168762063,28);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(7409,24);
manlo <= conv_std_logic_vector(170656881,28);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(7425,24);
manlo <= conv_std_logic_vector(172555797,28);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(7441,24);
manlo <= conv_std_logic_vector(174458810,28);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(7457,24);
manlo <= conv_std_logic_vector(176365921,28);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(7473,24);
manlo <= conv_std_logic_vector(178277130,28);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(7489,24);
manlo <= conv_std_logic_vector(180192437,28);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(7505,24);
manlo <= conv_std_logic_vector(182111842,28);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(7521,24);
manlo <= conv_std_logic_vector(184035345,28);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(7537,24);
manlo <= conv_std_logic_vector(185962945,28);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(7553,24);
manlo <= conv_std_logic_vector(187894643,28);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(7569,24);
manlo <= conv_std_logic_vector(189830439,28);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(7585,24);
manlo <= conv_std_logic_vector(191770333,28);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(7601,24);
manlo <= conv_std_logic_vector(193714325,28);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(7617,24);
manlo <= conv_std_logic_vector(195662415,28);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(7633,24);
manlo <= conv_std_logic_vector(197614602,28);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(7649,24);
manlo <= conv_std_logic_vector(199570888,28);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(7665,24);
manlo <= conv_std_logic_vector(201531271,28);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7681,24);
manlo <= conv_std_logic_vector(203495752,28);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(7697,24);
manlo <= conv_std_logic_vector(205464331,28);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(7713,24);
manlo <= conv_std_logic_vector(207437008,28);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(7729,24);
manlo <= conv_std_logic_vector(209413783,28);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(7745,24);
manlo <= conv_std_logic_vector(211394656,28);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(7761,24);
manlo <= conv_std_logic_vector(213379626,28);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(7777,24);
manlo <= conv_std_logic_vector(215368695,28);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(7793,24);
manlo <= conv_std_logic_vector(217361861,28);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(7809,24);
manlo <= conv_std_logic_vector(219359125,28);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7825,24);
manlo <= conv_std_logic_vector(221360487,28);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(7841,24);
manlo <= conv_std_logic_vector(223365947,28);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(7857,24);
manlo <= conv_std_logic_vector(225375505,28);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(7873,24);
manlo <= conv_std_logic_vector(227389161,28);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(7889,24);
manlo <= conv_std_logic_vector(229406915,28);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(7905,24);
manlo <= conv_std_logic_vector(231428767,28);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(7921,24);
manlo <= conv_std_logic_vector(233454716,28);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(7937,24);
manlo <= conv_std_logic_vector(235484764,28);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(7953,24);
manlo <= conv_std_logic_vector(237518910,28);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7969,24);
manlo <= conv_std_logic_vector(239557153,28);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(7985,24);
manlo <= conv_std_logic_vector(241599495,28);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(8001,24);
manlo <= conv_std_logic_vector(243645934,28);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(8017,24);
manlo <= conv_std_logic_vector(245696471,28);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(8033,24);
manlo <= conv_std_logic_vector(247751107,28);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(8049,24);
manlo <= conv_std_logic_vector(249809840,28);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(8065,24);
manlo <= conv_std_logic_vector(251872671,28);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(8081,24);
manlo <= conv_std_logic_vector(253939600,28);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(8097,24);
manlo <= conv_std_logic_vector(256010627,28);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(8113,24);
manlo <= conv_std_logic_vector(258085753,28);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(8129,24);
manlo <= conv_std_logic_vector(260164976,28);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(8145,24);
manlo <= conv_std_logic_vector(262248297,28);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(8161,24);
manlo <= conv_std_logic_vector(264335716,28);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(8177,24);
manlo <= conv_std_logic_vector(266427233,28);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(8194,24);
manlo <= conv_std_logic_vector(87392,28);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(8210,24);
manlo <= conv_std_logic_vector(2187105,28);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(8226,24);
manlo <= conv_std_logic_vector(4290916,28);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(8242,24);
manlo <= conv_std_logic_vector(6398825,28);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8258,24);
manlo <= conv_std_logic_vector(8510832,28);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(8274,24);
manlo <= conv_std_logic_vector(10626938,28);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(8290,24);
manlo <= conv_std_logic_vector(12747141,28);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(8306,24);
manlo <= conv_std_logic_vector(14871442,28);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(8322,24);
manlo <= conv_std_logic_vector(16999841,28);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(8338,24);
manlo <= conv_std_logic_vector(19132338,28);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(8354,24);
manlo <= conv_std_logic_vector(21268934,28);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(8370,24);
manlo <= conv_std_logic_vector(23409627,28);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(8386,24);
manlo <= conv_std_logic_vector(25554418,28);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8402,24);
manlo <= conv_std_logic_vector(27703308,28);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(8418,24);
manlo <= conv_std_logic_vector(29856295,28);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(8434,24);
manlo <= conv_std_logic_vector(32013381,28);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(8450,24);
manlo <= conv_std_logic_vector(34174564,28);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(8466,24);
manlo <= conv_std_logic_vector(36339846,28);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(8482,24);
manlo <= conv_std_logic_vector(38509225,28);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(8498,24);
manlo <= conv_std_logic_vector(40682703,28);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(8514,24);
manlo <= conv_std_logic_vector(42860279,28);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(8530,24);
manlo <= conv_std_logic_vector(45041953,28);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8546,24);
manlo <= conv_std_logic_vector(47227725,28);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(8562,24);
manlo <= conv_std_logic_vector(49417595,28);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(8578,24);
manlo <= conv_std_logic_vector(51611563,28);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(8594,24);
manlo <= conv_std_logic_vector(53809629,28);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(8610,24);
manlo <= conv_std_logic_vector(56011794,28);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(8626,24);
manlo <= conv_std_logic_vector(58218056,28);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(8642,24);
manlo <= conv_std_logic_vector(60428417,28);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(8658,24);
manlo <= conv_std_logic_vector(62642876,28);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(8674,24);
manlo <= conv_std_logic_vector(64861432,28);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8690,24);
manlo <= conv_std_logic_vector(67084087,28);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(8706,24);
manlo <= conv_std_logic_vector(69310840,28);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(8722,24);
manlo <= conv_std_logic_vector(71541691,28);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(8738,24);
manlo <= conv_std_logic_vector(73776641,28);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(8754,24);
manlo <= conv_std_logic_vector(76015688,28);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(8770,24);
manlo <= conv_std_logic_vector(78258834,28);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(8786,24);
manlo <= conv_std_logic_vector(80506077,28);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(8802,24);
manlo <= conv_std_logic_vector(82757419,28);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(8818,24);
manlo <= conv_std_logic_vector(85012859,28);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(8834,24);
manlo <= conv_std_logic_vector(87272397,28);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(8850,24);
manlo <= conv_std_logic_vector(89536034,28);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(8866,24);
manlo <= conv_std_logic_vector(91803768,28);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(8882,24);
manlo <= conv_std_logic_vector(94075601,28);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(8898,24);
manlo <= conv_std_logic_vector(96351532,28);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(8914,24);
manlo <= conv_std_logic_vector(98631561,28);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(8930,24);
manlo <= conv_std_logic_vector(100915688,28);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(8946,24);
manlo <= conv_std_logic_vector(103203913,28);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(8962,24);
manlo <= conv_std_logic_vector(105496237,28);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(8978,24);
manlo <= conv_std_logic_vector(107792658,28);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(8994,24);
manlo <= conv_std_logic_vector(110093178,28);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(9010,24);
manlo <= conv_std_logic_vector(112397796,28);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(9026,24);
manlo <= conv_std_logic_vector(114706513,28);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(9042,24);
manlo <= conv_std_logic_vector(117019327,28);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(9058,24);
manlo <= conv_std_logic_vector(119336240,28);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(9074,24);
manlo <= conv_std_logic_vector(121657251,28);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(9090,24);
manlo <= conv_std_logic_vector(123982360,28);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(9106,24);
manlo <= conv_std_logic_vector(126311567,28);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9122,24);
manlo <= conv_std_logic_vector(128644873,28);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(9138,24);
manlo <= conv_std_logic_vector(130982277,28);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(9154,24);
manlo <= conv_std_logic_vector(133323779,28);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(9170,24);
manlo <= conv_std_logic_vector(135669379,28);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(9186,24);
manlo <= conv_std_logic_vector(138019077,28);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(9202,24);
manlo <= conv_std_logic_vector(140372874,28);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(9218,24);
manlo <= conv_std_logic_vector(142730769,28);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(9234,24);
manlo <= conv_std_logic_vector(145092762,28);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(9250,24);
manlo <= conv_std_logic_vector(147458854,28);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(9266,24);
manlo <= conv_std_logic_vector(149829044,28);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(9282,24);
manlo <= conv_std_logic_vector(152203332,28);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(9298,24);
manlo <= conv_std_logic_vector(154581718,28);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(9314,24);
manlo <= conv_std_logic_vector(156964202,28);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(9330,24);
manlo <= conv_std_logic_vector(159350785,28);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(9346,24);
manlo <= conv_std_logic_vector(161741466,28);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(9362,24);
manlo <= conv_std_logic_vector(164136246,28);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(9378,24);
manlo <= conv_std_logic_vector(166535123,28);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(9394,24);
manlo <= conv_std_logic_vector(168938099,28);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(9410,24);
manlo <= conv_std_logic_vector(171345174,28);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(9426,24);
manlo <= conv_std_logic_vector(173756346,28);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(9442,24);
manlo <= conv_std_logic_vector(176171617,28);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(9458,24);
manlo <= conv_std_logic_vector(178590986,28);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(9474,24);
manlo <= conv_std_logic_vector(181014454,28);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(9490,24);
manlo <= conv_std_logic_vector(183442020,28);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(9506,24);
manlo <= conv_std_logic_vector(185873684,28);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(9522,24);
manlo <= conv_std_logic_vector(188309446,28);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(9538,24);
manlo <= conv_std_logic_vector(190749307,28);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(9554,24);
manlo <= conv_std_logic_vector(193193266,28);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(9570,24);
manlo <= conv_std_logic_vector(195641323,28);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(9586,24);
manlo <= conv_std_logic_vector(198093479,28);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(9602,24);
manlo <= conv_std_logic_vector(200549733,28);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(9618,24);
manlo <= conv_std_logic_vector(203010086,28);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(9634,24);
manlo <= conv_std_logic_vector(205474536,28);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(9650,24);
manlo <= conv_std_logic_vector(207943085,28);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(9666,24);
manlo <= conv_std_logic_vector(210415733,28);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(9682,24);
manlo <= conv_std_logic_vector(212892479,28);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(9698,24);
manlo <= conv_std_logic_vector(215373323,28);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(9714,24);
manlo <= conv_std_logic_vector(217858266,28);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(9730,24);
manlo <= conv_std_logic_vector(220347307,28);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(9746,24);
manlo <= conv_std_logic_vector(222840446,28);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(9762,24);
manlo <= conv_std_logic_vector(225337684,28);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(9778,24);
manlo <= conv_std_logic_vector(227839020,28);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(9794,24);
manlo <= conv_std_logic_vector(230344454,28);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9810,24);
manlo <= conv_std_logic_vector(232853987,28);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(9826,24);
manlo <= conv_std_logic_vector(235367618,28);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(9842,24);
manlo <= conv_std_logic_vector(237885348,28);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(9858,24);
manlo <= conv_std_logic_vector(240407176,28);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(9874,24);
manlo <= conv_std_logic_vector(242933102,28);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(9890,24);
manlo <= conv_std_logic_vector(245463127,28);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(9906,24);
manlo <= conv_std_logic_vector(247997251,28);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(9922,24);
manlo <= conv_std_logic_vector(250535472,28);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(9938,24);
manlo <= conv_std_logic_vector(253077793,28);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9954,24);
manlo <= conv_std_logic_vector(255624211,28);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(9970,24);
manlo <= conv_std_logic_vector(258174728,28);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(9986,24);
manlo <= conv_std_logic_vector(260729344,28);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(10002,24);
manlo <= conv_std_logic_vector(263288057,28);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(10018,24);
manlo <= conv_std_logic_vector(265850870,28);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(10034,24);
manlo <= conv_std_logic_vector(268417780,28);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(10051,24);
manlo <= conv_std_logic_vector(2553334,28);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(10067,24);
manlo <= conv_std_logic_vector(5128441,28);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(10083,24);
manlo <= conv_std_logic_vector(7707647,28);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(10099,24);
manlo <= conv_std_logic_vector(10290952,28);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(10115,24);
manlo <= conv_std_logic_vector(12878355,28);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(10131,24);
manlo <= conv_std_logic_vector(15469857,28);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(10147,24);
manlo <= conv_std_logic_vector(18065457,28);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(10163,24);
manlo <= conv_std_logic_vector(20665155,28);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(10179,24);
manlo <= conv_std_logic_vector(23268952,28);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(10195,24);
manlo <= conv_std_logic_vector(25876847,28);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(10211,24);
manlo <= conv_std_logic_vector(28488841,28);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(10227,24);
manlo <= conv_std_logic_vector(31104934,28);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10243,24);
manlo <= conv_std_logic_vector(33725125,28);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(10259,24);
manlo <= conv_std_logic_vector(36349414,28);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(10275,24);
manlo <= conv_std_logic_vector(38977802,28);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(10291,24);
manlo <= conv_std_logic_vector(41610288,28);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(10307,24);
manlo <= conv_std_logic_vector(44246873,28);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(10323,24);
manlo <= conv_std_logic_vector(46887557,28);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(10339,24);
manlo <= conv_std_logic_vector(49532339,28);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(10355,24);
manlo <= conv_std_logic_vector(52181219,28);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(10371,24);
manlo <= conv_std_logic_vector(54834198,28);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10387,24);
manlo <= conv_std_logic_vector(57491276,28);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(10403,24);
manlo <= conv_std_logic_vector(60152452,28);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(10419,24);
manlo <= conv_std_logic_vector(62817727,28);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(10435,24);
manlo <= conv_std_logic_vector(65487100,28);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(10451,24);
manlo <= conv_std_logic_vector(68160572,28);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(10467,24);
manlo <= conv_std_logic_vector(70838142,28);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(10483,24);
manlo <= conv_std_logic_vector(73519811,28);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(10499,24);
manlo <= conv_std_logic_vector(76205578,28);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(10515,24);
manlo <= conv_std_logic_vector(78895444,28);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10531,24);
manlo <= conv_std_logic_vector(81589409,28);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(10547,24);
manlo <= conv_std_logic_vector(84287472,28);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(10563,24);
manlo <= conv_std_logic_vector(86989633,28);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(10579,24);
manlo <= conv_std_logic_vector(89695894,28);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(10595,24);
manlo <= conv_std_logic_vector(92406252,28);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(10611,24);
manlo <= conv_std_logic_vector(95120710,28);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(10627,24);
manlo <= conv_std_logic_vector(97839266,28);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(10643,24);
manlo <= conv_std_logic_vector(100561920,28);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(10659,24);
manlo <= conv_std_logic_vector(103288674,28);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10675,24);
manlo <= conv_std_logic_vector(106019525,28);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(10691,24);
manlo <= conv_std_logic_vector(108754476,28);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(10707,24);
manlo <= conv_std_logic_vector(111493525,28);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(10723,24);
manlo <= conv_std_logic_vector(114236673,28);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(10739,24);
manlo <= conv_std_logic_vector(116983919,28);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(10755,24);
manlo <= conv_std_logic_vector(119735264,28);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(10771,24);
manlo <= conv_std_logic_vector(122490707,28);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(10787,24);
manlo <= conv_std_logic_vector(125250249,28);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(10803,24);
manlo <= conv_std_logic_vector(128013890,28);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(10819,24);
manlo <= conv_std_logic_vector(130781629,28);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(10835,24);
manlo <= conv_std_logic_vector(133553468,28);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(10851,24);
manlo <= conv_std_logic_vector(136329404,28);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(10867,24);
manlo <= conv_std_logic_vector(139109440,28);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(10883,24);
manlo <= conv_std_logic_vector(141893574,28);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(10899,24);
manlo <= conv_std_logic_vector(144681806,28);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(10915,24);
manlo <= conv_std_logic_vector(147474137,28);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(10931,24);
manlo <= conv_std_logic_vector(150270567,28);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(10947,24);
manlo <= conv_std_logic_vector(153071096,28);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(10963,24);
manlo <= conv_std_logic_vector(155875723,28);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(10979,24);
manlo <= conv_std_logic_vector(158684449,28);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(10995,24);
manlo <= conv_std_logic_vector(161497274,28);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(11011,24);
manlo <= conv_std_logic_vector(164314197,28);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(11027,24);
manlo <= conv_std_logic_vector(167135219,28);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(11043,24);
manlo <= conv_std_logic_vector(169960340,28);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(11059,24);
manlo <= conv_std_logic_vector(172789560,28);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(11075,24);
manlo <= conv_std_logic_vector(175622878,28);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(11091,24);
manlo <= conv_std_logic_vector(178460295,28);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11107,24);
manlo <= conv_std_logic_vector(181301810,28);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(11123,24);
manlo <= conv_std_logic_vector(184147424,28);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(11139,24);
manlo <= conv_std_logic_vector(186997137,28);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(11155,24);
manlo <= conv_std_logic_vector(189850949,28);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(11171,24);
manlo <= conv_std_logic_vector(192708860,28);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(11187,24);
manlo <= conv_std_logic_vector(195570869,28);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(11203,24);
manlo <= conv_std_logic_vector(198436977,28);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(11219,24);
manlo <= conv_std_logic_vector(201307183,28);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(11235,24);
manlo <= conv_std_logic_vector(204181489,28);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(11251,24);
manlo <= conv_std_logic_vector(207059893,28);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(11267,24);
manlo <= conv_std_logic_vector(209942395,28);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(11283,24);
manlo <= conv_std_logic_vector(212828997,28);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(11299,24);
manlo <= conv_std_logic_vector(215719697,28);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(11315,24);
manlo <= conv_std_logic_vector(218614497,28);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(11331,24);
manlo <= conv_std_logic_vector(221513394,28);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(11347,24);
manlo <= conv_std_logic_vector(224416391,28);
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(11363,24);
manlo <= conv_std_logic_vector(227323486,28);
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(11379,24);
manlo <= conv_std_logic_vector(230234681,28);
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(11395,24);
manlo <= conv_std_logic_vector(233149974,28);
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(11411,24);
manlo <= conv_std_logic_vector(236069365,28);
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(11427,24);
manlo <= conv_std_logic_vector(238992856,28);
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(11443,24);
manlo <= conv_std_logic_vector(241920445,28);
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(11459,24);
manlo <= conv_std_logic_vector(244852133,28);
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(11475,24);
manlo <= conv_std_logic_vector(247787920,28);
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(11491,24);
manlo <= conv_std_logic_vector(250727806,28);
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(11507,24);
manlo <= conv_std_logic_vector(253671790,28);
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(11523,24);
manlo <= conv_std_logic_vector(256619874,28);
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(11539,24);
manlo <= conv_std_logic_vector(259572056,28);
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(11555,24);
manlo <= conv_std_logic_vector(262528337,28);
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(11571,24);
manlo <= conv_std_logic_vector(265488717,28);
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(11588,24);
manlo <= conv_std_logic_vector(17739,28);
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(11604,24);
manlo <= conv_std_logic_vector(2986317,28);
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(11620,24);
manlo <= conv_std_logic_vector(5958993,28);
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(11636,24);
manlo <= conv_std_logic_vector(8935768,28);
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(11652,24);
manlo <= conv_std_logic_vector(11916642,28);
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(11668,24);
manlo <= conv_std_logic_vector(14901615,28);
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(11684,24);
manlo <= conv_std_logic_vector(17890686,28);
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(11700,24);
manlo <= conv_std_logic_vector(20883857,28);
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(11716,24);
manlo <= conv_std_logic_vector(23881126,28);
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(11732,24);
manlo <= conv_std_logic_vector(26882494,28);
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(11748,24);
manlo <= conv_std_logic_vector(29887961,28);
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(11764,24);
manlo <= conv_std_logic_vector(32897527,28);
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(11780,24);
manlo <= conv_std_logic_vector(35911192,28);
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(11796,24);
manlo <= conv_std_logic_vector(38928956,28);
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(11812,24);
manlo <= conv_std_logic_vector(41950818,28);
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(11828,24);
manlo <= conv_std_logic_vector(44976780,28);
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(11844,24);
manlo <= conv_std_logic_vector(48006840,28);
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(11860,24);
manlo <= conv_std_logic_vector(51040999,28);
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(11876,24);
manlo <= conv_std_logic_vector(54079258,28);
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(11892,24);
manlo <= conv_std_logic_vector(57121615,28);
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(11908,24);
manlo <= conv_std_logic_vector(60168071,28);
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(11924,24);
manlo <= conv_std_logic_vector(63218625,28);
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(11940,24);
manlo <= conv_std_logic_vector(66273279,28);
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(11956,24);
manlo <= conv_std_logic_vector(69332032,28);
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(11972,24);
manlo <= conv_std_logic_vector(72394883,28);
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(11988,24);
manlo <= conv_std_logic_vector(75461834,28);
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(12004,24);
manlo <= conv_std_logic_vector(78532883,28);
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(12020,24);
manlo <= conv_std_logic_vector(81608032,28);
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(12036,24);
manlo <= conv_std_logic_vector(84687279,28);
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(12052,24);
manlo <= conv_std_logic_vector(87770625,28);
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(12068,24);
manlo <= conv_std_logic_vector(90858070,28);
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(12084,24);
manlo <= conv_std_logic_vector(93949615,28);
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(12100,24);
manlo <= conv_std_logic_vector(97045258,28);
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(12116,24);
manlo <= conv_std_logic_vector(100145000,28);
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(12132,24);
manlo <= conv_std_logic_vector(103248841,28);
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(12148,24);
manlo <= conv_std_logic_vector(106356781,28);
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(12164,24);
manlo <= conv_std_logic_vector(109468819,28);
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(12180,24);
manlo <= conv_std_logic_vector(112584957,28);
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(12196,24);
manlo <= conv_std_logic_vector(115705194,28);
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(12212,24);
manlo <= conv_std_logic_vector(118829530,28);
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(12228,24);
manlo <= conv_std_logic_vector(121957965,28);
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(12244,24);
manlo <= conv_std_logic_vector(125090499,28);
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(12260,24);
manlo <= conv_std_logic_vector(128227131,28);
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(12276,24);
manlo <= conv_std_logic_vector(131367863,28);
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(12292,24);
manlo <= conv_std_logic_vector(134512694,28);
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(12308,24);
manlo <= conv_std_logic_vector(137661624,28);
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(12324,24);
manlo <= conv_std_logic_vector(140814653,28);
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(12340,24);
manlo <= conv_std_logic_vector(143971780,28);
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(12356,24);
manlo <= conv_std_logic_vector(147133007,28);
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(12372,24);
manlo <= conv_std_logic_vector(150298333,28);
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(12388,24);
manlo <= conv_std_logic_vector(153467758,28);
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(12404,24);
manlo <= conv_std_logic_vector(156641282,28);
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(12420,24);
manlo <= conv_std_logic_vector(159818905,28);
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(12436,24);
manlo <= conv_std_logic_vector(163000627,28);
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(12452,24);
manlo <= conv_std_logic_vector(166186448,28);
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(12468,24);
manlo <= conv_std_logic_vector(169376368,28);
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(12484,24);
manlo <= conv_std_logic_vector(172570387,28);
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(12500,24);
manlo <= conv_std_logic_vector(175768505,28);
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(12516,24);
manlo <= conv_std_logic_vector(178970722,28);
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(12532,24);
manlo <= conv_std_logic_vector(182177038,28);
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(12548,24);
manlo <= conv_std_logic_vector(185387453,28);
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(12564,24);
manlo <= conv_std_logic_vector(188601968,28);
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(12580,24);
manlo <= conv_std_logic_vector(191820581,28);
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(12596,24);
manlo <= conv_std_logic_vector(195043294,28);
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(12612,24);
manlo <= conv_std_logic_vector(198270105,28);
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(12628,24);
manlo <= conv_std_logic_vector(201501016,28);
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(12644,24);
manlo <= conv_std_logic_vector(204736025,28);
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(12660,24);
manlo <= conv_std_logic_vector(207975134,28);
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(12676,24);
manlo <= conv_std_logic_vector(211218342,28);
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(12692,24);
manlo <= conv_std_logic_vector(214465649,28);
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(12708,24);
manlo <= conv_std_logic_vector(217717055,28);
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(12724,24);
manlo <= conv_std_logic_vector(220972560,28);
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(12740,24);
manlo <= conv_std_logic_vector(224232165,28);
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(12756,24);
manlo <= conv_std_logic_vector(227495868,28);
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(12772,24);
manlo <= conv_std_logic_vector(230763671,28);
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(12788,24);
manlo <= conv_std_logic_vector(234035572,28);
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(12804,24);
manlo <= conv_std_logic_vector(237311573,28);
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(12820,24);
manlo <= conv_std_logic_vector(240591673,28);
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(12836,24);
manlo <= conv_std_logic_vector(243875872,28);
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(12852,24);
manlo <= conv_std_logic_vector(247164170,28);
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(12868,24);
manlo <= conv_std_logic_vector(250456567,28);
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(12884,24);
manlo <= conv_std_logic_vector(253753064,28);
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(12900,24);
manlo <= conv_std_logic_vector(257053659,28);
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(12916,24);
manlo <= conv_std_logic_vector(260358354,28);
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(12932,24);
manlo <= conv_std_logic_vector(263667148,28);
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(12948,24);
manlo <= conv_std_logic_vector(266980041,28);
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(12965,24);
manlo <= conv_std_logic_vector(1861577,28);
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(12981,24);
manlo <= conv_std_logic_vector(5182668,28);
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(12997,24);
manlo <= conv_std_logic_vector(8507859,28);
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(13013,24);
manlo <= conv_std_logic_vector(11837149,28);
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(13029,24);
manlo <= conv_std_logic_vector(15170538,28);
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(13045,24);
manlo <= conv_std_logic_vector(18508026,28);
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(13061,24);
manlo <= conv_std_logic_vector(21849613,28);
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(13077,24);
manlo <= conv_std_logic_vector(25195299,28);
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(13093,24);
manlo <= conv_std_logic_vector(28545085,28);
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(13109,24);
manlo <= conv_std_logic_vector(31898970,28);
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(13125,24);
manlo <= conv_std_logic_vector(35256954,28);
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(13141,24);
manlo <= conv_std_logic_vector(38619037,28);
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(13157,24);
manlo <= conv_std_logic_vector(41985219,28);
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(13173,24);
manlo <= conv_std_logic_vector(45355501,28);
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(13189,24);
manlo <= conv_std_logic_vector(48729882,28);
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(13205,24);
manlo <= conv_std_logic_vector(52108362,28);
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(13221,24);
manlo <= conv_std_logic_vector(55490941,28);
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(13237,24);
manlo <= conv_std_logic_vector(58877620,28);
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(13253,24);
manlo <= conv_std_logic_vector(62268398,28);
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(13269,24);
manlo <= conv_std_logic_vector(65663275,28);
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(13285,24);
manlo <= conv_std_logic_vector(69062251,28);
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(13301,24);
manlo <= conv_std_logic_vector(72465326,28);
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(13317,24);
manlo <= conv_std_logic_vector(75872501,28);
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(13333,24);
manlo <= conv_std_logic_vector(79283775,28);
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(13349,24);
manlo <= conv_std_logic_vector(82699148,28);
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(13365,24);
manlo <= conv_std_logic_vector(86118621,28);
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(13381,24);
manlo <= conv_std_logic_vector(89542193,28);
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(13397,24);
manlo <= conv_std_logic_vector(92969864,28);
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(13413,24);
manlo <= conv_std_logic_vector(96401634,28);
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(13429,24);
manlo <= conv_std_logic_vector(99837503,28);
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(13445,24);
manlo <= conv_std_logic_vector(103277472,28);
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(13461,24);
manlo <= conv_std_logic_vector(106721540,28);
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(13477,24);
manlo <= conv_std_logic_vector(110169708,28);
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(13493,24);
manlo <= conv_std_logic_vector(113621975,28);
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(13509,24);
manlo <= conv_std_logic_vector(117078341,28);
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(13525,24);
manlo <= conv_std_logic_vector(120538806,28);
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(13541,24);
manlo <= conv_std_logic_vector(124003370,28);
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(13557,24);
manlo <= conv_std_logic_vector(127472034,28);
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(13573,24);
manlo <= conv_std_logic_vector(130944798,28);
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(13589,24);
manlo <= conv_std_logic_vector(134421660,28);
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(13605,24);
manlo <= conv_std_logic_vector(137902622,28);
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(13621,24);
manlo <= conv_std_logic_vector(141387683,28);
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(13637,24);
manlo <= conv_std_logic_vector(144876844,28);
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(13653,24);
manlo <= conv_std_logic_vector(148370104,28);
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(13669,24);
manlo <= conv_std_logic_vector(151867463,28);
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(13685,24);
manlo <= conv_std_logic_vector(155368921,28);
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(13701,24);
manlo <= conv_std_logic_vector(158874479,28);
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(13717,24);
manlo <= conv_std_logic_vector(162384136,28);
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(13733,24);
manlo <= conv_std_logic_vector(165897893,28);
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(13749,24);
manlo <= conv_std_logic_vector(169415749,28);
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(13765,24);
manlo <= conv_std_logic_vector(172937704,28);
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(13781,24);
manlo <= conv_std_logic_vector(176463758,28);
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(13797,24);
manlo <= conv_std_logic_vector(179993912,28);
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(13813,24);
manlo <= conv_std_logic_vector(183528166,28);
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(13829,24);
manlo <= conv_std_logic_vector(187066519,28);
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(13845,24);
manlo <= conv_std_logic_vector(190608971,28);
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(13861,24);
manlo <= conv_std_logic_vector(194155522,28);
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(13877,24);
manlo <= conv_std_logic_vector(197706173,28);
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(13893,24);
manlo <= conv_std_logic_vector(201260923,28);
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(13909,24);
manlo <= conv_std_logic_vector(204819773,28);
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(13925,24);
manlo <= conv_std_logic_vector(208382722,28);
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(13941,24);
manlo <= conv_std_logic_vector(211949770,28);
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(13957,24);
manlo <= conv_std_logic_vector(215520918,28);
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(13973,24);
manlo <= conv_std_logic_vector(219096165,28);
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(13989,24);
manlo <= conv_std_logic_vector(222675512,28);
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(14005,24);
manlo <= conv_std_logic_vector(226258958,28);
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(14021,24);
manlo <= conv_std_logic_vector(229846504,28);
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(14037,24);
manlo <= conv_std_logic_vector(233438148,28);
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(14053,24);
manlo <= conv_std_logic_vector(237033893,28);
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(14069,24);
manlo <= conv_std_logic_vector(240633737,28);
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(14085,24);
manlo <= conv_std_logic_vector(244237680,28);
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(14101,24);
manlo <= conv_std_logic_vector(247845722,28);
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(14117,24);
manlo <= conv_std_logic_vector(251457864,28);
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(14133,24);
manlo <= conv_std_logic_vector(255074106,28);
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(14149,24);
manlo <= conv_std_logic_vector(258694447,28);
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(14165,24);
manlo <= conv_std_logic_vector(262318887,28);
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(14181,24);
manlo <= conv_std_logic_vector(265947427,28);
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(14198,24);
manlo <= conv_std_logic_vector(1144611,28);
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(14214,24);
manlo <= conv_std_logic_vector(4781350,28);
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(14230,24);
manlo <= conv_std_logic_vector(8422188,28);
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(14246,24);
manlo <= conv_std_logic_vector(12067126,28);
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(14262,24);
manlo <= conv_std_logic_vector(15716163,28);
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(14278,24);
manlo <= conv_std_logic_vector(19369300,28);
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(14294,24);
manlo <= conv_std_logic_vector(23026536,28);
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(14310,24);
manlo <= conv_std_logic_vector(26687871,28);
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(14326,24);
manlo <= conv_std_logic_vector(30353307,28);
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(14342,24);
manlo <= conv_std_logic_vector(34022841,28);
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(14358,24);
manlo <= conv_std_logic_vector(37696476,28);
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(14374,24);
manlo <= conv_std_logic_vector(41374209,28);
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(14390,24);
manlo <= conv_std_logic_vector(45056043,28);
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(14406,24);
manlo <= conv_std_logic_vector(48741975,28);
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(14422,24);
manlo <= conv_std_logic_vector(52432007,28);
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(14438,24);
manlo <= conv_std_logic_vector(56126139,28);
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(14454,24);
manlo <= conv_std_logic_vector(59824371,28);
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(14470,24);
manlo <= conv_std_logic_vector(63526701,28);
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(14486,24);
manlo <= conv_std_logic_vector(67233132,28);
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(14502,24);
manlo <= conv_std_logic_vector(70943662,28);
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(14518,24);
manlo <= conv_std_logic_vector(74658291,28);
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(14534,24);
manlo <= conv_std_logic_vector(78377020,28);
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(14550,24);
manlo <= conv_std_logic_vector(82099849,28);
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(14566,24);
manlo <= conv_std_logic_vector(85826777,28);
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(14582,24);
manlo <= conv_std_logic_vector(89557804,28);
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(14598,24);
manlo <= conv_std_logic_vector(93292931,28);
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(14614,24);
manlo <= conv_std_logic_vector(97032158,28);
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(14630,24);
manlo <= conv_std_logic_vector(100775484,28);
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(14646,24);
manlo <= conv_std_logic_vector(104522910,28);
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(14662,24);
manlo <= conv_std_logic_vector(108274436,28);
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(14678,24);
manlo <= conv_std_logic_vector(112030061,28);
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(14694,24);
manlo <= conv_std_logic_vector(115789786,28);
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(14710,24);
manlo <= conv_std_logic_vector(119553610,28);
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(14726,24);
manlo <= conv_std_logic_vector(123321534,28);
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(14742,24);
manlo <= conv_std_logic_vector(127093557,28);
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(14758,24);
manlo <= conv_std_logic_vector(130869680,28);
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(14774,24);
manlo <= conv_std_logic_vector(134649903,28);
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(14790,24);
manlo <= conv_std_logic_vector(138434225,28);
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(14806,24);
manlo <= conv_std_logic_vector(142222647,28);
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(14822,24);
manlo <= conv_std_logic_vector(146015168,28);
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(14838,24);
manlo <= conv_std_logic_vector(149811789,28);
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(14854,24);
manlo <= conv_std_logic_vector(153612510,28);
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(14870,24);
manlo <= conv_std_logic_vector(157417330,28);
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(14886,24);
manlo <= conv_std_logic_vector(161226250,28);
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(14902,24);
manlo <= conv_std_logic_vector(165039270,28);
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(14918,24);
manlo <= conv_std_logic_vector(168856389,28);
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(14934,24);
manlo <= conv_std_logic_vector(172677608,28);
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(14950,24);
manlo <= conv_std_logic_vector(176502926,28);
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(14966,24);
manlo <= conv_std_logic_vector(180332344,28);
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(14982,24);
manlo <= conv_std_logic_vector(184165862,28);
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(14998,24);
manlo <= conv_std_logic_vector(188003480,28);
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(15014,24);
manlo <= conv_std_logic_vector(191845197,28);
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(15030,24);
manlo <= conv_std_logic_vector(195691014,28);
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(15046,24);
manlo <= conv_std_logic_vector(199540930,28);
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(15062,24);
manlo <= conv_std_logic_vector(203394946,28);
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(15078,24);
manlo <= conv_std_logic_vector(207253062,28);
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(15094,24);
manlo <= conv_std_logic_vector(211115277,28);
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(15110,24);
manlo <= conv_std_logic_vector(214981593,28);
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(15126,24);
manlo <= conv_std_logic_vector(218852007,28);
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(15142,24);
manlo <= conv_std_logic_vector(222726522,28);
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(15158,24);
manlo <= conv_std_logic_vector(226605136,28);
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(15174,24);
manlo <= conv_std_logic_vector(230487850,28);
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(15190,24);
manlo <= conv_std_logic_vector(234374664,28);
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(15206,24);
manlo <= conv_std_logic_vector(238265577,28);
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(15222,24);
manlo <= conv_std_logic_vector(242160590,28);
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(15238,24);
manlo <= conv_std_logic_vector(246059703,28);
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(15254,24);
manlo <= conv_std_logic_vector(249962916,28);
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(15270,24);
manlo <= conv_std_logic_vector(253870228,28);
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(15286,24);
manlo <= conv_std_logic_vector(257781640,28);
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(15302,24);
manlo <= conv_std_logic_vector(261697152,28);
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(15318,24);
manlo <= conv_std_logic_vector(265616763,28);
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(15335,24);
manlo <= conv_std_logic_vector(1105018,28);
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(15351,24);
manlo <= conv_std_logic_vector(5032829,28);
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(15367,24);
manlo <= conv_std_logic_vector(8964740,28);
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(15383,24);
manlo <= conv_std_logic_vector(12900750,28);
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(15399,24);
manlo <= conv_std_logic_vector(16840860,28);
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(15415,24);
manlo <= conv_std_logic_vector(20785070,28);
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(15431,24);
manlo <= conv_std_logic_vector(24733380,28);
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(15447,24);
manlo <= conv_std_logic_vector(28685790,28);
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(15463,24);
manlo <= conv_std_logic_vector(32642299,28);
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(15479,24);
manlo <= conv_std_logic_vector(36602908,28);
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(15495,24);
manlo <= conv_std_logic_vector(40567617,28);
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(15511,24);
manlo <= conv_std_logic_vector(44536425,28);
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(15527,24);
manlo <= conv_std_logic_vector(48509334,28);
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(15543,24);
manlo <= conv_std_logic_vector(52486342,28);
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(15559,24);
manlo <= conv_std_logic_vector(56467450,28);
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(15575,24);
manlo <= conv_std_logic_vector(60452657,28);
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(15591,24);
manlo <= conv_std_logic_vector(64441965,28);
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(15607,24);
manlo <= conv_std_logic_vector(68435372,28);
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(15623,24);
manlo <= conv_std_logic_vector(72432880,28);
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(15639,24);
manlo <= conv_std_logic_vector(76434487,28);
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(15655,24);
manlo <= conv_std_logic_vector(80440193,28);
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(15671,24);
manlo <= conv_std_logic_vector(84450000,28);
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(15687,24);
manlo <= conv_std_logic_vector(88463906,28);
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(15703,24);
manlo <= conv_std_logic_vector(92481913,28);
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(15719,24);
manlo <= conv_std_logic_vector(96504019,28);
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(15735,24);
manlo <= conv_std_logic_vector(100530225,28);
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(15751,24);
manlo <= conv_std_logic_vector(104560531,28);
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(15767,24);
manlo <= conv_std_logic_vector(108594936,28);
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(15783,24);
manlo <= conv_std_logic_vector(112633442,28);
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(15799,24);
manlo <= conv_std_logic_vector(116676047,28);
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(15815,24);
manlo <= conv_std_logic_vector(120722752,28);
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(15831,24);
manlo <= conv_std_logic_vector(124773557,28);
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(15847,24);
manlo <= conv_std_logic_vector(128828462,28);
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(15863,24);
manlo <= conv_std_logic_vector(132887467,28);
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(15879,24);
manlo <= conv_std_logic_vector(136950572,28);
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(15895,24);
manlo <= conv_std_logic_vector(141017776,28);
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(15911,24);
manlo <= conv_std_logic_vector(145089081,28);
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(15927,24);
manlo <= conv_std_logic_vector(149164485,28);
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(15943,24);
manlo <= conv_std_logic_vector(153243989,28);
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(15959,24);
manlo <= conv_std_logic_vector(157327593,28);
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(15975,24);
manlo <= conv_std_logic_vector(161415297,28);
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(15991,24);
manlo <= conv_std_logic_vector(165507101,28);
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(16007,24);
manlo <= conv_std_logic_vector(169603005,28);
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(16023,24);
manlo <= conv_std_logic_vector(173703009,28);
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(16039,24);
manlo <= conv_std_logic_vector(177807112,28);
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(16055,24);
manlo <= conv_std_logic_vector(181915316,28);
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(16071,24);
manlo <= conv_std_logic_vector(186027619,28);
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(16087,24);
manlo <= conv_std_logic_vector(190144023,28);
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(16103,24);
manlo <= conv_std_logic_vector(194264526,28);
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(16119,24);
manlo <= conv_std_logic_vector(198389129,28);
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(16135,24);
manlo <= conv_std_logic_vector(202517832,28);
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(16151,24);
manlo <= conv_std_logic_vector(206650635,28);
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(16167,24);
manlo <= conv_std_logic_vector(210787538,28);
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(16183,24);
manlo <= conv_std_logic_vector(214928541,28);
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(16199,24);
manlo <= conv_std_logic_vector(219073644,28);
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(16215,24);
manlo <= conv_std_logic_vector(223222847,28);
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(16231,24);
manlo <= conv_std_logic_vector(227376150,28);
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(16247,24);
manlo <= conv_std_logic_vector(231533553,28);
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(16263,24);
manlo <= conv_std_logic_vector(235695056,28);
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(16279,24);
manlo <= conv_std_logic_vector(239860659,28);
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(16295,24);
manlo <= conv_std_logic_vector(244030361,28);
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(16311,24);
manlo <= conv_std_logic_vector(248204164,28);
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(16327,24);
manlo <= conv_std_logic_vector(252382067,28);
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(16343,24);
manlo <= conv_std_logic_vector(256564069,28);
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(16359,24);
manlo <= conv_std_logic_vector(260750172,28);
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(16375,24);
manlo <= conv_std_logic_vector(264940375,28);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT20.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut20 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
END dp_explut20;
ARCHITECTURE rtl OF dp_explut20 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16,24);
manlo <= conv_std_logic_vector(2048,28);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32,24);
manlo <= conv_std_logic_vector(8192,28);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(48,24);
manlo <= conv_std_logic_vector(18432,28);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(64,24);
manlo <= conv_std_logic_vector(32768,28);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(80,24);
manlo <= conv_std_logic_vector(51200,28);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(96,24);
manlo <= conv_std_logic_vector(73728,28);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(112,24);
manlo <= conv_std_logic_vector(100352,28);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(128,24);
manlo <= conv_std_logic_vector(131072,28);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(144,24);
manlo <= conv_std_logic_vector(165888,28);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(160,24);
manlo <= conv_std_logic_vector(204801,28);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(176,24);
manlo <= conv_std_logic_vector(247809,28);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(192,24);
manlo <= conv_std_logic_vector(294913,28);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(208,24);
manlo <= conv_std_logic_vector(346113,28);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(224,24);
manlo <= conv_std_logic_vector(401410,28);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(240,24);
manlo <= conv_std_logic_vector(460802,28);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(256,24);
manlo <= conv_std_logic_vector(524291,28);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(272,24);
manlo <= conv_std_logic_vector(591875,28);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(288,24);
manlo <= conv_std_logic_vector(663556,28);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(304,24);
manlo <= conv_std_logic_vector(739332,28);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(320,24);
manlo <= conv_std_logic_vector(819205,28);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(336,24);
manlo <= conv_std_logic_vector(903174,28);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(352,24);
manlo <= conv_std_logic_vector(991239,28);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(368,24);
manlo <= conv_std_logic_vector(1083400,28);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(384,24);
manlo <= conv_std_logic_vector(1179657,28);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(400,24);
manlo <= conv_std_logic_vector(1280010,28);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(416,24);
manlo <= conv_std_logic_vector(1384459,28);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(432,24);
manlo <= conv_std_logic_vector(1493005,28);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(448,24);
manlo <= conv_std_logic_vector(1605646,28);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(464,24);
manlo <= conv_std_logic_vector(1722384,28);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(480,24);
manlo <= conv_std_logic_vector(1843218,28);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(496,24);
manlo <= conv_std_logic_vector(1968147,28);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(512,24);
manlo <= conv_std_logic_vector(2097173,28);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(528,24);
manlo <= conv_std_logic_vector(2230295,28);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(544,24);
manlo <= conv_std_logic_vector(2367514,28);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(560,24);
manlo <= conv_std_logic_vector(2508828,28);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(576,24);
manlo <= conv_std_logic_vector(2654238,28);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(592,24);
manlo <= conv_std_logic_vector(2803745,28);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(608,24);
manlo <= conv_std_logic_vector(2957348,28);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(624,24);
manlo <= conv_std_logic_vector(3115047,28);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(640,24);
manlo <= conv_std_logic_vector(3276842,28);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(656,24);
manlo <= conv_std_logic_vector(3442733,28);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(672,24);
manlo <= conv_std_logic_vector(3612720,28);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(688,24);
manlo <= conv_std_logic_vector(3786804,28);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(704,24);
manlo <= conv_std_logic_vector(3964983,28);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(720,24);
manlo <= conv_std_logic_vector(4147259,28);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(736,24);
manlo <= conv_std_logic_vector(4333631,28);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(752,24);
manlo <= conv_std_logic_vector(4524100,28);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(768,24);
manlo <= conv_std_logic_vector(4718664,28);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(784,24);
manlo <= conv_std_logic_vector(4917325,28);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(800,24);
manlo <= conv_std_logic_vector(5120081,28);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(816,24);
manlo <= conv_std_logic_vector(5326934,28);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(832,24);
manlo <= conv_std_logic_vector(5537884,28);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(848,24);
manlo <= conv_std_logic_vector(5752929,28);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(864,24);
manlo <= conv_std_logic_vector(5972071,28);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(880,24);
manlo <= conv_std_logic_vector(6195308,28);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(896,24);
manlo <= conv_std_logic_vector(6422642,28);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(912,24);
manlo <= conv_std_logic_vector(6654073,28);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(928,24);
manlo <= conv_std_logic_vector(6889599,28);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(944,24);
manlo <= conv_std_logic_vector(7129222,28);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(960,24);
manlo <= conv_std_logic_vector(7372941,28);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(976,24);
manlo <= conv_std_logic_vector(7620756,28);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(992,24);
manlo <= conv_std_logic_vector(7872667,28);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1008,24);
manlo <= conv_std_logic_vector(8128675,28);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1024,24);
manlo <= conv_std_logic_vector(8388779,28);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1040,24);
manlo <= conv_std_logic_vector(8652979,28);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1056,24);
manlo <= conv_std_logic_vector(8921275,28);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1072,24);
manlo <= conv_std_logic_vector(9193668,28);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1088,24);
manlo <= conv_std_logic_vector(9470157,28);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1104,24);
manlo <= conv_std_logic_vector(9750742,28);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1120,24);
manlo <= conv_std_logic_vector(10035423,28);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1136,24);
manlo <= conv_std_logic_vector(10324201,28);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1152,24);
manlo <= conv_std_logic_vector(10617075,28);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1168,24);
manlo <= conv_std_logic_vector(10914045,28);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1184,24);
manlo <= conv_std_logic_vector(11215112,28);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1200,24);
manlo <= conv_std_logic_vector(11520275,28);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1216,24);
manlo <= conv_std_logic_vector(11829534,28);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1232,24);
manlo <= conv_std_logic_vector(12142889,28);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1248,24);
manlo <= conv_std_logic_vector(12460341,28);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1264,24);
manlo <= conv_std_logic_vector(12781889,28);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1280,24);
manlo <= conv_std_logic_vector(13107533,28);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1296,24);
manlo <= conv_std_logic_vector(13437274,28);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1312,24);
manlo <= conv_std_logic_vector(13771111,28);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1328,24);
manlo <= conv_std_logic_vector(14109044,28);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1344,24);
manlo <= conv_std_logic_vector(14451074,28);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1360,24);
manlo <= conv_std_logic_vector(14797200,28);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1376,24);
manlo <= conv_std_logic_vector(15147422,28);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1392,24);
manlo <= conv_std_logic_vector(15501741,28);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1408,24);
manlo <= conv_std_logic_vector(15860156,28);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1424,24);
manlo <= conv_std_logic_vector(16222667,28);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1440,24);
manlo <= conv_std_logic_vector(16589275,28);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1456,24);
manlo <= conv_std_logic_vector(16959979,28);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1472,24);
manlo <= conv_std_logic_vector(17334779,28);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1488,24);
manlo <= conv_std_logic_vector(17713676,28);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1504,24);
manlo <= conv_std_logic_vector(18096669,28);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1520,24);
manlo <= conv_std_logic_vector(18483758,28);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1536,24);
manlo <= conv_std_logic_vector(18874944,28);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1552,24);
manlo <= conv_std_logic_vector(19270226,28);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1568,24);
manlo <= conv_std_logic_vector(19669605,28);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1584,24);
manlo <= conv_std_logic_vector(20073080,28);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1600,24);
manlo <= conv_std_logic_vector(20480651,28);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1616,24);
manlo <= conv_std_logic_vector(20892319,28);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1632,24);
manlo <= conv_std_logic_vector(21308083,28);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1648,24);
manlo <= conv_std_logic_vector(21727943,28);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1664,24);
manlo <= conv_std_logic_vector(22151900,28);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1680,24);
manlo <= conv_std_logic_vector(22579954,28);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1696,24);
manlo <= conv_std_logic_vector(23012103,28);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1712,24);
manlo <= conv_std_logic_vector(23448350,28);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1728,24);
manlo <= conv_std_logic_vector(23888692,28);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1744,24);
manlo <= conv_std_logic_vector(24333131,28);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1760,24);
manlo <= conv_std_logic_vector(24781667,28);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1776,24);
manlo <= conv_std_logic_vector(25234298,28);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1792,24);
manlo <= conv_std_logic_vector(25691027,28);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1808,24);
manlo <= conv_std_logic_vector(26151851,28);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1824,24);
manlo <= conv_std_logic_vector(26616773,28);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1840,24);
manlo <= conv_std_logic_vector(27085790,28);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(1856,24);
manlo <= conv_std_logic_vector(27558904,28);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(1872,24);
manlo <= conv_std_logic_vector(28036115,28);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(1888,24);
manlo <= conv_std_logic_vector(28517422,28);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(1904,24);
manlo <= conv_std_logic_vector(29002825,28);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(1920,24);
manlo <= conv_std_logic_vector(29492325,28);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(1936,24);
manlo <= conv_std_logic_vector(29985921,28);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(1952,24);
manlo <= conv_std_logic_vector(30483614,28);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(1968,24);
manlo <= conv_std_logic_vector(30985404,28);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1984,24);
manlo <= conv_std_logic_vector(31491289,28);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2000,24);
manlo <= conv_std_logic_vector(32001272,28);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2016,24);
manlo <= conv_std_logic_vector(32515350,28);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2032,24);
manlo <= conv_std_logic_vector(33033526,28);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2048,24);
manlo <= conv_std_logic_vector(33555797,28);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2064,24);
manlo <= conv_std_logic_vector(34082166,28);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2080,24);
manlo <= conv_std_logic_vector(34612630,28);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2096,24);
manlo <= conv_std_logic_vector(35147192,28);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2112,24);
manlo <= conv_std_logic_vector(35685849,28);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2128,24);
manlo <= conv_std_logic_vector(36228604,28);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2144,24);
manlo <= conv_std_logic_vector(36775455,28);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2160,24);
manlo <= conv_std_logic_vector(37326402,28);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2176,24);
manlo <= conv_std_logic_vector(37881446,28);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2192,24);
manlo <= conv_std_logic_vector(38440586,28);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2208,24);
manlo <= conv_std_logic_vector(39003823,28);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2224,24);
manlo <= conv_std_logic_vector(39571157,28);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2240,24);
manlo <= conv_std_logic_vector(40142587,28);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2256,24);
manlo <= conv_std_logic_vector(40718113,28);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2272,24);
manlo <= conv_std_logic_vector(41297736,28);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2288,24);
manlo <= conv_std_logic_vector(41881456,28);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2304,24);
manlo <= conv_std_logic_vector(42469272,28);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2320,24);
manlo <= conv_std_logic_vector(43061185,28);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2336,24);
manlo <= conv_std_logic_vector(43657194,28);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2352,24);
manlo <= conv_std_logic_vector(44257300,28);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2368,24);
manlo <= conv_std_logic_vector(44861503,28);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2384,24);
manlo <= conv_std_logic_vector(45469802,28);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2400,24);
manlo <= conv_std_logic_vector(46082197,28);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2416,24);
manlo <= conv_std_logic_vector(46698690,28);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2432,24);
manlo <= conv_std_logic_vector(47319278,28);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2448,24);
manlo <= conv_std_logic_vector(47943964,28);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2464,24);
manlo <= conv_std_logic_vector(48572746,28);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2480,24);
manlo <= conv_std_logic_vector(49205624,28);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2496,24);
manlo <= conv_std_logic_vector(49842600,28);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2512,24);
manlo <= conv_std_logic_vector(50483672,28);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2528,24);
manlo <= conv_std_logic_vector(51128840,28);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2544,24);
manlo <= conv_std_logic_vector(51778105,28);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2560,24);
manlo <= conv_std_logic_vector(52431467,28);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2576,24);
manlo <= conv_std_logic_vector(53088925,28);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2592,24);
manlo <= conv_std_logic_vector(53750480,28);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2608,24);
manlo <= conv_std_logic_vector(54416132,28);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2624,24);
manlo <= conv_std_logic_vector(55085880,28);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2640,24);
manlo <= conv_std_logic_vector(55759725,28);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2656,24);
manlo <= conv_std_logic_vector(56437666,28);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2672,24);
manlo <= conv_std_logic_vector(57119704,28);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2688,24);
manlo <= conv_std_logic_vector(57805839,28);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2704,24);
manlo <= conv_std_logic_vector(58496071,28);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(2720,24);
manlo <= conv_std_logic_vector(59190399,28);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(2736,24);
manlo <= conv_std_logic_vector(59888823,28);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(2752,24);
manlo <= conv_std_logic_vector(60591345,28);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(2768,24);
manlo <= conv_std_logic_vector(61297963,28);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(2784,24);
manlo <= conv_std_logic_vector(62008678,28);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(2800,24);
manlo <= conv_std_logic_vector(62723489,28);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(2816,24);
manlo <= conv_std_logic_vector(63442397,28);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(2832,24);
manlo <= conv_std_logic_vector(64165402,28);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2848,24);
manlo <= conv_std_logic_vector(64892504,28);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(2864,24);
manlo <= conv_std_logic_vector(65623702,28);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(2880,24);
manlo <= conv_std_logic_vector(66358997,28);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(2896,24);
manlo <= conv_std_logic_vector(67098389,28);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(2912,24);
manlo <= conv_std_logic_vector(67841877,28);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(2928,24);
manlo <= conv_std_logic_vector(68589462,28);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(2944,24);
manlo <= conv_std_logic_vector(69341144,28);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(2960,24);
manlo <= conv_std_logic_vector(70096922,28);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(2976,24);
manlo <= conv_std_logic_vector(70856798,28);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2992,24);
manlo <= conv_std_logic_vector(71620769,28);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3008,24);
manlo <= conv_std_logic_vector(72388838,28);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3024,24);
manlo <= conv_std_logic_vector(73161004,28);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3040,24);
manlo <= conv_std_logic_vector(73937266,28);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3056,24);
manlo <= conv_std_logic_vector(74717625,28);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3072,24);
manlo <= conv_std_logic_vector(75502080,28);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3088,24);
manlo <= conv_std_logic_vector(76290633,28);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3104,24);
manlo <= conv_std_logic_vector(77083282,28);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3120,24);
manlo <= conv_std_logic_vector(77880028,28);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3136,24);
manlo <= conv_std_logic_vector(78680870,28);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3152,24);
manlo <= conv_std_logic_vector(79485810,28);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3168,24);
manlo <= conv_std_logic_vector(80294846,28);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3184,24);
manlo <= conv_std_logic_vector(81107979,28);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3200,24);
manlo <= conv_std_logic_vector(81925209,28);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3216,24);
manlo <= conv_std_logic_vector(82746535,28);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3232,24);
manlo <= conv_std_logic_vector(83571958,28);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3248,24);
manlo <= conv_std_logic_vector(84401479,28);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3264,24);
manlo <= conv_std_logic_vector(85235095,28);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3280,24);
manlo <= conv_std_logic_vector(86072809,28);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3296,24);
manlo <= conv_std_logic_vector(86914620,28);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3312,24);
manlo <= conv_std_logic_vector(87760527,28);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3328,24);
manlo <= conv_std_logic_vector(88610531,28);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3344,24);
manlo <= conv_std_logic_vector(89464632,28);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3360,24);
manlo <= conv_std_logic_vector(90322830,28);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3376,24);
manlo <= conv_std_logic_vector(91185124,28);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3392,24);
manlo <= conv_std_logic_vector(92051516,28);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3408,24);
manlo <= conv_std_logic_vector(92922004,28);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3424,24);
manlo <= conv_std_logic_vector(93796589,28);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3440,24);
manlo <= conv_std_logic_vector(94675271,28);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3456,24);
manlo <= conv_std_logic_vector(95558049,28);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3472,24);
manlo <= conv_std_logic_vector(96444925,28);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3488,24);
manlo <= conv_std_logic_vector(97335897,28);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(3504,24);
manlo <= conv_std_logic_vector(98230967,28);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(3520,24);
manlo <= conv_std_logic_vector(99130133,28);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(3536,24);
manlo <= conv_std_logic_vector(100033396,28);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(3552,24);
manlo <= conv_std_logic_vector(100940755,28);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3568,24);
manlo <= conv_std_logic_vector(101852212,28);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(3584,24);
manlo <= conv_std_logic_vector(102767766,28);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(3600,24);
manlo <= conv_std_logic_vector(103687416,28);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(3616,24);
manlo <= conv_std_logic_vector(104611163,28);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(3632,24);
manlo <= conv_std_logic_vector(105539008,28);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(3648,24);
manlo <= conv_std_logic_vector(106470949,28);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(3664,24);
manlo <= conv_std_logic_vector(107406987,28);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(3680,24);
manlo <= conv_std_logic_vector(108347122,28);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(3696,24);
manlo <= conv_std_logic_vector(109291353,28);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3712,24);
manlo <= conv_std_logic_vector(110239682,28);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(3728,24);
manlo <= conv_std_logic_vector(111192108,28);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(3744,24);
manlo <= conv_std_logic_vector(112148630,28);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(3760,24);
manlo <= conv_std_logic_vector(113109250,28);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(3776,24);
manlo <= conv_std_logic_vector(114073966,28);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(3792,24);
manlo <= conv_std_logic_vector(115042779,28);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(3808,24);
manlo <= conv_std_logic_vector(116015689,28);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(3824,24);
manlo <= conv_std_logic_vector(116992696,28);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(3840,24);
manlo <= conv_std_logic_vector(117973801,28);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(3856,24);
manlo <= conv_std_logic_vector(118959001,28);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(3872,24);
manlo <= conv_std_logic_vector(119948299,28);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(3888,24);
manlo <= conv_std_logic_vector(120941694,28);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(3904,24);
manlo <= conv_std_logic_vector(121939186,28);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(3920,24);
manlo <= conv_std_logic_vector(122940775,28);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(3936,24);
manlo <= conv_std_logic_vector(123946461,28);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(3952,24);
manlo <= conv_std_logic_vector(124956243,28);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(3968,24);
manlo <= conv_std_logic_vector(125970123,28);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(3984,24);
manlo <= conv_std_logic_vector(126988100,28);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4000,24);
manlo <= conv_std_logic_vector(128010173,28);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4016,24);
manlo <= conv_std_logic_vector(129036344,28);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4032,24);
manlo <= conv_std_logic_vector(130066611,28);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4048,24);
manlo <= conv_std_logic_vector(131100976,28);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4064,24);
manlo <= conv_std_logic_vector(132139437,28);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4080,24);
manlo <= conv_std_logic_vector(133181996,28);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4096,24);
manlo <= conv_std_logic_vector(134228651,28);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4112,24);
manlo <= conv_std_logic_vector(135279404,28);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4128,24);
manlo <= conv_std_logic_vector(136334253,28);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4144,24);
manlo <= conv_std_logic_vector(137393200,28);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4160,24);
manlo <= conv_std_logic_vector(138456243,28);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4176,24);
manlo <= conv_std_logic_vector(139523384,28);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4192,24);
manlo <= conv_std_logic_vector(140594622,28);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4208,24);
manlo <= conv_std_logic_vector(141669956,28);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4224,24);
manlo <= conv_std_logic_vector(142749388,28);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4240,24);
manlo <= conv_std_logic_vector(143832916,28);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4256,24);
manlo <= conv_std_logic_vector(144920542,28);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4272,24);
manlo <= conv_std_logic_vector(146012265,28);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4288,24);
manlo <= conv_std_logic_vector(147108085,28);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(4304,24);
manlo <= conv_std_logic_vector(148208001,28);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(4320,24);
manlo <= conv_std_logic_vector(149312015,28);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(4336,24);
manlo <= conv_std_logic_vector(150420126,28);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(4352,24);
manlo <= conv_std_logic_vector(151532334,28);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(4368,24);
manlo <= conv_std_logic_vector(152648639,28);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(4384,24);
manlo <= conv_std_logic_vector(153769041,28);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(4400,24);
manlo <= conv_std_logic_vector(154893541,28);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(4416,24);
manlo <= conv_std_logic_vector(156022137,28);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4432,24);
manlo <= conv_std_logic_vector(157154830,28);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(4448,24);
manlo <= conv_std_logic_vector(158291621,28);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(4464,24);
manlo <= conv_std_logic_vector(159432508,28);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(4480,24);
manlo <= conv_std_logic_vector(160577493,28);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(4496,24);
manlo <= conv_std_logic_vector(161726574,28);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(4512,24);
manlo <= conv_std_logic_vector(162879753,28);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(4528,24);
manlo <= conv_std_logic_vector(164037029,28);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(4544,24);
manlo <= conv_std_logic_vector(165198402,28);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(4560,24);
manlo <= conv_std_logic_vector(166363872,28);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(4576,24);
manlo <= conv_std_logic_vector(167533439,28);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(4592,24);
manlo <= conv_std_logic_vector(168707104,28);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(4608,24);
manlo <= conv_std_logic_vector(169884865,28);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(4624,24);
manlo <= conv_std_logic_vector(171066724,28);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(4640,24);
manlo <= conv_std_logic_vector(172252679,28);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(4656,24);
manlo <= conv_std_logic_vector(173442732,28);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(4672,24);
manlo <= conv_std_logic_vector(174636882,28);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(4688,24);
manlo <= conv_std_logic_vector(175835129,28);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(4704,24);
manlo <= conv_std_logic_vector(177037474,28);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(4720,24);
manlo <= conv_std_logic_vector(178243915,28);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(4736,24);
manlo <= conv_std_logic_vector(179454454,28);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(4752,24);
manlo <= conv_std_logic_vector(180669089,28);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(4768,24);
manlo <= conv_std_logic_vector(181887822,28);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(4784,24);
manlo <= conv_std_logic_vector(183110652,28);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(4800,24);
manlo <= conv_std_logic_vector(184337579,28);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(4816,24);
manlo <= conv_std_logic_vector(185568604,28);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(4832,24);
manlo <= conv_std_logic_vector(186803725,28);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(4848,24);
manlo <= conv_std_logic_vector(188042944,28);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(4864,24);
manlo <= conv_std_logic_vector(189286260,28);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(4880,24);
manlo <= conv_std_logic_vector(190533673,28);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(4896,24);
manlo <= conv_std_logic_vector(191785183,28);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(4912,24);
manlo <= conv_std_logic_vector(193040791,28);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(4928,24);
manlo <= conv_std_logic_vector(194300496,28);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(4944,24);
manlo <= conv_std_logic_vector(195564298,28);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(4960,24);
manlo <= conv_std_logic_vector(196832197,28);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4976,24);
manlo <= conv_std_logic_vector(198104193,28);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(4992,24);
manlo <= conv_std_logic_vector(199380286,28);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5008,24);
manlo <= conv_std_logic_vector(200660477,28);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(5024,24);
manlo <= conv_std_logic_vector(201944765,28);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(5040,24);
manlo <= conv_std_logic_vector(203233150,28);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(5056,24);
manlo <= conv_std_logic_vector(204525633,28);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(5072,24);
manlo <= conv_std_logic_vector(205822213,28);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(5088,24);
manlo <= conv_std_logic_vector(207122889,28);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(5104,24);
manlo <= conv_std_logic_vector(208427664,28);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(5120,24);
manlo <= conv_std_logic_vector(209736535,28);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(5136,24);
manlo <= conv_std_logic_vector(211049504,28);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(5152,24);
manlo <= conv_std_logic_vector(212366570,28);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(5168,24);
manlo <= conv_std_logic_vector(213687733,28);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(5184,24);
manlo <= conv_std_logic_vector(215012993,28);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(5200,24);
manlo <= conv_std_logic_vector(216342351,28);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(5216,24);
manlo <= conv_std_logic_vector(217675806,28);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(5232,24);
manlo <= conv_std_logic_vector(219013358,28);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(5248,24);
manlo <= conv_std_logic_vector(220355007,28);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(5264,24);
manlo <= conv_std_logic_vector(221700754,28);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(5280,24);
manlo <= conv_std_logic_vector(223050598,28);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(5296,24);
manlo <= conv_std_logic_vector(224404540,28);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(5312,24);
manlo <= conv_std_logic_vector(225762578,28);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(5328,24);
manlo <= conv_std_logic_vector(227124714,28);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(5344,24);
manlo <= conv_std_logic_vector(228490948,28);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(5360,24);
manlo <= conv_std_logic_vector(229861278,28);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(5376,24);
manlo <= conv_std_logic_vector(231235706,28);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(5392,24);
manlo <= conv_std_logic_vector(232614231,28);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(5408,24);
manlo <= conv_std_logic_vector(233996854,28);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(5424,24);
manlo <= conv_std_logic_vector(235383573,28);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(5440,24);
manlo <= conv_std_logic_vector(236774391,28);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(5456,24);
manlo <= conv_std_logic_vector(238169305,28);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(5472,24);
manlo <= conv_std_logic_vector(239568317,28);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(5488,24);
manlo <= conv_std_logic_vector(240971426,28);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(5504,24);
manlo <= conv_std_logic_vector(242378633,28);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(5520,24);
manlo <= conv_std_logic_vector(243789936,28);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(5536,24);
manlo <= conv_std_logic_vector(245205338,28);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5552,24);
manlo <= conv_std_logic_vector(246624836,28);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(5568,24);
manlo <= conv_std_logic_vector(248048432,28);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(5584,24);
manlo <= conv_std_logic_vector(249476125,28);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(5600,24);
manlo <= conv_std_logic_vector(250907916,28);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(5616,24);
manlo <= conv_std_logic_vector(252343804,28);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(5632,24);
manlo <= conv_std_logic_vector(253783789,28);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(5648,24);
manlo <= conv_std_logic_vector(255227872,28);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(5664,24);
manlo <= conv_std_logic_vector(256676052,28);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(5680,24);
manlo <= conv_std_logic_vector(258128329,28);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5696,24);
manlo <= conv_std_logic_vector(259584704,28);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(5712,24);
manlo <= conv_std_logic_vector(261045176,28);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(5728,24);
manlo <= conv_std_logic_vector(262509746,28);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(5744,24);
manlo <= conv_std_logic_vector(263978413,28);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(5760,24);
manlo <= conv_std_logic_vector(265451178,28);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(5776,24);
manlo <= conv_std_logic_vector(266928039,28);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(5792,24);
manlo <= conv_std_logic_vector(268408999,28);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(5809,24);
manlo <= conv_std_logic_vector(1458599,28);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(5825,24);
manlo <= conv_std_logic_vector(2947754,28);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5841,24);
manlo <= conv_std_logic_vector(4441005,28);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(5857,24);
manlo <= conv_std_logic_vector(5938354,28);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(5873,24);
manlo <= conv_std_logic_vector(7439800,28);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(5889,24);
manlo <= conv_std_logic_vector(8945344,28);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(5905,24);
manlo <= conv_std_logic_vector(10454985,28);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(5921,24);
manlo <= conv_std_logic_vector(11968724,28);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(5937,24);
manlo <= conv_std_logic_vector(13486560,28);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(5953,24);
manlo <= conv_std_logic_vector(15008494,28);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(5969,24);
manlo <= conv_std_logic_vector(16534525,28);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5985,24);
manlo <= conv_std_logic_vector(18064653,28);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(6001,24);
manlo <= conv_std_logic_vector(19598879,28);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(6017,24);
manlo <= conv_std_logic_vector(21137203,28);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(6033,24);
manlo <= conv_std_logic_vector(22679624,28);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(6049,24);
manlo <= conv_std_logic_vector(24226142,28);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(6065,24);
manlo <= conv_std_logic_vector(25776758,28);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(6081,24);
manlo <= conv_std_logic_vector(27331471,28);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(6097,24);
manlo <= conv_std_logic_vector(28890282,28);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(6113,24);
manlo <= conv_std_logic_vector(30453190,28);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6129,24);
manlo <= conv_std_logic_vector(32020196,28);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(6145,24);
manlo <= conv_std_logic_vector(33591299,28);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(6161,24);
manlo <= conv_std_logic_vector(35166500,28);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(6177,24);
manlo <= conv_std_logic_vector(36745798,28);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(6193,24);
manlo <= conv_std_logic_vector(38329194,28);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(6209,24);
manlo <= conv_std_logic_vector(39916688,28);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(6225,24);
manlo <= conv_std_logic_vector(41508278,28);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(6241,24);
manlo <= conv_std_logic_vector(43103967,28);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(6257,24);
manlo <= conv_std_logic_vector(44703753,28);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6273,24);
manlo <= conv_std_logic_vector(46307636,28);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(6289,24);
manlo <= conv_std_logic_vector(47915617,28);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(6305,24);
manlo <= conv_std_logic_vector(49527695,28);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(6321,24);
manlo <= conv_std_logic_vector(51143871,28);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(6337,24);
manlo <= conv_std_logic_vector(52764145,28);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(6353,24);
manlo <= conv_std_logic_vector(54388516,28);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(6369,24);
manlo <= conv_std_logic_vector(56016985,28);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(6385,24);
manlo <= conv_std_logic_vector(57649551,28);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(6401,24);
manlo <= conv_std_logic_vector(59286215,28);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6417,24);
manlo <= conv_std_logic_vector(60926976,28);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(6433,24);
manlo <= conv_std_logic_vector(62571835,28);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(6449,24);
manlo <= conv_std_logic_vector(64220791,28);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(6465,24);
manlo <= conv_std_logic_vector(65873845,28);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(6481,24);
manlo <= conv_std_logic_vector(67530997,28);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(6497,24);
manlo <= conv_std_logic_vector(69192246,28);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(6513,24);
manlo <= conv_std_logic_vector(70857593,28);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(6529,24);
manlo <= conv_std_logic_vector(72527037,28);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(6545,24);
manlo <= conv_std_logic_vector(74200579,28);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6561,24);
manlo <= conv_std_logic_vector(75878219,28);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(6577,24);
manlo <= conv_std_logic_vector(77559956,28);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(6593,24);
manlo <= conv_std_logic_vector(79245791,28);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(6609,24);
manlo <= conv_std_logic_vector(80935723,28);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(6625,24);
manlo <= conv_std_logic_vector(82629753,28);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(6641,24);
manlo <= conv_std_logic_vector(84327881,28);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(6657,24);
manlo <= conv_std_logic_vector(86030106,28);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(6673,24);
manlo <= conv_std_logic_vector(87736429,28);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(6689,24);
manlo <= conv_std_logic_vector(89446849,28);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(6705,24);
manlo <= conv_std_logic_vector(91161367,28);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(6721,24);
manlo <= conv_std_logic_vector(92879983,28);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(6737,24);
manlo <= conv_std_logic_vector(94602697,28);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(6753,24);
manlo <= conv_std_logic_vector(96329508,28);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(6769,24);
manlo <= conv_std_logic_vector(98060416,28);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(6785,24);
manlo <= conv_std_logic_vector(99795423,28);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(6801,24);
manlo <= conv_std_logic_vector(101534527,28);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(6817,24);
manlo <= conv_std_logic_vector(103277728,28);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(6833,24);
manlo <= conv_std_logic_vector(105025028,28);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(6849,24);
manlo <= conv_std_logic_vector(106776425,28);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(6865,24);
manlo <= conv_std_logic_vector(108531919,28);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(6881,24);
manlo <= conv_std_logic_vector(110291512,28);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(6897,24);
manlo <= conv_std_logic_vector(112055202,28);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(6913,24);
manlo <= conv_std_logic_vector(113822989,28);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(6929,24);
manlo <= conv_std_logic_vector(115594875,28);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(6945,24);
manlo <= conv_std_logic_vector(117370858,28);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(6961,24);
manlo <= conv_std_logic_vector(119150939,28);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(6977,24);
manlo <= conv_std_logic_vector(120935117,28);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(6993,24);
manlo <= conv_std_logic_vector(122723393,28);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(7009,24);
manlo <= conv_std_logic_vector(124515767,28);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(7025,24);
manlo <= conv_std_logic_vector(126312239,28);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(7041,24);
manlo <= conv_std_logic_vector(128112808,28);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(7057,24);
manlo <= conv_std_logic_vector(129917475,28);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(7073,24);
manlo <= conv_std_logic_vector(131726240,28);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(7089,24);
manlo <= conv_std_logic_vector(133539102,28);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(7105,24);
manlo <= conv_std_logic_vector(135356063,28);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(7121,24);
manlo <= conv_std_logic_vector(137177121,28);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7137,24);
manlo <= conv_std_logic_vector(139002276,28);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(7153,24);
manlo <= conv_std_logic_vector(140831530,28);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(7169,24);
manlo <= conv_std_logic_vector(142664881,28);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(7185,24);
manlo <= conv_std_logic_vector(144502330,28);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(7201,24);
manlo <= conv_std_logic_vector(146343877,28);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(7217,24);
manlo <= conv_std_logic_vector(148189521,28);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(7233,24);
manlo <= conv_std_logic_vector(150039263,28);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(7249,24);
manlo <= conv_std_logic_vector(151893103,28);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(7265,24);
manlo <= conv_std_logic_vector(153751041,28);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(7281,24);
manlo <= conv_std_logic_vector(155613076,28);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(7297,24);
manlo <= conv_std_logic_vector(157479210,28);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(7313,24);
manlo <= conv_std_logic_vector(159349441,28);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(7329,24);
manlo <= conv_std_logic_vector(161223770,28);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(7345,24);
manlo <= conv_std_logic_vector(163102196,28);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(7361,24);
manlo <= conv_std_logic_vector(164984721,28);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(7377,24);
manlo <= conv_std_logic_vector(166871343,28);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(7393,24);
manlo <= conv_std_logic_vector(168762063,28);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(7409,24);
manlo <= conv_std_logic_vector(170656881,28);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(7425,24);
manlo <= conv_std_logic_vector(172555797,28);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(7441,24);
manlo <= conv_std_logic_vector(174458810,28);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(7457,24);
manlo <= conv_std_logic_vector(176365921,28);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(7473,24);
manlo <= conv_std_logic_vector(178277130,28);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(7489,24);
manlo <= conv_std_logic_vector(180192437,28);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(7505,24);
manlo <= conv_std_logic_vector(182111842,28);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(7521,24);
manlo <= conv_std_logic_vector(184035345,28);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(7537,24);
manlo <= conv_std_logic_vector(185962945,28);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(7553,24);
manlo <= conv_std_logic_vector(187894643,28);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(7569,24);
manlo <= conv_std_logic_vector(189830439,28);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(7585,24);
manlo <= conv_std_logic_vector(191770333,28);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(7601,24);
manlo <= conv_std_logic_vector(193714325,28);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(7617,24);
manlo <= conv_std_logic_vector(195662415,28);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(7633,24);
manlo <= conv_std_logic_vector(197614602,28);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(7649,24);
manlo <= conv_std_logic_vector(199570888,28);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(7665,24);
manlo <= conv_std_logic_vector(201531271,28);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7681,24);
manlo <= conv_std_logic_vector(203495752,28);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(7697,24);
manlo <= conv_std_logic_vector(205464331,28);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(7713,24);
manlo <= conv_std_logic_vector(207437008,28);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(7729,24);
manlo <= conv_std_logic_vector(209413783,28);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(7745,24);
manlo <= conv_std_logic_vector(211394656,28);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(7761,24);
manlo <= conv_std_logic_vector(213379626,28);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(7777,24);
manlo <= conv_std_logic_vector(215368695,28);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(7793,24);
manlo <= conv_std_logic_vector(217361861,28);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(7809,24);
manlo <= conv_std_logic_vector(219359125,28);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7825,24);
manlo <= conv_std_logic_vector(221360487,28);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(7841,24);
manlo <= conv_std_logic_vector(223365947,28);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(7857,24);
manlo <= conv_std_logic_vector(225375505,28);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(7873,24);
manlo <= conv_std_logic_vector(227389161,28);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(7889,24);
manlo <= conv_std_logic_vector(229406915,28);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(7905,24);
manlo <= conv_std_logic_vector(231428767,28);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(7921,24);
manlo <= conv_std_logic_vector(233454716,28);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(7937,24);
manlo <= conv_std_logic_vector(235484764,28);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(7953,24);
manlo <= conv_std_logic_vector(237518910,28);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7969,24);
manlo <= conv_std_logic_vector(239557153,28);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(7985,24);
manlo <= conv_std_logic_vector(241599495,28);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(8001,24);
manlo <= conv_std_logic_vector(243645934,28);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(8017,24);
manlo <= conv_std_logic_vector(245696471,28);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(8033,24);
manlo <= conv_std_logic_vector(247751107,28);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(8049,24);
manlo <= conv_std_logic_vector(249809840,28);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(8065,24);
manlo <= conv_std_logic_vector(251872671,28);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(8081,24);
manlo <= conv_std_logic_vector(253939600,28);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(8097,24);
manlo <= conv_std_logic_vector(256010627,28);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(8113,24);
manlo <= conv_std_logic_vector(258085753,28);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(8129,24);
manlo <= conv_std_logic_vector(260164976,28);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(8145,24);
manlo <= conv_std_logic_vector(262248297,28);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(8161,24);
manlo <= conv_std_logic_vector(264335716,28);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(8177,24);
manlo <= conv_std_logic_vector(266427233,28);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(8194,24);
manlo <= conv_std_logic_vector(87392,28);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(8210,24);
manlo <= conv_std_logic_vector(2187105,28);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(8226,24);
manlo <= conv_std_logic_vector(4290916,28);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(8242,24);
manlo <= conv_std_logic_vector(6398825,28);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8258,24);
manlo <= conv_std_logic_vector(8510832,28);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(8274,24);
manlo <= conv_std_logic_vector(10626938,28);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(8290,24);
manlo <= conv_std_logic_vector(12747141,28);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(8306,24);
manlo <= conv_std_logic_vector(14871442,28);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(8322,24);
manlo <= conv_std_logic_vector(16999841,28);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(8338,24);
manlo <= conv_std_logic_vector(19132338,28);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(8354,24);
manlo <= conv_std_logic_vector(21268934,28);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(8370,24);
manlo <= conv_std_logic_vector(23409627,28);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(8386,24);
manlo <= conv_std_logic_vector(25554418,28);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8402,24);
manlo <= conv_std_logic_vector(27703308,28);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(8418,24);
manlo <= conv_std_logic_vector(29856295,28);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(8434,24);
manlo <= conv_std_logic_vector(32013381,28);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(8450,24);
manlo <= conv_std_logic_vector(34174564,28);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(8466,24);
manlo <= conv_std_logic_vector(36339846,28);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(8482,24);
manlo <= conv_std_logic_vector(38509225,28);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(8498,24);
manlo <= conv_std_logic_vector(40682703,28);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(8514,24);
manlo <= conv_std_logic_vector(42860279,28);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(8530,24);
manlo <= conv_std_logic_vector(45041953,28);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8546,24);
manlo <= conv_std_logic_vector(47227725,28);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(8562,24);
manlo <= conv_std_logic_vector(49417595,28);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(8578,24);
manlo <= conv_std_logic_vector(51611563,28);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(8594,24);
manlo <= conv_std_logic_vector(53809629,28);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(8610,24);
manlo <= conv_std_logic_vector(56011794,28);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(8626,24);
manlo <= conv_std_logic_vector(58218056,28);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(8642,24);
manlo <= conv_std_logic_vector(60428417,28);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(8658,24);
manlo <= conv_std_logic_vector(62642876,28);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(8674,24);
manlo <= conv_std_logic_vector(64861432,28);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8690,24);
manlo <= conv_std_logic_vector(67084087,28);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(8706,24);
manlo <= conv_std_logic_vector(69310840,28);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(8722,24);
manlo <= conv_std_logic_vector(71541691,28);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(8738,24);
manlo <= conv_std_logic_vector(73776641,28);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(8754,24);
manlo <= conv_std_logic_vector(76015688,28);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(8770,24);
manlo <= conv_std_logic_vector(78258834,28);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(8786,24);
manlo <= conv_std_logic_vector(80506077,28);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(8802,24);
manlo <= conv_std_logic_vector(82757419,28);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(8818,24);
manlo <= conv_std_logic_vector(85012859,28);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(8834,24);
manlo <= conv_std_logic_vector(87272397,28);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(8850,24);
manlo <= conv_std_logic_vector(89536034,28);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(8866,24);
manlo <= conv_std_logic_vector(91803768,28);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(8882,24);
manlo <= conv_std_logic_vector(94075601,28);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(8898,24);
manlo <= conv_std_logic_vector(96351532,28);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(8914,24);
manlo <= conv_std_logic_vector(98631561,28);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(8930,24);
manlo <= conv_std_logic_vector(100915688,28);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(8946,24);
manlo <= conv_std_logic_vector(103203913,28);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(8962,24);
manlo <= conv_std_logic_vector(105496237,28);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(8978,24);
manlo <= conv_std_logic_vector(107792658,28);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(8994,24);
manlo <= conv_std_logic_vector(110093178,28);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(9010,24);
manlo <= conv_std_logic_vector(112397796,28);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(9026,24);
manlo <= conv_std_logic_vector(114706513,28);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(9042,24);
manlo <= conv_std_logic_vector(117019327,28);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(9058,24);
manlo <= conv_std_logic_vector(119336240,28);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(9074,24);
manlo <= conv_std_logic_vector(121657251,28);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(9090,24);
manlo <= conv_std_logic_vector(123982360,28);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(9106,24);
manlo <= conv_std_logic_vector(126311567,28);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9122,24);
manlo <= conv_std_logic_vector(128644873,28);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(9138,24);
manlo <= conv_std_logic_vector(130982277,28);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(9154,24);
manlo <= conv_std_logic_vector(133323779,28);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(9170,24);
manlo <= conv_std_logic_vector(135669379,28);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(9186,24);
manlo <= conv_std_logic_vector(138019077,28);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(9202,24);
manlo <= conv_std_logic_vector(140372874,28);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(9218,24);
manlo <= conv_std_logic_vector(142730769,28);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(9234,24);
manlo <= conv_std_logic_vector(145092762,28);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(9250,24);
manlo <= conv_std_logic_vector(147458854,28);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(9266,24);
manlo <= conv_std_logic_vector(149829044,28);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(9282,24);
manlo <= conv_std_logic_vector(152203332,28);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(9298,24);
manlo <= conv_std_logic_vector(154581718,28);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(9314,24);
manlo <= conv_std_logic_vector(156964202,28);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(9330,24);
manlo <= conv_std_logic_vector(159350785,28);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(9346,24);
manlo <= conv_std_logic_vector(161741466,28);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(9362,24);
manlo <= conv_std_logic_vector(164136246,28);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(9378,24);
manlo <= conv_std_logic_vector(166535123,28);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(9394,24);
manlo <= conv_std_logic_vector(168938099,28);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(9410,24);
manlo <= conv_std_logic_vector(171345174,28);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(9426,24);
manlo <= conv_std_logic_vector(173756346,28);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(9442,24);
manlo <= conv_std_logic_vector(176171617,28);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(9458,24);
manlo <= conv_std_logic_vector(178590986,28);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(9474,24);
manlo <= conv_std_logic_vector(181014454,28);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(9490,24);
manlo <= conv_std_logic_vector(183442020,28);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(9506,24);
manlo <= conv_std_logic_vector(185873684,28);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(9522,24);
manlo <= conv_std_logic_vector(188309446,28);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(9538,24);
manlo <= conv_std_logic_vector(190749307,28);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(9554,24);
manlo <= conv_std_logic_vector(193193266,28);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(9570,24);
manlo <= conv_std_logic_vector(195641323,28);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(9586,24);
manlo <= conv_std_logic_vector(198093479,28);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(9602,24);
manlo <= conv_std_logic_vector(200549733,28);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(9618,24);
manlo <= conv_std_logic_vector(203010086,28);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(9634,24);
manlo <= conv_std_logic_vector(205474536,28);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(9650,24);
manlo <= conv_std_logic_vector(207943085,28);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(9666,24);
manlo <= conv_std_logic_vector(210415733,28);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(9682,24);
manlo <= conv_std_logic_vector(212892479,28);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(9698,24);
manlo <= conv_std_logic_vector(215373323,28);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(9714,24);
manlo <= conv_std_logic_vector(217858266,28);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(9730,24);
manlo <= conv_std_logic_vector(220347307,28);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(9746,24);
manlo <= conv_std_logic_vector(222840446,28);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(9762,24);
manlo <= conv_std_logic_vector(225337684,28);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(9778,24);
manlo <= conv_std_logic_vector(227839020,28);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(9794,24);
manlo <= conv_std_logic_vector(230344454,28);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9810,24);
manlo <= conv_std_logic_vector(232853987,28);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(9826,24);
manlo <= conv_std_logic_vector(235367618,28);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(9842,24);
manlo <= conv_std_logic_vector(237885348,28);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(9858,24);
manlo <= conv_std_logic_vector(240407176,28);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(9874,24);
manlo <= conv_std_logic_vector(242933102,28);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(9890,24);
manlo <= conv_std_logic_vector(245463127,28);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(9906,24);
manlo <= conv_std_logic_vector(247997251,28);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(9922,24);
manlo <= conv_std_logic_vector(250535472,28);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(9938,24);
manlo <= conv_std_logic_vector(253077793,28);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9954,24);
manlo <= conv_std_logic_vector(255624211,28);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(9970,24);
manlo <= conv_std_logic_vector(258174728,28);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(9986,24);
manlo <= conv_std_logic_vector(260729344,28);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(10002,24);
manlo <= conv_std_logic_vector(263288057,28);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(10018,24);
manlo <= conv_std_logic_vector(265850870,28);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(10034,24);
manlo <= conv_std_logic_vector(268417780,28);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(10051,24);
manlo <= conv_std_logic_vector(2553334,28);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(10067,24);
manlo <= conv_std_logic_vector(5128441,28);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(10083,24);
manlo <= conv_std_logic_vector(7707647,28);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(10099,24);
manlo <= conv_std_logic_vector(10290952,28);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(10115,24);
manlo <= conv_std_logic_vector(12878355,28);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(10131,24);
manlo <= conv_std_logic_vector(15469857,28);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(10147,24);
manlo <= conv_std_logic_vector(18065457,28);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(10163,24);
manlo <= conv_std_logic_vector(20665155,28);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(10179,24);
manlo <= conv_std_logic_vector(23268952,28);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(10195,24);
manlo <= conv_std_logic_vector(25876847,28);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(10211,24);
manlo <= conv_std_logic_vector(28488841,28);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(10227,24);
manlo <= conv_std_logic_vector(31104934,28);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10243,24);
manlo <= conv_std_logic_vector(33725125,28);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(10259,24);
manlo <= conv_std_logic_vector(36349414,28);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(10275,24);
manlo <= conv_std_logic_vector(38977802,28);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(10291,24);
manlo <= conv_std_logic_vector(41610288,28);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(10307,24);
manlo <= conv_std_logic_vector(44246873,28);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(10323,24);
manlo <= conv_std_logic_vector(46887557,28);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(10339,24);
manlo <= conv_std_logic_vector(49532339,28);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(10355,24);
manlo <= conv_std_logic_vector(52181219,28);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(10371,24);
manlo <= conv_std_logic_vector(54834198,28);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10387,24);
manlo <= conv_std_logic_vector(57491276,28);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(10403,24);
manlo <= conv_std_logic_vector(60152452,28);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(10419,24);
manlo <= conv_std_logic_vector(62817727,28);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(10435,24);
manlo <= conv_std_logic_vector(65487100,28);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(10451,24);
manlo <= conv_std_logic_vector(68160572,28);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(10467,24);
manlo <= conv_std_logic_vector(70838142,28);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(10483,24);
manlo <= conv_std_logic_vector(73519811,28);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(10499,24);
manlo <= conv_std_logic_vector(76205578,28);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(10515,24);
manlo <= conv_std_logic_vector(78895444,28);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10531,24);
manlo <= conv_std_logic_vector(81589409,28);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(10547,24);
manlo <= conv_std_logic_vector(84287472,28);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(10563,24);
manlo <= conv_std_logic_vector(86989633,28);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(10579,24);
manlo <= conv_std_logic_vector(89695894,28);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(10595,24);
manlo <= conv_std_logic_vector(92406252,28);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(10611,24);
manlo <= conv_std_logic_vector(95120710,28);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(10627,24);
manlo <= conv_std_logic_vector(97839266,28);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(10643,24);
manlo <= conv_std_logic_vector(100561920,28);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(10659,24);
manlo <= conv_std_logic_vector(103288674,28);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10675,24);
manlo <= conv_std_logic_vector(106019525,28);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(10691,24);
manlo <= conv_std_logic_vector(108754476,28);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(10707,24);
manlo <= conv_std_logic_vector(111493525,28);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(10723,24);
manlo <= conv_std_logic_vector(114236673,28);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(10739,24);
manlo <= conv_std_logic_vector(116983919,28);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(10755,24);
manlo <= conv_std_logic_vector(119735264,28);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(10771,24);
manlo <= conv_std_logic_vector(122490707,28);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(10787,24);
manlo <= conv_std_logic_vector(125250249,28);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(10803,24);
manlo <= conv_std_logic_vector(128013890,28);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(10819,24);
manlo <= conv_std_logic_vector(130781629,28);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(10835,24);
manlo <= conv_std_logic_vector(133553468,28);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(10851,24);
manlo <= conv_std_logic_vector(136329404,28);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(10867,24);
manlo <= conv_std_logic_vector(139109440,28);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(10883,24);
manlo <= conv_std_logic_vector(141893574,28);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(10899,24);
manlo <= conv_std_logic_vector(144681806,28);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(10915,24);
manlo <= conv_std_logic_vector(147474137,28);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(10931,24);
manlo <= conv_std_logic_vector(150270567,28);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(10947,24);
manlo <= conv_std_logic_vector(153071096,28);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(10963,24);
manlo <= conv_std_logic_vector(155875723,28);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(10979,24);
manlo <= conv_std_logic_vector(158684449,28);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(10995,24);
manlo <= conv_std_logic_vector(161497274,28);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(11011,24);
manlo <= conv_std_logic_vector(164314197,28);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(11027,24);
manlo <= conv_std_logic_vector(167135219,28);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(11043,24);
manlo <= conv_std_logic_vector(169960340,28);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(11059,24);
manlo <= conv_std_logic_vector(172789560,28);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(11075,24);
manlo <= conv_std_logic_vector(175622878,28);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(11091,24);
manlo <= conv_std_logic_vector(178460295,28);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11107,24);
manlo <= conv_std_logic_vector(181301810,28);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(11123,24);
manlo <= conv_std_logic_vector(184147424,28);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(11139,24);
manlo <= conv_std_logic_vector(186997137,28);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(11155,24);
manlo <= conv_std_logic_vector(189850949,28);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(11171,24);
manlo <= conv_std_logic_vector(192708860,28);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(11187,24);
manlo <= conv_std_logic_vector(195570869,28);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(11203,24);
manlo <= conv_std_logic_vector(198436977,28);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(11219,24);
manlo <= conv_std_logic_vector(201307183,28);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(11235,24);
manlo <= conv_std_logic_vector(204181489,28);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(11251,24);
manlo <= conv_std_logic_vector(207059893,28);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(11267,24);
manlo <= conv_std_logic_vector(209942395,28);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(11283,24);
manlo <= conv_std_logic_vector(212828997,28);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(11299,24);
manlo <= conv_std_logic_vector(215719697,28);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(11315,24);
manlo <= conv_std_logic_vector(218614497,28);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(11331,24);
manlo <= conv_std_logic_vector(221513394,28);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(11347,24);
manlo <= conv_std_logic_vector(224416391,28);
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(11363,24);
manlo <= conv_std_logic_vector(227323486,28);
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(11379,24);
manlo <= conv_std_logic_vector(230234681,28);
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(11395,24);
manlo <= conv_std_logic_vector(233149974,28);
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(11411,24);
manlo <= conv_std_logic_vector(236069365,28);
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(11427,24);
manlo <= conv_std_logic_vector(238992856,28);
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(11443,24);
manlo <= conv_std_logic_vector(241920445,28);
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(11459,24);
manlo <= conv_std_logic_vector(244852133,28);
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(11475,24);
manlo <= conv_std_logic_vector(247787920,28);
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(11491,24);
manlo <= conv_std_logic_vector(250727806,28);
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(11507,24);
manlo <= conv_std_logic_vector(253671790,28);
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(11523,24);
manlo <= conv_std_logic_vector(256619874,28);
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(11539,24);
manlo <= conv_std_logic_vector(259572056,28);
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(11555,24);
manlo <= conv_std_logic_vector(262528337,28);
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(11571,24);
manlo <= conv_std_logic_vector(265488717,28);
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(11588,24);
manlo <= conv_std_logic_vector(17739,28);
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(11604,24);
manlo <= conv_std_logic_vector(2986317,28);
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(11620,24);
manlo <= conv_std_logic_vector(5958993,28);
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(11636,24);
manlo <= conv_std_logic_vector(8935768,28);
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(11652,24);
manlo <= conv_std_logic_vector(11916642,28);
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(11668,24);
manlo <= conv_std_logic_vector(14901615,28);
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(11684,24);
manlo <= conv_std_logic_vector(17890686,28);
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(11700,24);
manlo <= conv_std_logic_vector(20883857,28);
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(11716,24);
manlo <= conv_std_logic_vector(23881126,28);
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(11732,24);
manlo <= conv_std_logic_vector(26882494,28);
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(11748,24);
manlo <= conv_std_logic_vector(29887961,28);
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(11764,24);
manlo <= conv_std_logic_vector(32897527,28);
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(11780,24);
manlo <= conv_std_logic_vector(35911192,28);
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(11796,24);
manlo <= conv_std_logic_vector(38928956,28);
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(11812,24);
manlo <= conv_std_logic_vector(41950818,28);
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(11828,24);
manlo <= conv_std_logic_vector(44976780,28);
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(11844,24);
manlo <= conv_std_logic_vector(48006840,28);
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(11860,24);
manlo <= conv_std_logic_vector(51040999,28);
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(11876,24);
manlo <= conv_std_logic_vector(54079258,28);
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(11892,24);
manlo <= conv_std_logic_vector(57121615,28);
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(11908,24);
manlo <= conv_std_logic_vector(60168071,28);
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(11924,24);
manlo <= conv_std_logic_vector(63218625,28);
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(11940,24);
manlo <= conv_std_logic_vector(66273279,28);
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(11956,24);
manlo <= conv_std_logic_vector(69332032,28);
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(11972,24);
manlo <= conv_std_logic_vector(72394883,28);
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(11988,24);
manlo <= conv_std_logic_vector(75461834,28);
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(12004,24);
manlo <= conv_std_logic_vector(78532883,28);
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(12020,24);
manlo <= conv_std_logic_vector(81608032,28);
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(12036,24);
manlo <= conv_std_logic_vector(84687279,28);
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(12052,24);
manlo <= conv_std_logic_vector(87770625,28);
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(12068,24);
manlo <= conv_std_logic_vector(90858070,28);
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(12084,24);
manlo <= conv_std_logic_vector(93949615,28);
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(12100,24);
manlo <= conv_std_logic_vector(97045258,28);
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(12116,24);
manlo <= conv_std_logic_vector(100145000,28);
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(12132,24);
manlo <= conv_std_logic_vector(103248841,28);
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(12148,24);
manlo <= conv_std_logic_vector(106356781,28);
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(12164,24);
manlo <= conv_std_logic_vector(109468819,28);
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(12180,24);
manlo <= conv_std_logic_vector(112584957,28);
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(12196,24);
manlo <= conv_std_logic_vector(115705194,28);
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(12212,24);
manlo <= conv_std_logic_vector(118829530,28);
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(12228,24);
manlo <= conv_std_logic_vector(121957965,28);
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(12244,24);
manlo <= conv_std_logic_vector(125090499,28);
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(12260,24);
manlo <= conv_std_logic_vector(128227131,28);
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(12276,24);
manlo <= conv_std_logic_vector(131367863,28);
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(12292,24);
manlo <= conv_std_logic_vector(134512694,28);
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(12308,24);
manlo <= conv_std_logic_vector(137661624,28);
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(12324,24);
manlo <= conv_std_logic_vector(140814653,28);
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(12340,24);
manlo <= conv_std_logic_vector(143971780,28);
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(12356,24);
manlo <= conv_std_logic_vector(147133007,28);
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(12372,24);
manlo <= conv_std_logic_vector(150298333,28);
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(12388,24);
manlo <= conv_std_logic_vector(153467758,28);
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(12404,24);
manlo <= conv_std_logic_vector(156641282,28);
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(12420,24);
manlo <= conv_std_logic_vector(159818905,28);
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(12436,24);
manlo <= conv_std_logic_vector(163000627,28);
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(12452,24);
manlo <= conv_std_logic_vector(166186448,28);
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(12468,24);
manlo <= conv_std_logic_vector(169376368,28);
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(12484,24);
manlo <= conv_std_logic_vector(172570387,28);
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(12500,24);
manlo <= conv_std_logic_vector(175768505,28);
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(12516,24);
manlo <= conv_std_logic_vector(178970722,28);
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(12532,24);
manlo <= conv_std_logic_vector(182177038,28);
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(12548,24);
manlo <= conv_std_logic_vector(185387453,28);
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(12564,24);
manlo <= conv_std_logic_vector(188601968,28);
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(12580,24);
manlo <= conv_std_logic_vector(191820581,28);
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(12596,24);
manlo <= conv_std_logic_vector(195043294,28);
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(12612,24);
manlo <= conv_std_logic_vector(198270105,28);
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(12628,24);
manlo <= conv_std_logic_vector(201501016,28);
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(12644,24);
manlo <= conv_std_logic_vector(204736025,28);
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(12660,24);
manlo <= conv_std_logic_vector(207975134,28);
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(12676,24);
manlo <= conv_std_logic_vector(211218342,28);
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(12692,24);
manlo <= conv_std_logic_vector(214465649,28);
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(12708,24);
manlo <= conv_std_logic_vector(217717055,28);
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(12724,24);
manlo <= conv_std_logic_vector(220972560,28);
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(12740,24);
manlo <= conv_std_logic_vector(224232165,28);
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(12756,24);
manlo <= conv_std_logic_vector(227495868,28);
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(12772,24);
manlo <= conv_std_logic_vector(230763671,28);
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(12788,24);
manlo <= conv_std_logic_vector(234035572,28);
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(12804,24);
manlo <= conv_std_logic_vector(237311573,28);
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(12820,24);
manlo <= conv_std_logic_vector(240591673,28);
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(12836,24);
manlo <= conv_std_logic_vector(243875872,28);
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(12852,24);
manlo <= conv_std_logic_vector(247164170,28);
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(12868,24);
manlo <= conv_std_logic_vector(250456567,28);
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(12884,24);
manlo <= conv_std_logic_vector(253753064,28);
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(12900,24);
manlo <= conv_std_logic_vector(257053659,28);
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(12916,24);
manlo <= conv_std_logic_vector(260358354,28);
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(12932,24);
manlo <= conv_std_logic_vector(263667148,28);
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(12948,24);
manlo <= conv_std_logic_vector(266980041,28);
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(12965,24);
manlo <= conv_std_logic_vector(1861577,28);
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(12981,24);
manlo <= conv_std_logic_vector(5182668,28);
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(12997,24);
manlo <= conv_std_logic_vector(8507859,28);
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(13013,24);
manlo <= conv_std_logic_vector(11837149,28);
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(13029,24);
manlo <= conv_std_logic_vector(15170538,28);
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(13045,24);
manlo <= conv_std_logic_vector(18508026,28);
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(13061,24);
manlo <= conv_std_logic_vector(21849613,28);
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(13077,24);
manlo <= conv_std_logic_vector(25195299,28);
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(13093,24);
manlo <= conv_std_logic_vector(28545085,28);
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(13109,24);
manlo <= conv_std_logic_vector(31898970,28);
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(13125,24);
manlo <= conv_std_logic_vector(35256954,28);
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(13141,24);
manlo <= conv_std_logic_vector(38619037,28);
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(13157,24);
manlo <= conv_std_logic_vector(41985219,28);
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(13173,24);
manlo <= conv_std_logic_vector(45355501,28);
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(13189,24);
manlo <= conv_std_logic_vector(48729882,28);
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(13205,24);
manlo <= conv_std_logic_vector(52108362,28);
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(13221,24);
manlo <= conv_std_logic_vector(55490941,28);
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(13237,24);
manlo <= conv_std_logic_vector(58877620,28);
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(13253,24);
manlo <= conv_std_logic_vector(62268398,28);
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(13269,24);
manlo <= conv_std_logic_vector(65663275,28);
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(13285,24);
manlo <= conv_std_logic_vector(69062251,28);
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(13301,24);
manlo <= conv_std_logic_vector(72465326,28);
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(13317,24);
manlo <= conv_std_logic_vector(75872501,28);
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(13333,24);
manlo <= conv_std_logic_vector(79283775,28);
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(13349,24);
manlo <= conv_std_logic_vector(82699148,28);
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(13365,24);
manlo <= conv_std_logic_vector(86118621,28);
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(13381,24);
manlo <= conv_std_logic_vector(89542193,28);
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(13397,24);
manlo <= conv_std_logic_vector(92969864,28);
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(13413,24);
manlo <= conv_std_logic_vector(96401634,28);
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(13429,24);
manlo <= conv_std_logic_vector(99837503,28);
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(13445,24);
manlo <= conv_std_logic_vector(103277472,28);
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(13461,24);
manlo <= conv_std_logic_vector(106721540,28);
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(13477,24);
manlo <= conv_std_logic_vector(110169708,28);
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(13493,24);
manlo <= conv_std_logic_vector(113621975,28);
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(13509,24);
manlo <= conv_std_logic_vector(117078341,28);
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(13525,24);
manlo <= conv_std_logic_vector(120538806,28);
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(13541,24);
manlo <= conv_std_logic_vector(124003370,28);
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(13557,24);
manlo <= conv_std_logic_vector(127472034,28);
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(13573,24);
manlo <= conv_std_logic_vector(130944798,28);
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(13589,24);
manlo <= conv_std_logic_vector(134421660,28);
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(13605,24);
manlo <= conv_std_logic_vector(137902622,28);
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(13621,24);
manlo <= conv_std_logic_vector(141387683,28);
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(13637,24);
manlo <= conv_std_logic_vector(144876844,28);
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(13653,24);
manlo <= conv_std_logic_vector(148370104,28);
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(13669,24);
manlo <= conv_std_logic_vector(151867463,28);
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(13685,24);
manlo <= conv_std_logic_vector(155368921,28);
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(13701,24);
manlo <= conv_std_logic_vector(158874479,28);
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(13717,24);
manlo <= conv_std_logic_vector(162384136,28);
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(13733,24);
manlo <= conv_std_logic_vector(165897893,28);
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(13749,24);
manlo <= conv_std_logic_vector(169415749,28);
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(13765,24);
manlo <= conv_std_logic_vector(172937704,28);
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(13781,24);
manlo <= conv_std_logic_vector(176463758,28);
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(13797,24);
manlo <= conv_std_logic_vector(179993912,28);
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(13813,24);
manlo <= conv_std_logic_vector(183528166,28);
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(13829,24);
manlo <= conv_std_logic_vector(187066519,28);
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(13845,24);
manlo <= conv_std_logic_vector(190608971,28);
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(13861,24);
manlo <= conv_std_logic_vector(194155522,28);
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(13877,24);
manlo <= conv_std_logic_vector(197706173,28);
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(13893,24);
manlo <= conv_std_logic_vector(201260923,28);
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(13909,24);
manlo <= conv_std_logic_vector(204819773,28);
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(13925,24);
manlo <= conv_std_logic_vector(208382722,28);
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(13941,24);
manlo <= conv_std_logic_vector(211949770,28);
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(13957,24);
manlo <= conv_std_logic_vector(215520918,28);
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(13973,24);
manlo <= conv_std_logic_vector(219096165,28);
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(13989,24);
manlo <= conv_std_logic_vector(222675512,28);
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(14005,24);
manlo <= conv_std_logic_vector(226258958,28);
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(14021,24);
manlo <= conv_std_logic_vector(229846504,28);
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(14037,24);
manlo <= conv_std_logic_vector(233438148,28);
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(14053,24);
manlo <= conv_std_logic_vector(237033893,28);
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(14069,24);
manlo <= conv_std_logic_vector(240633737,28);
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(14085,24);
manlo <= conv_std_logic_vector(244237680,28);
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(14101,24);
manlo <= conv_std_logic_vector(247845722,28);
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(14117,24);
manlo <= conv_std_logic_vector(251457864,28);
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(14133,24);
manlo <= conv_std_logic_vector(255074106,28);
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(14149,24);
manlo <= conv_std_logic_vector(258694447,28);
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(14165,24);
manlo <= conv_std_logic_vector(262318887,28);
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(14181,24);
manlo <= conv_std_logic_vector(265947427,28);
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(14198,24);
manlo <= conv_std_logic_vector(1144611,28);
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(14214,24);
manlo <= conv_std_logic_vector(4781350,28);
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(14230,24);
manlo <= conv_std_logic_vector(8422188,28);
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(14246,24);
manlo <= conv_std_logic_vector(12067126,28);
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(14262,24);
manlo <= conv_std_logic_vector(15716163,28);
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(14278,24);
manlo <= conv_std_logic_vector(19369300,28);
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(14294,24);
manlo <= conv_std_logic_vector(23026536,28);
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(14310,24);
manlo <= conv_std_logic_vector(26687871,28);
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(14326,24);
manlo <= conv_std_logic_vector(30353307,28);
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(14342,24);
manlo <= conv_std_logic_vector(34022841,28);
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(14358,24);
manlo <= conv_std_logic_vector(37696476,28);
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(14374,24);
manlo <= conv_std_logic_vector(41374209,28);
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(14390,24);
manlo <= conv_std_logic_vector(45056043,28);
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(14406,24);
manlo <= conv_std_logic_vector(48741975,28);
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(14422,24);
manlo <= conv_std_logic_vector(52432007,28);
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(14438,24);
manlo <= conv_std_logic_vector(56126139,28);
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(14454,24);
manlo <= conv_std_logic_vector(59824371,28);
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(14470,24);
manlo <= conv_std_logic_vector(63526701,28);
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(14486,24);
manlo <= conv_std_logic_vector(67233132,28);
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(14502,24);
manlo <= conv_std_logic_vector(70943662,28);
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(14518,24);
manlo <= conv_std_logic_vector(74658291,28);
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(14534,24);
manlo <= conv_std_logic_vector(78377020,28);
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(14550,24);
manlo <= conv_std_logic_vector(82099849,28);
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(14566,24);
manlo <= conv_std_logic_vector(85826777,28);
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(14582,24);
manlo <= conv_std_logic_vector(89557804,28);
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(14598,24);
manlo <= conv_std_logic_vector(93292931,28);
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(14614,24);
manlo <= conv_std_logic_vector(97032158,28);
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(14630,24);
manlo <= conv_std_logic_vector(100775484,28);
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(14646,24);
manlo <= conv_std_logic_vector(104522910,28);
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(14662,24);
manlo <= conv_std_logic_vector(108274436,28);
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(14678,24);
manlo <= conv_std_logic_vector(112030061,28);
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(14694,24);
manlo <= conv_std_logic_vector(115789786,28);
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(14710,24);
manlo <= conv_std_logic_vector(119553610,28);
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(14726,24);
manlo <= conv_std_logic_vector(123321534,28);
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(14742,24);
manlo <= conv_std_logic_vector(127093557,28);
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(14758,24);
manlo <= conv_std_logic_vector(130869680,28);
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(14774,24);
manlo <= conv_std_logic_vector(134649903,28);
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(14790,24);
manlo <= conv_std_logic_vector(138434225,28);
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(14806,24);
manlo <= conv_std_logic_vector(142222647,28);
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(14822,24);
manlo <= conv_std_logic_vector(146015168,28);
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(14838,24);
manlo <= conv_std_logic_vector(149811789,28);
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(14854,24);
manlo <= conv_std_logic_vector(153612510,28);
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(14870,24);
manlo <= conv_std_logic_vector(157417330,28);
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(14886,24);
manlo <= conv_std_logic_vector(161226250,28);
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(14902,24);
manlo <= conv_std_logic_vector(165039270,28);
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(14918,24);
manlo <= conv_std_logic_vector(168856389,28);
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(14934,24);
manlo <= conv_std_logic_vector(172677608,28);
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(14950,24);
manlo <= conv_std_logic_vector(176502926,28);
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(14966,24);
manlo <= conv_std_logic_vector(180332344,28);
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(14982,24);
manlo <= conv_std_logic_vector(184165862,28);
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(14998,24);
manlo <= conv_std_logic_vector(188003480,28);
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(15014,24);
manlo <= conv_std_logic_vector(191845197,28);
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(15030,24);
manlo <= conv_std_logic_vector(195691014,28);
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(15046,24);
manlo <= conv_std_logic_vector(199540930,28);
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(15062,24);
manlo <= conv_std_logic_vector(203394946,28);
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(15078,24);
manlo <= conv_std_logic_vector(207253062,28);
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(15094,24);
manlo <= conv_std_logic_vector(211115277,28);
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(15110,24);
manlo <= conv_std_logic_vector(214981593,28);
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(15126,24);
manlo <= conv_std_logic_vector(218852007,28);
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(15142,24);
manlo <= conv_std_logic_vector(222726522,28);
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(15158,24);
manlo <= conv_std_logic_vector(226605136,28);
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(15174,24);
manlo <= conv_std_logic_vector(230487850,28);
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(15190,24);
manlo <= conv_std_logic_vector(234374664,28);
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(15206,24);
manlo <= conv_std_logic_vector(238265577,28);
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(15222,24);
manlo <= conv_std_logic_vector(242160590,28);
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(15238,24);
manlo <= conv_std_logic_vector(246059703,28);
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(15254,24);
manlo <= conv_std_logic_vector(249962916,28);
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(15270,24);
manlo <= conv_std_logic_vector(253870228,28);
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(15286,24);
manlo <= conv_std_logic_vector(257781640,28);
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(15302,24);
manlo <= conv_std_logic_vector(261697152,28);
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(15318,24);
manlo <= conv_std_logic_vector(265616763,28);
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(15335,24);
manlo <= conv_std_logic_vector(1105018,28);
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(15351,24);
manlo <= conv_std_logic_vector(5032829,28);
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(15367,24);
manlo <= conv_std_logic_vector(8964740,28);
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(15383,24);
manlo <= conv_std_logic_vector(12900750,28);
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(15399,24);
manlo <= conv_std_logic_vector(16840860,28);
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(15415,24);
manlo <= conv_std_logic_vector(20785070,28);
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(15431,24);
manlo <= conv_std_logic_vector(24733380,28);
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(15447,24);
manlo <= conv_std_logic_vector(28685790,28);
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(15463,24);
manlo <= conv_std_logic_vector(32642299,28);
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(15479,24);
manlo <= conv_std_logic_vector(36602908,28);
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(15495,24);
manlo <= conv_std_logic_vector(40567617,28);
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(15511,24);
manlo <= conv_std_logic_vector(44536425,28);
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(15527,24);
manlo <= conv_std_logic_vector(48509334,28);
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(15543,24);
manlo <= conv_std_logic_vector(52486342,28);
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(15559,24);
manlo <= conv_std_logic_vector(56467450,28);
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(15575,24);
manlo <= conv_std_logic_vector(60452657,28);
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(15591,24);
manlo <= conv_std_logic_vector(64441965,28);
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(15607,24);
manlo <= conv_std_logic_vector(68435372,28);
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(15623,24);
manlo <= conv_std_logic_vector(72432880,28);
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(15639,24);
manlo <= conv_std_logic_vector(76434487,28);
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(15655,24);
manlo <= conv_std_logic_vector(80440193,28);
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(15671,24);
manlo <= conv_std_logic_vector(84450000,28);
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(15687,24);
manlo <= conv_std_logic_vector(88463906,28);
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(15703,24);
manlo <= conv_std_logic_vector(92481913,28);
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(15719,24);
manlo <= conv_std_logic_vector(96504019,28);
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(15735,24);
manlo <= conv_std_logic_vector(100530225,28);
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(15751,24);
manlo <= conv_std_logic_vector(104560531,28);
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(15767,24);
manlo <= conv_std_logic_vector(108594936,28);
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(15783,24);
manlo <= conv_std_logic_vector(112633442,28);
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(15799,24);
manlo <= conv_std_logic_vector(116676047,28);
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(15815,24);
manlo <= conv_std_logic_vector(120722752,28);
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(15831,24);
manlo <= conv_std_logic_vector(124773557,28);
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(15847,24);
manlo <= conv_std_logic_vector(128828462,28);
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(15863,24);
manlo <= conv_std_logic_vector(132887467,28);
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(15879,24);
manlo <= conv_std_logic_vector(136950572,28);
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(15895,24);
manlo <= conv_std_logic_vector(141017776,28);
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(15911,24);
manlo <= conv_std_logic_vector(145089081,28);
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(15927,24);
manlo <= conv_std_logic_vector(149164485,28);
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(15943,24);
manlo <= conv_std_logic_vector(153243989,28);
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(15959,24);
manlo <= conv_std_logic_vector(157327593,28);
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(15975,24);
manlo <= conv_std_logic_vector(161415297,28);
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(15991,24);
manlo <= conv_std_logic_vector(165507101,28);
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(16007,24);
manlo <= conv_std_logic_vector(169603005,28);
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(16023,24);
manlo <= conv_std_logic_vector(173703009,28);
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(16039,24);
manlo <= conv_std_logic_vector(177807112,28);
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(16055,24);
manlo <= conv_std_logic_vector(181915316,28);
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(16071,24);
manlo <= conv_std_logic_vector(186027619,28);
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(16087,24);
manlo <= conv_std_logic_vector(190144023,28);
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(16103,24);
manlo <= conv_std_logic_vector(194264526,28);
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(16119,24);
manlo <= conv_std_logic_vector(198389129,28);
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(16135,24);
manlo <= conv_std_logic_vector(202517832,28);
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(16151,24);
manlo <= conv_std_logic_vector(206650635,28);
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(16167,24);
manlo <= conv_std_logic_vector(210787538,28);
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(16183,24);
manlo <= conv_std_logic_vector(214928541,28);
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(16199,24);
manlo <= conv_std_logic_vector(219073644,28);
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(16215,24);
manlo <= conv_std_logic_vector(223222847,28);
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(16231,24);
manlo <= conv_std_logic_vector(227376150,28);
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(16247,24);
manlo <= conv_std_logic_vector(231533553,28);
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(16263,24);
manlo <= conv_std_logic_vector(235695056,28);
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(16279,24);
manlo <= conv_std_logic_vector(239860659,28);
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(16295,24);
manlo <= conv_std_logic_vector(244030361,28);
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(16311,24);
manlo <= conv_std_logic_vector(248204164,28);
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(16327,24);
manlo <= conv_std_logic_vector(252382067,28);
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(16343,24);
manlo <= conv_std_logic_vector(256564069,28);
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(16359,24);
manlo <= conv_std_logic_vector(260750172,28);
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(16375,24);
manlo <= conv_std_logic_vector(264940375,28);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT20.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut20 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
END dp_explut20;
ARCHITECTURE rtl OF dp_explut20 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16,24);
manlo <= conv_std_logic_vector(2048,28);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32,24);
manlo <= conv_std_logic_vector(8192,28);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(48,24);
manlo <= conv_std_logic_vector(18432,28);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(64,24);
manlo <= conv_std_logic_vector(32768,28);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(80,24);
manlo <= conv_std_logic_vector(51200,28);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(96,24);
manlo <= conv_std_logic_vector(73728,28);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(112,24);
manlo <= conv_std_logic_vector(100352,28);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(128,24);
manlo <= conv_std_logic_vector(131072,28);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(144,24);
manlo <= conv_std_logic_vector(165888,28);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(160,24);
manlo <= conv_std_logic_vector(204801,28);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(176,24);
manlo <= conv_std_logic_vector(247809,28);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(192,24);
manlo <= conv_std_logic_vector(294913,28);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(208,24);
manlo <= conv_std_logic_vector(346113,28);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(224,24);
manlo <= conv_std_logic_vector(401410,28);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(240,24);
manlo <= conv_std_logic_vector(460802,28);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(256,24);
manlo <= conv_std_logic_vector(524291,28);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(272,24);
manlo <= conv_std_logic_vector(591875,28);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(288,24);
manlo <= conv_std_logic_vector(663556,28);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(304,24);
manlo <= conv_std_logic_vector(739332,28);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(320,24);
manlo <= conv_std_logic_vector(819205,28);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(336,24);
manlo <= conv_std_logic_vector(903174,28);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(352,24);
manlo <= conv_std_logic_vector(991239,28);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(368,24);
manlo <= conv_std_logic_vector(1083400,28);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(384,24);
manlo <= conv_std_logic_vector(1179657,28);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(400,24);
manlo <= conv_std_logic_vector(1280010,28);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(416,24);
manlo <= conv_std_logic_vector(1384459,28);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(432,24);
manlo <= conv_std_logic_vector(1493005,28);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(448,24);
manlo <= conv_std_logic_vector(1605646,28);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(464,24);
manlo <= conv_std_logic_vector(1722384,28);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(480,24);
manlo <= conv_std_logic_vector(1843218,28);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(496,24);
manlo <= conv_std_logic_vector(1968147,28);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(512,24);
manlo <= conv_std_logic_vector(2097173,28);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(528,24);
manlo <= conv_std_logic_vector(2230295,28);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(544,24);
manlo <= conv_std_logic_vector(2367514,28);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(560,24);
manlo <= conv_std_logic_vector(2508828,28);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(576,24);
manlo <= conv_std_logic_vector(2654238,28);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(592,24);
manlo <= conv_std_logic_vector(2803745,28);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(608,24);
manlo <= conv_std_logic_vector(2957348,28);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(624,24);
manlo <= conv_std_logic_vector(3115047,28);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(640,24);
manlo <= conv_std_logic_vector(3276842,28);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(656,24);
manlo <= conv_std_logic_vector(3442733,28);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(672,24);
manlo <= conv_std_logic_vector(3612720,28);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(688,24);
manlo <= conv_std_logic_vector(3786804,28);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(704,24);
manlo <= conv_std_logic_vector(3964983,28);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(720,24);
manlo <= conv_std_logic_vector(4147259,28);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(736,24);
manlo <= conv_std_logic_vector(4333631,28);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(752,24);
manlo <= conv_std_logic_vector(4524100,28);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(768,24);
manlo <= conv_std_logic_vector(4718664,28);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(784,24);
manlo <= conv_std_logic_vector(4917325,28);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(800,24);
manlo <= conv_std_logic_vector(5120081,28);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(816,24);
manlo <= conv_std_logic_vector(5326934,28);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(832,24);
manlo <= conv_std_logic_vector(5537884,28);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(848,24);
manlo <= conv_std_logic_vector(5752929,28);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(864,24);
manlo <= conv_std_logic_vector(5972071,28);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(880,24);
manlo <= conv_std_logic_vector(6195308,28);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(896,24);
manlo <= conv_std_logic_vector(6422642,28);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(912,24);
manlo <= conv_std_logic_vector(6654073,28);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(928,24);
manlo <= conv_std_logic_vector(6889599,28);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(944,24);
manlo <= conv_std_logic_vector(7129222,28);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(960,24);
manlo <= conv_std_logic_vector(7372941,28);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(976,24);
manlo <= conv_std_logic_vector(7620756,28);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(992,24);
manlo <= conv_std_logic_vector(7872667,28);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1008,24);
manlo <= conv_std_logic_vector(8128675,28);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1024,24);
manlo <= conv_std_logic_vector(8388779,28);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1040,24);
manlo <= conv_std_logic_vector(8652979,28);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1056,24);
manlo <= conv_std_logic_vector(8921275,28);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1072,24);
manlo <= conv_std_logic_vector(9193668,28);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1088,24);
manlo <= conv_std_logic_vector(9470157,28);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1104,24);
manlo <= conv_std_logic_vector(9750742,28);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1120,24);
manlo <= conv_std_logic_vector(10035423,28);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1136,24);
manlo <= conv_std_logic_vector(10324201,28);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1152,24);
manlo <= conv_std_logic_vector(10617075,28);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1168,24);
manlo <= conv_std_logic_vector(10914045,28);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1184,24);
manlo <= conv_std_logic_vector(11215112,28);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1200,24);
manlo <= conv_std_logic_vector(11520275,28);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1216,24);
manlo <= conv_std_logic_vector(11829534,28);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1232,24);
manlo <= conv_std_logic_vector(12142889,28);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1248,24);
manlo <= conv_std_logic_vector(12460341,28);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1264,24);
manlo <= conv_std_logic_vector(12781889,28);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1280,24);
manlo <= conv_std_logic_vector(13107533,28);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1296,24);
manlo <= conv_std_logic_vector(13437274,28);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1312,24);
manlo <= conv_std_logic_vector(13771111,28);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1328,24);
manlo <= conv_std_logic_vector(14109044,28);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1344,24);
manlo <= conv_std_logic_vector(14451074,28);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1360,24);
manlo <= conv_std_logic_vector(14797200,28);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1376,24);
manlo <= conv_std_logic_vector(15147422,28);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1392,24);
manlo <= conv_std_logic_vector(15501741,28);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1408,24);
manlo <= conv_std_logic_vector(15860156,28);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1424,24);
manlo <= conv_std_logic_vector(16222667,28);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1440,24);
manlo <= conv_std_logic_vector(16589275,28);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1456,24);
manlo <= conv_std_logic_vector(16959979,28);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1472,24);
manlo <= conv_std_logic_vector(17334779,28);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1488,24);
manlo <= conv_std_logic_vector(17713676,28);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1504,24);
manlo <= conv_std_logic_vector(18096669,28);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1520,24);
manlo <= conv_std_logic_vector(18483758,28);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1536,24);
manlo <= conv_std_logic_vector(18874944,28);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1552,24);
manlo <= conv_std_logic_vector(19270226,28);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1568,24);
manlo <= conv_std_logic_vector(19669605,28);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1584,24);
manlo <= conv_std_logic_vector(20073080,28);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1600,24);
manlo <= conv_std_logic_vector(20480651,28);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1616,24);
manlo <= conv_std_logic_vector(20892319,28);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1632,24);
manlo <= conv_std_logic_vector(21308083,28);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1648,24);
manlo <= conv_std_logic_vector(21727943,28);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1664,24);
manlo <= conv_std_logic_vector(22151900,28);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1680,24);
manlo <= conv_std_logic_vector(22579954,28);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1696,24);
manlo <= conv_std_logic_vector(23012103,28);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1712,24);
manlo <= conv_std_logic_vector(23448350,28);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1728,24);
manlo <= conv_std_logic_vector(23888692,28);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1744,24);
manlo <= conv_std_logic_vector(24333131,28);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1760,24);
manlo <= conv_std_logic_vector(24781667,28);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1776,24);
manlo <= conv_std_logic_vector(25234298,28);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1792,24);
manlo <= conv_std_logic_vector(25691027,28);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1808,24);
manlo <= conv_std_logic_vector(26151851,28);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1824,24);
manlo <= conv_std_logic_vector(26616773,28);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1840,24);
manlo <= conv_std_logic_vector(27085790,28);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(1856,24);
manlo <= conv_std_logic_vector(27558904,28);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(1872,24);
manlo <= conv_std_logic_vector(28036115,28);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(1888,24);
manlo <= conv_std_logic_vector(28517422,28);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(1904,24);
manlo <= conv_std_logic_vector(29002825,28);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(1920,24);
manlo <= conv_std_logic_vector(29492325,28);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(1936,24);
manlo <= conv_std_logic_vector(29985921,28);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(1952,24);
manlo <= conv_std_logic_vector(30483614,28);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(1968,24);
manlo <= conv_std_logic_vector(30985404,28);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1984,24);
manlo <= conv_std_logic_vector(31491289,28);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2000,24);
manlo <= conv_std_logic_vector(32001272,28);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2016,24);
manlo <= conv_std_logic_vector(32515350,28);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2032,24);
manlo <= conv_std_logic_vector(33033526,28);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2048,24);
manlo <= conv_std_logic_vector(33555797,28);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2064,24);
manlo <= conv_std_logic_vector(34082166,28);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2080,24);
manlo <= conv_std_logic_vector(34612630,28);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2096,24);
manlo <= conv_std_logic_vector(35147192,28);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2112,24);
manlo <= conv_std_logic_vector(35685849,28);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2128,24);
manlo <= conv_std_logic_vector(36228604,28);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2144,24);
manlo <= conv_std_logic_vector(36775455,28);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2160,24);
manlo <= conv_std_logic_vector(37326402,28);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2176,24);
manlo <= conv_std_logic_vector(37881446,28);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2192,24);
manlo <= conv_std_logic_vector(38440586,28);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2208,24);
manlo <= conv_std_logic_vector(39003823,28);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2224,24);
manlo <= conv_std_logic_vector(39571157,28);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2240,24);
manlo <= conv_std_logic_vector(40142587,28);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2256,24);
manlo <= conv_std_logic_vector(40718113,28);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2272,24);
manlo <= conv_std_logic_vector(41297736,28);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2288,24);
manlo <= conv_std_logic_vector(41881456,28);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2304,24);
manlo <= conv_std_logic_vector(42469272,28);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2320,24);
manlo <= conv_std_logic_vector(43061185,28);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2336,24);
manlo <= conv_std_logic_vector(43657194,28);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2352,24);
manlo <= conv_std_logic_vector(44257300,28);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2368,24);
manlo <= conv_std_logic_vector(44861503,28);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2384,24);
manlo <= conv_std_logic_vector(45469802,28);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2400,24);
manlo <= conv_std_logic_vector(46082197,28);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2416,24);
manlo <= conv_std_logic_vector(46698690,28);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2432,24);
manlo <= conv_std_logic_vector(47319278,28);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2448,24);
manlo <= conv_std_logic_vector(47943964,28);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2464,24);
manlo <= conv_std_logic_vector(48572746,28);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2480,24);
manlo <= conv_std_logic_vector(49205624,28);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2496,24);
manlo <= conv_std_logic_vector(49842600,28);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2512,24);
manlo <= conv_std_logic_vector(50483672,28);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2528,24);
manlo <= conv_std_logic_vector(51128840,28);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2544,24);
manlo <= conv_std_logic_vector(51778105,28);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2560,24);
manlo <= conv_std_logic_vector(52431467,28);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2576,24);
manlo <= conv_std_logic_vector(53088925,28);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2592,24);
manlo <= conv_std_logic_vector(53750480,28);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2608,24);
manlo <= conv_std_logic_vector(54416132,28);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2624,24);
manlo <= conv_std_logic_vector(55085880,28);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2640,24);
manlo <= conv_std_logic_vector(55759725,28);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2656,24);
manlo <= conv_std_logic_vector(56437666,28);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2672,24);
manlo <= conv_std_logic_vector(57119704,28);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2688,24);
manlo <= conv_std_logic_vector(57805839,28);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2704,24);
manlo <= conv_std_logic_vector(58496071,28);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(2720,24);
manlo <= conv_std_logic_vector(59190399,28);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(2736,24);
manlo <= conv_std_logic_vector(59888823,28);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(2752,24);
manlo <= conv_std_logic_vector(60591345,28);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(2768,24);
manlo <= conv_std_logic_vector(61297963,28);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(2784,24);
manlo <= conv_std_logic_vector(62008678,28);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(2800,24);
manlo <= conv_std_logic_vector(62723489,28);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(2816,24);
manlo <= conv_std_logic_vector(63442397,28);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(2832,24);
manlo <= conv_std_logic_vector(64165402,28);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2848,24);
manlo <= conv_std_logic_vector(64892504,28);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(2864,24);
manlo <= conv_std_logic_vector(65623702,28);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(2880,24);
manlo <= conv_std_logic_vector(66358997,28);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(2896,24);
manlo <= conv_std_logic_vector(67098389,28);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(2912,24);
manlo <= conv_std_logic_vector(67841877,28);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(2928,24);
manlo <= conv_std_logic_vector(68589462,28);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(2944,24);
manlo <= conv_std_logic_vector(69341144,28);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(2960,24);
manlo <= conv_std_logic_vector(70096922,28);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(2976,24);
manlo <= conv_std_logic_vector(70856798,28);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2992,24);
manlo <= conv_std_logic_vector(71620769,28);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3008,24);
manlo <= conv_std_logic_vector(72388838,28);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3024,24);
manlo <= conv_std_logic_vector(73161004,28);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3040,24);
manlo <= conv_std_logic_vector(73937266,28);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3056,24);
manlo <= conv_std_logic_vector(74717625,28);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3072,24);
manlo <= conv_std_logic_vector(75502080,28);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3088,24);
manlo <= conv_std_logic_vector(76290633,28);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3104,24);
manlo <= conv_std_logic_vector(77083282,28);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3120,24);
manlo <= conv_std_logic_vector(77880028,28);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3136,24);
manlo <= conv_std_logic_vector(78680870,28);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3152,24);
manlo <= conv_std_logic_vector(79485810,28);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3168,24);
manlo <= conv_std_logic_vector(80294846,28);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3184,24);
manlo <= conv_std_logic_vector(81107979,28);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3200,24);
manlo <= conv_std_logic_vector(81925209,28);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3216,24);
manlo <= conv_std_logic_vector(82746535,28);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3232,24);
manlo <= conv_std_logic_vector(83571958,28);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3248,24);
manlo <= conv_std_logic_vector(84401479,28);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3264,24);
manlo <= conv_std_logic_vector(85235095,28);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3280,24);
manlo <= conv_std_logic_vector(86072809,28);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3296,24);
manlo <= conv_std_logic_vector(86914620,28);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3312,24);
manlo <= conv_std_logic_vector(87760527,28);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3328,24);
manlo <= conv_std_logic_vector(88610531,28);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3344,24);
manlo <= conv_std_logic_vector(89464632,28);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3360,24);
manlo <= conv_std_logic_vector(90322830,28);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3376,24);
manlo <= conv_std_logic_vector(91185124,28);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3392,24);
manlo <= conv_std_logic_vector(92051516,28);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3408,24);
manlo <= conv_std_logic_vector(92922004,28);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3424,24);
manlo <= conv_std_logic_vector(93796589,28);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3440,24);
manlo <= conv_std_logic_vector(94675271,28);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3456,24);
manlo <= conv_std_logic_vector(95558049,28);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3472,24);
manlo <= conv_std_logic_vector(96444925,28);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3488,24);
manlo <= conv_std_logic_vector(97335897,28);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(3504,24);
manlo <= conv_std_logic_vector(98230967,28);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(3520,24);
manlo <= conv_std_logic_vector(99130133,28);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(3536,24);
manlo <= conv_std_logic_vector(100033396,28);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(3552,24);
manlo <= conv_std_logic_vector(100940755,28);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3568,24);
manlo <= conv_std_logic_vector(101852212,28);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(3584,24);
manlo <= conv_std_logic_vector(102767766,28);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(3600,24);
manlo <= conv_std_logic_vector(103687416,28);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(3616,24);
manlo <= conv_std_logic_vector(104611163,28);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(3632,24);
manlo <= conv_std_logic_vector(105539008,28);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(3648,24);
manlo <= conv_std_logic_vector(106470949,28);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(3664,24);
manlo <= conv_std_logic_vector(107406987,28);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(3680,24);
manlo <= conv_std_logic_vector(108347122,28);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(3696,24);
manlo <= conv_std_logic_vector(109291353,28);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3712,24);
manlo <= conv_std_logic_vector(110239682,28);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(3728,24);
manlo <= conv_std_logic_vector(111192108,28);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(3744,24);
manlo <= conv_std_logic_vector(112148630,28);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(3760,24);
manlo <= conv_std_logic_vector(113109250,28);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(3776,24);
manlo <= conv_std_logic_vector(114073966,28);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(3792,24);
manlo <= conv_std_logic_vector(115042779,28);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(3808,24);
manlo <= conv_std_logic_vector(116015689,28);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(3824,24);
manlo <= conv_std_logic_vector(116992696,28);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(3840,24);
manlo <= conv_std_logic_vector(117973801,28);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(3856,24);
manlo <= conv_std_logic_vector(118959001,28);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(3872,24);
manlo <= conv_std_logic_vector(119948299,28);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(3888,24);
manlo <= conv_std_logic_vector(120941694,28);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(3904,24);
manlo <= conv_std_logic_vector(121939186,28);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(3920,24);
manlo <= conv_std_logic_vector(122940775,28);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(3936,24);
manlo <= conv_std_logic_vector(123946461,28);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(3952,24);
manlo <= conv_std_logic_vector(124956243,28);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(3968,24);
manlo <= conv_std_logic_vector(125970123,28);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(3984,24);
manlo <= conv_std_logic_vector(126988100,28);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4000,24);
manlo <= conv_std_logic_vector(128010173,28);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4016,24);
manlo <= conv_std_logic_vector(129036344,28);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4032,24);
manlo <= conv_std_logic_vector(130066611,28);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4048,24);
manlo <= conv_std_logic_vector(131100976,28);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4064,24);
manlo <= conv_std_logic_vector(132139437,28);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4080,24);
manlo <= conv_std_logic_vector(133181996,28);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4096,24);
manlo <= conv_std_logic_vector(134228651,28);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4112,24);
manlo <= conv_std_logic_vector(135279404,28);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4128,24);
manlo <= conv_std_logic_vector(136334253,28);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4144,24);
manlo <= conv_std_logic_vector(137393200,28);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4160,24);
manlo <= conv_std_logic_vector(138456243,28);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4176,24);
manlo <= conv_std_logic_vector(139523384,28);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4192,24);
manlo <= conv_std_logic_vector(140594622,28);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4208,24);
manlo <= conv_std_logic_vector(141669956,28);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4224,24);
manlo <= conv_std_logic_vector(142749388,28);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4240,24);
manlo <= conv_std_logic_vector(143832916,28);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4256,24);
manlo <= conv_std_logic_vector(144920542,28);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4272,24);
manlo <= conv_std_logic_vector(146012265,28);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4288,24);
manlo <= conv_std_logic_vector(147108085,28);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(4304,24);
manlo <= conv_std_logic_vector(148208001,28);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(4320,24);
manlo <= conv_std_logic_vector(149312015,28);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(4336,24);
manlo <= conv_std_logic_vector(150420126,28);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(4352,24);
manlo <= conv_std_logic_vector(151532334,28);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(4368,24);
manlo <= conv_std_logic_vector(152648639,28);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(4384,24);
manlo <= conv_std_logic_vector(153769041,28);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(4400,24);
manlo <= conv_std_logic_vector(154893541,28);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(4416,24);
manlo <= conv_std_logic_vector(156022137,28);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4432,24);
manlo <= conv_std_logic_vector(157154830,28);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(4448,24);
manlo <= conv_std_logic_vector(158291621,28);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(4464,24);
manlo <= conv_std_logic_vector(159432508,28);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(4480,24);
manlo <= conv_std_logic_vector(160577493,28);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(4496,24);
manlo <= conv_std_logic_vector(161726574,28);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(4512,24);
manlo <= conv_std_logic_vector(162879753,28);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(4528,24);
manlo <= conv_std_logic_vector(164037029,28);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(4544,24);
manlo <= conv_std_logic_vector(165198402,28);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(4560,24);
manlo <= conv_std_logic_vector(166363872,28);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(4576,24);
manlo <= conv_std_logic_vector(167533439,28);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(4592,24);
manlo <= conv_std_logic_vector(168707104,28);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(4608,24);
manlo <= conv_std_logic_vector(169884865,28);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(4624,24);
manlo <= conv_std_logic_vector(171066724,28);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(4640,24);
manlo <= conv_std_logic_vector(172252679,28);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(4656,24);
manlo <= conv_std_logic_vector(173442732,28);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(4672,24);
manlo <= conv_std_logic_vector(174636882,28);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(4688,24);
manlo <= conv_std_logic_vector(175835129,28);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(4704,24);
manlo <= conv_std_logic_vector(177037474,28);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(4720,24);
manlo <= conv_std_logic_vector(178243915,28);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(4736,24);
manlo <= conv_std_logic_vector(179454454,28);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(4752,24);
manlo <= conv_std_logic_vector(180669089,28);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(4768,24);
manlo <= conv_std_logic_vector(181887822,28);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(4784,24);
manlo <= conv_std_logic_vector(183110652,28);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(4800,24);
manlo <= conv_std_logic_vector(184337579,28);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(4816,24);
manlo <= conv_std_logic_vector(185568604,28);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(4832,24);
manlo <= conv_std_logic_vector(186803725,28);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(4848,24);
manlo <= conv_std_logic_vector(188042944,28);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(4864,24);
manlo <= conv_std_logic_vector(189286260,28);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(4880,24);
manlo <= conv_std_logic_vector(190533673,28);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(4896,24);
manlo <= conv_std_logic_vector(191785183,28);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(4912,24);
manlo <= conv_std_logic_vector(193040791,28);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(4928,24);
manlo <= conv_std_logic_vector(194300496,28);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(4944,24);
manlo <= conv_std_logic_vector(195564298,28);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(4960,24);
manlo <= conv_std_logic_vector(196832197,28);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4976,24);
manlo <= conv_std_logic_vector(198104193,28);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(4992,24);
manlo <= conv_std_logic_vector(199380286,28);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5008,24);
manlo <= conv_std_logic_vector(200660477,28);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(5024,24);
manlo <= conv_std_logic_vector(201944765,28);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(5040,24);
manlo <= conv_std_logic_vector(203233150,28);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(5056,24);
manlo <= conv_std_logic_vector(204525633,28);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(5072,24);
manlo <= conv_std_logic_vector(205822213,28);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(5088,24);
manlo <= conv_std_logic_vector(207122889,28);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(5104,24);
manlo <= conv_std_logic_vector(208427664,28);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(5120,24);
manlo <= conv_std_logic_vector(209736535,28);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(5136,24);
manlo <= conv_std_logic_vector(211049504,28);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(5152,24);
manlo <= conv_std_logic_vector(212366570,28);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(5168,24);
manlo <= conv_std_logic_vector(213687733,28);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(5184,24);
manlo <= conv_std_logic_vector(215012993,28);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(5200,24);
manlo <= conv_std_logic_vector(216342351,28);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(5216,24);
manlo <= conv_std_logic_vector(217675806,28);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(5232,24);
manlo <= conv_std_logic_vector(219013358,28);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(5248,24);
manlo <= conv_std_logic_vector(220355007,28);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(5264,24);
manlo <= conv_std_logic_vector(221700754,28);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(5280,24);
manlo <= conv_std_logic_vector(223050598,28);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(5296,24);
manlo <= conv_std_logic_vector(224404540,28);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(5312,24);
manlo <= conv_std_logic_vector(225762578,28);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(5328,24);
manlo <= conv_std_logic_vector(227124714,28);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(5344,24);
manlo <= conv_std_logic_vector(228490948,28);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(5360,24);
manlo <= conv_std_logic_vector(229861278,28);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(5376,24);
manlo <= conv_std_logic_vector(231235706,28);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(5392,24);
manlo <= conv_std_logic_vector(232614231,28);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(5408,24);
manlo <= conv_std_logic_vector(233996854,28);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(5424,24);
manlo <= conv_std_logic_vector(235383573,28);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(5440,24);
manlo <= conv_std_logic_vector(236774391,28);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(5456,24);
manlo <= conv_std_logic_vector(238169305,28);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(5472,24);
manlo <= conv_std_logic_vector(239568317,28);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(5488,24);
manlo <= conv_std_logic_vector(240971426,28);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(5504,24);
manlo <= conv_std_logic_vector(242378633,28);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(5520,24);
manlo <= conv_std_logic_vector(243789936,28);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(5536,24);
manlo <= conv_std_logic_vector(245205338,28);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5552,24);
manlo <= conv_std_logic_vector(246624836,28);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(5568,24);
manlo <= conv_std_logic_vector(248048432,28);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(5584,24);
manlo <= conv_std_logic_vector(249476125,28);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(5600,24);
manlo <= conv_std_logic_vector(250907916,28);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(5616,24);
manlo <= conv_std_logic_vector(252343804,28);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(5632,24);
manlo <= conv_std_logic_vector(253783789,28);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(5648,24);
manlo <= conv_std_logic_vector(255227872,28);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(5664,24);
manlo <= conv_std_logic_vector(256676052,28);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(5680,24);
manlo <= conv_std_logic_vector(258128329,28);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5696,24);
manlo <= conv_std_logic_vector(259584704,28);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(5712,24);
manlo <= conv_std_logic_vector(261045176,28);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(5728,24);
manlo <= conv_std_logic_vector(262509746,28);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(5744,24);
manlo <= conv_std_logic_vector(263978413,28);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(5760,24);
manlo <= conv_std_logic_vector(265451178,28);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(5776,24);
manlo <= conv_std_logic_vector(266928039,28);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(5792,24);
manlo <= conv_std_logic_vector(268408999,28);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(5809,24);
manlo <= conv_std_logic_vector(1458599,28);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(5825,24);
manlo <= conv_std_logic_vector(2947754,28);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5841,24);
manlo <= conv_std_logic_vector(4441005,28);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(5857,24);
manlo <= conv_std_logic_vector(5938354,28);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(5873,24);
manlo <= conv_std_logic_vector(7439800,28);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(5889,24);
manlo <= conv_std_logic_vector(8945344,28);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(5905,24);
manlo <= conv_std_logic_vector(10454985,28);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(5921,24);
manlo <= conv_std_logic_vector(11968724,28);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(5937,24);
manlo <= conv_std_logic_vector(13486560,28);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(5953,24);
manlo <= conv_std_logic_vector(15008494,28);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(5969,24);
manlo <= conv_std_logic_vector(16534525,28);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5985,24);
manlo <= conv_std_logic_vector(18064653,28);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(6001,24);
manlo <= conv_std_logic_vector(19598879,28);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(6017,24);
manlo <= conv_std_logic_vector(21137203,28);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(6033,24);
manlo <= conv_std_logic_vector(22679624,28);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(6049,24);
manlo <= conv_std_logic_vector(24226142,28);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(6065,24);
manlo <= conv_std_logic_vector(25776758,28);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(6081,24);
manlo <= conv_std_logic_vector(27331471,28);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(6097,24);
manlo <= conv_std_logic_vector(28890282,28);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(6113,24);
manlo <= conv_std_logic_vector(30453190,28);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6129,24);
manlo <= conv_std_logic_vector(32020196,28);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(6145,24);
manlo <= conv_std_logic_vector(33591299,28);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(6161,24);
manlo <= conv_std_logic_vector(35166500,28);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(6177,24);
manlo <= conv_std_logic_vector(36745798,28);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(6193,24);
manlo <= conv_std_logic_vector(38329194,28);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(6209,24);
manlo <= conv_std_logic_vector(39916688,28);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(6225,24);
manlo <= conv_std_logic_vector(41508278,28);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(6241,24);
manlo <= conv_std_logic_vector(43103967,28);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(6257,24);
manlo <= conv_std_logic_vector(44703753,28);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6273,24);
manlo <= conv_std_logic_vector(46307636,28);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(6289,24);
manlo <= conv_std_logic_vector(47915617,28);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(6305,24);
manlo <= conv_std_logic_vector(49527695,28);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(6321,24);
manlo <= conv_std_logic_vector(51143871,28);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(6337,24);
manlo <= conv_std_logic_vector(52764145,28);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(6353,24);
manlo <= conv_std_logic_vector(54388516,28);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(6369,24);
manlo <= conv_std_logic_vector(56016985,28);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(6385,24);
manlo <= conv_std_logic_vector(57649551,28);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(6401,24);
manlo <= conv_std_logic_vector(59286215,28);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6417,24);
manlo <= conv_std_logic_vector(60926976,28);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(6433,24);
manlo <= conv_std_logic_vector(62571835,28);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(6449,24);
manlo <= conv_std_logic_vector(64220791,28);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(6465,24);
manlo <= conv_std_logic_vector(65873845,28);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(6481,24);
manlo <= conv_std_logic_vector(67530997,28);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(6497,24);
manlo <= conv_std_logic_vector(69192246,28);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(6513,24);
manlo <= conv_std_logic_vector(70857593,28);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(6529,24);
manlo <= conv_std_logic_vector(72527037,28);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(6545,24);
manlo <= conv_std_logic_vector(74200579,28);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6561,24);
manlo <= conv_std_logic_vector(75878219,28);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(6577,24);
manlo <= conv_std_logic_vector(77559956,28);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(6593,24);
manlo <= conv_std_logic_vector(79245791,28);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(6609,24);
manlo <= conv_std_logic_vector(80935723,28);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(6625,24);
manlo <= conv_std_logic_vector(82629753,28);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(6641,24);
manlo <= conv_std_logic_vector(84327881,28);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(6657,24);
manlo <= conv_std_logic_vector(86030106,28);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(6673,24);
manlo <= conv_std_logic_vector(87736429,28);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(6689,24);
manlo <= conv_std_logic_vector(89446849,28);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(6705,24);
manlo <= conv_std_logic_vector(91161367,28);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(6721,24);
manlo <= conv_std_logic_vector(92879983,28);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(6737,24);
manlo <= conv_std_logic_vector(94602697,28);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(6753,24);
manlo <= conv_std_logic_vector(96329508,28);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(6769,24);
manlo <= conv_std_logic_vector(98060416,28);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(6785,24);
manlo <= conv_std_logic_vector(99795423,28);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(6801,24);
manlo <= conv_std_logic_vector(101534527,28);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(6817,24);
manlo <= conv_std_logic_vector(103277728,28);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(6833,24);
manlo <= conv_std_logic_vector(105025028,28);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(6849,24);
manlo <= conv_std_logic_vector(106776425,28);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(6865,24);
manlo <= conv_std_logic_vector(108531919,28);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(6881,24);
manlo <= conv_std_logic_vector(110291512,28);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(6897,24);
manlo <= conv_std_logic_vector(112055202,28);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(6913,24);
manlo <= conv_std_logic_vector(113822989,28);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(6929,24);
manlo <= conv_std_logic_vector(115594875,28);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(6945,24);
manlo <= conv_std_logic_vector(117370858,28);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(6961,24);
manlo <= conv_std_logic_vector(119150939,28);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(6977,24);
manlo <= conv_std_logic_vector(120935117,28);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(6993,24);
manlo <= conv_std_logic_vector(122723393,28);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(7009,24);
manlo <= conv_std_logic_vector(124515767,28);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(7025,24);
manlo <= conv_std_logic_vector(126312239,28);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(7041,24);
manlo <= conv_std_logic_vector(128112808,28);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(7057,24);
manlo <= conv_std_logic_vector(129917475,28);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(7073,24);
manlo <= conv_std_logic_vector(131726240,28);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(7089,24);
manlo <= conv_std_logic_vector(133539102,28);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(7105,24);
manlo <= conv_std_logic_vector(135356063,28);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(7121,24);
manlo <= conv_std_logic_vector(137177121,28);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7137,24);
manlo <= conv_std_logic_vector(139002276,28);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(7153,24);
manlo <= conv_std_logic_vector(140831530,28);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(7169,24);
manlo <= conv_std_logic_vector(142664881,28);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(7185,24);
manlo <= conv_std_logic_vector(144502330,28);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(7201,24);
manlo <= conv_std_logic_vector(146343877,28);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(7217,24);
manlo <= conv_std_logic_vector(148189521,28);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(7233,24);
manlo <= conv_std_logic_vector(150039263,28);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(7249,24);
manlo <= conv_std_logic_vector(151893103,28);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(7265,24);
manlo <= conv_std_logic_vector(153751041,28);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(7281,24);
manlo <= conv_std_logic_vector(155613076,28);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(7297,24);
manlo <= conv_std_logic_vector(157479210,28);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(7313,24);
manlo <= conv_std_logic_vector(159349441,28);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(7329,24);
manlo <= conv_std_logic_vector(161223770,28);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(7345,24);
manlo <= conv_std_logic_vector(163102196,28);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(7361,24);
manlo <= conv_std_logic_vector(164984721,28);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(7377,24);
manlo <= conv_std_logic_vector(166871343,28);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(7393,24);
manlo <= conv_std_logic_vector(168762063,28);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(7409,24);
manlo <= conv_std_logic_vector(170656881,28);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(7425,24);
manlo <= conv_std_logic_vector(172555797,28);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(7441,24);
manlo <= conv_std_logic_vector(174458810,28);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(7457,24);
manlo <= conv_std_logic_vector(176365921,28);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(7473,24);
manlo <= conv_std_logic_vector(178277130,28);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(7489,24);
manlo <= conv_std_logic_vector(180192437,28);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(7505,24);
manlo <= conv_std_logic_vector(182111842,28);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(7521,24);
manlo <= conv_std_logic_vector(184035345,28);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(7537,24);
manlo <= conv_std_logic_vector(185962945,28);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(7553,24);
manlo <= conv_std_logic_vector(187894643,28);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(7569,24);
manlo <= conv_std_logic_vector(189830439,28);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(7585,24);
manlo <= conv_std_logic_vector(191770333,28);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(7601,24);
manlo <= conv_std_logic_vector(193714325,28);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(7617,24);
manlo <= conv_std_logic_vector(195662415,28);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(7633,24);
manlo <= conv_std_logic_vector(197614602,28);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(7649,24);
manlo <= conv_std_logic_vector(199570888,28);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(7665,24);
manlo <= conv_std_logic_vector(201531271,28);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7681,24);
manlo <= conv_std_logic_vector(203495752,28);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(7697,24);
manlo <= conv_std_logic_vector(205464331,28);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(7713,24);
manlo <= conv_std_logic_vector(207437008,28);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(7729,24);
manlo <= conv_std_logic_vector(209413783,28);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(7745,24);
manlo <= conv_std_logic_vector(211394656,28);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(7761,24);
manlo <= conv_std_logic_vector(213379626,28);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(7777,24);
manlo <= conv_std_logic_vector(215368695,28);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(7793,24);
manlo <= conv_std_logic_vector(217361861,28);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(7809,24);
manlo <= conv_std_logic_vector(219359125,28);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7825,24);
manlo <= conv_std_logic_vector(221360487,28);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(7841,24);
manlo <= conv_std_logic_vector(223365947,28);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(7857,24);
manlo <= conv_std_logic_vector(225375505,28);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(7873,24);
manlo <= conv_std_logic_vector(227389161,28);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(7889,24);
manlo <= conv_std_logic_vector(229406915,28);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(7905,24);
manlo <= conv_std_logic_vector(231428767,28);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(7921,24);
manlo <= conv_std_logic_vector(233454716,28);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(7937,24);
manlo <= conv_std_logic_vector(235484764,28);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(7953,24);
manlo <= conv_std_logic_vector(237518910,28);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7969,24);
manlo <= conv_std_logic_vector(239557153,28);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(7985,24);
manlo <= conv_std_logic_vector(241599495,28);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(8001,24);
manlo <= conv_std_logic_vector(243645934,28);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(8017,24);
manlo <= conv_std_logic_vector(245696471,28);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(8033,24);
manlo <= conv_std_logic_vector(247751107,28);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(8049,24);
manlo <= conv_std_logic_vector(249809840,28);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(8065,24);
manlo <= conv_std_logic_vector(251872671,28);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(8081,24);
manlo <= conv_std_logic_vector(253939600,28);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(8097,24);
manlo <= conv_std_logic_vector(256010627,28);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(8113,24);
manlo <= conv_std_logic_vector(258085753,28);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(8129,24);
manlo <= conv_std_logic_vector(260164976,28);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(8145,24);
manlo <= conv_std_logic_vector(262248297,28);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(8161,24);
manlo <= conv_std_logic_vector(264335716,28);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(8177,24);
manlo <= conv_std_logic_vector(266427233,28);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(8194,24);
manlo <= conv_std_logic_vector(87392,28);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(8210,24);
manlo <= conv_std_logic_vector(2187105,28);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(8226,24);
manlo <= conv_std_logic_vector(4290916,28);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(8242,24);
manlo <= conv_std_logic_vector(6398825,28);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8258,24);
manlo <= conv_std_logic_vector(8510832,28);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(8274,24);
manlo <= conv_std_logic_vector(10626938,28);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(8290,24);
manlo <= conv_std_logic_vector(12747141,28);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(8306,24);
manlo <= conv_std_logic_vector(14871442,28);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(8322,24);
manlo <= conv_std_logic_vector(16999841,28);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(8338,24);
manlo <= conv_std_logic_vector(19132338,28);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(8354,24);
manlo <= conv_std_logic_vector(21268934,28);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(8370,24);
manlo <= conv_std_logic_vector(23409627,28);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(8386,24);
manlo <= conv_std_logic_vector(25554418,28);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8402,24);
manlo <= conv_std_logic_vector(27703308,28);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(8418,24);
manlo <= conv_std_logic_vector(29856295,28);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(8434,24);
manlo <= conv_std_logic_vector(32013381,28);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(8450,24);
manlo <= conv_std_logic_vector(34174564,28);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(8466,24);
manlo <= conv_std_logic_vector(36339846,28);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(8482,24);
manlo <= conv_std_logic_vector(38509225,28);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(8498,24);
manlo <= conv_std_logic_vector(40682703,28);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(8514,24);
manlo <= conv_std_logic_vector(42860279,28);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(8530,24);
manlo <= conv_std_logic_vector(45041953,28);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8546,24);
manlo <= conv_std_logic_vector(47227725,28);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(8562,24);
manlo <= conv_std_logic_vector(49417595,28);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(8578,24);
manlo <= conv_std_logic_vector(51611563,28);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(8594,24);
manlo <= conv_std_logic_vector(53809629,28);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(8610,24);
manlo <= conv_std_logic_vector(56011794,28);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(8626,24);
manlo <= conv_std_logic_vector(58218056,28);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(8642,24);
manlo <= conv_std_logic_vector(60428417,28);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(8658,24);
manlo <= conv_std_logic_vector(62642876,28);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(8674,24);
manlo <= conv_std_logic_vector(64861432,28);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8690,24);
manlo <= conv_std_logic_vector(67084087,28);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(8706,24);
manlo <= conv_std_logic_vector(69310840,28);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(8722,24);
manlo <= conv_std_logic_vector(71541691,28);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(8738,24);
manlo <= conv_std_logic_vector(73776641,28);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(8754,24);
manlo <= conv_std_logic_vector(76015688,28);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(8770,24);
manlo <= conv_std_logic_vector(78258834,28);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(8786,24);
manlo <= conv_std_logic_vector(80506077,28);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(8802,24);
manlo <= conv_std_logic_vector(82757419,28);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(8818,24);
manlo <= conv_std_logic_vector(85012859,28);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(8834,24);
manlo <= conv_std_logic_vector(87272397,28);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(8850,24);
manlo <= conv_std_logic_vector(89536034,28);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(8866,24);
manlo <= conv_std_logic_vector(91803768,28);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(8882,24);
manlo <= conv_std_logic_vector(94075601,28);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(8898,24);
manlo <= conv_std_logic_vector(96351532,28);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(8914,24);
manlo <= conv_std_logic_vector(98631561,28);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(8930,24);
manlo <= conv_std_logic_vector(100915688,28);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(8946,24);
manlo <= conv_std_logic_vector(103203913,28);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(8962,24);
manlo <= conv_std_logic_vector(105496237,28);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(8978,24);
manlo <= conv_std_logic_vector(107792658,28);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(8994,24);
manlo <= conv_std_logic_vector(110093178,28);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(9010,24);
manlo <= conv_std_logic_vector(112397796,28);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(9026,24);
manlo <= conv_std_logic_vector(114706513,28);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(9042,24);
manlo <= conv_std_logic_vector(117019327,28);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(9058,24);
manlo <= conv_std_logic_vector(119336240,28);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(9074,24);
manlo <= conv_std_logic_vector(121657251,28);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(9090,24);
manlo <= conv_std_logic_vector(123982360,28);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(9106,24);
manlo <= conv_std_logic_vector(126311567,28);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9122,24);
manlo <= conv_std_logic_vector(128644873,28);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(9138,24);
manlo <= conv_std_logic_vector(130982277,28);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(9154,24);
manlo <= conv_std_logic_vector(133323779,28);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(9170,24);
manlo <= conv_std_logic_vector(135669379,28);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(9186,24);
manlo <= conv_std_logic_vector(138019077,28);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(9202,24);
manlo <= conv_std_logic_vector(140372874,28);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(9218,24);
manlo <= conv_std_logic_vector(142730769,28);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(9234,24);
manlo <= conv_std_logic_vector(145092762,28);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(9250,24);
manlo <= conv_std_logic_vector(147458854,28);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(9266,24);
manlo <= conv_std_logic_vector(149829044,28);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(9282,24);
manlo <= conv_std_logic_vector(152203332,28);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(9298,24);
manlo <= conv_std_logic_vector(154581718,28);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(9314,24);
manlo <= conv_std_logic_vector(156964202,28);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(9330,24);
manlo <= conv_std_logic_vector(159350785,28);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(9346,24);
manlo <= conv_std_logic_vector(161741466,28);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(9362,24);
manlo <= conv_std_logic_vector(164136246,28);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(9378,24);
manlo <= conv_std_logic_vector(166535123,28);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(9394,24);
manlo <= conv_std_logic_vector(168938099,28);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(9410,24);
manlo <= conv_std_logic_vector(171345174,28);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(9426,24);
manlo <= conv_std_logic_vector(173756346,28);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(9442,24);
manlo <= conv_std_logic_vector(176171617,28);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(9458,24);
manlo <= conv_std_logic_vector(178590986,28);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(9474,24);
manlo <= conv_std_logic_vector(181014454,28);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(9490,24);
manlo <= conv_std_logic_vector(183442020,28);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(9506,24);
manlo <= conv_std_logic_vector(185873684,28);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(9522,24);
manlo <= conv_std_logic_vector(188309446,28);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(9538,24);
manlo <= conv_std_logic_vector(190749307,28);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(9554,24);
manlo <= conv_std_logic_vector(193193266,28);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(9570,24);
manlo <= conv_std_logic_vector(195641323,28);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(9586,24);
manlo <= conv_std_logic_vector(198093479,28);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(9602,24);
manlo <= conv_std_logic_vector(200549733,28);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(9618,24);
manlo <= conv_std_logic_vector(203010086,28);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(9634,24);
manlo <= conv_std_logic_vector(205474536,28);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(9650,24);
manlo <= conv_std_logic_vector(207943085,28);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(9666,24);
manlo <= conv_std_logic_vector(210415733,28);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(9682,24);
manlo <= conv_std_logic_vector(212892479,28);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(9698,24);
manlo <= conv_std_logic_vector(215373323,28);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(9714,24);
manlo <= conv_std_logic_vector(217858266,28);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(9730,24);
manlo <= conv_std_logic_vector(220347307,28);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(9746,24);
manlo <= conv_std_logic_vector(222840446,28);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(9762,24);
manlo <= conv_std_logic_vector(225337684,28);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(9778,24);
manlo <= conv_std_logic_vector(227839020,28);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(9794,24);
manlo <= conv_std_logic_vector(230344454,28);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9810,24);
manlo <= conv_std_logic_vector(232853987,28);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(9826,24);
manlo <= conv_std_logic_vector(235367618,28);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(9842,24);
manlo <= conv_std_logic_vector(237885348,28);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(9858,24);
manlo <= conv_std_logic_vector(240407176,28);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(9874,24);
manlo <= conv_std_logic_vector(242933102,28);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(9890,24);
manlo <= conv_std_logic_vector(245463127,28);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(9906,24);
manlo <= conv_std_logic_vector(247997251,28);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(9922,24);
manlo <= conv_std_logic_vector(250535472,28);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(9938,24);
manlo <= conv_std_logic_vector(253077793,28);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9954,24);
manlo <= conv_std_logic_vector(255624211,28);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(9970,24);
manlo <= conv_std_logic_vector(258174728,28);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(9986,24);
manlo <= conv_std_logic_vector(260729344,28);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(10002,24);
manlo <= conv_std_logic_vector(263288057,28);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(10018,24);
manlo <= conv_std_logic_vector(265850870,28);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(10034,24);
manlo <= conv_std_logic_vector(268417780,28);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(10051,24);
manlo <= conv_std_logic_vector(2553334,28);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(10067,24);
manlo <= conv_std_logic_vector(5128441,28);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(10083,24);
manlo <= conv_std_logic_vector(7707647,28);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(10099,24);
manlo <= conv_std_logic_vector(10290952,28);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(10115,24);
manlo <= conv_std_logic_vector(12878355,28);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(10131,24);
manlo <= conv_std_logic_vector(15469857,28);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(10147,24);
manlo <= conv_std_logic_vector(18065457,28);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(10163,24);
manlo <= conv_std_logic_vector(20665155,28);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(10179,24);
manlo <= conv_std_logic_vector(23268952,28);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(10195,24);
manlo <= conv_std_logic_vector(25876847,28);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(10211,24);
manlo <= conv_std_logic_vector(28488841,28);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(10227,24);
manlo <= conv_std_logic_vector(31104934,28);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10243,24);
manlo <= conv_std_logic_vector(33725125,28);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(10259,24);
manlo <= conv_std_logic_vector(36349414,28);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(10275,24);
manlo <= conv_std_logic_vector(38977802,28);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(10291,24);
manlo <= conv_std_logic_vector(41610288,28);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(10307,24);
manlo <= conv_std_logic_vector(44246873,28);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(10323,24);
manlo <= conv_std_logic_vector(46887557,28);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(10339,24);
manlo <= conv_std_logic_vector(49532339,28);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(10355,24);
manlo <= conv_std_logic_vector(52181219,28);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(10371,24);
manlo <= conv_std_logic_vector(54834198,28);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10387,24);
manlo <= conv_std_logic_vector(57491276,28);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(10403,24);
manlo <= conv_std_logic_vector(60152452,28);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(10419,24);
manlo <= conv_std_logic_vector(62817727,28);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(10435,24);
manlo <= conv_std_logic_vector(65487100,28);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(10451,24);
manlo <= conv_std_logic_vector(68160572,28);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(10467,24);
manlo <= conv_std_logic_vector(70838142,28);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(10483,24);
manlo <= conv_std_logic_vector(73519811,28);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(10499,24);
manlo <= conv_std_logic_vector(76205578,28);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(10515,24);
manlo <= conv_std_logic_vector(78895444,28);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10531,24);
manlo <= conv_std_logic_vector(81589409,28);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(10547,24);
manlo <= conv_std_logic_vector(84287472,28);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(10563,24);
manlo <= conv_std_logic_vector(86989633,28);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(10579,24);
manlo <= conv_std_logic_vector(89695894,28);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(10595,24);
manlo <= conv_std_logic_vector(92406252,28);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(10611,24);
manlo <= conv_std_logic_vector(95120710,28);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(10627,24);
manlo <= conv_std_logic_vector(97839266,28);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(10643,24);
manlo <= conv_std_logic_vector(100561920,28);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(10659,24);
manlo <= conv_std_logic_vector(103288674,28);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10675,24);
manlo <= conv_std_logic_vector(106019525,28);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(10691,24);
manlo <= conv_std_logic_vector(108754476,28);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(10707,24);
manlo <= conv_std_logic_vector(111493525,28);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(10723,24);
manlo <= conv_std_logic_vector(114236673,28);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(10739,24);
manlo <= conv_std_logic_vector(116983919,28);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(10755,24);
manlo <= conv_std_logic_vector(119735264,28);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(10771,24);
manlo <= conv_std_logic_vector(122490707,28);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(10787,24);
manlo <= conv_std_logic_vector(125250249,28);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(10803,24);
manlo <= conv_std_logic_vector(128013890,28);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(10819,24);
manlo <= conv_std_logic_vector(130781629,28);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(10835,24);
manlo <= conv_std_logic_vector(133553468,28);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(10851,24);
manlo <= conv_std_logic_vector(136329404,28);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(10867,24);
manlo <= conv_std_logic_vector(139109440,28);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(10883,24);
manlo <= conv_std_logic_vector(141893574,28);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(10899,24);
manlo <= conv_std_logic_vector(144681806,28);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(10915,24);
manlo <= conv_std_logic_vector(147474137,28);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(10931,24);
manlo <= conv_std_logic_vector(150270567,28);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(10947,24);
manlo <= conv_std_logic_vector(153071096,28);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(10963,24);
manlo <= conv_std_logic_vector(155875723,28);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(10979,24);
manlo <= conv_std_logic_vector(158684449,28);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(10995,24);
manlo <= conv_std_logic_vector(161497274,28);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(11011,24);
manlo <= conv_std_logic_vector(164314197,28);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(11027,24);
manlo <= conv_std_logic_vector(167135219,28);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(11043,24);
manlo <= conv_std_logic_vector(169960340,28);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(11059,24);
manlo <= conv_std_logic_vector(172789560,28);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(11075,24);
manlo <= conv_std_logic_vector(175622878,28);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(11091,24);
manlo <= conv_std_logic_vector(178460295,28);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11107,24);
manlo <= conv_std_logic_vector(181301810,28);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(11123,24);
manlo <= conv_std_logic_vector(184147424,28);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(11139,24);
manlo <= conv_std_logic_vector(186997137,28);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(11155,24);
manlo <= conv_std_logic_vector(189850949,28);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(11171,24);
manlo <= conv_std_logic_vector(192708860,28);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(11187,24);
manlo <= conv_std_logic_vector(195570869,28);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(11203,24);
manlo <= conv_std_logic_vector(198436977,28);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(11219,24);
manlo <= conv_std_logic_vector(201307183,28);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(11235,24);
manlo <= conv_std_logic_vector(204181489,28);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(11251,24);
manlo <= conv_std_logic_vector(207059893,28);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(11267,24);
manlo <= conv_std_logic_vector(209942395,28);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(11283,24);
manlo <= conv_std_logic_vector(212828997,28);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(11299,24);
manlo <= conv_std_logic_vector(215719697,28);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(11315,24);
manlo <= conv_std_logic_vector(218614497,28);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(11331,24);
manlo <= conv_std_logic_vector(221513394,28);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(11347,24);
manlo <= conv_std_logic_vector(224416391,28);
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(11363,24);
manlo <= conv_std_logic_vector(227323486,28);
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(11379,24);
manlo <= conv_std_logic_vector(230234681,28);
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(11395,24);
manlo <= conv_std_logic_vector(233149974,28);
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(11411,24);
manlo <= conv_std_logic_vector(236069365,28);
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(11427,24);
manlo <= conv_std_logic_vector(238992856,28);
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(11443,24);
manlo <= conv_std_logic_vector(241920445,28);
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(11459,24);
manlo <= conv_std_logic_vector(244852133,28);
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(11475,24);
manlo <= conv_std_logic_vector(247787920,28);
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(11491,24);
manlo <= conv_std_logic_vector(250727806,28);
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(11507,24);
manlo <= conv_std_logic_vector(253671790,28);
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(11523,24);
manlo <= conv_std_logic_vector(256619874,28);
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(11539,24);
manlo <= conv_std_logic_vector(259572056,28);
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(11555,24);
manlo <= conv_std_logic_vector(262528337,28);
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(11571,24);
manlo <= conv_std_logic_vector(265488717,28);
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(11588,24);
manlo <= conv_std_logic_vector(17739,28);
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(11604,24);
manlo <= conv_std_logic_vector(2986317,28);
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(11620,24);
manlo <= conv_std_logic_vector(5958993,28);
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(11636,24);
manlo <= conv_std_logic_vector(8935768,28);
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(11652,24);
manlo <= conv_std_logic_vector(11916642,28);
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(11668,24);
manlo <= conv_std_logic_vector(14901615,28);
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(11684,24);
manlo <= conv_std_logic_vector(17890686,28);
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(11700,24);
manlo <= conv_std_logic_vector(20883857,28);
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(11716,24);
manlo <= conv_std_logic_vector(23881126,28);
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(11732,24);
manlo <= conv_std_logic_vector(26882494,28);
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(11748,24);
manlo <= conv_std_logic_vector(29887961,28);
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(11764,24);
manlo <= conv_std_logic_vector(32897527,28);
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(11780,24);
manlo <= conv_std_logic_vector(35911192,28);
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(11796,24);
manlo <= conv_std_logic_vector(38928956,28);
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(11812,24);
manlo <= conv_std_logic_vector(41950818,28);
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(11828,24);
manlo <= conv_std_logic_vector(44976780,28);
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(11844,24);
manlo <= conv_std_logic_vector(48006840,28);
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(11860,24);
manlo <= conv_std_logic_vector(51040999,28);
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(11876,24);
manlo <= conv_std_logic_vector(54079258,28);
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(11892,24);
manlo <= conv_std_logic_vector(57121615,28);
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(11908,24);
manlo <= conv_std_logic_vector(60168071,28);
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(11924,24);
manlo <= conv_std_logic_vector(63218625,28);
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(11940,24);
manlo <= conv_std_logic_vector(66273279,28);
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(11956,24);
manlo <= conv_std_logic_vector(69332032,28);
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(11972,24);
manlo <= conv_std_logic_vector(72394883,28);
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(11988,24);
manlo <= conv_std_logic_vector(75461834,28);
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(12004,24);
manlo <= conv_std_logic_vector(78532883,28);
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(12020,24);
manlo <= conv_std_logic_vector(81608032,28);
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(12036,24);
manlo <= conv_std_logic_vector(84687279,28);
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(12052,24);
manlo <= conv_std_logic_vector(87770625,28);
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(12068,24);
manlo <= conv_std_logic_vector(90858070,28);
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(12084,24);
manlo <= conv_std_logic_vector(93949615,28);
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(12100,24);
manlo <= conv_std_logic_vector(97045258,28);
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(12116,24);
manlo <= conv_std_logic_vector(100145000,28);
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(12132,24);
manlo <= conv_std_logic_vector(103248841,28);
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(12148,24);
manlo <= conv_std_logic_vector(106356781,28);
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(12164,24);
manlo <= conv_std_logic_vector(109468819,28);
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(12180,24);
manlo <= conv_std_logic_vector(112584957,28);
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(12196,24);
manlo <= conv_std_logic_vector(115705194,28);
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(12212,24);
manlo <= conv_std_logic_vector(118829530,28);
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(12228,24);
manlo <= conv_std_logic_vector(121957965,28);
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(12244,24);
manlo <= conv_std_logic_vector(125090499,28);
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(12260,24);
manlo <= conv_std_logic_vector(128227131,28);
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(12276,24);
manlo <= conv_std_logic_vector(131367863,28);
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(12292,24);
manlo <= conv_std_logic_vector(134512694,28);
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(12308,24);
manlo <= conv_std_logic_vector(137661624,28);
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(12324,24);
manlo <= conv_std_logic_vector(140814653,28);
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(12340,24);
manlo <= conv_std_logic_vector(143971780,28);
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(12356,24);
manlo <= conv_std_logic_vector(147133007,28);
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(12372,24);
manlo <= conv_std_logic_vector(150298333,28);
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(12388,24);
manlo <= conv_std_logic_vector(153467758,28);
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(12404,24);
manlo <= conv_std_logic_vector(156641282,28);
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(12420,24);
manlo <= conv_std_logic_vector(159818905,28);
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(12436,24);
manlo <= conv_std_logic_vector(163000627,28);
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(12452,24);
manlo <= conv_std_logic_vector(166186448,28);
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(12468,24);
manlo <= conv_std_logic_vector(169376368,28);
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(12484,24);
manlo <= conv_std_logic_vector(172570387,28);
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(12500,24);
manlo <= conv_std_logic_vector(175768505,28);
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(12516,24);
manlo <= conv_std_logic_vector(178970722,28);
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(12532,24);
manlo <= conv_std_logic_vector(182177038,28);
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(12548,24);
manlo <= conv_std_logic_vector(185387453,28);
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(12564,24);
manlo <= conv_std_logic_vector(188601968,28);
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(12580,24);
manlo <= conv_std_logic_vector(191820581,28);
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(12596,24);
manlo <= conv_std_logic_vector(195043294,28);
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(12612,24);
manlo <= conv_std_logic_vector(198270105,28);
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(12628,24);
manlo <= conv_std_logic_vector(201501016,28);
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(12644,24);
manlo <= conv_std_logic_vector(204736025,28);
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(12660,24);
manlo <= conv_std_logic_vector(207975134,28);
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(12676,24);
manlo <= conv_std_logic_vector(211218342,28);
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(12692,24);
manlo <= conv_std_logic_vector(214465649,28);
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(12708,24);
manlo <= conv_std_logic_vector(217717055,28);
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(12724,24);
manlo <= conv_std_logic_vector(220972560,28);
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(12740,24);
manlo <= conv_std_logic_vector(224232165,28);
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(12756,24);
manlo <= conv_std_logic_vector(227495868,28);
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(12772,24);
manlo <= conv_std_logic_vector(230763671,28);
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(12788,24);
manlo <= conv_std_logic_vector(234035572,28);
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(12804,24);
manlo <= conv_std_logic_vector(237311573,28);
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(12820,24);
manlo <= conv_std_logic_vector(240591673,28);
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(12836,24);
manlo <= conv_std_logic_vector(243875872,28);
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(12852,24);
manlo <= conv_std_logic_vector(247164170,28);
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(12868,24);
manlo <= conv_std_logic_vector(250456567,28);
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(12884,24);
manlo <= conv_std_logic_vector(253753064,28);
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(12900,24);
manlo <= conv_std_logic_vector(257053659,28);
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(12916,24);
manlo <= conv_std_logic_vector(260358354,28);
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(12932,24);
manlo <= conv_std_logic_vector(263667148,28);
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(12948,24);
manlo <= conv_std_logic_vector(266980041,28);
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(12965,24);
manlo <= conv_std_logic_vector(1861577,28);
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(12981,24);
manlo <= conv_std_logic_vector(5182668,28);
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(12997,24);
manlo <= conv_std_logic_vector(8507859,28);
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(13013,24);
manlo <= conv_std_logic_vector(11837149,28);
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(13029,24);
manlo <= conv_std_logic_vector(15170538,28);
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(13045,24);
manlo <= conv_std_logic_vector(18508026,28);
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(13061,24);
manlo <= conv_std_logic_vector(21849613,28);
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(13077,24);
manlo <= conv_std_logic_vector(25195299,28);
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(13093,24);
manlo <= conv_std_logic_vector(28545085,28);
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(13109,24);
manlo <= conv_std_logic_vector(31898970,28);
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(13125,24);
manlo <= conv_std_logic_vector(35256954,28);
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(13141,24);
manlo <= conv_std_logic_vector(38619037,28);
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(13157,24);
manlo <= conv_std_logic_vector(41985219,28);
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(13173,24);
manlo <= conv_std_logic_vector(45355501,28);
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(13189,24);
manlo <= conv_std_logic_vector(48729882,28);
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(13205,24);
manlo <= conv_std_logic_vector(52108362,28);
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(13221,24);
manlo <= conv_std_logic_vector(55490941,28);
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(13237,24);
manlo <= conv_std_logic_vector(58877620,28);
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(13253,24);
manlo <= conv_std_logic_vector(62268398,28);
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(13269,24);
manlo <= conv_std_logic_vector(65663275,28);
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(13285,24);
manlo <= conv_std_logic_vector(69062251,28);
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(13301,24);
manlo <= conv_std_logic_vector(72465326,28);
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(13317,24);
manlo <= conv_std_logic_vector(75872501,28);
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(13333,24);
manlo <= conv_std_logic_vector(79283775,28);
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(13349,24);
manlo <= conv_std_logic_vector(82699148,28);
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(13365,24);
manlo <= conv_std_logic_vector(86118621,28);
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(13381,24);
manlo <= conv_std_logic_vector(89542193,28);
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(13397,24);
manlo <= conv_std_logic_vector(92969864,28);
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(13413,24);
manlo <= conv_std_logic_vector(96401634,28);
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(13429,24);
manlo <= conv_std_logic_vector(99837503,28);
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(13445,24);
manlo <= conv_std_logic_vector(103277472,28);
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(13461,24);
manlo <= conv_std_logic_vector(106721540,28);
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(13477,24);
manlo <= conv_std_logic_vector(110169708,28);
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(13493,24);
manlo <= conv_std_logic_vector(113621975,28);
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(13509,24);
manlo <= conv_std_logic_vector(117078341,28);
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(13525,24);
manlo <= conv_std_logic_vector(120538806,28);
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(13541,24);
manlo <= conv_std_logic_vector(124003370,28);
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(13557,24);
manlo <= conv_std_logic_vector(127472034,28);
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(13573,24);
manlo <= conv_std_logic_vector(130944798,28);
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(13589,24);
manlo <= conv_std_logic_vector(134421660,28);
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(13605,24);
manlo <= conv_std_logic_vector(137902622,28);
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(13621,24);
manlo <= conv_std_logic_vector(141387683,28);
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(13637,24);
manlo <= conv_std_logic_vector(144876844,28);
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(13653,24);
manlo <= conv_std_logic_vector(148370104,28);
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(13669,24);
manlo <= conv_std_logic_vector(151867463,28);
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(13685,24);
manlo <= conv_std_logic_vector(155368921,28);
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(13701,24);
manlo <= conv_std_logic_vector(158874479,28);
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(13717,24);
manlo <= conv_std_logic_vector(162384136,28);
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(13733,24);
manlo <= conv_std_logic_vector(165897893,28);
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(13749,24);
manlo <= conv_std_logic_vector(169415749,28);
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(13765,24);
manlo <= conv_std_logic_vector(172937704,28);
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(13781,24);
manlo <= conv_std_logic_vector(176463758,28);
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(13797,24);
manlo <= conv_std_logic_vector(179993912,28);
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(13813,24);
manlo <= conv_std_logic_vector(183528166,28);
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(13829,24);
manlo <= conv_std_logic_vector(187066519,28);
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(13845,24);
manlo <= conv_std_logic_vector(190608971,28);
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(13861,24);
manlo <= conv_std_logic_vector(194155522,28);
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(13877,24);
manlo <= conv_std_logic_vector(197706173,28);
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(13893,24);
manlo <= conv_std_logic_vector(201260923,28);
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(13909,24);
manlo <= conv_std_logic_vector(204819773,28);
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(13925,24);
manlo <= conv_std_logic_vector(208382722,28);
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(13941,24);
manlo <= conv_std_logic_vector(211949770,28);
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(13957,24);
manlo <= conv_std_logic_vector(215520918,28);
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(13973,24);
manlo <= conv_std_logic_vector(219096165,28);
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(13989,24);
manlo <= conv_std_logic_vector(222675512,28);
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(14005,24);
manlo <= conv_std_logic_vector(226258958,28);
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(14021,24);
manlo <= conv_std_logic_vector(229846504,28);
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(14037,24);
manlo <= conv_std_logic_vector(233438148,28);
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(14053,24);
manlo <= conv_std_logic_vector(237033893,28);
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(14069,24);
manlo <= conv_std_logic_vector(240633737,28);
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(14085,24);
manlo <= conv_std_logic_vector(244237680,28);
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(14101,24);
manlo <= conv_std_logic_vector(247845722,28);
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(14117,24);
manlo <= conv_std_logic_vector(251457864,28);
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(14133,24);
manlo <= conv_std_logic_vector(255074106,28);
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(14149,24);
manlo <= conv_std_logic_vector(258694447,28);
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(14165,24);
manlo <= conv_std_logic_vector(262318887,28);
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(14181,24);
manlo <= conv_std_logic_vector(265947427,28);
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(14198,24);
manlo <= conv_std_logic_vector(1144611,28);
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(14214,24);
manlo <= conv_std_logic_vector(4781350,28);
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(14230,24);
manlo <= conv_std_logic_vector(8422188,28);
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(14246,24);
manlo <= conv_std_logic_vector(12067126,28);
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(14262,24);
manlo <= conv_std_logic_vector(15716163,28);
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(14278,24);
manlo <= conv_std_logic_vector(19369300,28);
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(14294,24);
manlo <= conv_std_logic_vector(23026536,28);
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(14310,24);
manlo <= conv_std_logic_vector(26687871,28);
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(14326,24);
manlo <= conv_std_logic_vector(30353307,28);
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(14342,24);
manlo <= conv_std_logic_vector(34022841,28);
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(14358,24);
manlo <= conv_std_logic_vector(37696476,28);
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(14374,24);
manlo <= conv_std_logic_vector(41374209,28);
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(14390,24);
manlo <= conv_std_logic_vector(45056043,28);
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(14406,24);
manlo <= conv_std_logic_vector(48741975,28);
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(14422,24);
manlo <= conv_std_logic_vector(52432007,28);
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(14438,24);
manlo <= conv_std_logic_vector(56126139,28);
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(14454,24);
manlo <= conv_std_logic_vector(59824371,28);
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(14470,24);
manlo <= conv_std_logic_vector(63526701,28);
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(14486,24);
manlo <= conv_std_logic_vector(67233132,28);
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(14502,24);
manlo <= conv_std_logic_vector(70943662,28);
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(14518,24);
manlo <= conv_std_logic_vector(74658291,28);
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(14534,24);
manlo <= conv_std_logic_vector(78377020,28);
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(14550,24);
manlo <= conv_std_logic_vector(82099849,28);
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(14566,24);
manlo <= conv_std_logic_vector(85826777,28);
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(14582,24);
manlo <= conv_std_logic_vector(89557804,28);
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(14598,24);
manlo <= conv_std_logic_vector(93292931,28);
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(14614,24);
manlo <= conv_std_logic_vector(97032158,28);
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(14630,24);
manlo <= conv_std_logic_vector(100775484,28);
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(14646,24);
manlo <= conv_std_logic_vector(104522910,28);
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(14662,24);
manlo <= conv_std_logic_vector(108274436,28);
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(14678,24);
manlo <= conv_std_logic_vector(112030061,28);
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(14694,24);
manlo <= conv_std_logic_vector(115789786,28);
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(14710,24);
manlo <= conv_std_logic_vector(119553610,28);
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(14726,24);
manlo <= conv_std_logic_vector(123321534,28);
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(14742,24);
manlo <= conv_std_logic_vector(127093557,28);
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(14758,24);
manlo <= conv_std_logic_vector(130869680,28);
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(14774,24);
manlo <= conv_std_logic_vector(134649903,28);
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(14790,24);
manlo <= conv_std_logic_vector(138434225,28);
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(14806,24);
manlo <= conv_std_logic_vector(142222647,28);
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(14822,24);
manlo <= conv_std_logic_vector(146015168,28);
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(14838,24);
manlo <= conv_std_logic_vector(149811789,28);
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(14854,24);
manlo <= conv_std_logic_vector(153612510,28);
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(14870,24);
manlo <= conv_std_logic_vector(157417330,28);
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(14886,24);
manlo <= conv_std_logic_vector(161226250,28);
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(14902,24);
manlo <= conv_std_logic_vector(165039270,28);
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(14918,24);
manlo <= conv_std_logic_vector(168856389,28);
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(14934,24);
manlo <= conv_std_logic_vector(172677608,28);
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(14950,24);
manlo <= conv_std_logic_vector(176502926,28);
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(14966,24);
manlo <= conv_std_logic_vector(180332344,28);
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(14982,24);
manlo <= conv_std_logic_vector(184165862,28);
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(14998,24);
manlo <= conv_std_logic_vector(188003480,28);
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(15014,24);
manlo <= conv_std_logic_vector(191845197,28);
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(15030,24);
manlo <= conv_std_logic_vector(195691014,28);
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(15046,24);
manlo <= conv_std_logic_vector(199540930,28);
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(15062,24);
manlo <= conv_std_logic_vector(203394946,28);
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(15078,24);
manlo <= conv_std_logic_vector(207253062,28);
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(15094,24);
manlo <= conv_std_logic_vector(211115277,28);
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(15110,24);
manlo <= conv_std_logic_vector(214981593,28);
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(15126,24);
manlo <= conv_std_logic_vector(218852007,28);
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(15142,24);
manlo <= conv_std_logic_vector(222726522,28);
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(15158,24);
manlo <= conv_std_logic_vector(226605136,28);
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(15174,24);
manlo <= conv_std_logic_vector(230487850,28);
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(15190,24);
manlo <= conv_std_logic_vector(234374664,28);
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(15206,24);
manlo <= conv_std_logic_vector(238265577,28);
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(15222,24);
manlo <= conv_std_logic_vector(242160590,28);
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(15238,24);
manlo <= conv_std_logic_vector(246059703,28);
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(15254,24);
manlo <= conv_std_logic_vector(249962916,28);
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(15270,24);
manlo <= conv_std_logic_vector(253870228,28);
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(15286,24);
manlo <= conv_std_logic_vector(257781640,28);
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(15302,24);
manlo <= conv_std_logic_vector(261697152,28);
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(15318,24);
manlo <= conv_std_logic_vector(265616763,28);
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(15335,24);
manlo <= conv_std_logic_vector(1105018,28);
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(15351,24);
manlo <= conv_std_logic_vector(5032829,28);
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(15367,24);
manlo <= conv_std_logic_vector(8964740,28);
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(15383,24);
manlo <= conv_std_logic_vector(12900750,28);
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(15399,24);
manlo <= conv_std_logic_vector(16840860,28);
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(15415,24);
manlo <= conv_std_logic_vector(20785070,28);
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(15431,24);
manlo <= conv_std_logic_vector(24733380,28);
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(15447,24);
manlo <= conv_std_logic_vector(28685790,28);
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(15463,24);
manlo <= conv_std_logic_vector(32642299,28);
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(15479,24);
manlo <= conv_std_logic_vector(36602908,28);
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(15495,24);
manlo <= conv_std_logic_vector(40567617,28);
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(15511,24);
manlo <= conv_std_logic_vector(44536425,28);
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(15527,24);
manlo <= conv_std_logic_vector(48509334,28);
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(15543,24);
manlo <= conv_std_logic_vector(52486342,28);
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(15559,24);
manlo <= conv_std_logic_vector(56467450,28);
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(15575,24);
manlo <= conv_std_logic_vector(60452657,28);
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(15591,24);
manlo <= conv_std_logic_vector(64441965,28);
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(15607,24);
manlo <= conv_std_logic_vector(68435372,28);
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(15623,24);
manlo <= conv_std_logic_vector(72432880,28);
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(15639,24);
manlo <= conv_std_logic_vector(76434487,28);
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(15655,24);
manlo <= conv_std_logic_vector(80440193,28);
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(15671,24);
manlo <= conv_std_logic_vector(84450000,28);
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(15687,24);
manlo <= conv_std_logic_vector(88463906,28);
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(15703,24);
manlo <= conv_std_logic_vector(92481913,28);
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(15719,24);
manlo <= conv_std_logic_vector(96504019,28);
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(15735,24);
manlo <= conv_std_logic_vector(100530225,28);
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(15751,24);
manlo <= conv_std_logic_vector(104560531,28);
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(15767,24);
manlo <= conv_std_logic_vector(108594936,28);
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(15783,24);
manlo <= conv_std_logic_vector(112633442,28);
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(15799,24);
manlo <= conv_std_logic_vector(116676047,28);
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(15815,24);
manlo <= conv_std_logic_vector(120722752,28);
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(15831,24);
manlo <= conv_std_logic_vector(124773557,28);
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(15847,24);
manlo <= conv_std_logic_vector(128828462,28);
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(15863,24);
manlo <= conv_std_logic_vector(132887467,28);
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(15879,24);
manlo <= conv_std_logic_vector(136950572,28);
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(15895,24);
manlo <= conv_std_logic_vector(141017776,28);
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(15911,24);
manlo <= conv_std_logic_vector(145089081,28);
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(15927,24);
manlo <= conv_std_logic_vector(149164485,28);
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(15943,24);
manlo <= conv_std_logic_vector(153243989,28);
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(15959,24);
manlo <= conv_std_logic_vector(157327593,28);
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(15975,24);
manlo <= conv_std_logic_vector(161415297,28);
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(15991,24);
manlo <= conv_std_logic_vector(165507101,28);
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(16007,24);
manlo <= conv_std_logic_vector(169603005,28);
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(16023,24);
manlo <= conv_std_logic_vector(173703009,28);
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(16039,24);
manlo <= conv_std_logic_vector(177807112,28);
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(16055,24);
manlo <= conv_std_logic_vector(181915316,28);
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(16071,24);
manlo <= conv_std_logic_vector(186027619,28);
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(16087,24);
manlo <= conv_std_logic_vector(190144023,28);
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(16103,24);
manlo <= conv_std_logic_vector(194264526,28);
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(16119,24);
manlo <= conv_std_logic_vector(198389129,28);
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(16135,24);
manlo <= conv_std_logic_vector(202517832,28);
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(16151,24);
manlo <= conv_std_logic_vector(206650635,28);
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(16167,24);
manlo <= conv_std_logic_vector(210787538,28);
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(16183,24);
manlo <= conv_std_logic_vector(214928541,28);
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(16199,24);
manlo <= conv_std_logic_vector(219073644,28);
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(16215,24);
manlo <= conv_std_logic_vector(223222847,28);
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(16231,24);
manlo <= conv_std_logic_vector(227376150,28);
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(16247,24);
manlo <= conv_std_logic_vector(231533553,28);
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(16263,24);
manlo <= conv_std_logic_vector(235695056,28);
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(16279,24);
manlo <= conv_std_logic_vector(239860659,28);
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(16295,24);
manlo <= conv_std_logic_vector(244030361,28);
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(16311,24);
manlo <= conv_std_logic_vector(248204164,28);
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(16327,24);
manlo <= conv_std_logic_vector(252382067,28);
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(16343,24);
manlo <= conv_std_logic_vector(256564069,28);
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(16359,24);
manlo <= conv_std_logic_vector(260750172,28);
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(16375,24);
manlo <= conv_std_logic_vector(264940375,28);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
END CASE;
END PROCESS;
END rtl;
|
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